include/hw/i386/pc.h

   1 #ifndef HW_PC_H
   2 #define HW_PC_H
   3
   4 #include "qemu-common.h"
   5 #include "exec/memory.h"
   6 #include "hw/isa/isa.h"
   7 #include "hw/block/fdc.h"
   8 #include "net/net.h"
   9 #include "hw/i386/ioapic.h"
  10
  11 #include "qemu/range.h"
  12 #include "qemu/bitmap.h"
  13 #include "sysemu/sysemu.h"
  14 #include "hw/pci/pci.h"
  15 #include "hw/boards.h"
  16
  17 #define HPET_INTCAP "hpet-intcap"
  18
  19 /**
  20  * PCMachineState:
  21  * @hotplug_memory_base: address in guest RAM address space where hotplug memory
  22  * address space begins.
  23  * @hotplug_memory: hotplug memory addess space container
  24  * @acpi_dev: link to ACPI PM device that performs ACPI hotplug handling
  25  */
  26 struct PCMachineState {
  27     /*< private >*/
  28     MachineState parent_obj;
  29
  30     /* <public> */
  31     ram_addr_t hotplug_memory_base;
  32     MemoryRegion hotplug_memory;
  33
  34     HotplugHandler *acpi_dev;
  35 };
  36
  37 #define PC_MACHINE_ACPI_DEVICE_PROP "acpi-device"
  38
  39 /**
  40  * PCMachineClass:
  41  * @get_hotplug_handler: pointer to parent class callback @get_hotplug_handler
  42  */
  43 struct PCMachineClass {
  44     /*< private >*/
  45     MachineClass parent_class;
  46
  47     /*< public >*/
  48     HotplugHandler *(*get_hotplug_handler)(MachineState *machine,
  49                                            DeviceState *dev);
  50 };
  51
  52 typedef struct PCMachineState PCMachineState;
  53 typedef struct PCMachineClass PCMachineClass;
  54
  55 #define TYPE_PC_MACHINE "generic-pc-machine"
  56 #define PC_MACHINE(obj) \
  57     OBJECT_CHECK(PCMachineState, (obj), TYPE_PC_MACHINE)
  58 #define PC_MACHINE_GET_CLASS(obj) \
  59     OBJECT_GET_CLASS(PCMachineClass, (obj), TYPE_PC_MACHINE)
  60 #define PC_MACHINE_CLASS(klass) \
  61     OBJECT_CLASS_CHECK(PCMachineClass, (klass), TYPE_PC_MACHINE)
  62
  63 void qemu_register_pc_machine(QEMUMachine *m);
  64
  65 /* PC-style peripherals (also used by other machines).  */
  66
  67 typedef struct PcPciInfo {
  68     Range w32;
  69     Range w64;
  70 } PcPciInfo;
  71
  72 #define ACPI_PM_PROP_S3_DISABLED "disable_s3"
  73 #define ACPI_PM_PROP_S4_DISABLED "disable_s4"
  74 #define ACPI_PM_PROP_S4_VAL "s4_val"
  75 #define ACPI_PM_PROP_SCI_INT "sci_int"
  76 #define ACPI_PM_PROP_ACPI_ENABLE_CMD "acpi_enable_cmd"
  77 #define ACPI_PM_PROP_ACPI_DISABLE_CMD "acpi_disable_cmd"
  78 #define ACPI_PM_PROP_PM_IO_BASE "pm_io_base"
  79 #define ACPI_PM_PROP_GPE0_BLK "gpe0_blk"
  80 #define ACPI_PM_PROP_GPE0_BLK_LEN "gpe0_blk_len"
  81
  82 struct PcGuestInfo {
  83     bool has_pci_info;
  84     bool isapc_ram_fw;
  85     hwaddr ram_size, ram_size_below_4g;
  86     unsigned apic_id_limit;
  87     bool apic_xrupt_override;
  88     uint64_t numa_nodes;
  89     uint64_t *node_mem;
  90     uint64_t *node_cpu;
  91     FWCfgState *fw_cfg;
  92     bool has_acpi_build;
  93     bool has_reserved_memory;
  94 };
  95
  96 /* parallel.c */
  97 static inline bool parallel_init(ISABus *bus, int index, CharDriverState *chr)
  98 {
  99     DeviceState *dev;
 100     ISADevice *isadev;
 101
 102     isadev = isa_try_create(bus, "isa-parallel");
 103     if (!isadev) {
 104         return false;
 105     }
 106     dev = DEVICE(isadev);
 107     qdev_prop_set_uint32(dev, "index", index);
 108     qdev_prop_set_chr(dev, "chardev", chr);
 109     if (qdev_init(dev) < 0) {
 110         return false;
 111     }
 112     return true;
 113 }
 114
 115 bool parallel_mm_init(MemoryRegion *address_space,
 116                       hwaddr base, int it_shift, qemu_irq irq,
 117                       CharDriverState *chr);
 118
 119 /* i8259.c */
 120
 121 extern DeviceState *isa_pic;
 122 qemu_irq *i8259_init(ISABus *bus, qemu_irq parent_irq);
 123 qemu_irq *kvm_i8259_init(ISABus *bus);
 124 int pic_read_irq(DeviceState *d);
 125 int pic_get_output(DeviceState *d);
 126 void pic_info(Monitor *mon, const QDict *qdict);
 127 void irq_info(Monitor *mon, const QDict *qdict);
 128
 129 /* Global System Interrupts */
 130
 131 #define GSI_NUM_PINS IOAPIC_NUM_PINS
 132
 133 typedef struct GSIState {
 134     qemu_irq i8259_irq[ISA_NUM_IRQS];
 135     qemu_irq ioapic_irq[IOAPIC_NUM_PINS];
 136 } GSIState;
 137
 138 void gsi_handler(void *opaque, int n, int level);
 139
 140 /* vmport.c */
 141 typedef uint32_t (VMPortReadFunc)(void *opaque, uint32_t address);
 142
 143 static inline void vmport_init(ISABus *bus)
 144 {
 145     isa_create_simple(bus, "vmport");
 146 }
 147
 148 void vmport_register(unsigned char command, VMPortReadFunc *func, void *opaque);
 149 void vmmouse_get_data(uint32_t *data);
 150 void vmmouse_set_data(const uint32_t *data);
 151
 152 /* pckbd.c */
 153
 154 void i8042_init(qemu_irq kbd_irq, qemu_irq mouse_irq, uint32_t io_base);
 155 void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq,
 156                    MemoryRegion *region, ram_addr_t size,
 157                    hwaddr mask);
 158 void i8042_isa_mouse_fake_event(void *opaque);
 159 void i8042_setup_a20_line(ISADevice *dev, qemu_irq *a20_out);
 160
 161 /* pc.c */
 162 extern int fd_bootchk;
 163
 164 void pc_register_ferr_irq(qemu_irq irq);
 165 void pc_acpi_smi_interrupt(void *opaque, int irq, int level);
 166
 167 void pc_cpus_init(const char *cpu_model, DeviceState *icc_bridge);
 168 void pc_hot_add_cpu(const int64_t id, Error **errp);
 169 void pc_acpi_init(const char *default_dsdt);
 170
 171 PcGuestInfo *pc_guest_info_init(ram_addr_t below_4g_mem_size,
 172                                 ram_addr_t above_4g_mem_size);
 173
 174 #define PCI_HOST_PROP_PCI_HOLE_START   "pci-hole-start"
 175 #define PCI_HOST_PROP_PCI_HOLE_END     "pci-hole-end"
 176 #define PCI_HOST_PROP_PCI_HOLE64_START "pci-hole64-start"
 177 #define PCI_HOST_PROP_PCI_HOLE64_END   "pci-hole64-end"
 178 #define PCI_HOST_PROP_PCI_HOLE64_SIZE  "pci-hole64-size"
 179 #define DEFAULT_PCI_HOLE64_SIZE (~0x0ULL)
 180
 181
 182 void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory,
 183                             MemoryRegion *pci_address_space);
 184
 185 FWCfgState *pc_memory_init(MemoryRegion *system_memory,
 186                            const char *kernel_filename,
 187                            const char *kernel_cmdline,
 188                            const char *initrd_filename,
 189                            ram_addr_t below_4g_mem_size,
 190                            ram_addr_t above_4g_mem_size,
 191                            MemoryRegion *rom_memory,
 192                            MemoryRegion **ram_memory,
 193                            PcGuestInfo *guest_info);
 194 qemu_irq *pc_allocate_cpu_irq(void);
 195 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus);
 196 void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi,
 197                           ISADevice **rtc_state,
 198                           ISADevice **floppy,
 199                           bool no_vmport,
 200                           uint32 hpet_irqs);
 201 void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd);
 202 void pc_cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size,
 203                   const char *boot_device,
 204                   ISADevice *floppy, BusState *ide0, BusState *ide1,
 205                   ISADevice *s);
 206 void pc_nic_init(ISABus *isa_bus, PCIBus *pci_bus);
 207 void pc_pci_device_init(PCIBus *pci_bus);
 208
 209 typedef void (*cpu_set_smm_t)(int smm, void *arg);
 210 void cpu_smm_register(cpu_set_smm_t callback, void *arg);
 211
 212 void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name);
 213
 214 /* acpi_piix.c */
 215
 216 I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
 217                       qemu_irq sci_irq, qemu_irq smi_irq,
 218                       int kvm_enabled, FWCfgState *fw_cfg,
 219                       DeviceState **piix4_pm);
 220 void piix4_smbus_register_device(SMBusDevice *dev, uint8_t addr);
 221
 222 /* hpet.c */
 223 extern int no_hpet;
 224
 225 /* piix_pci.c */
 226 struct PCII440FXState;
 227 typedef struct PCII440FXState PCII440FXState;
 228
 229 PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int *piix_devfn,
 230                     ISABus **isa_bus, qemu_irq *pic,
 231                     MemoryRegion *address_space_mem,
 232                     MemoryRegion *address_space_io,
 233                     ram_addr_t ram_size,
 234                     ram_addr_t below_4g_mem_size,
 235                     ram_addr_t above_4g_mem_size,
 236                     MemoryRegion *pci_memory,
 237                     MemoryRegion *ram_memory);
 238
 239 PCIBus *find_i440fx(void);
 240 /* piix4.c */
 241 extern PCIDevice *piix4_dev;
 242 int piix4_init(PCIBus *bus, ISABus **isa_bus, int devfn);
 243
 244 /* vga.c */
 245 enum vga_retrace_method {
 246     VGA_RETRACE_DUMB,
 247     VGA_RETRACE_PRECISE
 248 };
 249
 250 extern enum vga_retrace_method vga_retrace_method;
 251
 252 int isa_vga_mm_init(hwaddr vram_base,
 253                     hwaddr ctrl_base, int it_shift,
 254                     MemoryRegion *address_space);
 255
 256 /* ne2000.c */
 257 static inline bool isa_ne2000_init(ISABus *bus, int base, int irq, NICInfo *nd)
 258 {
 259     DeviceState *dev;
 260     ISADevice *isadev;
 261
 262     qemu_check_nic_model(nd, "ne2k_isa");
 263
 264     isadev = isa_try_create(bus, "ne2k_isa");
 265     if (!isadev) {
 266         return false;
 267     }
 268     dev = DEVICE(isadev);
 269     qdev_prop_set_uint32(dev, "iobase", base);
 270     qdev_prop_set_uint32(dev, "irq",    irq);
 271     qdev_set_nic_properties(dev, nd);
 272     qdev_init_nofail(dev);
 273     return true;
 274 }
 275
 276 /* pc_sysfw.c */
 277 void pc_system_firmware_init(MemoryRegion *rom_memory,
 278                              bool isapc_ram_fw);
 279
 280 /* pvpanic.c */
 281 uint16_t pvpanic_port(void);
 282
 283 /* e820 types */
 284 #define E820_RAM        1
 285 #define E820_RESERVED   2
 286 #define E820_ACPI       3
 287 #define E820_NVS        4
 288 #define E820_UNUSABLE   5
 289
 290 int e820_add_entry(uint64_t, uint64_t, uint32_t);
 291 int e820_get_num_entries(void);
 292 bool e820_get_entry(int, uint32_t, uint64_t *, uint64_t *);
 293
 294 #define PC_Q35_COMPAT_2_0 \
 295         PC_COMPAT_2_0, \
 296         {\
 297             .driver   = "ICH9 LPC",\
 298             .property = "memory-hotplug-support",\
 299             .value    = "off",\
 300         }
 301
 302 #define PC_Q35_COMPAT_1_7 \
 303         PC_COMPAT_1_7, \
 304         PC_Q35_COMPAT_2_0, \
 305         {\
 306             .driver   = "hpet",\
 307             .property = HPET_INTCAP,\
 308             .value    = stringify(4),\
 309         }
 310
 311 #define PC_Q35_COMPAT_1_6 \
 312         PC_COMPAT_1_6, \
 313         PC_Q35_COMPAT_1_7
 314
 315 #define PC_Q35_COMPAT_1_5 \
 316         PC_COMPAT_1_5, \
 317         PC_Q35_COMPAT_1_6
 318
 319 #define PC_Q35_COMPAT_1_4 \
 320         PC_COMPAT_1_4, \
 321         PC_Q35_COMPAT_1_5
 322
 323 #define PC_COMPAT_2_0 \
 324         {\
 325             .driver   = "PIIX4_PM",\
 326             .property = "memory-hotplug-support",\
 327             .value    = "off",\
 328         },\
 329         {\
 330             .driver   = "apic",\
 331             .property = "version",\
 332             .value    = stringify(0x11),\
 333         },\
 334         {\
 335             .driver   = "nec-usb-xhci",\
 336             .property = "superspeed-ports-first",\
 337             .value    = "off",\
 338         },\
 339         {\
 340             .driver   = "pci-serial",\
 341             .property = "prog_if",\
 342             .value    = stringify(0),\
 343         },\
 344         {\
 345             .driver   = "pci-serial-2x",\
 346             .property = "prof_if",\
 347             .value    = stringify(0),\
 348         },\
 349         {\
 350             .driver   = "pci-serial-4x",\
 351             .property = "prog_if",\
 352             .value    = stringify(0),\
 353         }
 354
 355 #define PC_COMPAT_1_7 \
 356         PC_COMPAT_2_0, \
 357         {\
 358             .driver   = TYPE_USB_DEVICE,\
 359             .property = "msos-desc",\
 360             .value    = "no",\
 361         },\
 362         {\
 363             .driver   = "PIIX4_PM",\
 364             .property = "acpi-pci-hotplug-with-bridge-support",\
 365             .value    = "off",\
 366         }
 367
 368 #define PC_COMPAT_1_6 \
 369         PC_COMPAT_1_7, \
 370         {\
 371             .driver   = "e1000",\
 372             .property = "mitigation",\
 373             .value    = "off",\
 374         },{\
 375             .driver   = "qemu64-" TYPE_X86_CPU,\
 376             .property = "model",\
 377             .value    = stringify(2),\
 378         },{\
 379             .driver   = "qemu32-" TYPE_X86_CPU,\
 380             .property = "model",\
 381             .value    = stringify(3),\
 382         },{\
 383             .driver   = "i440FX-pcihost",\
 384             .property = "short_root_bus",\
 385             .value    = stringify(1),\
 386         },{\
 387             .driver   = "q35-pcihost",\
 388             .property = "short_root_bus",\
 389             .value    = stringify(1),\
 390         }
 391
 392 #define PC_COMPAT_1_5 \
 393         PC_COMPAT_1_6, \
 394         {\
 395             .driver   = "Conroe-" TYPE_X86_CPU,\
 396             .property = "model",\
 397             .value    = stringify(2),\
 398         },{\
 399             .driver   = "Conroe-" TYPE_X86_CPU,\
 400             .property = "level",\
 401             .value    = stringify(2),\
 402         },{\
 403             .driver   = "Penryn-" TYPE_X86_CPU,\
 404             .property = "model",\
 405             .value    = stringify(2),\
 406         },{\
 407             .driver   = "Penryn-" TYPE_X86_CPU,\
 408             .property = "level",\
 409             .value    = stringify(2),\
 410         },{\
 411             .driver   = "Nehalem-" TYPE_X86_CPU,\
 412             .property = "model",\
 413             .value    = stringify(2),\
 414         },{\
 415             .driver   = "Nehalem-" TYPE_X86_CPU,\
 416             .property = "level",\
 417             .value    = stringify(2),\
 418         },{\
 419             .driver   = "virtio-net-pci",\
 420             .property = "any_layout",\
 421             .value    = "off",\
 422         },{\
 423             .driver = TYPE_X86_CPU,\
 424             .property = "pmu",\
 425             .value = "on",\
 426         },{\
 427             .driver   = "i440FX-pcihost",\
 428             .property = "short_root_bus",\
 429             .value    = stringify(0),\
 430         },{\
 431             .driver   = "q35-pcihost",\
 432             .property = "short_root_bus",\
 433             .value    = stringify(0),\
 434         }
 435
 436 #define PC_COMPAT_1_4 \
 437         PC_COMPAT_1_5, \
 438         {\
 439             .driver   = "scsi-hd",\
 440             .property = "discard_granularity",\
 441             .value    = stringify(0),\
 442         },{\
 443             .driver   = "scsi-cd",\
 444             .property = "discard_granularity",\
 445             .value    = stringify(0),\
 446         },{\
 447             .driver   = "scsi-disk",\
 448             .property = "discard_granularity",\
 449             .value    = stringify(0),\
 450         },{\
 451             .driver   = "ide-hd",\
 452             .property = "discard_granularity",\
 453             .value    = stringify(0),\
 454         },{\
 455             .driver   = "ide-cd",\
 456             .property = "discard_granularity",\
 457             .value    = stringify(0),\
 458         },{\
 459             .driver   = "ide-drive",\
 460             .property = "discard_granularity",\
 461             .value    = stringify(0),\
 462         },{\
 463             .driver   = "virtio-blk-pci",\
 464             .property = "discard_granularity",\
 465             .value    = stringify(0),\
 466         },{\
 467             .driver   = "virtio-serial-pci",\
 468             .property = "vectors",\
 469             /* DEV_NVECTORS_UNSPECIFIED as a uint32_t string */\
 470             .value    = stringify(0xFFFFFFFF),\
 471         },{ \
 472             .driver   = "virtio-net-pci", \
 473             .property = "ctrl_guest_offloads", \
 474             .value    = "off", \
 475         },{\
 476             .driver   = "e1000",\
 477             .property = "romfile",\
 478             .value    = "pxe-e1000.rom",\
 479         },{\
 480             .driver   = "ne2k_pci",\
 481             .property = "romfile",\
 482             .value    = "pxe-ne2k_pci.rom",\
 483         },{\
 484             .driver   = "pcnet",\
 485             .property = "romfile",\
 486             .value    = "pxe-pcnet.rom",\
 487         },{\
 488             .driver   = "rtl8139",\
 489             .property = "romfile",\
 490             .value    = "pxe-rtl8139.rom",\
 491         },{\
 492             .driver   = "virtio-net-pci",\
 493             .property = "romfile",\
 494             .value    = "pxe-virtio.rom",\
 495         },{\
 496             .driver   = "486-" TYPE_X86_CPU,\
 497             .property = "model",\
 498             .value    = stringify(0),\
 499         }
 500
 501 #define PC_COMMON_MACHINE_OPTIONS \
 502     .default_boot_order = "cad"
 503
 504 #define PC_DEFAULT_MACHINE_OPTIONS \
 505     PC_COMMON_MACHINE_OPTIONS, \
 506     .hot_add_cpu = pc_hot_add_cpu, \
 507     .max_cpus = 255
 508
 509 #endif