hw/pci-host/pnv_phb4_pec.c

   1 /*
   2  * QEMU PowerPC PowerNV (POWER9) PHB4 model
   3  *
   4  * Copyright (c) 2018-2020, IBM Corporation.
   5  *
   6  * This code is licensed under the GPL version 2 or later. See the
   7  * COPYING file in the top-level directory.
   8  */
   9 #include "qemu/osdep.h"
  10 #include "qapi/error.h"
  11 #include "qemu/log.h"
  12 #include "target/ppc/cpu.h"
  13 #include "hw/ppc/fdt.h"
  14 #include "hw/pci-host/pnv_phb4_regs.h"
  15 #include "hw/pci-host/pnv_phb4.h"
  16 #include "hw/ppc/pnv_xscom.h"
  17 #include "hw/pci/pci_bridge.h"
  18 #include "hw/pci/pci_bus.h"
  19 #include "hw/ppc/pnv.h"
  20 #include "hw/qdev-properties.h"
  21 #include "sysemu/sysemu.h"
  22
  23 #include <libfdt.h>
  24
  25 #define phb_pec_error(pec, fmt, ...)                                    \
  26     qemu_log_mask(LOG_GUEST_ERROR, "phb4_pec[%d:%d]: " fmt "\n",        \
  27                   (pec)->chip_id, (pec)->index, ## __VA_ARGS__)
  28
  29
  30 static uint64_t pnv_pec_nest_xscom_read(void *opaque, hwaddr addr,
  31                                         unsigned size)
  32 {
  33     PnvPhb4PecState *pec = PNV_PHB4_PEC(opaque);
  34     uint32_t reg = addr >> 3;
  35
  36     /* TODO: add list of allowed registers and error out if not */
  37     return pec->nest_regs[reg];
  38 }
  39
  40 static void pnv_pec_nest_xscom_write(void *opaque, hwaddr addr,
  41                                      uint64_t val, unsigned size)
  42 {
  43     PnvPhb4PecState *pec = PNV_PHB4_PEC(opaque);
  44     uint32_t reg = addr >> 3;
  45
  46     switch (reg) {
  47     case PEC_NEST_PBCQ_HW_CONFIG:
  48     case PEC_NEST_DROP_PRIO_CTRL:
  49     case PEC_NEST_PBCQ_ERR_INJECT:
  50     case PEC_NEST_PCI_NEST_CLK_TRACE_CTL:
  51     case PEC_NEST_PBCQ_PMON_CTRL:
  52     case PEC_NEST_PBCQ_PBUS_ADDR_EXT:
  53     case PEC_NEST_PBCQ_PRED_VEC_TIMEOUT:
  54     case PEC_NEST_CAPP_CTRL:
  55     case PEC_NEST_PBCQ_READ_STK_OVR:
  56     case PEC_NEST_PBCQ_WRITE_STK_OVR:
  57     case PEC_NEST_PBCQ_STORE_STK_OVR:
  58     case PEC_NEST_PBCQ_RETRY_BKOFF_CTRL:
  59         pec->nest_regs[reg] = val;
  60         break;
  61     default:
  62         phb_pec_error(pec, "%s @0x%"HWADDR_PRIx"=%"PRIx64"\n", __func__,
  63                       addr, val);
  64     }
  65 }
  66
  67 static const MemoryRegionOps pnv_pec_nest_xscom_ops = {
  68     .read = pnv_pec_nest_xscom_read,
  69     .write = pnv_pec_nest_xscom_write,
  70     .valid.min_access_size = 8,
  71     .valid.max_access_size = 8,
  72     .impl.min_access_size = 8,
  73     .impl.max_access_size = 8,
  74     .endianness = DEVICE_BIG_ENDIAN,
  75 };
  76
  77 static uint64_t pnv_pec_pci_xscom_read(void *opaque, hwaddr addr,
  78                                        unsigned size)
  79 {
  80     PnvPhb4PecState *pec = PNV_PHB4_PEC(opaque);
  81     uint32_t reg = addr >> 3;
  82
  83     /* TODO: add list of allowed registers and error out if not */
  84     return pec->pci_regs[reg];
  85 }
  86
  87 static void pnv_pec_pci_xscom_write(void *opaque, hwaddr addr,
  88                                     uint64_t val, unsigned size)
  89 {
  90     PnvPhb4PecState *pec = PNV_PHB4_PEC(opaque);
  91     uint32_t reg = addr >> 3;
  92
  93     switch (reg) {
  94     case PEC_PCI_PBAIB_HW_CONFIG:
  95     case PEC_PCI_PBAIB_READ_STK_OVR:
  96         pec->pci_regs[reg] = val;
  97         break;
  98     default:
  99         phb_pec_error(pec, "%s @0x%"HWADDR_PRIx"=%"PRIx64"\n", __func__,
 100                       addr, val);
 101     }
 102 }
 103
 104 static const MemoryRegionOps pnv_pec_pci_xscom_ops = {
 105     .read = pnv_pec_pci_xscom_read,
 106     .write = pnv_pec_pci_xscom_write,
 107     .valid.min_access_size = 8,
 108     .valid.max_access_size = 8,
 109     .impl.min_access_size = 8,
 110     .impl.max_access_size = 8,
 111     .endianness = DEVICE_BIG_ENDIAN,
 112 };
 113
 114 static void pnv_pec_default_phb_realize(PnvPhb4PecState *pec,
 115                                         int stack_no,
 116                                         Error **errp)
 117 {
 118     PnvPHB *phb = PNV_PHB(qdev_new(TYPE_PNV_PHB));
 119     int phb_id = pnv_phb4_pec_get_phb_id(pec, stack_no);
 120
 121     object_property_add_child(OBJECT(pec), "phb[*]", OBJECT(phb));
 122     object_property_set_link(OBJECT(phb), "pec", OBJECT(pec),
 123                              &error_abort);
 124     object_property_set_int(OBJECT(phb), "chip-id", pec->chip_id,
 125                             &error_fatal);
 126     object_property_set_int(OBJECT(phb), "index", phb_id,
 127                             &error_fatal);
 128
 129     if (!sysbus_realize(SYS_BUS_DEVICE(phb), errp)) {
 130         return;
 131     }
 132 }
 133
 134 static void pnv_pec_realize(DeviceState *dev, Error **errp)
 135 {
 136     PnvPhb4PecState *pec = PNV_PHB4_PEC(dev);
 137     PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec);
 138     char name[64];
 139     int i;
 140
 141     if (pec->index >= PNV_CHIP_GET_CLASS(pec->chip)->num_pecs) {
 142         error_setg(errp, "invalid PEC index: %d", pec->index);
 143         return;
 144     }
 145
 146     pec->num_phbs = pecc->num_phbs[pec->index];
 147
 148     /* Create PHBs if running with defaults */
 149     if (defaults_enabled()) {
 150         for (i = 0; i < pec->num_phbs; i++) {
 151             pnv_pec_default_phb_realize(pec, i, errp);
 152         }
 153     }
 154
 155     /* Initialize the XSCOM regions for the PEC registers */
 156     snprintf(name, sizeof(name), "xscom-pec-%d.%d-nest", pec->chip_id,
 157              pec->index);
 158     pnv_xscom_region_init(&pec->nest_regs_mr, OBJECT(dev),
 159                           &pnv_pec_nest_xscom_ops, pec, name,
 160                           PHB4_PEC_NEST_REGS_COUNT);
 161
 162     snprintf(name, sizeof(name), "xscom-pec-%d.%d-pci", pec->chip_id,
 163              pec->index);
 164     pnv_xscom_region_init(&pec->pci_regs_mr, OBJECT(dev),
 165                           &pnv_pec_pci_xscom_ops, pec, name,
 166                           PHB4_PEC_PCI_REGS_COUNT);
 167 }
 168
 169 static int pnv_pec_dt_xscom(PnvXScomInterface *dev, void *fdt,
 170                             int xscom_offset)
 171 {
 172     PnvPhb4PecState *pec = PNV_PHB4_PEC(dev);
 173     PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(dev);
 174     uint32_t nbase = pecc->xscom_nest_base(pec);
 175     uint32_t pbase = pecc->xscom_pci_base(pec);
 176     int offset, i;
 177     char *name;
 178     uint32_t reg[] = {
 179         cpu_to_be32(nbase),
 180         cpu_to_be32(pecc->xscom_nest_size),
 181         cpu_to_be32(pbase),
 182         cpu_to_be32(pecc->xscom_pci_size),
 183     };
 184
 185     name = g_strdup_printf("pbcq@%x", nbase);
 186     offset = fdt_add_subnode(fdt, xscom_offset, name);
 187     _FDT(offset);
 188     g_free(name);
 189
 190     _FDT((fdt_setprop(fdt, offset, "reg", reg, sizeof(reg))));
 191
 192     _FDT((fdt_setprop_cell(fdt, offset, "ibm,pec-index", pec->index)));
 193     _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 1)));
 194     _FDT((fdt_setprop_cell(fdt, offset, "#size-cells", 0)));
 195     _FDT((fdt_setprop(fdt, offset, "compatible", pecc->compat,
 196                       pecc->compat_size)));
 197
 198     for (i = 0; i < pec->num_phbs; i++) {
 199         int phb_id = pnv_phb4_pec_get_phb_id(pec, i);
 200         int stk_offset;
 201
 202         name = g_strdup_printf("stack@%x", i);
 203         stk_offset = fdt_add_subnode(fdt, offset, name);
 204         _FDT(stk_offset);
 205         g_free(name);
 206         _FDT((fdt_setprop(fdt, stk_offset, "compatible", pecc->stk_compat,
 207                           pecc->stk_compat_size)));
 208         _FDT((fdt_setprop_cell(fdt, stk_offset, "reg", i)));
 209         _FDT((fdt_setprop_cell(fdt, stk_offset, "ibm,phb-index", phb_id)));
 210     }
 211
 212     return 0;
 213 }
 214
 215 static Property pnv_pec_properties[] = {
 216     DEFINE_PROP_UINT32("index", PnvPhb4PecState, index, 0),
 217     DEFINE_PROP_UINT32("chip-id", PnvPhb4PecState, chip_id, 0),
 218     DEFINE_PROP_LINK("chip", PnvPhb4PecState, chip, TYPE_PNV_CHIP,
 219                      PnvChip *),
 220     DEFINE_PROP_END_OF_LIST(),
 221 };
 222
 223 static uint32_t pnv_pec_xscom_pci_base(PnvPhb4PecState *pec)
 224 {
 225     return PNV9_XSCOM_PEC_PCI_BASE + 0x1000000 * pec->index;
 226 }
 227
 228 static uint32_t pnv_pec_xscom_nest_base(PnvPhb4PecState *pec)
 229 {
 230     return PNV9_XSCOM_PEC_NEST_BASE + 0x400 * pec->index;
 231 }
 232
 233 /*
 234  * PEC0 -> 1 phb
 235  * PEC1 -> 2 phb
 236  * PEC2 -> 3 phbs
 237  */
 238 static const uint32_t pnv_pec_num_phbs[] = { 1, 2, 3 };
 239
 240 static void pnv_pec_class_init(ObjectClass *klass, void *data)
 241 {
 242     DeviceClass *dc = DEVICE_CLASS(klass);
 243     PnvXScomInterfaceClass *xdc = PNV_XSCOM_INTERFACE_CLASS(klass);
 244     PnvPhb4PecClass *pecc = PNV_PHB4_PEC_CLASS(klass);
 245     static const char compat[] = "ibm,power9-pbcq";
 246     static const char stk_compat[] = "ibm,power9-phb-stack";
 247
 248     xdc->dt_xscom = pnv_pec_dt_xscom;
 249
 250     dc->realize = pnv_pec_realize;
 251     device_class_set_props(dc, pnv_pec_properties);
 252     dc->user_creatable = false;
 253
 254     pecc->xscom_nest_base = pnv_pec_xscom_nest_base;
 255     pecc->xscom_pci_base  = pnv_pec_xscom_pci_base;
 256     pecc->xscom_nest_size = PNV9_XSCOM_PEC_NEST_SIZE;
 257     pecc->xscom_pci_size  = PNV9_XSCOM_PEC_PCI_SIZE;
 258     pecc->compat = compat;
 259     pecc->compat_size = sizeof(compat);
 260     pecc->stk_compat = stk_compat;
 261     pecc->stk_compat_size = sizeof(stk_compat);
 262     pecc->version = PNV_PHB4_VERSION;
 263     pecc->phb_type = TYPE_PNV_PHB4;
 264     pecc->num_phbs = pnv_pec_num_phbs;
 265 }
 266
 267 static const TypeInfo pnv_pec_type_info = {
 268     .name          = TYPE_PNV_PHB4_PEC,
 269     .parent        = TYPE_DEVICE,
 270     .instance_size = sizeof(PnvPhb4PecState),
 271     .class_init    = pnv_pec_class_init,
 272     .class_size    = sizeof(PnvPhb4PecClass),
 273     .interfaces    = (InterfaceInfo[]) {
 274         { TYPE_PNV_XSCOM_INTERFACE },
 275         { }
 276     }
 277 };
 278
 279 /*
 280  * POWER10 definitions
 281  */
 282
 283 static uint32_t pnv_phb5_pec_xscom_pci_base(PnvPhb4PecState *pec)
 284 {
 285     return PNV10_XSCOM_PEC_PCI_BASE + 0x1000000 * pec->index;
 286 }
 287
 288 static uint32_t pnv_phb5_pec_xscom_nest_base(PnvPhb4PecState *pec)
 289 {
 290     /* index goes down ... */
 291     return PNV10_XSCOM_PEC_NEST_BASE - 0x1000000 * pec->index;
 292 }
 293
 294 /*
 295  * PEC0 -> 3 stacks
 296  * PEC1 -> 3 stacks
 297  */
 298 static const uint32_t pnv_phb5_pec_num_stacks[] = { 3, 3 };
 299
 300 static void pnv_phb5_pec_class_init(ObjectClass *klass, void *data)
 301 {
 302     PnvPhb4PecClass *pecc = PNV_PHB4_PEC_CLASS(klass);
 303     static const char compat[] = "ibm,power10-pbcq";
 304     static const char stk_compat[] = "ibm,power10-phb-stack";
 305
 306     pecc->xscom_nest_base = pnv_phb5_pec_xscom_nest_base;
 307     pecc->xscom_pci_base  = pnv_phb5_pec_xscom_pci_base;
 308     pecc->xscom_nest_size = PNV10_XSCOM_PEC_NEST_SIZE;
 309     pecc->xscom_pci_size  = PNV10_XSCOM_PEC_PCI_SIZE;
 310     pecc->compat = compat;
 311     pecc->compat_size = sizeof(compat);
 312     pecc->stk_compat = stk_compat;
 313     pecc->stk_compat_size = sizeof(stk_compat);
 314     pecc->version = PNV_PHB5_VERSION;
 315     pecc->phb_type = TYPE_PNV_PHB5;
 316     pecc->num_phbs = pnv_phb5_pec_num_stacks;
 317 }
 318
 319 static const TypeInfo pnv_phb5_pec_type_info = {
 320     .name          = TYPE_PNV_PHB5_PEC,
 321     .parent        = TYPE_PNV_PHB4_PEC,
 322     .instance_size = sizeof(PnvPhb4PecState),
 323     .class_init    = pnv_phb5_pec_class_init,
 324     .class_size    = sizeof(PnvPhb4PecClass),
 325     .interfaces    = (InterfaceInfo[]) {
 326         { TYPE_PNV_XSCOM_INTERFACE },
 327         { }
 328     }
 329 };
 330
 331 static void pnv_pec_register_types(void)
 332 {
 333     type_register_static(&pnv_pec_type_info);
 334     type_register_static(&pnv_phb5_pec_type_info);
 335 }
 336
 337 type_init(pnv_pec_register_types);