hw/pci-host/pnv_phb4_pec.c

   1 /*
   2  * QEMU PowerPC PowerNV (POWER9) PHB4 model
   3  *
   4  * Copyright (c) 2018-2020, IBM Corporation.
   5  *
   6  * This code is licensed under the GPL version 2 or later. See the
   7  * COPYING file in the top-level directory.
   8  */
   9 #include "qemu/osdep.h"
  10 #include "qapi/error.h"
  11 #include "qemu/log.h"
  12 #include "target/ppc/cpu.h"
  13 #include "hw/ppc/fdt.h"
  14 #include "hw/pci-host/pnv_phb4_regs.h"
  15 #include "hw/pci-host/pnv_phb4.h"
  16 #include "hw/ppc/pnv_xscom.h"
  17 #include "hw/pci/pci_bridge.h"
  18 #include "hw/pci/pci_bus.h"
  19 #include "hw/ppc/pnv.h"
  20 #include "hw/ppc/pnv_chip.h"
  21 #include "hw/qdev-properties.h"
  22 #include "sysemu/sysemu.h"
  23
  24 #include <libfdt.h>
  25
  26 #define phb_pec_error(pec, fmt, ...)                                    \
  27     qemu_log_mask(LOG_GUEST_ERROR, "phb4_pec[%d:%d]: " fmt "\n",        \
  28                   (pec)->chip_id, (pec)->index, ## __VA_ARGS__)
  29
  30
  31 static uint64_t pnv_pec_nest_xscom_read(void *opaque, hwaddr addr,
  32                                         unsigned size)
  33 {
  34     PnvPhb4PecState *pec = PNV_PHB4_PEC(opaque);
  35     uint32_t reg = addr >> 3;
  36
  37     /* TODO: add list of allowed registers and error out if not */
  38     return pec->nest_regs[reg];
  39 }
  40
  41 static void pnv_pec_nest_xscom_write(void *opaque, hwaddr addr,
  42                                      uint64_t val, unsigned size)
  43 {
  44     PnvPhb4PecState *pec = PNV_PHB4_PEC(opaque);
  45     uint32_t reg = addr >> 3;
  46
  47     switch (reg) {
  48     case PEC_NEST_PBCQ_HW_CONFIG:
  49     case PEC_NEST_DROP_PRIO_CTRL:
  50     case PEC_NEST_PBCQ_ERR_INJECT:
  51     case PEC_NEST_PCI_NEST_CLK_TRACE_CTL:
  52     case PEC_NEST_PBCQ_PMON_CTRL:
  53     case PEC_NEST_PBCQ_PBUS_ADDR_EXT:
  54     case PEC_NEST_PBCQ_PRED_VEC_TIMEOUT:
  55     case PEC_NEST_CAPP_CTRL:
  56     case PEC_NEST_PBCQ_READ_STK_OVR:
  57     case PEC_NEST_PBCQ_WRITE_STK_OVR:
  58     case PEC_NEST_PBCQ_STORE_STK_OVR:
  59     case PEC_NEST_PBCQ_RETRY_BKOFF_CTRL:
  60         pec->nest_regs[reg] = val;
  61         break;
  62     default:
  63         phb_pec_error(pec, "%s @0x%"HWADDR_PRIx"=%"PRIx64"\n", __func__,
  64                       addr, val);
  65     }
  66 }
  67
  68 static const MemoryRegionOps pnv_pec_nest_xscom_ops = {
  69     .read = pnv_pec_nest_xscom_read,
  70     .write = pnv_pec_nest_xscom_write,
  71     .valid.min_access_size = 8,
  72     .valid.max_access_size = 8,
  73     .impl.min_access_size = 8,
  74     .impl.max_access_size = 8,
  75     .endianness = DEVICE_BIG_ENDIAN,
  76 };
  77
  78 static uint64_t pnv_pec_pci_xscom_read(void *opaque, hwaddr addr,
  79                                        unsigned size)
  80 {
  81     PnvPhb4PecState *pec = PNV_PHB4_PEC(opaque);
  82     uint32_t reg = addr >> 3;
  83
  84     /* TODO: add list of allowed registers and error out if not */
  85     return pec->pci_regs[reg];
  86 }
  87
  88 static void pnv_pec_pci_xscom_write(void *opaque, hwaddr addr,
  89                                     uint64_t val, unsigned size)
  90 {
  91     PnvPhb4PecState *pec = PNV_PHB4_PEC(opaque);
  92     uint32_t reg = addr >> 3;
  93
  94     switch (reg) {
  95     case PEC_PCI_PBAIB_HW_CONFIG:
  96     case PEC_PCI_PBAIB_READ_STK_OVR:
  97         pec->pci_regs[reg] = val;
  98         break;
  99     default:
 100         phb_pec_error(pec, "%s @0x%"HWADDR_PRIx"=%"PRIx64"\n", __func__,
 101                       addr, val);
 102     }
 103 }
 104
 105 static const MemoryRegionOps pnv_pec_pci_xscom_ops = {
 106     .read = pnv_pec_pci_xscom_read,
 107     .write = pnv_pec_pci_xscom_write,
 108     .valid.min_access_size = 8,
 109     .valid.max_access_size = 8,
 110     .impl.min_access_size = 8,
 111     .impl.max_access_size = 8,
 112     .endianness = DEVICE_BIG_ENDIAN,
 113 };
 114
 115 static void pnv_pec_default_phb_realize(PnvPhb4PecState *pec,
 116                                         int stack_no,
 117                                         Error **errp)
 118 {
 119     PnvPHB *phb = PNV_PHB(qdev_new(TYPE_PNV_PHB));
 120     int phb_id = pnv_phb4_pec_get_phb_id(pec, stack_no);
 121
 122     object_property_add_child(OBJECT(pec), "phb[*]", OBJECT(phb));
 123     object_property_set_link(OBJECT(phb), "pec", OBJECT(pec),
 124                              &error_abort);
 125     object_property_set_int(OBJECT(phb), "chip-id", pec->chip_id,
 126                             &error_fatal);
 127     object_property_set_int(OBJECT(phb), "index", phb_id,
 128                             &error_fatal);
 129
 130     if (!sysbus_realize(SYS_BUS_DEVICE(phb), errp)) {
 131         return;
 132     }
 133 }
 134
 135 static void pnv_pec_realize(DeviceState *dev, Error **errp)
 136 {
 137     PnvPhb4PecState *pec = PNV_PHB4_PEC(dev);
 138     PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec);
 139     char name[64];
 140     int i;
 141
 142     if (pec->index >= PNV_CHIP_GET_CLASS(pec->chip)->num_pecs) {
 143         error_setg(errp, "invalid PEC index: %d", pec->index);
 144         return;
 145     }
 146
 147     pec->num_phbs = pecc->num_phbs[pec->index];
 148
 149     /* Create PHBs if running with defaults */
 150     if (defaults_enabled()) {
 151         for (i = 0; i < pec->num_phbs; i++) {
 152             pnv_pec_default_phb_realize(pec, i, errp);
 153         }
 154     }
 155
 156     /* Initialize the XSCOM regions for the PEC registers */
 157     snprintf(name, sizeof(name), "xscom-pec-%d.%d-nest", pec->chip_id,
 158              pec->index);
 159     pnv_xscom_region_init(&pec->nest_regs_mr, OBJECT(dev),
 160                           &pnv_pec_nest_xscom_ops, pec, name,
 161                           PHB4_PEC_NEST_REGS_COUNT);
 162
 163     snprintf(name, sizeof(name), "xscom-pec-%d.%d-pci", pec->chip_id,
 164              pec->index);
 165     pnv_xscom_region_init(&pec->pci_regs_mr, OBJECT(dev),
 166                           &pnv_pec_pci_xscom_ops, pec, name,
 167                           PHB4_PEC_PCI_REGS_COUNT);
 168 }
 169
 170 static int pnv_pec_dt_xscom(PnvXScomInterface *dev, void *fdt,
 171                             int xscom_offset)
 172 {
 173     PnvPhb4PecState *pec = PNV_PHB4_PEC(dev);
 174     PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(dev);
 175     uint32_t nbase = pecc->xscom_nest_base(pec);
 176     uint32_t pbase = pecc->xscom_pci_base(pec);
 177     int offset, i;
 178     char *name;
 179     uint32_t reg[] = {
 180         cpu_to_be32(nbase),
 181         cpu_to_be32(pecc->xscom_nest_size),
 182         cpu_to_be32(pbase),
 183         cpu_to_be32(pecc->xscom_pci_size),
 184     };
 185
 186     name = g_strdup_printf("pbcq@%x", nbase);
 187     offset = fdt_add_subnode(fdt, xscom_offset, name);
 188     _FDT(offset);
 189     g_free(name);
 190
 191     _FDT((fdt_setprop(fdt, offset, "reg", reg, sizeof(reg))));
 192
 193     _FDT((fdt_setprop_cell(fdt, offset, "ibm,pec-index", pec->index)));
 194     _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 1)));
 195     _FDT((fdt_setprop_cell(fdt, offset, "#size-cells", 0)));
 196     _FDT((fdt_setprop(fdt, offset, "compatible", pecc->compat,
 197                       pecc->compat_size)));
 198
 199     for (i = 0; i < pec->num_phbs; i++) {
 200         int phb_id = pnv_phb4_pec_get_phb_id(pec, i);
 201         int stk_offset;
 202
 203         name = g_strdup_printf("stack@%x", i);
 204         stk_offset = fdt_add_subnode(fdt, offset, name);
 205         _FDT(stk_offset);
 206         g_free(name);
 207         _FDT((fdt_setprop(fdt, stk_offset, "compatible", pecc->stk_compat,
 208                           pecc->stk_compat_size)));
 209         _FDT((fdt_setprop_cell(fdt, stk_offset, "reg", i)));
 210         _FDT((fdt_setprop_cell(fdt, stk_offset, "ibm,phb-index", phb_id)));
 211     }
 212
 213     return 0;
 214 }
 215
 216 static Property pnv_pec_properties[] = {
 217     DEFINE_PROP_UINT32("index", PnvPhb4PecState, index, 0),
 218     DEFINE_PROP_UINT32("chip-id", PnvPhb4PecState, chip_id, 0),
 219     DEFINE_PROP_LINK("chip", PnvPhb4PecState, chip, TYPE_PNV_CHIP,
 220                      PnvChip *),
 221     DEFINE_PROP_END_OF_LIST(),
 222 };
 223
 224 static uint32_t pnv_pec_xscom_pci_base(PnvPhb4PecState *pec)
 225 {
 226     return PNV9_XSCOM_PEC_PCI_BASE + 0x1000000 * pec->index;
 227 }
 228
 229 static uint32_t pnv_pec_xscom_nest_base(PnvPhb4PecState *pec)
 230 {
 231     return PNV9_XSCOM_PEC_NEST_BASE + 0x400 * pec->index;
 232 }
 233
 234 /*
 235  * PEC0 -> 1 phb
 236  * PEC1 -> 2 phb
 237  * PEC2 -> 3 phbs
 238  */
 239 static const uint32_t pnv_pec_num_phbs[] = { 1, 2, 3 };
 240
 241 static void pnv_pec_class_init(ObjectClass *klass, void *data)
 242 {
 243     DeviceClass *dc = DEVICE_CLASS(klass);
 244     PnvXScomInterfaceClass *xdc = PNV_XSCOM_INTERFACE_CLASS(klass);
 245     PnvPhb4PecClass *pecc = PNV_PHB4_PEC_CLASS(klass);
 246     static const char compat[] = "ibm,power9-pbcq";
 247     static const char stk_compat[] = "ibm,power9-phb-stack";
 248
 249     xdc->dt_xscom = pnv_pec_dt_xscom;
 250
 251     dc->realize = pnv_pec_realize;
 252     device_class_set_props(dc, pnv_pec_properties);
 253     dc->user_creatable = false;
 254
 255     pecc->xscom_nest_base = pnv_pec_xscom_nest_base;
 256     pecc->xscom_pci_base  = pnv_pec_xscom_pci_base;
 257     pecc->xscom_nest_size = PNV9_XSCOM_PEC_NEST_SIZE;
 258     pecc->xscom_pci_size  = PNV9_XSCOM_PEC_PCI_SIZE;
 259     pecc->compat = compat;
 260     pecc->compat_size = sizeof(compat);
 261     pecc->stk_compat = stk_compat;
 262     pecc->stk_compat_size = sizeof(stk_compat);
 263     pecc->version = PNV_PHB4_VERSION;
 264     pecc->phb_type = TYPE_PNV_PHB4;
 265     pecc->num_phbs = pnv_pec_num_phbs;
 266 }
 267
 268 static const TypeInfo pnv_pec_type_info = {
 269     .name          = TYPE_PNV_PHB4_PEC,
 270     .parent        = TYPE_DEVICE,
 271     .instance_size = sizeof(PnvPhb4PecState),
 272     .class_init    = pnv_pec_class_init,
 273     .class_size    = sizeof(PnvPhb4PecClass),
 274     .interfaces    = (InterfaceInfo[]) {
 275         { TYPE_PNV_XSCOM_INTERFACE },
 276         { }
 277     }
 278 };
 279
 280 /*
 281  * POWER10 definitions
 282  */
 283
 284 static uint32_t pnv_phb5_pec_xscom_pci_base(PnvPhb4PecState *pec)
 285 {
 286     return PNV10_XSCOM_PEC_PCI_BASE + 0x1000000 * pec->index;
 287 }
 288
 289 static uint32_t pnv_phb5_pec_xscom_nest_base(PnvPhb4PecState *pec)
 290 {
 291     /* index goes down ... */
 292     return PNV10_XSCOM_PEC_NEST_BASE - 0x1000000 * pec->index;
 293 }
 294
 295 /*
 296  * PEC0 -> 3 stacks
 297  * PEC1 -> 3 stacks
 298  */
 299 static const uint32_t pnv_phb5_pec_num_stacks[] = { 3, 3 };
 300
 301 static void pnv_phb5_pec_class_init(ObjectClass *klass, void *data)
 302 {
 303     PnvPhb4PecClass *pecc = PNV_PHB4_PEC_CLASS(klass);
 304     static const char compat[] = "ibm,power10-pbcq";
 305     static const char stk_compat[] = "ibm,power10-phb-stack";
 306
 307     pecc->xscom_nest_base = pnv_phb5_pec_xscom_nest_base;
 308     pecc->xscom_pci_base  = pnv_phb5_pec_xscom_pci_base;
 309     pecc->xscom_nest_size = PNV10_XSCOM_PEC_NEST_SIZE;
 310     pecc->xscom_pci_size  = PNV10_XSCOM_PEC_PCI_SIZE;
 311     pecc->compat = compat;
 312     pecc->compat_size = sizeof(compat);
 313     pecc->stk_compat = stk_compat;
 314     pecc->stk_compat_size = sizeof(stk_compat);
 315     pecc->version = PNV_PHB5_VERSION;
 316     pecc->phb_type = TYPE_PNV_PHB5;
 317     pecc->num_phbs = pnv_phb5_pec_num_stacks;
 318 }
 319
 320 static const TypeInfo pnv_phb5_pec_type_info = {
 321     .name          = TYPE_PNV_PHB5_PEC,
 322     .parent        = TYPE_PNV_PHB4_PEC,
 323     .instance_size = sizeof(PnvPhb4PecState),
 324     .class_init    = pnv_phb5_pec_class_init,
 325     .class_size    = sizeof(PnvPhb4PecClass),
 326     .interfaces    = (InterfaceInfo[]) {
 327         { TYPE_PNV_XSCOM_INTERFACE },
 328         { }
 329     }
 330 };
 331
 332 static void pnv_pec_register_types(void)
 333 {
 334     type_register_static(&pnv_pec_type_info);
 335     type_register_static(&pnv_phb5_pec_type_info);
 336 }
 337
 338 type_init(pnv_pec_register_types);