target/ppc/machine.c

   1 #include "qemu/osdep.h"
   2 #include "cpu.h"
   3 #include "exec/exec-all.h"
   4 #include "sysemu/kvm.h"
   5 #include "helper_regs.h"
   6 #include "mmu-hash64.h"
   7 #include "migration/cpu.h"
   8 #include "qapi/error.h"
   9 #include "qemu/main-loop.h"
  10 #include "kvm_ppc.h"
  11 #include "power8-pmu.h"
  12
  13 static void post_load_update_msr(CPUPPCState *env)
  14 {
  15     target_ulong msr = env->msr;
  16
  17     /*
  18      * Invalidate all supported msr bits except MSR_TGPR/MSR_HVB
  19      * before restoring.  Note that this recomputes hflags.
  20      */
  21     env->msr ^= env->msr_mask & ~((1ULL << MSR_TGPR) | MSR_HVB);
  22     ppc_store_msr(env, msr);
  23     pmu_update_summaries(env);
  24 }
  25
  26 static int cpu_load_old(QEMUFile *f, void *opaque, int version_id)
  27 {
  28     PowerPCCPU *cpu = opaque;
  29     CPUPPCState *env = &cpu->env;
  30     unsigned int i, j;
  31     target_ulong sdr1;
  32     uint32_t fpscr, vscr;
  33 #if defined(TARGET_PPC64)
  34     int32_t slb_nr;
  35 #endif
  36     target_ulong xer;
  37
  38     for (i = 0; i < 32; i++) {
  39         qemu_get_betls(f, &env->gpr[i]);
  40     }
  41 #if !defined(TARGET_PPC64)
  42     for (i = 0; i < 32; i++) {
  43         qemu_get_betls(f, &env->gprh[i]);
  44     }
  45 #endif
  46     qemu_get_betls(f, &env->lr);
  47     qemu_get_betls(f, &env->ctr);
  48     for (i = 0; i < 8; i++) {
  49         qemu_get_be32s(f, &env->crf[i]);
  50     }
  51     qemu_get_betls(f, &xer);
  52     cpu_write_xer(env, xer);
  53     qemu_get_betls(f, &env->reserve_addr);
  54     qemu_get_betls(f, &env->msr);
  55     for (i = 0; i < 4; i++) {
  56         qemu_get_betls(f, &env->tgpr[i]);
  57     }
  58     for (i = 0; i < 32; i++) {
  59         union {
  60             float64 d;
  61             uint64_t l;
  62         } u;
  63         u.l = qemu_get_be64(f);
  64         *cpu_fpr_ptr(env, i) = u.d;
  65     }
  66     qemu_get_be32s(f, &fpscr);
  67     env->fpscr = fpscr;
  68     qemu_get_sbe32s(f, &env->access_type);
  69 #if defined(TARGET_PPC64)
  70     qemu_get_betls(f, &env->spr[SPR_ASR]);
  71     qemu_get_sbe32s(f, &slb_nr);
  72 #endif
  73     qemu_get_betls(f, &sdr1);
  74     for (i = 0; i < 32; i++) {
  75         qemu_get_betls(f, &env->sr[i]);
  76     }
  77     for (i = 0; i < 2; i++) {
  78         for (j = 0; j < 8; j++) {
  79             qemu_get_betls(f, &env->DBAT[i][j]);
  80         }
  81     }
  82     for (i = 0; i < 2; i++) {
  83         for (j = 0; j < 8; j++) {
  84             qemu_get_betls(f, &env->IBAT[i][j]);
  85         }
  86     }
  87     qemu_get_sbe32s(f, &env->nb_tlb);
  88     qemu_get_sbe32s(f, &env->tlb_per_way);
  89     qemu_get_sbe32s(f, &env->nb_ways);
  90     qemu_get_sbe32s(f, &env->last_way);
  91     qemu_get_sbe32s(f, &env->id_tlbs);
  92     qemu_get_sbe32s(f, &env->nb_pids);
  93     if (env->tlb.tlb6) {
  94         /* XXX assumes 6xx */
  95         for (i = 0; i < env->nb_tlb; i++) {
  96             qemu_get_betls(f, &env->tlb.tlb6[i].pte0);
  97             qemu_get_betls(f, &env->tlb.tlb6[i].pte1);
  98             qemu_get_betls(f, &env->tlb.tlb6[i].EPN);
  99         }
 100     }
 101     for (i = 0; i < 4; i++) {
 102         qemu_get_betls(f, &env->pb[i]);
 103     }
 104     for (i = 0; i < 1024; i++) {
 105         qemu_get_betls(f, &env->spr[i]);
 106     }
 107     if (!cpu->vhyp) {
 108         ppc_store_sdr1(env, sdr1);
 109     }
 110     qemu_get_be32s(f, &vscr);
 111     ppc_store_vscr(env, vscr);
 112     qemu_get_be64s(f, &env->spe_acc);
 113     qemu_get_be32s(f, &env->spe_fscr);
 114     qemu_get_betls(f, &env->msr_mask);
 115     qemu_get_be32s(f, &env->flags);
 116     qemu_get_sbe32s(f, &env->error_code);
 117     qemu_get_be32s(f, &env->pending_interrupts);
 118     qemu_get_be32s(f, &env->irq_input_state);
 119     for (i = 0; i < POWERPC_EXCP_NB; i++) {
 120         qemu_get_betls(f, &env->excp_vectors[i]);
 121     }
 122     qemu_get_betls(f, &env->excp_prefix);
 123     qemu_get_betls(f, &env->ivor_mask);
 124     qemu_get_betls(f, &env->ivpr_mask);
 125     qemu_get_betls(f, &env->hreset_vector);
 126     qemu_get_betls(f, &env->nip);
 127     qemu_get_sbetl(f); /* Discard unused hflags */
 128     qemu_get_sbetl(f); /* Discard unused hflags_nmsr */
 129     qemu_get_sbe32(f); /* Discard unused mmu_idx */
 130     qemu_get_sbe32(f); /* Discard unused power_mode */
 131
 132     post_load_update_msr(env);
 133
 134     return 0;
 135 }
 136
 137 static int get_avr(QEMUFile *f, void *pv, size_t size,
 138                    const VMStateField *field)
 139 {
 140     ppc_avr_t *v = pv;
 141
 142     v->u64[0] = qemu_get_be64(f);
 143     v->u64[1] = qemu_get_be64(f);
 144
 145     return 0;
 146 }
 147
 148 static int put_avr(QEMUFile *f, void *pv, size_t size,
 149                    const VMStateField *field, JSONWriter *vmdesc)
 150 {
 151     ppc_avr_t *v = pv;
 152
 153     qemu_put_be64(f, v->u64[0]);
 154     qemu_put_be64(f, v->u64[1]);
 155     return 0;
 156 }
 157
 158 static const VMStateInfo vmstate_info_avr = {
 159     .name = "avr",
 160     .get  = get_avr,
 161     .put  = put_avr,
 162 };
 163
 164 #define VMSTATE_AVR_ARRAY_V(_f, _s, _n, _v)                       \
 165     VMSTATE_SUB_ARRAY(_f, _s, 32, _n, _v, vmstate_info_avr, ppc_avr_t)
 166
 167 #define VMSTATE_AVR_ARRAY(_f, _s, _n)                             \
 168     VMSTATE_AVR_ARRAY_V(_f, _s, _n, 0)
 169
 170 static int get_fpr(QEMUFile *f, void *pv, size_t size,
 171                    const VMStateField *field)
 172 {
 173     ppc_vsr_t *v = pv;
 174
 175     v->VsrD(0) = qemu_get_be64(f);
 176
 177     return 0;
 178 }
 179
 180 static int put_fpr(QEMUFile *f, void *pv, size_t size,
 181                    const VMStateField *field, JSONWriter *vmdesc)
 182 {
 183     ppc_vsr_t *v = pv;
 184
 185     qemu_put_be64(f, v->VsrD(0));
 186     return 0;
 187 }
 188
 189 static const VMStateInfo vmstate_info_fpr = {
 190     .name = "fpr",
 191     .get  = get_fpr,
 192     .put  = put_fpr,
 193 };
 194
 195 #define VMSTATE_FPR_ARRAY_V(_f, _s, _n, _v)                       \
 196     VMSTATE_SUB_ARRAY(_f, _s, 0, _n, _v, vmstate_info_fpr, ppc_vsr_t)
 197
 198 #define VMSTATE_FPR_ARRAY(_f, _s, _n)                             \
 199     VMSTATE_FPR_ARRAY_V(_f, _s, _n, 0)
 200
 201 static int get_vsr(QEMUFile *f, void *pv, size_t size,
 202                    const VMStateField *field)
 203 {
 204     ppc_vsr_t *v = pv;
 205
 206     v->VsrD(1) = qemu_get_be64(f);
 207
 208     return 0;
 209 }
 210
 211 static int put_vsr(QEMUFile *f, void *pv, size_t size,
 212                    const VMStateField *field, JSONWriter *vmdesc)
 213 {
 214     ppc_vsr_t *v = pv;
 215
 216     qemu_put_be64(f, v->VsrD(1));
 217     return 0;
 218 }
 219
 220 static const VMStateInfo vmstate_info_vsr = {
 221     .name = "vsr",
 222     .get  = get_vsr,
 223     .put  = put_vsr,
 224 };
 225
 226 #define VMSTATE_VSR_ARRAY_V(_f, _s, _n, _v)                       \
 227     VMSTATE_SUB_ARRAY(_f, _s, 0, _n, _v, vmstate_info_vsr, ppc_vsr_t)
 228
 229 #define VMSTATE_VSR_ARRAY(_f, _s, _n)                             \
 230     VMSTATE_VSR_ARRAY_V(_f, _s, _n, 0)
 231
 232 static bool cpu_pre_2_8_migration(void *opaque, int version_id)
 233 {
 234     PowerPCCPU *cpu = opaque;
 235
 236     return cpu->pre_2_8_migration;
 237 }
 238
 239 #if defined(TARGET_PPC64)
 240 static bool cpu_pre_3_0_migration(void *opaque, int version_id)
 241 {
 242     PowerPCCPU *cpu = opaque;
 243
 244     return cpu->pre_3_0_migration;
 245 }
 246 #endif
 247
 248 static int cpu_pre_save(void *opaque)
 249 {
 250     PowerPCCPU *cpu = opaque;
 251     CPUPPCState *env = &cpu->env;
 252     int i;
 253     uint64_t insns_compat_mask =
 254         PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB
 255         | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES
 256         | PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | PPC_FLOAT_FRSQRTES
 257         | PPC_FLOAT_STFIWX | PPC_FLOAT_EXT
 258         | PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ
 259         | PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC
 260         | PPC_64B | PPC_64BX | PPC_ALTIVEC
 261         | PPC_SEGMENT_64B | PPC_SLBI | PPC_POPCNTB | PPC_POPCNTWD;
 262     uint64_t insns_compat_mask2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX
 263         | PPC2_PERM_ISA206 | PPC2_DIVE_ISA206
 264         | PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206
 265         | PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207
 266         | PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207
 267         | PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | PPC2_TM;
 268
 269     env->spr[SPR_LR] = env->lr;
 270     env->spr[SPR_CTR] = env->ctr;
 271     env->spr[SPR_XER] = cpu_read_xer(env);
 272 #if defined(TARGET_PPC64)
 273     env->spr[SPR_CFAR] = env->cfar;
 274 #endif
 275     env->spr[SPR_BOOKE_SPEFSCR] = env->spe_fscr;
 276
 277     for (i = 0; (i < 4) && (i < env->nb_BATs); i++) {
 278         env->spr[SPR_DBAT0U + 2 * i] = env->DBAT[0][i];
 279         env->spr[SPR_DBAT0U + 2 * i + 1] = env->DBAT[1][i];
 280         env->spr[SPR_IBAT0U + 2 * i] = env->IBAT[0][i];
 281         env->spr[SPR_IBAT0U + 2 * i + 1] = env->IBAT[1][i];
 282     }
 283     for (i = 0; (i < 4) && ((i + 4) < env->nb_BATs); i++) {
 284         env->spr[SPR_DBAT4U + 2 * i] = env->DBAT[0][i + 4];
 285         env->spr[SPR_DBAT4U + 2 * i + 1] = env->DBAT[1][i + 4];
 286         env->spr[SPR_IBAT4U + 2 * i] = env->IBAT[0][i + 4];
 287         env->spr[SPR_IBAT4U + 2 * i + 1] = env->IBAT[1][i + 4];
 288     }
 289
 290     /* Hacks for migration compatibility between 2.6, 2.7 & 2.8 */
 291     if (cpu->pre_2_8_migration) {
 292         /*
 293          * Mask out bits that got added to msr_mask since the versions
 294          * which stupidly included it in the migration stream.
 295          */
 296         target_ulong metamask = 0
 297 #if defined(TARGET_PPC64)
 298             | (1ULL << MSR_TS0)
 299             | (1ULL << MSR_TS1)
 300 #endif
 301             ;
 302         cpu->mig_msr_mask = env->msr_mask & ~metamask;
 303         cpu->mig_insns_flags = env->insns_flags & insns_compat_mask;
 304         /*
 305          * CPU models supported by old machines all have
 306          * PPC_MEM_TLBIE, so we set it unconditionally to allow
 307          * backward migration from a POWER9 host to a POWER8 host.
 308          */
 309         cpu->mig_insns_flags |= PPC_MEM_TLBIE;
 310         cpu->mig_insns_flags2 = env->insns_flags2 & insns_compat_mask2;
 311         cpu->mig_nb_BATs = env->nb_BATs;
 312     }
 313     if (cpu->pre_3_0_migration) {
 314         if (cpu->hash64_opts) {
 315             cpu->mig_slb_nr = cpu->hash64_opts->slb_size;
 316         }
 317     }
 318
 319     /* Retain migration compatibility for pre 6.0 for 601 machines. */
 320     env->hflags_compat_nmsr = (env->flags & POWERPC_FLAG_HID0_LE
 321                                ? env->hflags & MSR_LE : 0);
 322
 323     return 0;
 324 }
 325
 326 /*
 327  * Determine if a given PVR is a "close enough" match to the CPU
 328  * object.  For TCG and KVM PR it would probably be sufficient to
 329  * require an exact PVR match.  However for KVM HV the user is
 330  * restricted to a PVR exactly matching the host CPU.  The correct way
 331  * to handle this is to put the guest into an architected
 332  * compatibility mode.  However, to allow a more forgiving transition
 333  * and migration from before this was widely done, we allow migration
 334  * between sufficiently similar PVRs, as determined by the CPU class's
 335  * pvr_match() hook.
 336  */
 337 static bool pvr_match(PowerPCCPU *cpu, uint32_t pvr)
 338 {
 339     PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
 340
 341     if (pvr == pcc->pvr) {
 342         return true;
 343     }
 344     return pcc->pvr_match(pcc, pvr);
 345 }
 346
 347 static int cpu_post_load(void *opaque, int version_id)
 348 {
 349     PowerPCCPU *cpu = opaque;
 350     CPUPPCState *env = &cpu->env;
 351     int i;
 352
 353     /*
 354      * If we're operating in compat mode, we should be ok as long as
 355      * the destination supports the same compatibility mode.
 356      *
 357      * Otherwise, however, we require that the destination has exactly
 358      * the same CPU model as the source.
 359      */
 360
 361 #if defined(TARGET_PPC64)
 362     if (cpu->compat_pvr) {
 363         uint32_t compat_pvr = cpu->compat_pvr;
 364         Error *local_err = NULL;
 365         int ret;
 366
 367         cpu->compat_pvr = 0;
 368         ret = ppc_set_compat(cpu, compat_pvr, &local_err);
 369         if (ret < 0) {
 370             error_report_err(local_err);
 371             return ret;
 372         }
 373     } else
 374 #endif
 375     {
 376         if (!pvr_match(cpu, env->spr[SPR_PVR])) {
 377             return -EINVAL;
 378         }
 379     }
 380
 381     /*
 382      * If we're running with KVM HV, there is a chance that the guest
 383      * is running with KVM HV and its kernel does not have the
 384      * capability of dealing with a different PVR other than this
 385      * exact host PVR in KVM_SET_SREGS. If that happens, the
 386      * guest freezes after migration.
 387      *
 388      * The function kvmppc_pvr_workaround_required does this verification
 389      * by first checking if the kernel has the cap, returning true immediately
 390      * if that is the case. Otherwise, it checks if we're running in KVM PR.
 391      * If the guest kernel does not have the cap and we're not running KVM-PR
 392      * (so, it is running KVM-HV), we need to ensure that KVM_SET_SREGS will
 393      * receive the PVR it expects as a workaround.
 394      *
 395      */
 396     if (kvmppc_pvr_workaround_required(cpu)) {
 397         env->spr[SPR_PVR] = env->spr_cb[SPR_PVR].default_value;
 398     }
 399
 400     env->lr = env->spr[SPR_LR];
 401     env->ctr = env->spr[SPR_CTR];
 402     cpu_write_xer(env, env->spr[SPR_XER]);
 403 #if defined(TARGET_PPC64)
 404     env->cfar = env->spr[SPR_CFAR];
 405 #endif
 406     env->spe_fscr = env->spr[SPR_BOOKE_SPEFSCR];
 407
 408     for (i = 0; (i < 4) && (i < env->nb_BATs); i++) {
 409         env->DBAT[0][i] = env->spr[SPR_DBAT0U + 2 * i];
 410         env->DBAT[1][i] = env->spr[SPR_DBAT0U + 2 * i + 1];
 411         env->IBAT[0][i] = env->spr[SPR_IBAT0U + 2 * i];
 412         env->IBAT[1][i] = env->spr[SPR_IBAT0U + 2 * i + 1];
 413     }
 414     for (i = 0; (i < 4) && ((i + 4) < env->nb_BATs); i++) {
 415         env->DBAT[0][i + 4] = env->spr[SPR_DBAT4U + 2 * i];
 416         env->DBAT[1][i + 4] = env->spr[SPR_DBAT4U + 2 * i + 1];
 417         env->IBAT[0][i + 4] = env->spr[SPR_IBAT4U + 2 * i];
 418         env->IBAT[1][i + 4] = env->spr[SPR_IBAT4U + 2 * i + 1];
 419     }
 420
 421     if (!cpu->vhyp) {
 422         ppc_store_sdr1(env, env->spr[SPR_SDR1]);
 423     }
 424
 425     post_load_update_msr(env);
 426
 427     return 0;
 428 }
 429
 430 static bool fpu_needed(void *opaque)
 431 {
 432     PowerPCCPU *cpu = opaque;
 433
 434     return cpu->env.insns_flags & PPC_FLOAT;
 435 }
 436
 437 static const VMStateDescription vmstate_fpu = {
 438     .name = "cpu/fpu",
 439     .version_id = 1,
 440     .minimum_version_id = 1,
 441     .needed = fpu_needed,
 442     .fields = (VMStateField[]) {
 443         VMSTATE_FPR_ARRAY(env.vsr, PowerPCCPU, 32),
 444         VMSTATE_UINTTL(env.fpscr, PowerPCCPU),
 445         VMSTATE_END_OF_LIST()
 446     },
 447 };
 448
 449 static bool altivec_needed(void *opaque)
 450 {
 451     PowerPCCPU *cpu = opaque;
 452
 453     return cpu->env.insns_flags & PPC_ALTIVEC;
 454 }
 455
 456 static int get_vscr(QEMUFile *f, void *opaque, size_t size,
 457                     const VMStateField *field)
 458 {
 459     PowerPCCPU *cpu = opaque;
 460     ppc_store_vscr(&cpu->env, qemu_get_be32(f));
 461     return 0;
 462 }
 463
 464 static int put_vscr(QEMUFile *f, void *opaque, size_t size,
 465                     const VMStateField *field, JSONWriter *vmdesc)
 466 {
 467     PowerPCCPU *cpu = opaque;
 468     qemu_put_be32(f, ppc_get_vscr(&cpu->env));
 469     return 0;
 470 }
 471
 472 static const VMStateInfo vmstate_vscr = {
 473     .name = "cpu/altivec/vscr",
 474     .get = get_vscr,
 475     .put = put_vscr,
 476 };
 477
 478 static const VMStateDescription vmstate_altivec = {
 479     .name = "cpu/altivec",
 480     .version_id = 1,
 481     .minimum_version_id = 1,
 482     .needed = altivec_needed,
 483     .fields = (VMStateField[]) {
 484         VMSTATE_AVR_ARRAY(env.vsr, PowerPCCPU, 32),
 485         /*
 486          * Save the architecture value of the vscr, not the internally
 487          * expanded version.  Since this architecture value does not
 488          * exist in memory to be stored, this requires a but of hoop
 489          * jumping.  We want OFFSET=0 so that we effectively pass CPU
 490          * to the helper functions.
 491          */
 492         {
 493             .name = "vscr",
 494             .version_id = 0,
 495             .size = sizeof(uint32_t),
 496             .info = &vmstate_vscr,
 497             .flags = VMS_SINGLE,
 498             .offset = 0
 499         },
 500         VMSTATE_END_OF_LIST()
 501     },
 502 };
 503
 504 static bool vsx_needed(void *opaque)
 505 {
 506     PowerPCCPU *cpu = opaque;
 507
 508     return cpu->env.insns_flags2 & PPC2_VSX;
 509 }
 510
 511 static const VMStateDescription vmstate_vsx = {
 512     .name = "cpu/vsx",
 513     .version_id = 1,
 514     .minimum_version_id = 1,
 515     .needed = vsx_needed,
 516     .fields = (VMStateField[]) {
 517         VMSTATE_VSR_ARRAY(env.vsr, PowerPCCPU, 32),
 518         VMSTATE_END_OF_LIST()
 519     },
 520 };
 521
 522 #ifdef TARGET_PPC64
 523 /* Transactional memory state */
 524 static bool tm_needed(void *opaque)
 525 {
 526     PowerPCCPU *cpu = opaque;
 527     CPUPPCState *env = &cpu->env;
 528     return msr_ts;
 529 }
 530
 531 static const VMStateDescription vmstate_tm = {
 532     .name = "cpu/tm",
 533     .version_id = 1,
 534     .minimum_version_id = 1,
 535     .minimum_version_id_old = 1,
 536     .needed = tm_needed,
 537     .fields      = (VMStateField []) {
 538         VMSTATE_UINTTL_ARRAY(env.tm_gpr, PowerPCCPU, 32),
 539         VMSTATE_AVR_ARRAY(env.tm_vsr, PowerPCCPU, 64),
 540         VMSTATE_UINT64(env.tm_cr, PowerPCCPU),
 541         VMSTATE_UINT64(env.tm_lr, PowerPCCPU),
 542         VMSTATE_UINT64(env.tm_ctr, PowerPCCPU),
 543         VMSTATE_UINT64(env.tm_fpscr, PowerPCCPU),
 544         VMSTATE_UINT64(env.tm_amr, PowerPCCPU),
 545         VMSTATE_UINT64(env.tm_ppr, PowerPCCPU),
 546         VMSTATE_UINT64(env.tm_vrsave, PowerPCCPU),
 547         VMSTATE_UINT32(env.tm_vscr, PowerPCCPU),
 548         VMSTATE_UINT64(env.tm_dscr, PowerPCCPU),
 549         VMSTATE_UINT64(env.tm_tar, PowerPCCPU),
 550         VMSTATE_END_OF_LIST()
 551     },
 552 };
 553 #endif
 554
 555 static bool sr_needed(void *opaque)
 556 {
 557 #ifdef TARGET_PPC64
 558     PowerPCCPU *cpu = opaque;
 559
 560     return !mmu_is_64bit(cpu->env.mmu_model);
 561 #else
 562     return true;
 563 #endif
 564 }
 565
 566 static const VMStateDescription vmstate_sr = {
 567     .name = "cpu/sr",
 568     .version_id = 1,
 569     .minimum_version_id = 1,
 570     .needed = sr_needed,
 571     .fields = (VMStateField[]) {
 572         VMSTATE_UINTTL_ARRAY(env.sr, PowerPCCPU, 32),
 573         VMSTATE_END_OF_LIST()
 574     },
 575 };
 576
 577 #ifdef TARGET_PPC64
 578 static int get_slbe(QEMUFile *f, void *pv, size_t size,
 579                     const VMStateField *field)
 580 {
 581     ppc_slb_t *v = pv;
 582
 583     v->esid = qemu_get_be64(f);
 584     v->vsid = qemu_get_be64(f);
 585
 586     return 0;
 587 }
 588
 589 static int put_slbe(QEMUFile *f, void *pv, size_t size,
 590                     const VMStateField *field, JSONWriter *vmdesc)
 591 {
 592     ppc_slb_t *v = pv;
 593
 594     qemu_put_be64(f, v->esid);
 595     qemu_put_be64(f, v->vsid);
 596     return 0;
 597 }
 598
 599 static const VMStateInfo vmstate_info_slbe = {
 600     .name = "slbe",
 601     .get  = get_slbe,
 602     .put  = put_slbe,
 603 };
 604
 605 #define VMSTATE_SLB_ARRAY_V(_f, _s, _n, _v)                       \
 606     VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_slbe, ppc_slb_t)
 607
 608 #define VMSTATE_SLB_ARRAY(_f, _s, _n)                             \
 609     VMSTATE_SLB_ARRAY_V(_f, _s, _n, 0)
 610
 611 static bool slb_needed(void *opaque)
 612 {
 613     PowerPCCPU *cpu = opaque;
 614
 615     /* We don't support any of the old segment table based 64-bit CPUs */
 616     return mmu_is_64bit(cpu->env.mmu_model);
 617 }
 618
 619 static int slb_post_load(void *opaque, int version_id)
 620 {
 621     PowerPCCPU *cpu = opaque;
 622     CPUPPCState *env = &cpu->env;
 623     int i;
 624
 625     /*
 626      * We've pulled in the raw esid and vsid values from the migration
 627      * stream, but we need to recompute the page size pointers
 628      */
 629     for (i = 0; i < cpu->hash64_opts->slb_size; i++) {
 630         if (ppc_store_slb(cpu, i, env->slb[i].esid, env->slb[i].vsid) < 0) {
 631             /* Migration source had bad values in its SLB */
 632             return -1;
 633         }
 634     }
 635
 636     return 0;
 637 }
 638
 639 static const VMStateDescription vmstate_slb = {
 640     .name = "cpu/slb",
 641     .version_id = 1,
 642     .minimum_version_id = 1,
 643     .needed = slb_needed,
 644     .post_load = slb_post_load,
 645     .fields = (VMStateField[]) {
 646         VMSTATE_INT32_TEST(mig_slb_nr, PowerPCCPU, cpu_pre_3_0_migration),
 647         VMSTATE_SLB_ARRAY(env.slb, PowerPCCPU, MAX_SLB_ENTRIES),
 648         VMSTATE_END_OF_LIST()
 649     }
 650 };
 651 #endif /* TARGET_PPC64 */
 652
 653 static const VMStateDescription vmstate_tlb6xx_entry = {
 654     .name = "cpu/tlb6xx_entry",
 655     .version_id = 1,
 656     .minimum_version_id = 1,
 657     .fields = (VMStateField[]) {
 658         VMSTATE_UINTTL(pte0, ppc6xx_tlb_t),
 659         VMSTATE_UINTTL(pte1, ppc6xx_tlb_t),
 660         VMSTATE_UINTTL(EPN, ppc6xx_tlb_t),
 661         VMSTATE_END_OF_LIST()
 662     },
 663 };
 664
 665 static bool tlb6xx_needed(void *opaque)
 666 {
 667     PowerPCCPU *cpu = opaque;
 668     CPUPPCState *env = &cpu->env;
 669
 670     return env->nb_tlb && (env->tlb_type == TLB_6XX);
 671 }
 672
 673 static const VMStateDescription vmstate_tlb6xx = {
 674     .name = "cpu/tlb6xx",
 675     .version_id = 1,
 676     .minimum_version_id = 1,
 677     .needed = tlb6xx_needed,
 678     .fields = (VMStateField[]) {
 679         VMSTATE_INT32_EQUAL(env.nb_tlb, PowerPCCPU, NULL),
 680         VMSTATE_STRUCT_VARRAY_POINTER_INT32(env.tlb.tlb6, PowerPCCPU,
 681                                             env.nb_tlb,
 682                                             vmstate_tlb6xx_entry,
 683                                             ppc6xx_tlb_t),
 684         VMSTATE_UINTTL_ARRAY(env.tgpr, PowerPCCPU, 4),
 685         VMSTATE_END_OF_LIST()
 686     }
 687 };
 688
 689 static const VMStateDescription vmstate_tlbemb_entry = {
 690     .name = "cpu/tlbemb_entry",
 691     .version_id = 1,
 692     .minimum_version_id = 1,
 693     .fields = (VMStateField[]) {
 694         VMSTATE_UINT64(RPN, ppcemb_tlb_t),
 695         VMSTATE_UINTTL(EPN, ppcemb_tlb_t),
 696         VMSTATE_UINTTL(PID, ppcemb_tlb_t),
 697         VMSTATE_UINTTL(size, ppcemb_tlb_t),
 698         VMSTATE_UINT32(prot, ppcemb_tlb_t),
 699         VMSTATE_UINT32(attr, ppcemb_tlb_t),
 700         VMSTATE_END_OF_LIST()
 701     },
 702 };
 703
 704 static bool tlbemb_needed(void *opaque)
 705 {
 706     PowerPCCPU *cpu = opaque;
 707     CPUPPCState *env = &cpu->env;
 708
 709     return env->nb_tlb && (env->tlb_type == TLB_EMB);
 710 }
 711
 712 static bool pbr403_needed(void *opaque)
 713 {
 714     PowerPCCPU *cpu = opaque;
 715     uint32_t pvr = cpu->env.spr[SPR_PVR];
 716
 717     return (pvr & 0xffff0000) == 0x00200000;
 718 }
 719
 720 static const VMStateDescription vmstate_pbr403 = {
 721     .name = "cpu/pbr403",
 722     .version_id = 1,
 723     .minimum_version_id = 1,
 724     .needed = pbr403_needed,
 725     .fields = (VMStateField[]) {
 726         VMSTATE_UINTTL_ARRAY(env.pb, PowerPCCPU, 4),
 727         VMSTATE_END_OF_LIST()
 728     },
 729 };
 730
 731 static const VMStateDescription vmstate_tlbemb = {
 732     .name = "cpu/tlb6xx",
 733     .version_id = 1,
 734     .minimum_version_id = 1,
 735     .needed = tlbemb_needed,
 736     .fields = (VMStateField[]) {
 737         VMSTATE_INT32_EQUAL(env.nb_tlb, PowerPCCPU, NULL),
 738         VMSTATE_STRUCT_VARRAY_POINTER_INT32(env.tlb.tlbe, PowerPCCPU,
 739                                             env.nb_tlb,
 740                                             vmstate_tlbemb_entry,
 741                                             ppcemb_tlb_t),
 742         /* 403 protection registers */
 743         VMSTATE_END_OF_LIST()
 744     },
 745     .subsections = (const VMStateDescription*[]) {
 746         &vmstate_pbr403,
 747         NULL
 748     }
 749 };
 750
 751 static const VMStateDescription vmstate_tlbmas_entry = {
 752     .name = "cpu/tlbmas_entry",
 753     .version_id = 1,
 754     .minimum_version_id = 1,
 755     .fields = (VMStateField[]) {
 756         VMSTATE_UINT32(mas8, ppcmas_tlb_t),
 757         VMSTATE_UINT32(mas1, ppcmas_tlb_t),
 758         VMSTATE_UINT64(mas2, ppcmas_tlb_t),
 759         VMSTATE_UINT64(mas7_3, ppcmas_tlb_t),
 760         VMSTATE_END_OF_LIST()
 761     },
 762 };
 763
 764 static bool tlbmas_needed(void *opaque)
 765 {
 766     PowerPCCPU *cpu = opaque;
 767     CPUPPCState *env = &cpu->env;
 768
 769     return env->nb_tlb && (env->tlb_type == TLB_MAS);
 770 }
 771
 772 static const VMStateDescription vmstate_tlbmas = {
 773     .name = "cpu/tlbmas",
 774     .version_id = 1,
 775     .minimum_version_id = 1,
 776     .needed = tlbmas_needed,
 777     .fields = (VMStateField[]) {
 778         VMSTATE_INT32_EQUAL(env.nb_tlb, PowerPCCPU, NULL),
 779         VMSTATE_STRUCT_VARRAY_POINTER_INT32(env.tlb.tlbm, PowerPCCPU,
 780                                             env.nb_tlb,
 781                                             vmstate_tlbmas_entry,
 782                                             ppcmas_tlb_t),
 783         VMSTATE_END_OF_LIST()
 784     }
 785 };
 786
 787 static bool compat_needed(void *opaque)
 788 {
 789     PowerPCCPU *cpu = opaque;
 790
 791     assert(!(cpu->compat_pvr && !cpu->vhyp));
 792     return !cpu->pre_2_10_migration && cpu->compat_pvr != 0;
 793 }
 794
 795 static const VMStateDescription vmstate_compat = {
 796     .name = "cpu/compat",
 797     .version_id = 1,
 798     .minimum_version_id = 1,
 799     .needed = compat_needed,
 800     .fields = (VMStateField[]) {
 801         VMSTATE_UINT32(compat_pvr, PowerPCCPU),
 802         VMSTATE_END_OF_LIST()
 803     }
 804 };
 805
 806 const VMStateDescription vmstate_ppc_cpu = {
 807     .name = "cpu",
 808     .version_id = 5,
 809     .minimum_version_id = 5,
 810     .minimum_version_id_old = 4,
 811     .load_state_old = cpu_load_old,
 812     .pre_save = cpu_pre_save,
 813     .post_load = cpu_post_load,
 814     .fields = (VMStateField[]) {
 815         VMSTATE_UNUSED(sizeof(target_ulong)), /* was _EQUAL(env.spr[SPR_PVR]) */
 816
 817         /* User mode architected state */
 818         VMSTATE_UINTTL_ARRAY(env.gpr, PowerPCCPU, 32),
 819 #if !defined(TARGET_PPC64)
 820         VMSTATE_UINTTL_ARRAY(env.gprh, PowerPCCPU, 32),
 821 #endif
 822         VMSTATE_UINT32_ARRAY(env.crf, PowerPCCPU, 8),
 823         VMSTATE_UINTTL(env.nip, PowerPCCPU),
 824
 825         /* SPRs */
 826         VMSTATE_UINTTL_ARRAY(env.spr, PowerPCCPU, 1024),
 827         VMSTATE_UINT64(env.spe_acc, PowerPCCPU),
 828
 829         /* Reservation */
 830         VMSTATE_UINTTL(env.reserve_addr, PowerPCCPU),
 831
 832         /* Supervisor mode architected state */
 833         VMSTATE_UINTTL(env.msr, PowerPCCPU),
 834
 835         /* Backward compatible internal state */
 836         VMSTATE_UINTTL(env.hflags_compat_nmsr, PowerPCCPU),
 837
 838         /* Sanity checking */
 839         VMSTATE_UINTTL_TEST(mig_msr_mask, PowerPCCPU, cpu_pre_2_8_migration),
 840         VMSTATE_UINT64_TEST(mig_insns_flags, PowerPCCPU, cpu_pre_2_8_migration),
 841         VMSTATE_UINT64_TEST(mig_insns_flags2, PowerPCCPU,
 842                             cpu_pre_2_8_migration),
 843         VMSTATE_UINT32_TEST(mig_nb_BATs, PowerPCCPU, cpu_pre_2_8_migration),
 844         VMSTATE_END_OF_LIST()
 845     },
 846     .subsections = (const VMStateDescription*[]) {
 847         &vmstate_fpu,
 848         &vmstate_altivec,
 849         &vmstate_vsx,
 850         &vmstate_sr,
 851 #ifdef TARGET_PPC64
 852         &vmstate_tm,
 853         &vmstate_slb,
 854 #endif /* TARGET_PPC64 */
 855         &vmstate_tlb6xx,
 856         &vmstate_tlbemb,
 857         &vmstate_tlbmas,
 858         &vmstate_compat,
 859         NULL
 860     }
 861 };