1 #include "qemu/osdep.h"
3 #include "exec/exec-all.h"
4 #include "sysemu/kvm.h"
5 #include "sysemu/tcg.h"
6 #include "helper_regs.h"
7 #include "mmu-hash64.h"
8 #include "migration/cpu.h"
9 #include "qapi/error.h"
10 #include "qemu/main-loop.h"
12 #include "power8-pmu.h"
14 static void post_load_update_msr(CPUPPCState
*env
)
16 target_ulong msr
= env
->msr
;
19 * Invalidate all supported msr bits except MSR_TGPR/MSR_HVB
20 * before restoring. Note that this recomputes hflags.
22 env
->msr
^= env
->msr_mask
& ~((1ULL << MSR_TGPR
) | MSR_HVB
);
23 ppc_store_msr(env
, msr
);
26 pmu_update_summaries(env
);
30 static int get_avr(QEMUFile
*f
, void *pv
, size_t size
,
31 const VMStateField
*field
)
35 v
->u64
[0] = qemu_get_be64(f
);
36 v
->u64
[1] = qemu_get_be64(f
);
41 static int put_avr(QEMUFile
*f
, void *pv
, size_t size
,
42 const VMStateField
*field
, JSONWriter
*vmdesc
)
46 qemu_put_be64(f
, v
->u64
[0]);
47 qemu_put_be64(f
, v
->u64
[1]);
51 static const VMStateInfo vmstate_info_avr
= {
57 #define VMSTATE_AVR_ARRAY_V(_f, _s, _n, _v) \
58 VMSTATE_SUB_ARRAY(_f, _s, 32, _n, _v, vmstate_info_avr, ppc_avr_t)
60 #define VMSTATE_AVR_ARRAY(_f, _s, _n) \
61 VMSTATE_AVR_ARRAY_V(_f, _s, _n, 0)
63 static int get_fpr(QEMUFile
*f
, void *pv
, size_t size
,
64 const VMStateField
*field
)
68 v
->VsrD(0) = qemu_get_be64(f
);
73 static int put_fpr(QEMUFile
*f
, void *pv
, size_t size
,
74 const VMStateField
*field
, JSONWriter
*vmdesc
)
78 qemu_put_be64(f
, v
->VsrD(0));
82 static const VMStateInfo vmstate_info_fpr
= {
88 #define VMSTATE_FPR_ARRAY_V(_f, _s, _n, _v) \
89 VMSTATE_SUB_ARRAY(_f, _s, 0, _n, _v, vmstate_info_fpr, ppc_vsr_t)
91 #define VMSTATE_FPR_ARRAY(_f, _s, _n) \
92 VMSTATE_FPR_ARRAY_V(_f, _s, _n, 0)
94 static int get_vsr(QEMUFile
*f
, void *pv
, size_t size
,
95 const VMStateField
*field
)
99 v
->VsrD(1) = qemu_get_be64(f
);
104 static int put_vsr(QEMUFile
*f
, void *pv
, size_t size
,
105 const VMStateField
*field
, JSONWriter
*vmdesc
)
109 qemu_put_be64(f
, v
->VsrD(1));
113 static const VMStateInfo vmstate_info_vsr
= {
119 #define VMSTATE_VSR_ARRAY_V(_f, _s, _n, _v) \
120 VMSTATE_SUB_ARRAY(_f, _s, 0, _n, _v, vmstate_info_vsr, ppc_vsr_t)
122 #define VMSTATE_VSR_ARRAY(_f, _s, _n) \
123 VMSTATE_VSR_ARRAY_V(_f, _s, _n, 0)
125 static bool cpu_pre_2_8_migration(void *opaque
, int version_id
)
127 PowerPCCPU
*cpu
= opaque
;
129 return cpu
->pre_2_8_migration
;
132 #if defined(TARGET_PPC64)
133 static bool cpu_pre_3_0_migration(void *opaque
, int version_id
)
135 PowerPCCPU
*cpu
= opaque
;
137 return cpu
->pre_3_0_migration
;
141 static int cpu_pre_save(void *opaque
)
143 PowerPCCPU
*cpu
= opaque
;
144 CPUPPCState
*env
= &cpu
->env
;
146 uint64_t insns_compat_mask
=
147 PPC_INSNS_BASE
| PPC_ISEL
| PPC_STRING
| PPC_MFTB
148 | PPC_FLOAT
| PPC_FLOAT_FSEL
| PPC_FLOAT_FRES
149 | PPC_FLOAT_FSQRT
| PPC_FLOAT_FRSQRTE
| PPC_FLOAT_FRSQRTES
150 | PPC_FLOAT_STFIWX
| PPC_FLOAT_EXT
151 | PPC_CACHE
| PPC_CACHE_ICBI
| PPC_CACHE_DCBZ
152 | PPC_MEM_SYNC
| PPC_MEM_EIEIO
| PPC_MEM_TLBIE
| PPC_MEM_TLBSYNC
153 | PPC_64B
| PPC_64BX
| PPC_ALTIVEC
154 | PPC_SEGMENT_64B
| PPC_SLBI
| PPC_POPCNTB
| PPC_POPCNTWD
;
155 uint64_t insns_compat_mask2
= PPC2_VSX
| PPC2_VSX207
| PPC2_DFP
| PPC2_DBRX
156 | PPC2_PERM_ISA206
| PPC2_DIVE_ISA206
157 | PPC2_ATOMIC_ISA206
| PPC2_FP_CVT_ISA206
158 | PPC2_FP_TST_ISA206
| PPC2_BCTAR_ISA207
159 | PPC2_LSQ_ISA207
| PPC2_ALTIVEC_207
160 | PPC2_ISA205
| PPC2_ISA207S
| PPC2_FP_CVT_S64
| PPC2_TM
;
162 env
->spr
[SPR_LR
] = env
->lr
;
163 env
->spr
[SPR_CTR
] = env
->ctr
;
164 env
->spr
[SPR_XER
] = cpu_read_xer(env
);
165 #if defined(TARGET_PPC64)
166 env
->spr
[SPR_CFAR
] = env
->cfar
;
168 env
->spr
[SPR_BOOKE_SPEFSCR
] = env
->spe_fscr
;
170 for (i
= 0; (i
< 4) && (i
< env
->nb_BATs
); i
++) {
171 env
->spr
[SPR_DBAT0U
+ 2 * i
] = env
->DBAT
[0][i
];
172 env
->spr
[SPR_DBAT0U
+ 2 * i
+ 1] = env
->DBAT
[1][i
];
173 env
->spr
[SPR_IBAT0U
+ 2 * i
] = env
->IBAT
[0][i
];
174 env
->spr
[SPR_IBAT0U
+ 2 * i
+ 1] = env
->IBAT
[1][i
];
176 for (i
= 0; (i
< 4) && ((i
+ 4) < env
->nb_BATs
); i
++) {
177 env
->spr
[SPR_DBAT4U
+ 2 * i
] = env
->DBAT
[0][i
+ 4];
178 env
->spr
[SPR_DBAT4U
+ 2 * i
+ 1] = env
->DBAT
[1][i
+ 4];
179 env
->spr
[SPR_IBAT4U
+ 2 * i
] = env
->IBAT
[0][i
+ 4];
180 env
->spr
[SPR_IBAT4U
+ 2 * i
+ 1] = env
->IBAT
[1][i
+ 4];
183 /* Hacks for migration compatibility between 2.6, 2.7 & 2.8 */
184 if (cpu
->pre_2_8_migration
) {
186 * Mask out bits that got added to msr_mask since the versions
187 * which stupidly included it in the migration stream.
189 target_ulong metamask
= 0
190 #if defined(TARGET_PPC64)
195 cpu
->mig_msr_mask
= env
->msr_mask
& ~metamask
;
196 cpu
->mig_insns_flags
= env
->insns_flags
& insns_compat_mask
;
198 * CPU models supported by old machines all have
199 * PPC_MEM_TLBIE, so we set it unconditionally to allow
200 * backward migration from a POWER9 host to a POWER8 host.
202 cpu
->mig_insns_flags
|= PPC_MEM_TLBIE
;
203 cpu
->mig_insns_flags2
= env
->insns_flags2
& insns_compat_mask2
;
204 cpu
->mig_nb_BATs
= env
->nb_BATs
;
206 if (cpu
->pre_3_0_migration
) {
207 if (cpu
->hash64_opts
) {
208 cpu
->mig_slb_nr
= cpu
->hash64_opts
->slb_size
;
212 /* Used to retain migration compatibility for pre 6.0 for 601 machines. */
213 env
->hflags_compat_nmsr
= 0;
219 * Determine if a given PVR is a "close enough" match to the CPU
220 * object. For TCG and KVM PR it would probably be sufficient to
221 * require an exact PVR match. However for KVM HV the user is
222 * restricted to a PVR exactly matching the host CPU. The correct way
223 * to handle this is to put the guest into an architected
224 * compatibility mode. However, to allow a more forgiving transition
225 * and migration from before this was widely done, we allow migration
226 * between sufficiently similar PVRs, as determined by the CPU class's
229 static bool pvr_match(PowerPCCPU
*cpu
, uint32_t pvr
)
231 PowerPCCPUClass
*pcc
= POWERPC_CPU_GET_CLASS(cpu
);
233 if (pvr
== pcc
->pvr
) {
236 return pcc
->pvr_match(pcc
, pvr
);
239 static int cpu_post_load(void *opaque
, int version_id
)
241 PowerPCCPU
*cpu
= opaque
;
242 CPUPPCState
*env
= &cpu
->env
;
246 * If we're operating in compat mode, we should be ok as long as
247 * the destination supports the same compatibility mode.
249 * Otherwise, however, we require that the destination has exactly
250 * the same CPU model as the source.
253 #if defined(TARGET_PPC64)
254 if (cpu
->compat_pvr
) {
255 uint32_t compat_pvr
= cpu
->compat_pvr
;
256 Error
*local_err
= NULL
;
260 ret
= ppc_set_compat(cpu
, compat_pvr
, &local_err
);
262 error_report_err(local_err
);
268 if (!pvr_match(cpu
, env
->spr
[SPR_PVR
])) {
274 * If we're running with KVM HV, there is a chance that the guest
275 * is running with KVM HV and its kernel does not have the
276 * capability of dealing with a different PVR other than this
277 * exact host PVR in KVM_SET_SREGS. If that happens, the
278 * guest freezes after migration.
280 * The function kvmppc_pvr_workaround_required does this verification
281 * by first checking if the kernel has the cap, returning true immediately
282 * if that is the case. Otherwise, it checks if we're running in KVM PR.
283 * If the guest kernel does not have the cap and we're not running KVM-PR
284 * (so, it is running KVM-HV), we need to ensure that KVM_SET_SREGS will
285 * receive the PVR it expects as a workaround.
288 if (kvmppc_pvr_workaround_required(cpu
)) {
289 env
->spr
[SPR_PVR
] = env
->spr_cb
[SPR_PVR
].default_value
;
292 env
->lr
= env
->spr
[SPR_LR
];
293 env
->ctr
= env
->spr
[SPR_CTR
];
294 cpu_write_xer(env
, env
->spr
[SPR_XER
]);
295 #if defined(TARGET_PPC64)
296 env
->cfar
= env
->spr
[SPR_CFAR
];
298 env
->spe_fscr
= env
->spr
[SPR_BOOKE_SPEFSCR
];
300 for (i
= 0; (i
< 4) && (i
< env
->nb_BATs
); i
++) {
301 env
->DBAT
[0][i
] = env
->spr
[SPR_DBAT0U
+ 2 * i
];
302 env
->DBAT
[1][i
] = env
->spr
[SPR_DBAT0U
+ 2 * i
+ 1];
303 env
->IBAT
[0][i
] = env
->spr
[SPR_IBAT0U
+ 2 * i
];
304 env
->IBAT
[1][i
] = env
->spr
[SPR_IBAT0U
+ 2 * i
+ 1];
306 for (i
= 0; (i
< 4) && ((i
+ 4) < env
->nb_BATs
); i
++) {
307 env
->DBAT
[0][i
+ 4] = env
->spr
[SPR_DBAT4U
+ 2 * i
];
308 env
->DBAT
[1][i
+ 4] = env
->spr
[SPR_DBAT4U
+ 2 * i
+ 1];
309 env
->IBAT
[0][i
+ 4] = env
->spr
[SPR_IBAT4U
+ 2 * i
];
310 env
->IBAT
[1][i
+ 4] = env
->spr
[SPR_IBAT4U
+ 2 * i
+ 1];
314 ppc_store_sdr1(env
, env
->spr
[SPR_SDR1
]);
317 post_load_update_msr(env
);
322 static bool fpu_needed(void *opaque
)
324 PowerPCCPU
*cpu
= opaque
;
326 return cpu
->env
.insns_flags
& PPC_FLOAT
;
329 static const VMStateDescription vmstate_fpu
= {
332 .minimum_version_id
= 1,
333 .needed
= fpu_needed
,
334 .fields
= (VMStateField
[]) {
335 VMSTATE_FPR_ARRAY(env
.vsr
, PowerPCCPU
, 32),
336 VMSTATE_UINTTL(env
.fpscr
, PowerPCCPU
),
337 VMSTATE_END_OF_LIST()
341 static bool altivec_needed(void *opaque
)
343 PowerPCCPU
*cpu
= opaque
;
345 return cpu
->env
.insns_flags
& PPC_ALTIVEC
;
348 static int get_vscr(QEMUFile
*f
, void *opaque
, size_t size
,
349 const VMStateField
*field
)
351 PowerPCCPU
*cpu
= opaque
;
352 ppc_store_vscr(&cpu
->env
, qemu_get_be32(f
));
356 static int put_vscr(QEMUFile
*f
, void *opaque
, size_t size
,
357 const VMStateField
*field
, JSONWriter
*vmdesc
)
359 PowerPCCPU
*cpu
= opaque
;
360 qemu_put_be32(f
, ppc_get_vscr(&cpu
->env
));
364 static const VMStateInfo vmstate_vscr
= {
365 .name
= "cpu/altivec/vscr",
370 static const VMStateDescription vmstate_altivec
= {
371 .name
= "cpu/altivec",
373 .minimum_version_id
= 1,
374 .needed
= altivec_needed
,
375 .fields
= (VMStateField
[]) {
376 VMSTATE_AVR_ARRAY(env
.vsr
, PowerPCCPU
, 32),
378 * Save the architecture value of the vscr, not the internally
379 * expanded version. Since this architecture value does not
380 * exist in memory to be stored, this requires a but of hoop
381 * jumping. We want OFFSET=0 so that we effectively pass CPU
382 * to the helper functions.
387 .size
= sizeof(uint32_t),
388 .info
= &vmstate_vscr
,
392 VMSTATE_END_OF_LIST()
396 static bool vsx_needed(void *opaque
)
398 PowerPCCPU
*cpu
= opaque
;
400 return cpu
->env
.insns_flags2
& PPC2_VSX
;
403 static const VMStateDescription vmstate_vsx
= {
406 .minimum_version_id
= 1,
407 .needed
= vsx_needed
,
408 .fields
= (VMStateField
[]) {
409 VMSTATE_VSR_ARRAY(env
.vsr
, PowerPCCPU
, 32),
410 VMSTATE_END_OF_LIST()
415 /* Transactional memory state */
416 static bool tm_needed(void *opaque
)
418 PowerPCCPU
*cpu
= opaque
;
419 CPUPPCState
*env
= &cpu
->env
;
423 static const VMStateDescription vmstate_tm
= {
426 .minimum_version_id
= 1,
428 .fields
= (VMStateField
[]) {
429 VMSTATE_UINTTL_ARRAY(env
.tm_gpr
, PowerPCCPU
, 32),
430 VMSTATE_AVR_ARRAY(env
.tm_vsr
, PowerPCCPU
, 64),
431 VMSTATE_UINT64(env
.tm_cr
, PowerPCCPU
),
432 VMSTATE_UINT64(env
.tm_lr
, PowerPCCPU
),
433 VMSTATE_UINT64(env
.tm_ctr
, PowerPCCPU
),
434 VMSTATE_UINT64(env
.tm_fpscr
, PowerPCCPU
),
435 VMSTATE_UINT64(env
.tm_amr
, PowerPCCPU
),
436 VMSTATE_UINT64(env
.tm_ppr
, PowerPCCPU
),
437 VMSTATE_UINT64(env
.tm_vrsave
, PowerPCCPU
),
438 VMSTATE_UINT32(env
.tm_vscr
, PowerPCCPU
),
439 VMSTATE_UINT64(env
.tm_dscr
, PowerPCCPU
),
440 VMSTATE_UINT64(env
.tm_tar
, PowerPCCPU
),
441 VMSTATE_END_OF_LIST()
446 static bool sr_needed(void *opaque
)
449 PowerPCCPU
*cpu
= opaque
;
451 return !mmu_is_64bit(cpu
->env
.mmu_model
);
457 static const VMStateDescription vmstate_sr
= {
460 .minimum_version_id
= 1,
462 .fields
= (VMStateField
[]) {
463 VMSTATE_UINTTL_ARRAY(env
.sr
, PowerPCCPU
, 32),
464 VMSTATE_END_OF_LIST()
469 static int get_slbe(QEMUFile
*f
, void *pv
, size_t size
,
470 const VMStateField
*field
)
474 v
->esid
= qemu_get_be64(f
);
475 v
->vsid
= qemu_get_be64(f
);
480 static int put_slbe(QEMUFile
*f
, void *pv
, size_t size
,
481 const VMStateField
*field
, JSONWriter
*vmdesc
)
485 qemu_put_be64(f
, v
->esid
);
486 qemu_put_be64(f
, v
->vsid
);
490 static const VMStateInfo vmstate_info_slbe
= {
496 #define VMSTATE_SLB_ARRAY_V(_f, _s, _n, _v) \
497 VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_slbe, ppc_slb_t)
499 #define VMSTATE_SLB_ARRAY(_f, _s, _n) \
500 VMSTATE_SLB_ARRAY_V(_f, _s, _n, 0)
502 static bool slb_needed(void *opaque
)
504 PowerPCCPU
*cpu
= opaque
;
506 /* We don't support any of the old segment table based 64-bit CPUs */
507 return mmu_is_64bit(cpu
->env
.mmu_model
);
510 static int slb_post_load(void *opaque
, int version_id
)
512 PowerPCCPU
*cpu
= opaque
;
513 CPUPPCState
*env
= &cpu
->env
;
517 * We've pulled in the raw esid and vsid values from the migration
518 * stream, but we need to recompute the page size pointers
520 for (i
= 0; i
< cpu
->hash64_opts
->slb_size
; i
++) {
521 if (ppc_store_slb(cpu
, i
, env
->slb
[i
].esid
, env
->slb
[i
].vsid
) < 0) {
522 /* Migration source had bad values in its SLB */
530 static const VMStateDescription vmstate_slb
= {
533 .minimum_version_id
= 1,
534 .needed
= slb_needed
,
535 .post_load
= slb_post_load
,
536 .fields
= (VMStateField
[]) {
537 VMSTATE_INT32_TEST(mig_slb_nr
, PowerPCCPU
, cpu_pre_3_0_migration
),
538 VMSTATE_SLB_ARRAY(env
.slb
, PowerPCCPU
, MAX_SLB_ENTRIES
),
539 VMSTATE_END_OF_LIST()
542 #endif /* TARGET_PPC64 */
544 static const VMStateDescription vmstate_tlb6xx_entry
= {
545 .name
= "cpu/tlb6xx_entry",
547 .minimum_version_id
= 1,
548 .fields
= (VMStateField
[]) {
549 VMSTATE_UINTTL(pte0
, ppc6xx_tlb_t
),
550 VMSTATE_UINTTL(pte1
, ppc6xx_tlb_t
),
551 VMSTATE_UINTTL(EPN
, ppc6xx_tlb_t
),
552 VMSTATE_END_OF_LIST()
556 static bool tlb6xx_needed(void *opaque
)
558 PowerPCCPU
*cpu
= opaque
;
559 CPUPPCState
*env
= &cpu
->env
;
561 return env
->nb_tlb
&& (env
->tlb_type
== TLB_6XX
);
564 static const VMStateDescription vmstate_tlb6xx
= {
565 .name
= "cpu/tlb6xx",
567 .minimum_version_id
= 1,
568 .needed
= tlb6xx_needed
,
569 .fields
= (VMStateField
[]) {
570 VMSTATE_INT32_EQUAL(env
.nb_tlb
, PowerPCCPU
, NULL
),
571 VMSTATE_STRUCT_VARRAY_POINTER_INT32(env
.tlb
.tlb6
, PowerPCCPU
,
573 vmstate_tlb6xx_entry
,
575 VMSTATE_UINTTL_ARRAY(env
.tgpr
, PowerPCCPU
, 4),
576 VMSTATE_END_OF_LIST()
580 static const VMStateDescription vmstate_tlbemb_entry
= {
581 .name
= "cpu/tlbemb_entry",
583 .minimum_version_id
= 1,
584 .fields
= (VMStateField
[]) {
585 VMSTATE_UINT64(RPN
, ppcemb_tlb_t
),
586 VMSTATE_UINTTL(EPN
, ppcemb_tlb_t
),
587 VMSTATE_UINTTL(PID
, ppcemb_tlb_t
),
588 VMSTATE_UINTTL(size
, ppcemb_tlb_t
),
589 VMSTATE_UINT32(prot
, ppcemb_tlb_t
),
590 VMSTATE_UINT32(attr
, ppcemb_tlb_t
),
591 VMSTATE_END_OF_LIST()
595 static bool tlbemb_needed(void *opaque
)
597 PowerPCCPU
*cpu
= opaque
;
598 CPUPPCState
*env
= &cpu
->env
;
600 return env
->nb_tlb
&& (env
->tlb_type
== TLB_EMB
);
603 static const VMStateDescription vmstate_tlbemb
= {
604 .name
= "cpu/tlb6xx",
606 .minimum_version_id
= 1,
607 .needed
= tlbemb_needed
,
608 .fields
= (VMStateField
[]) {
609 VMSTATE_INT32_EQUAL(env
.nb_tlb
, PowerPCCPU
, NULL
),
610 VMSTATE_STRUCT_VARRAY_POINTER_INT32(env
.tlb
.tlbe
, PowerPCCPU
,
612 vmstate_tlbemb_entry
,
614 VMSTATE_END_OF_LIST()
618 static const VMStateDescription vmstate_tlbmas_entry
= {
619 .name
= "cpu/tlbmas_entry",
621 .minimum_version_id
= 1,
622 .fields
= (VMStateField
[]) {
623 VMSTATE_UINT32(mas8
, ppcmas_tlb_t
),
624 VMSTATE_UINT32(mas1
, ppcmas_tlb_t
),
625 VMSTATE_UINT64(mas2
, ppcmas_tlb_t
),
626 VMSTATE_UINT64(mas7_3
, ppcmas_tlb_t
),
627 VMSTATE_END_OF_LIST()
631 static bool tlbmas_needed(void *opaque
)
633 PowerPCCPU
*cpu
= opaque
;
634 CPUPPCState
*env
= &cpu
->env
;
636 return env
->nb_tlb
&& (env
->tlb_type
== TLB_MAS
);
639 static const VMStateDescription vmstate_tlbmas
= {
640 .name
= "cpu/tlbmas",
642 .minimum_version_id
= 1,
643 .needed
= tlbmas_needed
,
644 .fields
= (VMStateField
[]) {
645 VMSTATE_INT32_EQUAL(env
.nb_tlb
, PowerPCCPU
, NULL
),
646 VMSTATE_STRUCT_VARRAY_POINTER_INT32(env
.tlb
.tlbm
, PowerPCCPU
,
648 vmstate_tlbmas_entry
,
650 VMSTATE_END_OF_LIST()
654 static bool compat_needed(void *opaque
)
656 PowerPCCPU
*cpu
= opaque
;
658 assert(!(cpu
->compat_pvr
&& !cpu
->vhyp
));
659 return !cpu
->pre_2_10_migration
&& cpu
->compat_pvr
!= 0;
662 static const VMStateDescription vmstate_compat
= {
663 .name
= "cpu/compat",
665 .minimum_version_id
= 1,
666 .needed
= compat_needed
,
667 .fields
= (VMStateField
[]) {
668 VMSTATE_UINT32(compat_pvr
, PowerPCCPU
),
669 VMSTATE_END_OF_LIST()
673 const VMStateDescription vmstate_ppc_cpu
= {
676 .minimum_version_id
= 5,
677 .pre_save
= cpu_pre_save
,
678 .post_load
= cpu_post_load
,
679 .fields
= (VMStateField
[]) {
680 VMSTATE_UNUSED(sizeof(target_ulong
)), /* was _EQUAL(env.spr[SPR_PVR]) */
682 /* User mode architected state */
683 VMSTATE_UINTTL_ARRAY(env
.gpr
, PowerPCCPU
, 32),
684 #if !defined(TARGET_PPC64)
685 VMSTATE_UINTTL_ARRAY(env
.gprh
, PowerPCCPU
, 32),
687 VMSTATE_UINT32_ARRAY(env
.crf
, PowerPCCPU
, 8),
688 VMSTATE_UINTTL(env
.nip
, PowerPCCPU
),
691 VMSTATE_UINTTL_ARRAY(env
.spr
, PowerPCCPU
, 1024),
692 VMSTATE_UINT64(env
.spe_acc
, PowerPCCPU
),
695 VMSTATE_UINTTL(env
.reserve_addr
, PowerPCCPU
),
697 /* Supervisor mode architected state */
698 VMSTATE_UINTTL(env
.msr
, PowerPCCPU
),
700 /* Backward compatible internal state */
701 VMSTATE_UINTTL(env
.hflags_compat_nmsr
, PowerPCCPU
),
703 /* Sanity checking */
704 VMSTATE_UINTTL_TEST(mig_msr_mask
, PowerPCCPU
, cpu_pre_2_8_migration
),
705 VMSTATE_UINT64_TEST(mig_insns_flags
, PowerPCCPU
, cpu_pre_2_8_migration
),
706 VMSTATE_UINT64_TEST(mig_insns_flags2
, PowerPCCPU
,
707 cpu_pre_2_8_migration
),
708 VMSTATE_UINT32_TEST(mig_nb_BATs
, PowerPCCPU
, cpu_pre_2_8_migration
),
709 VMSTATE_END_OF_LIST()
711 .subsections
= (const VMStateDescription
*[]) {
719 #endif /* TARGET_PPC64 */