2 * defines common to all virtual CPUs
4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
22 #include "qemu-common.h"
23 #include "exec/cpu-common.h"
24 #include "exec/memory.h"
25 #include "qemu/thread.h"
28 /* some important defines:
30 * WORDS_ALIGNED : if defined, the host cpu can only make word aligned
33 * HOST_WORDS_BIGENDIAN : if defined, the host cpu is big endian and
34 * otherwise little endian.
36 * (TARGET_WORDS_ALIGNED : same for target cpu (not supported yet))
38 * TARGET_WORDS_BIGENDIAN : same for target cpu
41 #if defined(HOST_WORDS_BIGENDIAN) != defined(TARGET_WORDS_BIGENDIAN)
47 static inline uint16_t tswap16(uint16_t s
)
52 static inline uint32_t tswap32(uint32_t s
)
57 static inline uint64_t tswap64(uint64_t s
)
62 static inline void tswap16s(uint16_t *s
)
67 static inline void tswap32s(uint32_t *s
)
72 static inline void tswap64s(uint64_t *s
)
79 static inline uint16_t tswap16(uint16_t s
)
84 static inline uint32_t tswap32(uint32_t s
)
89 static inline uint64_t tswap64(uint64_t s
)
94 static inline void tswap16s(uint16_t *s
)
98 static inline void tswap32s(uint32_t *s
)
102 static inline void tswap64s(uint64_t *s
)
108 #if TARGET_LONG_SIZE == 4
109 #define tswapl(s) tswap32(s)
110 #define tswapls(s) tswap32s((uint32_t *)(s))
111 #define bswaptls(s) bswap32s(s)
113 #define tswapl(s) tswap64(s)
114 #define tswapls(s) tswap64s((uint64_t *)(s))
115 #define bswaptls(s) bswap64s(s)
118 /* CPU memory access without any memory or io remapping */
121 * the generic syntax for the memory accesses is:
123 * load: ld{type}{sign}{size}{endian}_{access_type}(ptr)
125 * store: st{type}{size}{endian}_{access_type}(ptr, val)
128 * (empty): integer access
132 * (empty): for floats or 32 bit size
143 * (empty): target cpu endianness or 8 bit access
144 * r : reversed target cpu endianness (not implemented yet)
145 * be : big endian (not implemented yet)
146 * le : little endian (not implemented yet)
149 * raw : host memory access
150 * user : user mode access using soft MMU
151 * kernel : kernel mode access using soft MMU
154 /* target-endianness CPU memory access functions */
155 #if defined(TARGET_WORDS_BIGENDIAN)
156 #define lduw_p(p) lduw_be_p(p)
157 #define ldsw_p(p) ldsw_be_p(p)
158 #define ldl_p(p) ldl_be_p(p)
159 #define ldq_p(p) ldq_be_p(p)
160 #define ldfl_p(p) ldfl_be_p(p)
161 #define ldfq_p(p) ldfq_be_p(p)
162 #define stw_p(p, v) stw_be_p(p, v)
163 #define stl_p(p, v) stl_be_p(p, v)
164 #define stq_p(p, v) stq_be_p(p, v)
165 #define stfl_p(p, v) stfl_be_p(p, v)
166 #define stfq_p(p, v) stfq_be_p(p, v)
168 #define lduw_p(p) lduw_le_p(p)
169 #define ldsw_p(p) ldsw_le_p(p)
170 #define ldl_p(p) ldl_le_p(p)
171 #define ldq_p(p) ldq_le_p(p)
172 #define ldfl_p(p) ldfl_le_p(p)
173 #define ldfq_p(p) ldfq_le_p(p)
174 #define stw_p(p, v) stw_le_p(p, v)
175 #define stl_p(p, v) stl_le_p(p, v)
176 #define stq_p(p, v) stq_le_p(p, v)
177 #define stfl_p(p, v) stfl_le_p(p, v)
178 #define stfq_p(p, v) stfq_le_p(p, v)
181 /* MMU memory access macros */
183 #if defined(CONFIG_USER_ONLY)
185 #include "exec/user/abitypes.h"
187 /* On some host systems the guest address space is reserved on the host.
188 * This allows the guest address space to be offset to a convenient location.
190 #if defined(CONFIG_USE_GUEST_BASE)
191 extern unsigned long guest_base
;
192 extern int have_guest_base
;
193 extern unsigned long reserved_va
;
194 #define GUEST_BASE guest_base
195 #define RESERVED_VA reserved_va
197 #define GUEST_BASE 0ul
198 #define RESERVED_VA 0ul
201 #define GUEST_ADDR_MAX (RESERVED_VA ? RESERVED_VA : \
202 (1ul << TARGET_VIRT_ADDR_SPACE_BITS) - 1)
205 /* page related stuff */
207 #define TARGET_PAGE_SIZE (1 << TARGET_PAGE_BITS)
208 #define TARGET_PAGE_MASK ~(TARGET_PAGE_SIZE - 1)
209 #define TARGET_PAGE_ALIGN(addr) (((addr) + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK)
211 /* ??? These should be the larger of uintptr_t and target_ulong. */
212 extern uintptr_t qemu_real_host_page_size
;
213 extern uintptr_t qemu_host_page_size
;
214 extern uintptr_t qemu_host_page_mask
;
216 #define HOST_PAGE_ALIGN(addr) (((addr) + qemu_host_page_size - 1) & qemu_host_page_mask)
218 /* same as PROT_xxx */
219 #define PAGE_READ 0x0001
220 #define PAGE_WRITE 0x0002
221 #define PAGE_EXEC 0x0004
222 #define PAGE_BITS (PAGE_READ | PAGE_WRITE | PAGE_EXEC)
223 #define PAGE_VALID 0x0008
224 /* original state of the write flag (used when tracking self-modifying
226 #define PAGE_WRITE_ORG 0x0010
227 #if defined(CONFIG_BSD) && defined(CONFIG_USER_ONLY)
228 /* FIXME: Code that sets/uses this is broken and needs to go away. */
229 #define PAGE_RESERVED 0x0020
232 #if defined(CONFIG_USER_ONLY)
233 void page_dump(FILE *f
);
235 typedef int (*walk_memory_regions_fn
)(void *, abi_ulong
,
236 abi_ulong
, unsigned long);
237 int walk_memory_regions(void *, walk_memory_regions_fn
);
239 int page_get_flags(target_ulong address
);
240 void page_set_flags(target_ulong start
, target_ulong end
, int flags
);
241 int page_check_range(target_ulong start
, target_ulong len
, int flags
);
244 CPUArchState
*cpu_copy(CPUArchState
*env
);
246 /* Flags for use in ENV->INTERRUPT_PENDING.
248 The numbers assigned here are non-sequential in order to preserve
249 binary compatibility with the vmstate dump. Bit 0 (0x0001) was
250 previously used for CPU_INTERRUPT_EXIT, and is cleared when loading
253 /* External hardware interrupt pending. This is typically used for
254 interrupts from devices. */
255 #define CPU_INTERRUPT_HARD 0x0002
257 /* Exit the current TB. This is typically used when some system-level device
258 makes some change to the memory mapping. E.g. the a20 line change. */
259 #define CPU_INTERRUPT_EXITTB 0x0004
262 #define CPU_INTERRUPT_HALT 0x0020
264 /* Debug event pending. */
265 #define CPU_INTERRUPT_DEBUG 0x0080
268 #define CPU_INTERRUPT_RESET 0x0400
270 /* Several target-specific external hardware interrupts. Each target/cpu.h
271 should define proper names based on these defines. */
272 #define CPU_INTERRUPT_TGT_EXT_0 0x0008
273 #define CPU_INTERRUPT_TGT_EXT_1 0x0010
274 #define CPU_INTERRUPT_TGT_EXT_2 0x0040
275 #define CPU_INTERRUPT_TGT_EXT_3 0x0200
276 #define CPU_INTERRUPT_TGT_EXT_4 0x1000
278 /* Several target-specific internal interrupts. These differ from the
279 preceding target-specific interrupts in that they are intended to
280 originate from within the cpu itself, typically in response to some
281 instruction being executed. These, therefore, are not masked while
282 single-stepping within the debugger. */
283 #define CPU_INTERRUPT_TGT_INT_0 0x0100
284 #define CPU_INTERRUPT_TGT_INT_1 0x0800
285 #define CPU_INTERRUPT_TGT_INT_2 0x2000
287 /* First unused bit: 0x4000. */
289 /* The set of all bits that should be masked when single-stepping. */
290 #define CPU_INTERRUPT_SSTEP_MASK \
291 (CPU_INTERRUPT_HARD \
292 | CPU_INTERRUPT_TGT_EXT_0 \
293 | CPU_INTERRUPT_TGT_EXT_1 \
294 | CPU_INTERRUPT_TGT_EXT_2 \
295 | CPU_INTERRUPT_TGT_EXT_3 \
296 | CPU_INTERRUPT_TGT_EXT_4)
298 #if !defined(CONFIG_USER_ONLY)
302 typedef struct RAMBlock
{
303 struct MemoryRegion
*mr
;
309 /* Reads can take either the iothread or the ramlist lock.
310 * Writes must take both locks.
312 QTAILQ_ENTRY(RAMBlock
) next
;
316 typedef struct RAMList
{
318 /* Protected by the iothread lock. */
319 unsigned long *dirty_memory
[DIRTY_MEMORY_NUM
];
321 /* Protected by the ramlist lock. */
322 QTAILQ_HEAD(, RAMBlock
) blocks
;
325 extern RAMList ram_list
;
327 /* Flags stored in the low bits of the TLB virtual address. These are
328 defined so that fast path ram access is all zeros. */
329 /* Zero if TLB entry is valid. */
330 #define TLB_INVALID_MASK (1 << 3)
331 /* Set if TLB entry references a clean RAM page. The iotlb entry will
332 contain the page physical address. */
333 #define TLB_NOTDIRTY (1 << 4)
334 /* Set if TLB entry is an IO callback. */
335 #define TLB_MMIO (1 << 5)
337 void dump_exec_info(FILE *f
, fprintf_function cpu_fprintf
);
338 ram_addr_t
last_ram_offset(void);
339 void qemu_mutex_lock_ramlist(void);
340 void qemu_mutex_unlock_ramlist(void);
341 #endif /* !CONFIG_USER_ONLY */
343 int cpu_memory_rw_debug(CPUState
*cpu
, target_ulong addr
,
344 uint8_t *buf
, int len
, int is_write
);
346 #endif /* CPU_ALL_H */