Merge tag 'qemu-macppc-20230206' of https://github.com/mcayland/qemu into staging
[qemu.git] / include / exec / cpu-all.h
blob2eb11765380ce7602fbefa61ebedd0ff068681b4
1 /*
2 * defines common to all virtual CPUs
4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 #ifndef CPU_ALL_H
20 #define CPU_ALL_H
22 #include "exec/cpu-common.h"
23 #include "exec/memory.h"
24 #include "qemu/thread.h"
25 #include "hw/core/cpu.h"
26 #include "qemu/rcu.h"
28 #define EXCP_INTERRUPT 0x10000 /* async interruption */
29 #define EXCP_HLT 0x10001 /* hlt instruction reached */
30 #define EXCP_DEBUG 0x10002 /* cpu stopped after a breakpoint or singlestep */
31 #define EXCP_HALTED 0x10003 /* cpu is halted (waiting for external event) */
32 #define EXCP_YIELD 0x10004 /* cpu wants to yield timeslice to another */
33 #define EXCP_ATOMIC 0x10005 /* stop-the-world and emulate atomic */
35 /* some important defines:
37 * HOST_BIG_ENDIAN : whether the host cpu is big endian and
38 * otherwise little endian.
40 * TARGET_BIG_ENDIAN : same for the target cpu
43 #if HOST_BIG_ENDIAN != TARGET_BIG_ENDIAN
44 #define BSWAP_NEEDED
45 #endif
47 #ifdef BSWAP_NEEDED
49 static inline uint16_t tswap16(uint16_t s)
51 return bswap16(s);
54 static inline uint32_t tswap32(uint32_t s)
56 return bswap32(s);
59 static inline uint64_t tswap64(uint64_t s)
61 return bswap64(s);
64 static inline void tswap16s(uint16_t *s)
66 *s = bswap16(*s);
69 static inline void tswap32s(uint32_t *s)
71 *s = bswap32(*s);
74 static inline void tswap64s(uint64_t *s)
76 *s = bswap64(*s);
79 #else
81 static inline uint16_t tswap16(uint16_t s)
83 return s;
86 static inline uint32_t tswap32(uint32_t s)
88 return s;
91 static inline uint64_t tswap64(uint64_t s)
93 return s;
96 static inline void tswap16s(uint16_t *s)
100 static inline void tswap32s(uint32_t *s)
104 static inline void tswap64s(uint64_t *s)
108 #endif
110 #if TARGET_LONG_SIZE == 4
111 #define tswapl(s) tswap32(s)
112 #define tswapls(s) tswap32s((uint32_t *)(s))
113 #define bswaptls(s) bswap32s(s)
114 #else
115 #define tswapl(s) tswap64(s)
116 #define tswapls(s) tswap64s((uint64_t *)(s))
117 #define bswaptls(s) bswap64s(s)
118 #endif
120 /* Target-endianness CPU memory access functions. These fit into the
121 * {ld,st}{type}{sign}{size}{endian}_p naming scheme described in bswap.h.
123 #if TARGET_BIG_ENDIAN
124 #define lduw_p(p) lduw_be_p(p)
125 #define ldsw_p(p) ldsw_be_p(p)
126 #define ldl_p(p) ldl_be_p(p)
127 #define ldq_p(p) ldq_be_p(p)
128 #define stw_p(p, v) stw_be_p(p, v)
129 #define stl_p(p, v) stl_be_p(p, v)
130 #define stq_p(p, v) stq_be_p(p, v)
131 #define ldn_p(p, sz) ldn_be_p(p, sz)
132 #define stn_p(p, sz, v) stn_be_p(p, sz, v)
133 #else
134 #define lduw_p(p) lduw_le_p(p)
135 #define ldsw_p(p) ldsw_le_p(p)
136 #define ldl_p(p) ldl_le_p(p)
137 #define ldq_p(p) ldq_le_p(p)
138 #define stw_p(p, v) stw_le_p(p, v)
139 #define stl_p(p, v) stl_le_p(p, v)
140 #define stq_p(p, v) stq_le_p(p, v)
141 #define ldn_p(p, sz) ldn_le_p(p, sz)
142 #define stn_p(p, sz, v) stn_le_p(p, sz, v)
143 #endif
145 /* MMU memory access macros */
147 #if defined(CONFIG_USER_ONLY)
148 #include "exec/user/abitypes.h"
150 /* On some host systems the guest address space is reserved on the host.
151 * This allows the guest address space to be offset to a convenient location.
153 extern uintptr_t guest_base;
154 extern bool have_guest_base;
155 extern unsigned long reserved_va;
158 * Limit the guest addresses as best we can.
160 * When not using -R reserved_va, we cannot really limit the guest
161 * to less address space than the host. For 32-bit guests, this
162 * acts as a sanity check that we're not giving the guest an address
163 * that it cannot even represent. For 64-bit guests... the address
164 * might not be what the real kernel would give, but it is at least
165 * representable in the guest.
167 * TODO: Improve address allocation to avoid this problem, and to
168 * avoid setting bits at the top of guest addresses that might need
169 * to be used for tags.
171 #define GUEST_ADDR_MAX_ \
172 ((MIN_CONST(TARGET_VIRT_ADDR_SPACE_BITS, TARGET_ABI_BITS) <= 32) ? \
173 UINT32_MAX : ~0ul)
174 #define GUEST_ADDR_MAX (reserved_va ? reserved_va - 1 : GUEST_ADDR_MAX_)
176 #else
178 #include "exec/hwaddr.h"
180 #define SUFFIX
181 #define ARG1 as
182 #define ARG1_DECL AddressSpace *as
183 #define TARGET_ENDIANNESS
184 #include "exec/memory_ldst.h.inc"
186 #define SUFFIX _cached_slow
187 #define ARG1 cache
188 #define ARG1_DECL MemoryRegionCache *cache
189 #define TARGET_ENDIANNESS
190 #include "exec/memory_ldst.h.inc"
192 static inline void stl_phys_notdirty(AddressSpace *as, hwaddr addr, uint32_t val)
194 address_space_stl_notdirty(as, addr, val,
195 MEMTXATTRS_UNSPECIFIED, NULL);
198 #define SUFFIX
199 #define ARG1 as
200 #define ARG1_DECL AddressSpace *as
201 #define TARGET_ENDIANNESS
202 #include "exec/memory_ldst_phys.h.inc"
204 /* Inline fast path for direct RAM access. */
205 #define ENDIANNESS
206 #include "exec/memory_ldst_cached.h.inc"
208 #define SUFFIX _cached
209 #define ARG1 cache
210 #define ARG1_DECL MemoryRegionCache *cache
211 #define TARGET_ENDIANNESS
212 #include "exec/memory_ldst_phys.h.inc"
213 #endif
215 /* page related stuff */
217 #ifdef TARGET_PAGE_BITS_VARY
218 # include "exec/page-vary.h"
219 extern const TargetPageBits target_page;
220 #ifdef CONFIG_DEBUG_TCG
221 #define TARGET_PAGE_BITS ({ assert(target_page.decided); target_page.bits; })
222 #define TARGET_PAGE_MASK ({ assert(target_page.decided); \
223 (target_long)target_page.mask; })
224 #else
225 #define TARGET_PAGE_BITS target_page.bits
226 #define TARGET_PAGE_MASK ((target_long)target_page.mask)
227 #endif
228 #define TARGET_PAGE_SIZE (-(int)TARGET_PAGE_MASK)
229 #else
230 #define TARGET_PAGE_BITS_MIN TARGET_PAGE_BITS
231 #define TARGET_PAGE_SIZE (1 << TARGET_PAGE_BITS)
232 #define TARGET_PAGE_MASK ((target_long)-1 << TARGET_PAGE_BITS)
233 #endif
235 #define TARGET_PAGE_ALIGN(addr) ROUND_UP((addr), TARGET_PAGE_SIZE)
237 /* same as PROT_xxx */
238 #define PAGE_READ 0x0001
239 #define PAGE_WRITE 0x0002
240 #define PAGE_EXEC 0x0004
241 #define PAGE_BITS (PAGE_READ | PAGE_WRITE | PAGE_EXEC)
242 #define PAGE_VALID 0x0008
244 * Original state of the write flag (used when tracking self-modifying code)
246 #define PAGE_WRITE_ORG 0x0010
248 * Invalidate the TLB entry immediately, helpful for s390x
249 * Low-Address-Protection. Used with PAGE_WRITE in tlb_set_page_with_attrs()
251 #define PAGE_WRITE_INV 0x0020
252 /* For use with page_set_flags: page is being replaced; target_data cleared. */
253 #define PAGE_RESET 0x0040
254 /* For linux-user, indicates that the page is MAP_ANON. */
255 #define PAGE_ANON 0x0080
257 #if defined(CONFIG_BSD) && defined(CONFIG_USER_ONLY)
258 /* FIXME: Code that sets/uses this is broken and needs to go away. */
259 #define PAGE_RESERVED 0x0100
260 #endif
261 /* Target-specific bits that will be used via page_get_flags(). */
262 #define PAGE_TARGET_1 0x0200
263 #define PAGE_TARGET_2 0x0400
266 * For linux-user, indicates that the page is mapped with the same semantics
267 * in both guest and host.
269 #define PAGE_PASSTHROUGH 0x0800
271 #if defined(CONFIG_USER_ONLY)
272 void page_dump(FILE *f);
274 typedef int (*walk_memory_regions_fn)(void *, target_ulong,
275 target_ulong, unsigned long);
276 int walk_memory_regions(void *, walk_memory_regions_fn);
278 int page_get_flags(target_ulong address);
279 void page_set_flags(target_ulong start, target_ulong end, int flags);
280 void page_reset_target_data(target_ulong start, target_ulong end);
281 int page_check_range(target_ulong start, target_ulong len, int flags);
284 * page_get_target_data(address)
285 * @address: guest virtual address
287 * Return TARGET_PAGE_DATA_SIZE bytes of out-of-band data to associate
288 * with the guest page at @address, allocating it if necessary. The
289 * caller should already have verified that the address is valid.
291 * The memory will be freed when the guest page is deallocated,
292 * e.g. with the munmap system call.
294 void *page_get_target_data(target_ulong address)
295 __attribute__((returns_nonnull));
296 #endif
298 CPUArchState *cpu_copy(CPUArchState *env);
300 /* Flags for use in ENV->INTERRUPT_PENDING.
302 The numbers assigned here are non-sequential in order to preserve
303 binary compatibility with the vmstate dump. Bit 0 (0x0001) was
304 previously used for CPU_INTERRUPT_EXIT, and is cleared when loading
305 the vmstate dump. */
307 /* External hardware interrupt pending. This is typically used for
308 interrupts from devices. */
309 #define CPU_INTERRUPT_HARD 0x0002
311 /* Exit the current TB. This is typically used when some system-level device
312 makes some change to the memory mapping. E.g. the a20 line change. */
313 #define CPU_INTERRUPT_EXITTB 0x0004
315 /* Halt the CPU. */
316 #define CPU_INTERRUPT_HALT 0x0020
318 /* Debug event pending. */
319 #define CPU_INTERRUPT_DEBUG 0x0080
321 /* Reset signal. */
322 #define CPU_INTERRUPT_RESET 0x0400
324 /* Several target-specific external hardware interrupts. Each target/cpu.h
325 should define proper names based on these defines. */
326 #define CPU_INTERRUPT_TGT_EXT_0 0x0008
327 #define CPU_INTERRUPT_TGT_EXT_1 0x0010
328 #define CPU_INTERRUPT_TGT_EXT_2 0x0040
329 #define CPU_INTERRUPT_TGT_EXT_3 0x0200
330 #define CPU_INTERRUPT_TGT_EXT_4 0x1000
332 /* Several target-specific internal interrupts. These differ from the
333 preceding target-specific interrupts in that they are intended to
334 originate from within the cpu itself, typically in response to some
335 instruction being executed. These, therefore, are not masked while
336 single-stepping within the debugger. */
337 #define CPU_INTERRUPT_TGT_INT_0 0x0100
338 #define CPU_INTERRUPT_TGT_INT_1 0x0800
339 #define CPU_INTERRUPT_TGT_INT_2 0x2000
341 /* First unused bit: 0x4000. */
343 /* The set of all bits that should be masked when single-stepping. */
344 #define CPU_INTERRUPT_SSTEP_MASK \
345 (CPU_INTERRUPT_HARD \
346 | CPU_INTERRUPT_TGT_EXT_0 \
347 | CPU_INTERRUPT_TGT_EXT_1 \
348 | CPU_INTERRUPT_TGT_EXT_2 \
349 | CPU_INTERRUPT_TGT_EXT_3 \
350 | CPU_INTERRUPT_TGT_EXT_4)
352 #ifdef CONFIG_USER_ONLY
355 * Allow some level of source compatibility with softmmu. We do not
356 * support any of the more exotic features, so only invalid pages may
357 * be signaled by probe_access_flags().
359 #define TLB_INVALID_MASK (1 << (TARGET_PAGE_BITS_MIN - 1))
360 #define TLB_MMIO 0
361 #define TLB_WATCHPOINT 0
363 #else
366 * Flags stored in the low bits of the TLB virtual address.
367 * These are defined so that fast path ram access is all zeros.
368 * The flags all must be between TARGET_PAGE_BITS and
369 * maximum address alignment bit.
371 * Use TARGET_PAGE_BITS_MIN so that these bits are constant
372 * when TARGET_PAGE_BITS_VARY is in effect.
374 /* Zero if TLB entry is valid. */
375 #define TLB_INVALID_MASK (1 << (TARGET_PAGE_BITS_MIN - 1))
376 /* Set if TLB entry references a clean RAM page. The iotlb entry will
377 contain the page physical address. */
378 #define TLB_NOTDIRTY (1 << (TARGET_PAGE_BITS_MIN - 2))
379 /* Set if TLB entry is an IO callback. */
380 #define TLB_MMIO (1 << (TARGET_PAGE_BITS_MIN - 3))
381 /* Set if TLB entry contains a watchpoint. */
382 #define TLB_WATCHPOINT (1 << (TARGET_PAGE_BITS_MIN - 4))
383 /* Set if TLB entry requires byte swap. */
384 #define TLB_BSWAP (1 << (TARGET_PAGE_BITS_MIN - 5))
385 /* Set if TLB entry writes ignored. */
386 #define TLB_DISCARD_WRITE (1 << (TARGET_PAGE_BITS_MIN - 6))
388 /* Use this mask to check interception with an alignment mask
389 * in a TCG backend.
391 #define TLB_FLAGS_MASK \
392 (TLB_INVALID_MASK | TLB_NOTDIRTY | TLB_MMIO \
393 | TLB_WATCHPOINT | TLB_BSWAP | TLB_DISCARD_WRITE)
396 * tlb_hit_page: return true if page aligned @addr is a hit against the
397 * TLB entry @tlb_addr
399 * @addr: virtual address to test (must be page aligned)
400 * @tlb_addr: TLB entry address (a CPUTLBEntry addr_read/write/code value)
402 static inline bool tlb_hit_page(target_ulong tlb_addr, target_ulong addr)
404 return addr == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK));
408 * tlb_hit: return true if @addr is a hit against the TLB entry @tlb_addr
410 * @addr: virtual address to test (need not be page aligned)
411 * @tlb_addr: TLB entry address (a CPUTLBEntry addr_read/write/code value)
413 static inline bool tlb_hit(target_ulong tlb_addr, target_ulong addr)
415 return tlb_hit_page(tlb_addr, addr & TARGET_PAGE_MASK);
418 #ifdef CONFIG_TCG
419 /* accel/tcg/translate-all.c */
420 void dump_exec_info(GString *buf);
421 #endif /* CONFIG_TCG */
423 #endif /* !CONFIG_USER_ONLY */
425 /* accel/tcg/cpu-exec.c */
426 int cpu_exec(CPUState *cpu);
427 void tcg_exec_realizefn(CPUState *cpu, Error **errp);
428 void tcg_exec_unrealizefn(CPUState *cpu);
431 * cpu_set_cpustate_pointers(cpu)
432 * @cpu: The cpu object
434 * Set the generic pointers in CPUState into the outer object.
436 static inline void cpu_set_cpustate_pointers(ArchCPU *cpu)
438 cpu->parent_obj.env_ptr = &cpu->env;
439 cpu->parent_obj.icount_decr_ptr = &cpu->neg.icount_decr;
443 * env_archcpu(env)
444 * @env: The architecture environment
446 * Return the ArchCPU associated with the environment.
448 static inline ArchCPU *env_archcpu(CPUArchState *env)
450 return container_of(env, ArchCPU, env);
454 * env_cpu(env)
455 * @env: The architecture environment
457 * Return the CPUState associated with the environment.
459 static inline CPUState *env_cpu(CPUArchState *env)
461 return &env_archcpu(env)->parent_obj;
465 * env_neg(env)
466 * @env: The architecture environment
468 * Return the CPUNegativeOffsetState associated with the environment.
470 static inline CPUNegativeOffsetState *env_neg(CPUArchState *env)
472 ArchCPU *arch_cpu = container_of(env, ArchCPU, env);
473 return &arch_cpu->neg;
477 * cpu_neg(cpu)
478 * @cpu: The generic CPUState
480 * Return the CPUNegativeOffsetState associated with the cpu.
482 static inline CPUNegativeOffsetState *cpu_neg(CPUState *cpu)
484 ArchCPU *arch_cpu = container_of(cpu, ArchCPU, parent_obj);
485 return &arch_cpu->neg;
489 * env_tlb(env)
490 * @env: The architecture environment
492 * Return the CPUTLB state associated with the environment.
494 static inline CPUTLB *env_tlb(CPUArchState *env)
496 return &env_neg(env)->tlb;
499 #endif /* CPU_ALL_H */