4 * Copyright (c) 2009 Isaku Yamahata <yamahata at valinux co jp>
5 * VA Linux Systems Japan K.K.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, see <http://www.gnu.org/licenses/>.
21 #include "qemu/osdep.h"
22 #include "hw/pci/pci.h"
23 #include "hw/pci/pci_bridge.h"
24 #include "hw/pci/pci_host.h"
25 #include "qemu/module.h"
26 #include "hw/pci/pci_bus.h"
33 #define PCI_DPRINTF(fmt, ...) \
34 do { printf("pci_host_data: " fmt , ## __VA_ARGS__); } while (0)
36 #define PCI_DPRINTF(fmt, ...)
41 * bit 16 - 24: bus number
42 * bit 8 - 15: devfun number
43 * bit 0 - 7: offset in configuration space of a given pci device
46 /* the helper function to get a PCIDevice* for a given pci address */
47 static inline PCIDevice
*pci_dev_find_by_addr(PCIBus
*bus
, uint32_t addr
)
49 uint8_t bus_num
= addr
>> 16;
50 uint8_t devfn
= addr
>> 8;
52 return pci_find_device(bus
, bus_num
, devfn
);
55 static void pci_adjust_config_limit(PCIBus
*bus
, uint32_t *limit
)
57 if ((*limit
> PCI_CONFIG_SPACE_SIZE
) &&
58 !pci_bus_allows_extended_config_space(bus
)) {
59 *limit
= PCI_CONFIG_SPACE_SIZE
;
63 void pci_host_config_write_common(PCIDevice
*pci_dev
, uint32_t addr
,
64 uint32_t limit
, uint32_t val
, uint32_t len
)
66 pci_adjust_config_limit(pci_get_bus(pci_dev
), &limit
);
72 /* non-zero functions are only exposed when function 0 is present,
73 * allowing direct removal of unexposed functions.
75 if (pci_dev
->qdev
.hotplugged
&& !pci_get_function_0(pci_dev
)) {
79 trace_pci_cfg_write(pci_dev
->name
, PCI_SLOT(pci_dev
->devfn
),
80 PCI_FUNC(pci_dev
->devfn
), addr
, val
);
81 pci_dev
->config_write(pci_dev
, addr
, val
, MIN(len
, limit
- addr
));
84 uint32_t pci_host_config_read_common(PCIDevice
*pci_dev
, uint32_t addr
,
85 uint32_t limit
, uint32_t len
)
89 pci_adjust_config_limit(pci_get_bus(pci_dev
), &limit
);
95 /* non-zero functions are only exposed when function 0 is present,
96 * allowing direct removal of unexposed functions.
98 if (pci_dev
->qdev
.hotplugged
&& !pci_get_function_0(pci_dev
)) {
102 ret
= pci_dev
->config_read(pci_dev
, addr
, MIN(len
, limit
- addr
));
103 trace_pci_cfg_read(pci_dev
->name
, PCI_SLOT(pci_dev
->devfn
),
104 PCI_FUNC(pci_dev
->devfn
), addr
, ret
);
109 void pci_data_write(PCIBus
*s
, uint32_t addr
, uint32_t val
, int len
)
111 PCIDevice
*pci_dev
= pci_dev_find_by_addr(s
, addr
);
112 uint32_t config_addr
= addr
& (PCI_CONFIG_SPACE_SIZE
- 1);
118 PCI_DPRINTF("%s: %s: addr=%02" PRIx32
" val=%08" PRIx32
" len=%d\n",
119 __func__
, pci_dev
->name
, config_addr
, val
, len
);
120 pci_host_config_write_common(pci_dev
, config_addr
, PCI_CONFIG_SPACE_SIZE
,
124 uint32_t pci_data_read(PCIBus
*s
, uint32_t addr
, int len
)
126 PCIDevice
*pci_dev
= pci_dev_find_by_addr(s
, addr
);
127 uint32_t config_addr
= addr
& (PCI_CONFIG_SPACE_SIZE
- 1);
134 val
= pci_host_config_read_common(pci_dev
, config_addr
,
135 PCI_CONFIG_SPACE_SIZE
, len
);
136 PCI_DPRINTF("%s: %s: addr=%02"PRIx32
" val=%08"PRIx32
" len=%d\n",
137 __func__
, pci_dev
->name
, config_addr
, val
, len
);
142 static void pci_host_config_write(void *opaque
, hwaddr addr
,
143 uint64_t val
, unsigned len
)
145 PCIHostState
*s
= opaque
;
147 PCI_DPRINTF("%s addr " TARGET_FMT_plx
" len %d val %"PRIx64
"\n",
148 __func__
, addr
, len
, val
);
149 if (addr
!= 0 || len
!= 4) {
155 static uint64_t pci_host_config_read(void *opaque
, hwaddr addr
,
158 PCIHostState
*s
= opaque
;
159 uint32_t val
= s
->config_reg
;
161 PCI_DPRINTF("%s addr " TARGET_FMT_plx
" len %d val %"PRIx32
"\n",
162 __func__
, addr
, len
, val
);
166 static void pci_host_data_write(void *opaque
, hwaddr addr
,
167 uint64_t val
, unsigned len
)
169 PCIHostState
*s
= opaque
;
170 PCI_DPRINTF("write addr " TARGET_FMT_plx
" len %d val %x\n",
171 addr
, len
, (unsigned)val
);
172 if (s
->config_reg
& (1u << 31))
173 pci_data_write(s
->bus
, s
->config_reg
| (addr
& 3), val
, len
);
176 static uint64_t pci_host_data_read(void *opaque
,
177 hwaddr addr
, unsigned len
)
179 PCIHostState
*s
= opaque
;
181 if (!(s
->config_reg
& (1U << 31))) {
184 val
= pci_data_read(s
->bus
, s
->config_reg
| (addr
& 3), len
);
185 PCI_DPRINTF("read addr " TARGET_FMT_plx
" len %d val %x\n",
190 const MemoryRegionOps pci_host_conf_le_ops
= {
191 .read
= pci_host_config_read
,
192 .write
= pci_host_config_write
,
193 .endianness
= DEVICE_LITTLE_ENDIAN
,
196 const MemoryRegionOps pci_host_conf_be_ops
= {
197 .read
= pci_host_config_read
,
198 .write
= pci_host_config_write
,
199 .endianness
= DEVICE_BIG_ENDIAN
,
202 const MemoryRegionOps pci_host_data_le_ops
= {
203 .read
= pci_host_data_read
,
204 .write
= pci_host_data_write
,
205 .endianness
= DEVICE_LITTLE_ENDIAN
,
208 const MemoryRegionOps pci_host_data_be_ops
= {
209 .read
= pci_host_data_read
,
210 .write
= pci_host_data_write
,
211 .endianness
= DEVICE_BIG_ENDIAN
,
214 static const TypeInfo pci_host_type_info
= {
215 .name
= TYPE_PCI_HOST_BRIDGE
,
216 .parent
= TYPE_SYS_BUS_DEVICE
,
218 .class_size
= sizeof(PCIHostBridgeClass
),
219 .instance_size
= sizeof(PCIHostState
),
222 static void pci_host_register_types(void)
224 type_register_static(&pci_host_type_info
);
227 type_init(pci_host_register_types
)