Merge tag 'qemu-macppc-20230206' of https://github.com/mcayland/qemu into staging
[qemu.git] / hw / pci / pci_host.c
blobdfd185bbb449b18e4d3290a2280cbb5cb250c11f
1 /*
2 * pci_host.c
4 * Copyright (c) 2009 Isaku Yamahata <yamahata at valinux co jp>
5 * VA Linux Systems Japan K.K.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, see <http://www.gnu.org/licenses/>.
21 #include "qemu/osdep.h"
22 #include "hw/pci/pci.h"
23 #include "hw/pci/pci_bridge.h"
24 #include "hw/pci/pci_host.h"
25 #include "hw/qdev-properties.h"
26 #include "qemu/module.h"
27 #include "hw/pci/pci_bus.h"
28 #include "migration/vmstate.h"
29 #include "trace.h"
31 /* debug PCI */
32 //#define DEBUG_PCI
34 #ifdef DEBUG_PCI
35 #define PCI_DPRINTF(fmt, ...) \
36 do { printf("pci_host_data: " fmt , ## __VA_ARGS__); } while (0)
37 #else
38 #define PCI_DPRINTF(fmt, ...)
39 #endif
42 * PCI address
43 * bit 16 - 24: bus number
44 * bit 8 - 15: devfun number
45 * bit 0 - 7: offset in configuration space of a given pci device
48 /* the helper function to get a PCIDevice* for a given pci address */
49 static inline PCIDevice *pci_dev_find_by_addr(PCIBus *bus, uint32_t addr)
51 uint8_t bus_num = addr >> 16;
52 uint8_t devfn = addr >> 8;
54 return pci_find_device(bus, bus_num, devfn);
57 static void pci_adjust_config_limit(PCIBus *bus, uint32_t *limit)
59 if ((*limit > PCI_CONFIG_SPACE_SIZE) &&
60 !pci_bus_allows_extended_config_space(bus)) {
61 *limit = PCI_CONFIG_SPACE_SIZE;
65 void pci_host_config_write_common(PCIDevice *pci_dev, uint32_t addr,
66 uint32_t limit, uint32_t val, uint32_t len)
68 pci_adjust_config_limit(pci_get_bus(pci_dev), &limit);
69 if (limit <= addr) {
70 return;
73 assert(len <= 4);
74 /* non-zero functions are only exposed when function 0 is present,
75 * allowing direct removal of unexposed functions.
77 if ((pci_dev->qdev.hotplugged && !pci_get_function_0(pci_dev)) ||
78 !pci_dev->has_power) {
79 return;
82 trace_pci_cfg_write(pci_dev->name, pci_dev_bus_num(pci_dev),
83 PCI_SLOT(pci_dev->devfn),
84 PCI_FUNC(pci_dev->devfn), addr, val);
85 pci_dev->config_write(pci_dev, addr, val, MIN(len, limit - addr));
88 uint32_t pci_host_config_read_common(PCIDevice *pci_dev, uint32_t addr,
89 uint32_t limit, uint32_t len)
91 uint32_t ret;
93 pci_adjust_config_limit(pci_get_bus(pci_dev), &limit);
94 if (limit <= addr) {
95 return ~0x0;
98 assert(len <= 4);
99 /* non-zero functions are only exposed when function 0 is present,
100 * allowing direct removal of unexposed functions.
102 if ((pci_dev->qdev.hotplugged && !pci_get_function_0(pci_dev)) ||
103 !pci_dev->has_power) {
104 return ~0x0;
107 ret = pci_dev->config_read(pci_dev, addr, MIN(len, limit - addr));
108 trace_pci_cfg_read(pci_dev->name, pci_dev_bus_num(pci_dev),
109 PCI_SLOT(pci_dev->devfn),
110 PCI_FUNC(pci_dev->devfn), addr, ret);
112 return ret;
115 void pci_data_write(PCIBus *s, uint32_t addr, uint32_t val, unsigned len)
117 PCIDevice *pci_dev = pci_dev_find_by_addr(s, addr);
118 uint32_t config_addr = addr & (PCI_CONFIG_SPACE_SIZE - 1);
120 if (!pci_dev) {
121 trace_pci_cfg_write("empty", extract32(addr, 16, 8),
122 extract32(addr, 11, 5), extract32(addr, 8, 3),
123 config_addr, val);
124 return;
127 pci_host_config_write_common(pci_dev, config_addr, PCI_CONFIG_SPACE_SIZE,
128 val, len);
131 uint32_t pci_data_read(PCIBus *s, uint32_t addr, unsigned len)
133 PCIDevice *pci_dev = pci_dev_find_by_addr(s, addr);
134 uint32_t config_addr = addr & (PCI_CONFIG_SPACE_SIZE - 1);
136 if (!pci_dev) {
137 trace_pci_cfg_read("empty", extract32(addr, 16, 8),
138 extract32(addr, 11, 5), extract32(addr, 8, 3),
139 config_addr, ~0x0);
140 return ~0x0;
143 return pci_host_config_read_common(pci_dev, config_addr,
144 PCI_CONFIG_SPACE_SIZE, len);
147 static void pci_host_config_write(void *opaque, hwaddr addr,
148 uint64_t val, unsigned len)
150 PCIHostState *s = opaque;
152 PCI_DPRINTF("%s addr " HWADDR_FMT_plx " len %d val %"PRIx64"\n",
153 __func__, addr, len, val);
154 if (addr != 0 || len != 4) {
155 return;
157 s->config_reg = val;
160 static uint64_t pci_host_config_read(void *opaque, hwaddr addr,
161 unsigned len)
163 PCIHostState *s = opaque;
164 uint32_t val = s->config_reg;
166 PCI_DPRINTF("%s addr " HWADDR_FMT_plx " len %d val %"PRIx32"\n",
167 __func__, addr, len, val);
168 return val;
171 static void pci_host_data_write(void *opaque, hwaddr addr,
172 uint64_t val, unsigned len)
174 PCIHostState *s = opaque;
176 if (s->config_reg & (1u << 31))
177 pci_data_write(s->bus, s->config_reg | (addr & 3), val, len);
180 static uint64_t pci_host_data_read(void *opaque,
181 hwaddr addr, unsigned len)
183 PCIHostState *s = opaque;
185 if (!(s->config_reg & (1U << 31))) {
186 return 0xffffffff;
188 return pci_data_read(s->bus, s->config_reg | (addr & 3), len);
191 const MemoryRegionOps pci_host_conf_le_ops = {
192 .read = pci_host_config_read,
193 .write = pci_host_config_write,
194 .endianness = DEVICE_LITTLE_ENDIAN,
197 const MemoryRegionOps pci_host_conf_be_ops = {
198 .read = pci_host_config_read,
199 .write = pci_host_config_write,
200 .endianness = DEVICE_BIG_ENDIAN,
203 const MemoryRegionOps pci_host_data_le_ops = {
204 .read = pci_host_data_read,
205 .write = pci_host_data_write,
206 .endianness = DEVICE_LITTLE_ENDIAN,
209 const MemoryRegionOps pci_host_data_be_ops = {
210 .read = pci_host_data_read,
211 .write = pci_host_data_write,
212 .endianness = DEVICE_BIG_ENDIAN,
215 static bool pci_host_needed(void *opaque)
217 PCIHostState *s = opaque;
218 return s->mig_enabled;
221 const VMStateDescription vmstate_pcihost = {
222 .name = "PCIHost",
223 .needed = pci_host_needed,
224 .version_id = 1,
225 .minimum_version_id = 1,
226 .fields = (VMStateField[]) {
227 VMSTATE_UINT32(config_reg, PCIHostState),
228 VMSTATE_END_OF_LIST()
232 static Property pci_host_properties_common[] = {
233 DEFINE_PROP_BOOL("x-config-reg-migration-enabled", PCIHostState,
234 mig_enabled, true),
235 DEFINE_PROP_BOOL("bypass-iommu", PCIHostState, bypass_iommu, false),
236 DEFINE_PROP_END_OF_LIST(),
239 static void pci_host_class_init(ObjectClass *klass, void *data)
241 DeviceClass *dc = DEVICE_CLASS(klass);
242 device_class_set_props(dc, pci_host_properties_common);
243 dc->vmsd = &vmstate_pcihost;
246 static const TypeInfo pci_host_type_info = {
247 .name = TYPE_PCI_HOST_BRIDGE,
248 .parent = TYPE_SYS_BUS_DEVICE,
249 .abstract = true,
250 .class_size = sizeof(PCIHostBridgeClass),
251 .instance_size = sizeof(PCIHostState),
252 .class_init = pci_host_class_init,
255 static void pci_host_register_types(void)
257 type_register_static(&pci_host_type_info);
260 type_init(pci_host_register_types)