2 * QEMU PowerPC XIVE2 interrupt controller model (POWER10)
4 * Copyright (c) 2019-2022, IBM Corporation..
6 * This code is licensed under the GPL version 2 or later. See the
7 * COPYING file in the top-level directory.
10 #include "qemu/osdep.h"
12 #include "qemu/module.h"
13 #include "qapi/error.h"
14 #include "target/ppc/cpu.h"
15 #include "sysemu/cpus.h"
16 #include "sysemu/dma.h"
17 #include "hw/qdev-properties.h"
18 #include "monitor/monitor.h"
19 #include "hw/ppc/xive.h"
20 #include "hw/ppc/xive2.h"
21 #include "hw/ppc/xive2_regs.h"
23 void xive2_eas_pic_print_info(Xive2Eas
*eas
, uint32_t lisn
, Monitor
*mon
)
25 if (!xive2_eas_is_valid(eas
)) {
29 monitor_printf(mon
, " %08x %s end:%02x/%04x data:%08x\n",
30 lisn
, xive2_eas_is_masked(eas
) ? "M" : " ",
31 (uint8_t) xive_get_field64(EAS2_END_BLOCK
, eas
->w
),
32 (uint32_t) xive_get_field64(EAS2_END_INDEX
, eas
->w
),
33 (uint32_t) xive_get_field64(EAS2_END_DATA
, eas
->w
));
36 void xive2_end_queue_pic_print_info(Xive2End
*end
, uint32_t width
,
39 uint64_t qaddr_base
= xive2_end_qaddr(end
);
40 uint32_t qsize
= xive_get_field32(END2_W3_QSIZE
, end
->w3
);
41 uint32_t qindex
= xive_get_field32(END2_W1_PAGE_OFF
, end
->w1
);
42 uint32_t qentries
= 1 << (qsize
+ 10);
46 * print out the [ (qindex - (width - 1)) .. (qindex + 1)] window
48 monitor_printf(mon
, " [ ");
49 qindex
= (qindex
- (width
- 1)) & (qentries
- 1);
50 for (i
= 0; i
< width
; i
++) {
51 uint64_t qaddr
= qaddr_base
+ (qindex
<< 2);
54 if (dma_memory_read(&address_space_memory
, qaddr
, &qdata
,
55 sizeof(qdata
), MEMTXATTRS_UNSPECIFIED
)) {
56 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: failed to read EQ @0x%"
57 HWADDR_PRIx
"\n", qaddr
);
60 monitor_printf(mon
, "%s%08x ", i
== width
- 1 ? "^" : "",
62 qindex
= (qindex
+ 1) & (qentries
- 1);
64 monitor_printf(mon
, "]");
67 void xive2_end_pic_print_info(Xive2End
*end
, uint32_t end_idx
, Monitor
*mon
)
69 uint64_t qaddr_base
= xive2_end_qaddr(end
);
70 uint32_t qindex
= xive_get_field32(END2_W1_PAGE_OFF
, end
->w1
);
71 uint32_t qgen
= xive_get_field32(END2_W1_GENERATION
, end
->w1
);
72 uint32_t qsize
= xive_get_field32(END2_W3_QSIZE
, end
->w3
);
73 uint32_t qentries
= 1 << (qsize
+ 10);
75 uint32_t nvp_blk
= xive_get_field32(END2_W6_VP_BLOCK
, end
->w6
);
76 uint32_t nvp_idx
= xive_get_field32(END2_W6_VP_OFFSET
, end
->w6
);
77 uint8_t priority
= xive_get_field32(END2_W7_F0_PRIORITY
, end
->w7
);
80 if (!xive2_end_is_valid(end
)) {
84 pq
= xive_get_field32(END2_W1_ESn
, end
->w1
);
87 " %08x %c%c %c%c%c%c%c%c%c%c%c%c prio:%d nvp:%02x/%04x",
89 pq
& XIVE_ESB_VAL_P
? 'P' : '-',
90 pq
& XIVE_ESB_VAL_Q
? 'Q' : '-',
91 xive2_end_is_valid(end
) ? 'v' : '-',
92 xive2_end_is_enqueue(end
) ? 'q' : '-',
93 xive2_end_is_notify(end
) ? 'n' : '-',
94 xive2_end_is_backlog(end
) ? 'b' : '-',
95 xive2_end_is_escalate(end
) ? 'e' : '-',
96 xive2_end_is_escalate_end(end
) ? 'N' : '-',
97 xive2_end_is_uncond_escalation(end
) ? 'u' : '-',
98 xive2_end_is_silent_escalation(end
) ? 's' : '-',
99 xive2_end_is_firmware1(end
) ? 'f' : '-',
100 xive2_end_is_firmware2(end
) ? 'F' : '-',
101 priority
, nvp_blk
, nvp_idx
);
104 monitor_printf(mon
, " eq:@%08"PRIx64
"% 6d/%5d ^%d",
105 qaddr_base
, qindex
, qentries
, qgen
);
106 xive2_end_queue_pic_print_info(end
, 6, mon
);
108 monitor_printf(mon
, "\n");
111 void xive2_end_eas_pic_print_info(Xive2End
*end
, uint32_t end_idx
,
114 Xive2Eas
*eas
= (Xive2Eas
*) &end
->w4
;
117 if (!xive2_end_is_escalate(end
)) {
121 pq
= xive_get_field32(END2_W1_ESe
, end
->w1
);
123 monitor_printf(mon
, " %08x %c%c %c%c end:%02x/%04x data:%08x\n",
125 pq
& XIVE_ESB_VAL_P
? 'P' : '-',
126 pq
& XIVE_ESB_VAL_Q
? 'Q' : '-',
127 xive2_eas_is_valid(eas
) ? 'v' : ' ',
128 xive2_eas_is_masked(eas
) ? 'M' : ' ',
129 (uint8_t) xive_get_field64(EAS2_END_BLOCK
, eas
->w
),
130 (uint32_t) xive_get_field64(EAS2_END_INDEX
, eas
->w
),
131 (uint32_t) xive_get_field64(EAS2_END_DATA
, eas
->w
));
134 static void xive2_end_enqueue(Xive2End
*end
, uint32_t data
)
136 uint64_t qaddr_base
= xive2_end_qaddr(end
);
137 uint32_t qsize
= xive_get_field32(END2_W3_QSIZE
, end
->w3
);
138 uint32_t qindex
= xive_get_field32(END2_W1_PAGE_OFF
, end
->w1
);
139 uint32_t qgen
= xive_get_field32(END2_W1_GENERATION
, end
->w1
);
141 uint64_t qaddr
= qaddr_base
+ (qindex
<< 2);
142 uint32_t qdata
= cpu_to_be32((qgen
<< 31) | (data
& 0x7fffffff));
143 uint32_t qentries
= 1 << (qsize
+ 10);
145 if (dma_memory_write(&address_space_memory
, qaddr
, &qdata
, sizeof(qdata
),
146 MEMTXATTRS_UNSPECIFIED
)) {
147 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: failed to write END data @0x%"
148 HWADDR_PRIx
"\n", qaddr
);
152 qindex
= (qindex
+ 1) & (qentries
- 1);
155 end
->w1
= xive_set_field32(END2_W1_GENERATION
, end
->w1
, qgen
);
157 /* TODO(PowerNV): reset GF bit on a cache watch operation */
158 end
->w1
= xive_set_field32(END2_W1_GEN_FLIPPED
, end
->w1
, qgen
);
160 end
->w1
= xive_set_field32(END2_W1_PAGE_OFF
, end
->w1
, qindex
);
163 * XIVE Router (aka. Virtualization Controller or IVRE)
166 int xive2_router_get_eas(Xive2Router
*xrtr
, uint8_t eas_blk
, uint32_t eas_idx
,
169 Xive2RouterClass
*xrc
= XIVE2_ROUTER_GET_CLASS(xrtr
);
171 return xrc
->get_eas(xrtr
, eas_blk
, eas_idx
, eas
);
175 int xive2_router_get_pq(Xive2Router
*xrtr
, uint8_t eas_blk
, uint32_t eas_idx
,
178 Xive2RouterClass
*xrc
= XIVE2_ROUTER_GET_CLASS(xrtr
);
180 return xrc
->get_pq(xrtr
, eas_blk
, eas_idx
, pq
);
184 int xive2_router_set_pq(Xive2Router
*xrtr
, uint8_t eas_blk
, uint32_t eas_idx
,
187 Xive2RouterClass
*xrc
= XIVE2_ROUTER_GET_CLASS(xrtr
);
189 return xrc
->set_pq(xrtr
, eas_blk
, eas_idx
, pq
);
192 int xive2_router_get_end(Xive2Router
*xrtr
, uint8_t end_blk
, uint32_t end_idx
,
195 Xive2RouterClass
*xrc
= XIVE2_ROUTER_GET_CLASS(xrtr
);
197 return xrc
->get_end(xrtr
, end_blk
, end_idx
, end
);
200 int xive2_router_write_end(Xive2Router
*xrtr
, uint8_t end_blk
, uint32_t end_idx
,
201 Xive2End
*end
, uint8_t word_number
)
203 Xive2RouterClass
*xrc
= XIVE2_ROUTER_GET_CLASS(xrtr
);
205 return xrc
->write_end(xrtr
, end_blk
, end_idx
, end
, word_number
);
208 int xive2_router_get_nvp(Xive2Router
*xrtr
, uint8_t nvp_blk
, uint32_t nvp_idx
,
211 Xive2RouterClass
*xrc
= XIVE2_ROUTER_GET_CLASS(xrtr
);
213 return xrc
->get_nvp(xrtr
, nvp_blk
, nvp_idx
, nvp
);
216 int xive2_router_write_nvp(Xive2Router
*xrtr
, uint8_t nvp_blk
, uint32_t nvp_idx
,
217 Xive2Nvp
*nvp
, uint8_t word_number
)
219 Xive2RouterClass
*xrc
= XIVE2_ROUTER_GET_CLASS(xrtr
);
221 return xrc
->write_nvp(xrtr
, nvp_blk
, nvp_idx
, nvp
, word_number
);
224 static int xive2_router_get_block_id(Xive2Router
*xrtr
)
226 Xive2RouterClass
*xrc
= XIVE2_ROUTER_GET_CLASS(xrtr
);
228 return xrc
->get_block_id(xrtr
);
232 * Encode the HW CAM line with 7bit or 8bit thread id. The thread id
233 * width and block id width is configurable at the IC level.
235 * chipid << 24 | 0000 0000 0000 0000 1 threadid (7Bit)
236 * chipid << 24 | 0000 0000 0000 0001 threadid (8Bit)
238 static uint32_t xive2_tctx_hw_cam_line(XivePresenter
*xptr
, XiveTCTX
*tctx
)
240 Xive2Router
*xrtr
= XIVE2_ROUTER(xptr
);
241 CPUPPCState
*env
= &POWERPC_CPU(tctx
->cs
)->env
;
242 uint32_t pir
= env
->spr_cb
[SPR_PIR
].default_value
;
243 uint8_t blk
= xive2_router_get_block_id(xrtr
);
244 uint8_t tid_shift
= 7;
245 uint8_t tid_mask
= (1 << tid_shift
) - 1;
247 return xive2_nvp_cam_line(blk
, 1 << tid_shift
| (pir
& tid_mask
));
251 * The thread context register words are in big-endian format.
253 int xive2_presenter_tctx_match(XivePresenter
*xptr
, XiveTCTX
*tctx
,
255 uint8_t nvt_blk
, uint32_t nvt_idx
,
256 bool cam_ignore
, uint32_t logic_serv
)
258 uint32_t cam
= xive2_nvp_cam_line(nvt_blk
, nvt_idx
);
259 uint32_t qw3w2
= xive_tctx_word2(&tctx
->regs
[TM_QW3_HV_PHYS
]);
260 uint32_t qw2w2
= xive_tctx_word2(&tctx
->regs
[TM_QW2_HV_POOL
]);
261 uint32_t qw1w2
= xive_tctx_word2(&tctx
->regs
[TM_QW1_OS
]);
262 uint32_t qw0w2
= xive_tctx_word2(&tctx
->regs
[TM_QW0_USER
]);
265 * TODO (PowerNV): ignore mode. The low order bits of the NVT
266 * identifier are ignored in the "CAM" match.
270 if (cam_ignore
== true) {
272 * F=0 & i=1: Logical server notification (bits ignored at
273 * the end of the NVT identifier)
275 qemu_log_mask(LOG_UNIMP
, "XIVE: no support for LS NVT %x/%x\n",
280 /* F=0 & i=0: Specific NVT notification */
283 if ((be32_to_cpu(qw3w2
) & TM2_QW3W2_VT
) &&
284 cam
== xive2_tctx_hw_cam_line(xptr
, tctx
)) {
285 return TM_QW3_HV_PHYS
;
289 if ((be32_to_cpu(qw2w2
) & TM2_QW2W2_VP
) &&
290 cam
== xive_get_field32(TM2_QW2W2_POOL_CAM
, qw2w2
)) {
291 return TM_QW2_HV_POOL
;
295 if ((be32_to_cpu(qw1w2
) & TM2_QW1W2_VO
) &&
296 cam
== xive_get_field32(TM2_QW1W2_OS_CAM
, qw1w2
)) {
300 /* F=1 : User level Event-Based Branch (EBB) notification */
303 if ((be32_to_cpu(qw1w2
) & TM2_QW1W2_VO
) &&
304 (cam
== xive_get_field32(TM2_QW1W2_OS_CAM
, qw1w2
)) &&
305 (be32_to_cpu(qw0w2
) & TM2_QW0W2_VU
) &&
306 (logic_serv
== xive_get_field32(TM2_QW0W2_LOGIC_SERV
, qw0w2
))) {
313 static void xive2_router_realize(DeviceState
*dev
, Error
**errp
)
315 Xive2Router
*xrtr
= XIVE2_ROUTER(dev
);
321 * Notification using the END ESe/ESn bit (Event State Buffer for
322 * escalation and notification). Profide futher coalescing in the
325 static bool xive2_router_end_es_notify(Xive2Router
*xrtr
, uint8_t end_blk
,
326 uint32_t end_idx
, Xive2End
*end
,
329 uint8_t pq
= xive_get_field32(end_esmask
, end
->w1
);
330 bool notify
= xive_esb_trigger(&pq
);
332 if (pq
!= xive_get_field32(end_esmask
, end
->w1
)) {
333 end
->w1
= xive_set_field32(end_esmask
, end
->w1
, pq
);
334 xive2_router_write_end(xrtr
, end_blk
, end_idx
, end
, 1);
337 /* ESe/n[Q]=1 : end of notification */
342 * An END trigger can come from an event trigger (IPI or HW) or from
343 * another chip. We don't model the PowerBus but the END trigger
344 * message has the same parameters than in the function below.
346 static void xive2_router_end_notify(Xive2Router
*xrtr
, uint8_t end_blk
,
347 uint32_t end_idx
, uint32_t end_data
)
357 /* END cache lookup */
358 if (xive2_router_get_end(xrtr
, end_blk
, end_idx
, &end
)) {
359 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: No END %x/%x\n", end_blk
,
364 if (!xive2_end_is_valid(&end
)) {
365 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: END %x/%x is invalid\n",
370 if (xive2_end_is_enqueue(&end
)) {
371 xive2_end_enqueue(&end
, end_data
);
372 /* Enqueuing event data modifies the EQ toggle and index */
373 xive2_router_write_end(xrtr
, end_blk
, end_idx
, &end
, 1);
377 * When the END is silent, we skip the notification part.
379 if (xive2_end_is_silent_escalation(&end
)) {
384 * The W7 format depends on the F bit in W6. It defines the type
385 * of the notification :
387 * F=0 : single or multiple NVP notification
388 * F=1 : User level Event-Based Branch (EBB) notification, no
391 format
= xive_get_field32(END2_W6_FORMAT_BIT
, end
.w6
);
392 priority
= xive_get_field32(END2_W7_F0_PRIORITY
, end
.w7
);
394 /* The END is masked */
395 if (format
== 0 && priority
== 0xff) {
400 * Check the END ESn (Event State Buffer for notification) for
401 * even futher coalescing in the Router
403 if (!xive2_end_is_notify(&end
)) {
404 /* ESn[Q]=1 : end of notification */
405 if (!xive2_router_end_es_notify(xrtr
, end_blk
, end_idx
,
406 &end
, END2_W1_ESn
)) {
412 * Follows IVPE notification
414 nvp_blk
= xive_get_field32(END2_W6_VP_BLOCK
, end
.w6
);
415 nvp_idx
= xive_get_field32(END2_W6_VP_OFFSET
, end
.w6
);
417 /* NVP cache lookup */
418 if (xive2_router_get_nvp(xrtr
, nvp_blk
, nvp_idx
, &nvp
)) {
419 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: no NVP %x/%x\n",
424 if (!xive2_nvp_is_valid(&nvp
)) {
425 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: NVP %x/%x is invalid\n",
430 found
= xive_presenter_notify(xrtr
->xfb
, format
, nvp_blk
, nvp_idx
,
431 xive_get_field32(END2_W6_IGNORE
, end
.w7
),
433 xive_get_field32(END2_W7_F1_LOG_SERVER_ID
, end
.w7
));
435 /* TODO: Auto EOI. */
442 * If no matching NVP is dispatched on a HW thread :
443 * - specific VP: update the NVP structure if backlog is activated
444 * - logical server : forward request to IVPE (not supported)
446 if (xive2_end_is_backlog(&end
)) {
450 qemu_log_mask(LOG_GUEST_ERROR
,
451 "XIVE: END %x/%x invalid config: F1 & backlog\n",
457 * Record the IPB in the associated NVP structure for later
458 * use. The presenter will resend the interrupt when the vCPU
459 * is dispatched again on a HW thread.
461 ipb
= xive_get_field32(NVP2_W2_IPB
, nvp
.w2
) |
462 xive_priority_to_ipb(priority
);
463 nvp
.w2
= xive_set_field32(NVP2_W2_IPB
, nvp
.w2
, ipb
);
464 xive2_router_write_nvp(xrtr
, nvp_blk
, nvp_idx
, &nvp
, 2);
467 * On HW, follows a "Broadcast Backlog" to IVPEs
473 * If activated, escalate notification using the ESe PQ bits and
476 if (!xive2_end_is_escalate(&end
)) {
481 * Check the END ESe (Event State Buffer for escalation) for even
482 * futher coalescing in the Router
484 if (!xive2_end_is_uncond_escalation(&end
)) {
485 /* ESe[Q]=1 : end of escalation notification */
486 if (!xive2_router_end_es_notify(xrtr
, end_blk
, end_idx
,
487 &end
, END2_W1_ESe
)) {
493 * The END trigger becomes an Escalation trigger
495 xive2_router_end_notify(xrtr
,
496 xive_get_field32(END2_W4_END_BLOCK
, end
.w4
),
497 xive_get_field32(END2_W4_ESC_END_INDEX
, end
.w4
),
498 xive_get_field32(END2_W5_ESC_END_DATA
, end
.w5
));
501 void xive2_router_notify(XiveNotifier
*xn
, uint32_t lisn
, bool pq_checked
)
503 Xive2Router
*xrtr
= XIVE2_ROUTER(xn
);
504 uint8_t eas_blk
= XIVE_EAS_BLOCK(lisn
);
505 uint32_t eas_idx
= XIVE_EAS_INDEX(lisn
);
508 /* EAS cache lookup */
509 if (xive2_router_get_eas(xrtr
, eas_blk
, eas_idx
, &eas
)) {
510 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: Unknown LISN %x\n", lisn
);
518 /* PQ cache lookup */
519 if (xive2_router_get_pq(xrtr
, eas_blk
, eas_idx
, &pq
)) {
521 g_assert_not_reached();
524 notify
= xive_esb_trigger(&pq
);
526 if (xive2_router_set_pq(xrtr
, eas_blk
, eas_idx
, &pq
)) {
528 g_assert_not_reached();
536 if (!xive2_eas_is_valid(&eas
)) {
537 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: Invalid LISN %x\n", lisn
);
541 if (xive2_eas_is_masked(&eas
)) {
542 /* Notification completed */
547 * The event trigger becomes an END trigger
549 xive2_router_end_notify(xrtr
,
550 xive_get_field64(EAS2_END_BLOCK
, eas
.w
),
551 xive_get_field64(EAS2_END_INDEX
, eas
.w
),
552 xive_get_field64(EAS2_END_DATA
, eas
.w
));
555 static Property xive2_router_properties
[] = {
556 DEFINE_PROP_LINK("xive-fabric", Xive2Router
, xfb
,
557 TYPE_XIVE_FABRIC
, XiveFabric
*),
558 DEFINE_PROP_END_OF_LIST(),
561 static void xive2_router_class_init(ObjectClass
*klass
, void *data
)
563 DeviceClass
*dc
= DEVICE_CLASS(klass
);
564 XiveNotifierClass
*xnc
= XIVE_NOTIFIER_CLASS(klass
);
566 dc
->desc
= "XIVE2 Router Engine";
567 device_class_set_props(dc
, xive2_router_properties
);
568 /* Parent is SysBusDeviceClass. No need to call its realize hook */
569 dc
->realize
= xive2_router_realize
;
570 xnc
->notify
= xive2_router_notify
;
573 static const TypeInfo xive2_router_info
= {
574 .name
= TYPE_XIVE2_ROUTER
,
575 .parent
= TYPE_SYS_BUS_DEVICE
,
577 .instance_size
= sizeof(Xive2Router
),
578 .class_size
= sizeof(Xive2RouterClass
),
579 .class_init
= xive2_router_class_init
,
580 .interfaces
= (InterfaceInfo
[]) {
581 { TYPE_XIVE_NOTIFIER
},
582 { TYPE_XIVE_PRESENTER
},
587 static inline bool addr_is_even(hwaddr addr
, uint32_t shift
)
589 return !((addr
>> shift
) & 1);
592 static uint64_t xive2_end_source_read(void *opaque
, hwaddr addr
, unsigned size
)
594 Xive2EndSource
*xsrc
= XIVE2_END_SOURCE(opaque
);
595 uint32_t offset
= addr
& 0xFFF;
604 * The block id should be deduced from the load address on the END
605 * ESB MMIO but our model only supports a single block per XIVE chip.
607 end_blk
= xive2_router_get_block_id(xsrc
->xrtr
);
608 end_idx
= addr
>> (xsrc
->esb_shift
+ 1);
610 if (xive2_router_get_end(xsrc
->xrtr
, end_blk
, end_idx
, &end
)) {
611 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: No END %x/%x\n", end_blk
,
616 if (!xive2_end_is_valid(&end
)) {
617 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: END %x/%x is invalid\n",
622 end_esmask
= addr_is_even(addr
, xsrc
->esb_shift
) ? END2_W1_ESn
:
624 pq
= xive_get_field32(end_esmask
, end
.w1
);
627 case XIVE_ESB_LOAD_EOI
... XIVE_ESB_LOAD_EOI
+ 0x7FF:
628 ret
= xive_esb_eoi(&pq
);
630 /* Forward the source event notification for routing ?? */
633 case XIVE_ESB_GET
... XIVE_ESB_GET
+ 0x3FF:
637 case XIVE_ESB_SET_PQ_00
... XIVE_ESB_SET_PQ_00
+ 0x0FF:
638 case XIVE_ESB_SET_PQ_01
... XIVE_ESB_SET_PQ_01
+ 0x0FF:
639 case XIVE_ESB_SET_PQ_10
... XIVE_ESB_SET_PQ_10
+ 0x0FF:
640 case XIVE_ESB_SET_PQ_11
... XIVE_ESB_SET_PQ_11
+ 0x0FF:
641 ret
= xive_esb_set(&pq
, (offset
>> 8) & 0x3);
644 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: invalid END ESB load addr %d\n",
649 if (pq
!= xive_get_field32(end_esmask
, end
.w1
)) {
650 end
.w1
= xive_set_field32(end_esmask
, end
.w1
, pq
);
651 xive2_router_write_end(xsrc
->xrtr
, end_blk
, end_idx
, &end
, 1);
657 static void xive2_end_source_write(void *opaque
, hwaddr addr
,
658 uint64_t value
, unsigned size
)
660 Xive2EndSource
*xsrc
= XIVE2_END_SOURCE(opaque
);
661 uint32_t offset
= addr
& 0xFFF;
670 * The block id should be deduced from the load address on the END
671 * ESB MMIO but our model only supports a single block per XIVE chip.
673 end_blk
= xive2_router_get_block_id(xsrc
->xrtr
);
674 end_idx
= addr
>> (xsrc
->esb_shift
+ 1);
676 if (xive2_router_get_end(xsrc
->xrtr
, end_blk
, end_idx
, &end
)) {
677 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: No END %x/%x\n", end_blk
,
682 if (!xive2_end_is_valid(&end
)) {
683 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: END %x/%x is invalid\n",
688 end_esmask
= addr_is_even(addr
, xsrc
->esb_shift
) ? END2_W1_ESn
:
690 pq
= xive_get_field32(end_esmask
, end
.w1
);
694 notify
= xive_esb_trigger(&pq
);
697 case XIVE_ESB_STORE_EOI
... XIVE_ESB_STORE_EOI
+ 0x3FF:
698 /* TODO: can we check StoreEOI availability from the router ? */
699 notify
= xive_esb_eoi(&pq
);
702 case XIVE_ESB_INJECT
... XIVE_ESB_INJECT
+ 0x3FF:
703 if (end_esmask
== END2_W1_ESe
) {
704 qemu_log_mask(LOG_GUEST_ERROR
,
705 "XIVE: END %x/%x can not EQ inject on ESe\n",
713 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: invalid END ESB write addr %d\n",
718 if (pq
!= xive_get_field32(end_esmask
, end
.w1
)) {
719 end
.w1
= xive_set_field32(end_esmask
, end
.w1
, pq
);
720 xive2_router_write_end(xsrc
->xrtr
, end_blk
, end_idx
, &end
, 1);
723 /* TODO: Forward the source event notification for routing */
729 static const MemoryRegionOps xive2_end_source_ops
= {
730 .read
= xive2_end_source_read
,
731 .write
= xive2_end_source_write
,
732 .endianness
= DEVICE_BIG_ENDIAN
,
734 .min_access_size
= 8,
735 .max_access_size
= 8,
738 .min_access_size
= 8,
739 .max_access_size
= 8,
743 static void xive2_end_source_realize(DeviceState
*dev
, Error
**errp
)
745 Xive2EndSource
*xsrc
= XIVE2_END_SOURCE(dev
);
749 if (!xsrc
->nr_ends
) {
750 error_setg(errp
, "Number of interrupt needs to be greater than 0");
754 if (xsrc
->esb_shift
!= XIVE_ESB_4K
&&
755 xsrc
->esb_shift
!= XIVE_ESB_64K
) {
756 error_setg(errp
, "Invalid ESB shift setting");
761 * Each END is assigned an even/odd pair of MMIO pages, the even page
762 * manages the ESn field while the odd page manages the ESe field.
764 memory_region_init_io(&xsrc
->esb_mmio
, OBJECT(xsrc
),
765 &xive2_end_source_ops
, xsrc
, "xive.end",
766 (1ull << (xsrc
->esb_shift
+ 1)) * xsrc
->nr_ends
);
769 static Property xive2_end_source_properties
[] = {
770 DEFINE_PROP_UINT32("nr-ends", Xive2EndSource
, nr_ends
, 0),
771 DEFINE_PROP_UINT32("shift", Xive2EndSource
, esb_shift
, XIVE_ESB_64K
),
772 DEFINE_PROP_LINK("xive", Xive2EndSource
, xrtr
, TYPE_XIVE2_ROUTER
,
774 DEFINE_PROP_END_OF_LIST(),
777 static void xive2_end_source_class_init(ObjectClass
*klass
, void *data
)
779 DeviceClass
*dc
= DEVICE_CLASS(klass
);
781 dc
->desc
= "XIVE END Source";
782 device_class_set_props(dc
, xive2_end_source_properties
);
783 dc
->realize
= xive2_end_source_realize
;
786 static const TypeInfo xive2_end_source_info
= {
787 .name
= TYPE_XIVE2_END_SOURCE
,
788 .parent
= TYPE_DEVICE
,
789 .instance_size
= sizeof(Xive2EndSource
),
790 .class_init
= xive2_end_source_class_init
,
793 static void xive2_register_types(void)
795 type_register_static(&xive2_router_info
);
796 type_register_static(&xive2_end_source_info
);
799 type_init(xive2_register_types
)