4 #include "qemu-common.h"
8 /* PCI includes legacy ISA access. */
13 extern target_phys_addr_t pci_mem_base
;
15 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07))
16 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f)
17 #define PCI_FUNC(devfn) ((devfn) & 0x07)
19 /* Class, Vendor and Device IDs from Linux's pci_ids.h */
22 /* QEMU-specific Vendor and Device ID definitions */
25 #define PCI_DEVICE_ID_IBM_440GX 0x027f
26 #define PCI_DEVICE_ID_IBM_OPENPIC2 0xffff
28 /* Hitachi (0x1054) */
29 #define PCI_VENDOR_ID_HITACHI 0x1054
30 #define PCI_DEVICE_ID_HITACHI_SH7751R 0x350e
33 #define PCI_DEVICE_ID_APPLE_343S1201 0x0010
34 #define PCI_DEVICE_ID_APPLE_UNI_N_I_PCI 0x001e
35 #define PCI_DEVICE_ID_APPLE_UNI_N_PCI 0x001f
36 #define PCI_DEVICE_ID_APPLE_UNI_N_KEYL 0x0022
37 #define PCI_DEVICE_ID_APPLE_IPID_USB 0x003f
39 /* Realtek (0x10ec) */
40 #define PCI_DEVICE_ID_REALTEK_8029 0x8029
43 #define PCI_DEVICE_ID_XILINX_XC2VP30 0x0300
45 /* Marvell (0x11ab) */
46 #define PCI_DEVICE_ID_MARVELL_GT6412X 0x4620
48 /* QEMU/Bochs VGA (0x1234) */
49 #define PCI_VENDOR_ID_QEMU 0x1234
50 #define PCI_DEVICE_ID_QEMU_VGA 0x1111
53 #define PCI_VENDOR_ID_VMWARE 0x15ad
54 #define PCI_DEVICE_ID_VMWARE_SVGA2 0x0405
55 #define PCI_DEVICE_ID_VMWARE_SVGA 0x0710
56 #define PCI_DEVICE_ID_VMWARE_NET 0x0720
57 #define PCI_DEVICE_ID_VMWARE_SCSI 0x0730
58 #define PCI_DEVICE_ID_VMWARE_IDE 0x1729
61 #define PCI_DEVICE_ID_INTEL_82551IT 0x1209
63 /* Red Hat / Qumranet (for QEMU) -- see pci-ids.txt */
64 #define PCI_VENDOR_ID_REDHAT_QUMRANET 0x1af4
65 #define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4
66 #define PCI_SUBDEVICE_ID_QEMU 0x1100
68 #define PCI_DEVICE_ID_VIRTIO_NET 0x1000
69 #define PCI_DEVICE_ID_VIRTIO_BLOCK 0x1001
70 #define PCI_DEVICE_ID_VIRTIO_BALLOON 0x1002
71 #define PCI_DEVICE_ID_VIRTIO_CONSOLE 0x1003
73 typedef void PCIConfigWriteFunc(PCIDevice
*pci_dev
,
74 uint32_t address
, uint32_t data
, int len
);
75 typedef uint32_t PCIConfigReadFunc(PCIDevice
*pci_dev
,
76 uint32_t address
, int len
);
77 typedef void PCIMapIORegionFunc(PCIDevice
*pci_dev
, int region_num
,
78 uint32_t addr
, uint32_t size
, int type
);
79 typedef int PCIUnregisterFunc(PCIDevice
*pci_dev
);
81 #define PCI_ADDRESS_SPACE_MEM 0x00
82 #define PCI_ADDRESS_SPACE_IO 0x01
83 #define PCI_ADDRESS_SPACE_MEM_PREFETCH 0x08
85 typedef struct PCIIORegion
{
86 uint32_t addr
; /* current PCI mapping address. -1 means not mapped */
89 PCIMapIORegionFunc
*map_func
;
92 #define PCI_ROM_SLOT 6
93 #define PCI_NUM_REGIONS 7
95 /* Declarations from linux/pci_regs.h */
96 #define PCI_VENDOR_ID 0x00 /* 16 bits */
97 #define PCI_DEVICE_ID 0x02 /* 16 bits */
98 #define PCI_COMMAND 0x04 /* 16 bits */
99 #define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
100 #define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
101 #define PCI_COMMAND_MASTER 0x4 /* Enable bus master */
102 #define PCI_STATUS 0x06 /* 16 bits */
103 #define PCI_REVISION_ID 0x08 /* 8 bits */
104 #define PCI_CLASS_PROG 0x09 /* Reg. Level Programming Interface */
105 #define PCI_CLASS_DEVICE 0x0a /* Device class */
106 #define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */
107 #define PCI_LATENCY_TIMER 0x0d /* 8 bits */
108 #define PCI_HEADER_TYPE 0x0e /* 8 bits */
109 #define PCI_HEADER_TYPE_NORMAL 0
110 #define PCI_HEADER_TYPE_BRIDGE 1
111 #define PCI_HEADER_TYPE_CARDBUS 2
112 #define PCI_HEADER_TYPE_MULTI_FUNCTION 0x80
113 #define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */
114 #define PCI_PRIMARY_BUS 0x18 /* Primary bus number */
115 #define PCI_SECONDARY_BUS 0x19 /* Secondary bus number */
116 #define PCI_SEC_STATUS 0x1e /* Secondary status register, only bit 14 used */
117 #define PCI_SUBSYSTEM_VENDOR_ID 0x2c /* 16 bits */
118 #define PCI_SUBSYSTEM_ID 0x2e /* 16 bits */
119 #define PCI_CAPABILITY_LIST 0x34 /* Offset of first capability list entry */
120 #define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
121 #define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
122 #define PCI_MIN_GNT 0x3e /* 8 bits */
123 #define PCI_MAX_LAT 0x3f /* 8 bits */
125 /* Capability lists */
126 #define PCI_CAP_LIST_ID 0 /* Capability ID */
127 #define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */
129 #define PCI_REVISION 0x08 /* obsolete, use PCI_REVISION_ID */
130 #define PCI_SUBVENDOR_ID 0x2c /* obsolete, use PCI_SUBSYSTEM_VENDOR_ID */
131 #define PCI_SUBDEVICE_ID 0x2e /* obsolete, use PCI_SUBSYSTEM_ID */
133 /* Bits in the PCI Status Register (PCI 2.3 spec) */
134 #define PCI_STATUS_RESERVED1 0x007
135 #define PCI_STATUS_INT_STATUS 0x008
136 #define PCI_STATUS_CAP_LIST 0x010
137 #define PCI_STATUS_66MHZ 0x020
138 #define PCI_STATUS_RESERVED2 0x040
139 #define PCI_STATUS_FAST_BACK 0x080
140 #define PCI_STATUS_DEVSEL 0x600
142 #define PCI_STATUS_RESERVED_MASK_LO (PCI_STATUS_RESERVED1 | \
143 PCI_STATUS_INT_STATUS | PCI_STATUS_CAPABILITIES | \
144 PCI_STATUS_66MHZ | PCI_STATUS_RESERVED2 | PCI_STATUS_FAST_BACK)
146 #define PCI_STATUS_RESERVED_MASK_HI (PCI_STATUS_DEVSEL >> 8)
148 /* Bits in the PCI Command Register (PCI 2.3 spec) */
149 #define PCI_COMMAND_RESERVED 0xf800
151 #define PCI_COMMAND_RESERVED_MASK_HI (PCI_COMMAND_RESERVED >> 8)
153 /* Size of the standard PCI config header */
154 #define PCI_CONFIG_HEADER_SIZE 0x40
155 /* Size of the standard PCI config space */
156 #define PCI_CONFIG_SPACE_SIZE 0x100
158 /* Bits in cap_present field. */
160 QEMU_PCI_CAP_MSIX
= 0x1,
165 /* PCI config space */
166 uint8_t config
[PCI_CONFIG_SPACE_SIZE
];
168 /* Used to enable config checks on load. Note that writeable bits are
169 * never checked even if set in cmask. */
170 uint8_t cmask
[PCI_CONFIG_SPACE_SIZE
];
172 /* Used to implement R/W bytes */
173 uint8_t wmask
[PCI_CONFIG_SPACE_SIZE
];
175 /* Used to allocate config space for capabilities. */
176 uint8_t used
[PCI_CONFIG_SPACE_SIZE
];
178 /* the following fields are read only */
182 PCIIORegion io_regions
[PCI_NUM_REGIONS
];
184 /* do not access the following fields */
185 PCIConfigReadFunc
*config_read
;
186 PCIConfigWriteFunc
*config_write
;
187 PCIUnregisterFunc
*unregister
;
189 /* IRQ objects for the INTA-INTD pins. */
192 /* Current IRQ levels. Used internally by the generic PCI code. */
195 /* Capability bits */
196 uint32_t cap_present
;
198 /* Offset of MSI-X capability in config space */
204 /* Space to store MSIX table */
205 uint8_t *msix_table_page
;
206 /* MMIO index used to map MSIX table and pending bit entries. */
208 /* Reference-count for entries actually in use by driver. */
209 unsigned *msix_entry_used
;
210 /* Region including the MSI-X table */
211 uint32_t msix_bar_size
;
212 /* Version id needed for VMState */
216 PCIDevice
*pci_register_device(PCIBus
*bus
, const char *name
,
217 int instance_size
, int devfn
,
218 PCIConfigReadFunc
*config_read
,
219 PCIConfigWriteFunc
*config_write
);
220 int pci_unregister_device(PCIDevice
*pci_dev
);
222 void pci_register_bar(PCIDevice
*pci_dev
, int region_num
,
223 uint32_t size
, int type
,
224 PCIMapIORegionFunc
*map_func
);
226 int pci_add_capability(PCIDevice
*pci_dev
, uint8_t cap_id
, uint8_t cap_size
);
228 void pci_del_capability(PCIDevice
*pci_dev
, uint8_t cap_id
, uint8_t cap_size
);
230 void pci_reserve_capability(PCIDevice
*pci_dev
, uint8_t offset
, uint8_t size
);
232 uint8_t pci_find_capability(PCIDevice
*pci_dev
, uint8_t cap_id
);
235 uint32_t pci_default_read_config(PCIDevice
*d
,
236 uint32_t address
, int len
);
237 void pci_default_write_config(PCIDevice
*d
,
238 uint32_t address
, uint32_t val
, int len
);
239 void pci_device_save(PCIDevice
*s
, QEMUFile
*f
);
240 int pci_device_load(PCIDevice
*s
, QEMUFile
*f
);
242 typedef void (*pci_set_irq_fn
)(void *opaque
, int irq_num
, int level
);
243 typedef int (*pci_map_irq_fn
)(PCIDevice
*pci_dev
, int irq_num
);
244 PCIBus
*pci_register_bus(DeviceState
*parent
, const char *name
,
245 pci_set_irq_fn set_irq
, pci_map_irq_fn map_irq
,
246 void *irq_opaque
, int devfn_min
, int nirq
);
248 PCIDevice
*pci_nic_init(NICInfo
*nd
, const char *default_model
,
249 const char *default_devaddr
);
250 void pci_data_write(void *opaque
, uint32_t addr
, uint32_t val
, int len
);
251 uint32_t pci_data_read(void *opaque
, uint32_t addr
, int len
);
252 int pci_bus_num(PCIBus
*s
);
253 void pci_for_each_device(int bus_num
, void (*fn
)(PCIDevice
*d
));
254 PCIBus
*pci_find_bus(int bus_num
);
255 PCIDevice
*pci_find_device(int bus_num
, int slot
, int function
);
257 int pci_read_devaddr(Monitor
*mon
, const char *addr
, int *domp
, int *busp
,
260 void pci_info(Monitor
*mon
);
261 PCIBus
*pci_bridge_init(PCIBus
*bus
, int devfn
, uint16_t vid
, uint16_t did
,
262 pci_map_irq_fn map_irq
, const char *name
);
265 pci_set_byte(uint8_t *config
, uint8_t val
)
270 static inline uint8_t
271 pci_get_byte(uint8_t *config
)
277 pci_set_word(uint8_t *config
, uint16_t val
)
279 cpu_to_le16wu((uint16_t *)config
, val
);
282 static inline uint16_t
283 pci_get_word(uint8_t *config
)
285 return le16_to_cpupu((uint16_t *)config
);
289 pci_set_long(uint8_t *config
, uint32_t val
)
291 cpu_to_le32wu((uint32_t *)config
, val
);
294 static inline uint32_t
295 pci_get_long(uint8_t *config
)
297 return le32_to_cpupu((uint32_t *)config
);
301 pci_config_set_vendor_id(uint8_t *pci_config
, uint16_t val
)
303 pci_set_word(&pci_config
[PCI_VENDOR_ID
], val
);
307 pci_config_set_device_id(uint8_t *pci_config
, uint16_t val
)
309 pci_set_word(&pci_config
[PCI_DEVICE_ID
], val
);
313 pci_config_set_class(uint8_t *pci_config
, uint16_t val
)
315 pci_set_word(&pci_config
[PCI_CLASS_DEVICE
], val
);
318 typedef int (*pci_qdev_initfn
)(PCIDevice
*dev
);
321 pci_qdev_initfn init
;
322 PCIConfigReadFunc
*config_read
;
323 PCIConfigWriteFunc
*config_write
;
326 void pci_qdev_register(PCIDeviceInfo
*info
);
327 void pci_qdev_register_many(PCIDeviceInfo
*info
);
329 PCIDevice
*pci_create(const char *name
, const char *devaddr
);
330 PCIDevice
*pci_create_simple(PCIBus
*bus
, int devfn
, const char *name
);
333 #define LSI_MAX_DEVS 7
334 void lsi_scsi_attach(DeviceState
*host
, BlockDriverState
*bd
, int id
);
337 void pci_vmsvga_init(PCIBus
*bus
);
340 void usb_uhci_piix3_init(PCIBus
*bus
, int devfn
);
341 void usb_uhci_piix4_init(PCIBus
*bus
, int devfn
);
344 void usb_ohci_init_pci(struct PCIBus
*bus
, int devfn
);
347 PCIBus
*pci_prep_init(qemu_irq
*pic
);
350 PCIBus
*pci_apb_init(target_phys_addr_t special_base
,
351 target_phys_addr_t mem_base
,
352 qemu_irq
*pic
, PCIBus
**bus2
, PCIBus
**bus3
);
355 PCIBus
*sh_pci_register_bus(pci_set_irq_fn set_irq
, pci_map_irq_fn map_irq
,
356 void *pic
, int devfn_min
, int nirq
);