hw/pci.h

   1 #ifndef QEMU_PCI_H
   2 #define QEMU_PCI_H
   3
   4 #include "qemu-common.h"
   5
   6 #include "qdev.h"
   7
   8 struct kvm_irq_routing_entry;
   9
  10 /* PCI includes legacy ISA access.  */
  11 #include "isa.h"
  12
  13 /* imported from <linux/pci.h> */
  14 #define PCI_SLOT(devfn)         (((devfn) >> 3) & 0x1f)
  15 #define PCI_FUNC(devfn)         ((devfn) & 0x07)
  16
  17 /* PCI bus */
  18 extern target_phys_addr_t pci_mem_base;
  19
  20 #define PCI_DEVFN(slot, func)   ((((slot) & 0x1f) << 3) | ((func) & 0x07))
  21 #define PCI_SLOT(devfn)         (((devfn) >> 3) & 0x1f)
  22 #define PCI_FUNC(devfn)         ((devfn) & 0x07)
  23
  24 /* Class, Vendor and Device IDs from Linux's pci_ids.h */
  25 #include "pci_ids.h"
  26
  27 /* QEMU-specific Vendor and Device ID definitions */
  28
  29 /* IBM (0x1014) */
  30 #define PCI_DEVICE_ID_IBM_440GX          0x027f
  31 #define PCI_DEVICE_ID_IBM_OPENPIC2       0xffff
  32
  33 /* Hitachi (0x1054) */
  34 #define PCI_VENDOR_ID_HITACHI            0x1054
  35 #define PCI_DEVICE_ID_HITACHI_SH7751R    0x350e
  36
  37 /* Apple (0x106b) */
  38 #define PCI_DEVICE_ID_APPLE_343S1201     0x0010
  39 #define PCI_DEVICE_ID_APPLE_UNI_N_I_PCI  0x001e
  40 #define PCI_DEVICE_ID_APPLE_UNI_N_PCI    0x001f
  41 #define PCI_DEVICE_ID_APPLE_UNI_N_KEYL   0x0022
  42 #define PCI_DEVICE_ID_APPLE_IPID_USB     0x003f
  43
  44 /* Realtek (0x10ec) */
  45 #define PCI_DEVICE_ID_REALTEK_8029       0x8029
  46
  47 /* Xilinx (0x10ee) */
  48 #define PCI_DEVICE_ID_XILINX_XC2VP30     0x0300
  49
  50 /* Marvell (0x11ab) */
  51 #define PCI_DEVICE_ID_MARVELL_GT6412X    0x4620
  52
  53 /* QEMU/Bochs VGA (0x1234) */
  54 #define PCI_VENDOR_ID_QEMU               0x1234
  55 #define PCI_DEVICE_ID_QEMU_VGA           0x1111
  56
  57 /* VMWare (0x15ad) */
  58 #define PCI_VENDOR_ID_VMWARE             0x15ad
  59 #define PCI_DEVICE_ID_VMWARE_SVGA2       0x0405
  60 #define PCI_DEVICE_ID_VMWARE_SVGA        0x0710
  61 #define PCI_DEVICE_ID_VMWARE_NET         0x0720
  62 #define PCI_DEVICE_ID_VMWARE_SCSI        0x0730
  63 #define PCI_DEVICE_ID_VMWARE_IDE         0x1729
  64
  65 /* Intel (0x8086) */
  66 #define PCI_DEVICE_ID_INTEL_82551IT      0x1209
  67 #define PCI_DEVICE_ID_INTEL_82557        0x1229
  68
  69 /* Red Hat / Qumranet (for QEMU) -- see pci-ids.txt */
  70 #define PCI_VENDOR_ID_REDHAT_QUMRANET    0x1af4
  71 #define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4
  72 #define PCI_SUBDEVICE_ID_QEMU            0x1100
  73
  74 #define PCI_DEVICE_ID_VIRTIO_NET         0x1000
  75 #define PCI_DEVICE_ID_VIRTIO_BLOCK       0x1001
  76 #define PCI_DEVICE_ID_VIRTIO_BALLOON     0x1002
  77 #define PCI_DEVICE_ID_VIRTIO_CONSOLE     0x1003
  78
  79 typedef void PCIConfigWriteFunc(PCIDevice *pci_dev,
  80                                 uint32_t address, uint32_t data, int len);
  81 typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev,
  82                                    uint32_t address, int len);
  83 typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num,
  84                                 uint32_t addr, uint32_t size, int type);
  85 typedef int PCIUnregisterFunc(PCIDevice *pci_dev);
  86
  87 typedef void PCICapConfigWriteFunc(PCIDevice *pci_dev,
  88                                    uint32_t address, uint32_t val, int len);
  89 typedef uint32_t PCICapConfigReadFunc(PCIDevice *pci_dev,
  90                                       uint32_t address, int len);
  91 typedef int PCICapConfigInitFunc(PCIDevice *pci_dev);
  92
  93 #define PCI_ADDRESS_SPACE_MEM           0x00
  94 #define PCI_ADDRESS_SPACE_IO            0x01
  95 #define PCI_ADDRESS_SPACE_MEM_PREFETCH  0x08
  96
  97 typedef struct PCIIORegion {
  98     uint32_t addr; /* current PCI mapping address. -1 means not mapped */
  99     uint32_t size;
 100     uint8_t type;
 101     PCIMapIORegionFunc *map_func;
 102 } PCIIORegion;
 103
 104 #define PCI_ROM_SLOT 6
 105 #define PCI_NUM_REGIONS 7
 106
 107 /* Declarations from linux/pci_regs.h */
 108 #define PCI_VENDOR_ID           0x00    /* 16 bits */
 109 #define PCI_DEVICE_ID           0x02    /* 16 bits */
 110 #define PCI_COMMAND             0x04    /* 16 bits */
 111 #define  PCI_COMMAND_IO         0x1     /* Enable response in I/O space */
 112 #define  PCI_COMMAND_MEMORY     0x2     /* Enable response in Memory space */
 113 #define  PCI_COMMAND_MASTER     0x4     /* Enable bus master */
 114 #define PCI_STATUS              0x06    /* 16 bits */
 115 #define PCI_REVISION_ID         0x08    /* 8 bits  */
 116 #define PCI_CLASS_PROG          0x09    /* Reg. Level Programming Interface */
 117 #define PCI_CLASS_DEVICE        0x0a    /* Device class */
 118 #define PCI_CACHE_LINE_SIZE     0x0c    /* 8 bits */
 119 #define PCI_LATENCY_TIMER       0x0d    /* 8 bits */
 120 #define PCI_HEADER_TYPE         0x0e    /* 8 bits */
 121 #define  PCI_HEADER_TYPE_NORMAL         0
 122 #define  PCI_HEADER_TYPE_BRIDGE         1
 123 #define  PCI_HEADER_TYPE_CARDBUS        2
 124 #define  PCI_HEADER_TYPE_MULTI_FUNCTION 0x80
 125 #define PCI_BASE_ADDRESS_0      0x10    /* 32 bits */
 126 #define PCI_PRIMARY_BUS         0x18    /* Primary bus number */
 127 #define PCI_SECONDARY_BUS       0x19    /* Secondary bus number */
 128 #define PCI_SEC_STATUS          0x1e    /* Secondary status register, only bit 14 used */
 129 #define PCI_SUBSYSTEM_VENDOR_ID 0x2c    /* 16 bits */
 130 #define PCI_SUBSYSTEM_ID        0x2e    /* 16 bits */
 131 #define PCI_ROM_ADDRESS         0x30    /* Bits 31..11 are address, 10..1 reserved */
 132 #define  PCI_ROM_ADDRESS_ENABLE 0x01
 133 #define PCI_CAPABILITY_LIST     0x34    /* Offset of first capability list entry */
 134 #define PCI_INTERRUPT_LINE      0x3c    /* 8 bits */
 135 #define PCI_INTERRUPT_PIN       0x3d    /* 8 bits */
 136 #define PCI_MIN_GNT             0x3e    /* 8 bits */
 137 #define PCI_MAX_LAT             0x3f    /* 8 bits */
 138
 139 /* Capability lists */
 140 #define PCI_CAP_LIST_ID         0       /* Capability ID */
 141 #define PCI_CAP_LIST_NEXT       1       /* Next capability in the list */
 142
 143 #define PCI_REVISION            0x08    /* obsolete, use PCI_REVISION_ID */
 144 #define PCI_SUBVENDOR_ID        0x2c    /* obsolete, use PCI_SUBSYSTEM_VENDOR_ID */
 145 #define PCI_SUBDEVICE_ID        0x2e    /* obsolete, use PCI_SUBSYSTEM_ID */
 146
 147 /* Bits in the PCI Status Register (PCI 2.3 spec) */
 148 #define PCI_STATUS_RESERVED1    0x007
 149 #define PCI_STATUS_INT_STATUS   0x008
 150 #ifndef PCI_STATUS_CAP_LIST
 151 #define PCI_STATUS_CAP_LIST     0x010
 152 #endif
 153 #ifndef PCI_STATUS_66MHZ
 154 #define PCI_STATUS_66MHZ        0x020
 155 #endif
 156
 157 #define PCI_STATUS_RESERVED2    0x040
 158
 159 #ifndef PCI_STATUS_FAST_BACK
 160 #define PCI_STATUS_FAST_BACK    0x080
 161 #endif
 162
 163 #define PCI_STATUS_DEVSEL       0x600
 164
 165 #define PCI_STATUS_RESERVED_MASK_LO (PCI_STATUS_RESERVED1 | \
 166                 PCI_STATUS_INT_STATUS | PCI_STATUS_CAPABILITIES | \
 167                 PCI_STATUS_66MHZ | PCI_STATUS_RESERVED2 | PCI_STATUS_FAST_BACK)
 168
 169 #define PCI_STATUS_RESERVED_MASK_HI (PCI_STATUS_DEVSEL >> 8)
 170
 171 /* Bits in the PCI Command Register (PCI 2.3 spec) */
 172 #define PCI_COMMAND_RESERVED    0xf800
 173
 174 #define PCI_COMMAND_RESERVED_MASK_HI (PCI_COMMAND_RESERVED >> 8)
 175
 176 /* Size of the standard PCI config header */
 177 #define PCI_CONFIG_HEADER_SIZE 0x40
 178 /* Size of the standard PCI config space */
 179 #define PCI_CONFIG_SPACE_SIZE 0x100
 180
 181 /* Bits in cap_present field. */
 182 enum {
 183     QEMU_PCI_CAP_MSIX = 0x1,
 184 };
 185
 186 #define PCI_CAPABILITY_CONFIG_MAX_LENGTH 0x60
 187 #define PCI_CAPABILITY_CONFIG_DEFAULT_START_ADDR 0x40
 188 #define PCI_CAPABILITY_CONFIG_MSI_LENGTH 0x10
 189 #define PCI_CAPABILITY_CONFIG_MSIX_LENGTH 0x10
 190
 191 struct PCIDevice {
 192     DeviceState qdev;
 193     /* PCI config space */
 194     uint8_t config[PCI_CONFIG_SPACE_SIZE];
 195
 196     /* Used to enable config checks on load. Note that writeable bits are
 197      * never checked even if set in cmask. */
 198     uint8_t cmask[PCI_CONFIG_SPACE_SIZE];
 199
 200     /* Used to implement R/W bytes */
 201     uint8_t wmask[PCI_CONFIG_SPACE_SIZE];
 202
 203     /* Used to allocate config space for capabilities. */
 204     uint8_t used[PCI_CONFIG_SPACE_SIZE];
 205
 206     /* the following fields are read only */
 207     PCIBus *bus;
 208     uint32_t devfn;
 209     char name[64];
 210     PCIIORegion io_regions[PCI_NUM_REGIONS];
 211
 212     /* do not access the following fields */
 213     PCIConfigReadFunc *config_read;
 214     PCIConfigWriteFunc *config_write;
 215
 216     /* IRQ objects for the INTA-INTD pins.  */
 217     qemu_irq *irq;
 218
 219     /* Current IRQ levels.  Used internally by the generic PCI code.  */
 220     int irq_state[4];
 221
 222     /* Capability bits */
 223     uint32_t cap_present;
 224
 225     /* Offset of MSI-X capability in config space */
 226     uint8_t msix_cap;
 227
 228     /* MSI-X entries */
 229     int msix_entries_nr;
 230
 231     /* Space to store MSIX table */
 232     uint8_t *msix_table_page;
 233     /* MMIO index used to map MSIX table and pending bit entries. */
 234     int msix_mmio_index;
 235     /* Reference-count for entries actually in use by driver. */
 236     unsigned *msix_entry_used;
 237     /* Region including the MSI-X table */
 238     uint32_t msix_bar_size;
 239     /* Version id needed for VMState */
 240     int32_t version_id;
 241     /* How much space does an MSIX table need. */
 242     /* The spec requires giving the table structure
 243      * a 4K aligned region all by itself. Align it to
 244      * target pages so that drivers can do passthrough
 245      * on the rest of the region. */
 246     target_phys_addr_t msix_page_size;
 247
 248     struct kvm_irq_routing_entry *msix_irq_entries;
 249
 250     /* Device capability configuration space */
 251     struct {
 252         int supported;
 253         unsigned int start, length;
 254         PCICapConfigReadFunc *config_read;
 255         PCICapConfigWriteFunc *config_write;
 256     } cap;
 257 };
 258
 259 PCIDevice *pci_register_device(PCIBus *bus, const char *name,
 260                                int instance_size, int devfn,
 261                                PCIConfigReadFunc *config_read,
 262                                PCIConfigWriteFunc *config_write);
 263
 264 void pci_register_bar(PCIDevice *pci_dev, int region_num,
 265                             uint32_t size, int type,
 266                             PCIMapIORegionFunc *map_func);
 267
 268 int pci_enable_capability_support(PCIDevice *pci_dev,
 269                                   uint32_t config_start,
 270                                   PCICapConfigReadFunc *config_read,
 271                                   PCICapConfigWriteFunc *config_write,
 272                                   PCICapConfigInitFunc *config_init);
 273
 274 int pci_map_irq(PCIDevice *pci_dev, int pin);
 275
 276 int pci_add_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_size);
 277
 278 void pci_del_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_size);
 279
 280 void pci_reserve_capability(PCIDevice *pci_dev, uint8_t offset, uint8_t size);
 281
 282 uint8_t pci_find_capability(PCIDevice *pci_dev, uint8_t cap_id);
 283
 284 uint32_t pci_default_read_config(PCIDevice *d,
 285                                  uint32_t address, int len);
 286 void pci_default_write_config(PCIDevice *d,
 287                               uint32_t address, uint32_t val, int len);
 288 void pci_device_save(PCIDevice *s, QEMUFile *f);
 289 int pci_device_load(PCIDevice *s, QEMUFile *f);
 290 uint32_t pci_default_cap_read_config(PCIDevice *pci_dev,
 291                                      uint32_t address, int len);
 292 void pci_default_cap_write_config(PCIDevice *pci_dev,
 293                                   uint32_t address, uint32_t val, int len);
 294 int pci_access_cap_config(PCIDevice *pci_dev, uint32_t address, int len);
 295
 296 typedef void (*pci_set_irq_fn)(void *opaque, int irq_num, int level);
 297 typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num);
 298 typedef int (*pci_hotplug_fn)(PCIDevice *pci_dev, int state);
 299 void pci_bus_new_inplace(PCIBus *bus, DeviceState *parent,
 300                          const char *name, int devfn_min);
 301 PCIBus *pci_bus_new(DeviceState *parent, const char *name, int devfn_min);
 302 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
 303                   void *irq_opaque, int nirq);
 304 void pci_bus_hotplug(PCIBus *bus, pci_hotplug_fn hotplug);
 305 PCIBus *pci_register_bus(DeviceState *parent, const char *name,
 306                          pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
 307                          void *irq_opaque, int devfn_min, int nirq);
 308
 309 PCIDevice *pci_nic_init(NICInfo *nd, const char *default_model,
 310                         const char *default_devaddr);
 311 PCIDevice *pci_nic_init_nofail(NICInfo *nd, const char *default_model,
 312                                const char *default_devaddr);
 313 void pci_data_write(void *opaque, uint32_t addr, uint32_t val, int len);
 314 uint32_t pci_data_read(void *opaque, uint32_t addr, int len);
 315 int pci_bus_num(PCIBus *s);
 316 void pci_for_each_device(int bus_num, void (*fn)(PCIDevice *d));
 317 PCIBus *pci_find_bus(int bus_num);
 318 PCIDevice *pci_find_device(int bus_num, int slot, int function);
 319 PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr);
 320
 321 int pci_read_devaddr(Monitor *mon, const char *addr, int *domp, int *busp,
 322                      unsigned *slotp);
 323
 324 int pci_parse_host_devaddr(const char *addr, int *busp,
 325                            int *slotp, int *funcp);
 326
 327 void pci_info(Monitor *mon);
 328 PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint16_t vid, uint16_t did,
 329                         pci_map_irq_fn map_irq, const char *name);
 330
 331 static inline void
 332 pci_set_byte(uint8_t *config, uint8_t val)
 333 {
 334     *config = val;
 335 }
 336
 337 static inline uint8_t
 338 pci_get_byte(uint8_t *config)
 339 {
 340     return *config;
 341 }
 342
 343 static inline void
 344 pci_set_word(uint8_t *config, uint16_t val)
 345 {
 346     cpu_to_le16wu((uint16_t *)config, val);
 347 }
 348
 349 static inline uint16_t
 350 pci_get_word(uint8_t *config)
 351 {
 352     return le16_to_cpupu((uint16_t *)config);
 353 }
 354
 355 static inline void
 356 pci_set_long(uint8_t *config, uint32_t val)
 357 {
 358     cpu_to_le32wu((uint32_t *)config, val);
 359 }
 360
 361 static inline uint32_t
 362 pci_get_long(uint8_t *config)
 363 {
 364     return le32_to_cpupu((uint32_t *)config);
 365 }
 366
 367 static inline void
 368 pci_config_set_vendor_id(uint8_t *pci_config, uint16_t val)
 369 {
 370     pci_set_word(&pci_config[PCI_VENDOR_ID], val);
 371 }
 372
 373 static inline void
 374 pci_config_set_device_id(uint8_t *pci_config, uint16_t val)
 375 {
 376     pci_set_word(&pci_config[PCI_DEVICE_ID], val);
 377 }
 378
 379 static inline void
 380 pci_config_set_class(uint8_t *pci_config, uint16_t val)
 381 {
 382     pci_set_word(&pci_config[PCI_CLASS_DEVICE], val);
 383 }
 384
 385 typedef int (*pci_qdev_initfn)(PCIDevice *dev);
 386 typedef struct {
 387     DeviceInfo qdev;
 388     pci_qdev_initfn init;
 389     PCIUnregisterFunc *exit;
 390     PCIConfigReadFunc *config_read;
 391     PCIConfigWriteFunc *config_write;
 392 } PCIDeviceInfo;
 393
 394 void pci_qdev_register(PCIDeviceInfo *info);
 395 void pci_qdev_register_many(PCIDeviceInfo *info);
 396
 397 PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name);
 398 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name);
 399
 400 /* lsi53c895a.c */
 401 #define LSI_MAX_DEVS 7
 402
 403 /* vmware_vga.c */
 404 void pci_vmsvga_init(PCIBus *bus);
 405
 406 /* usb-uhci.c */
 407 void usb_uhci_piix3_init(PCIBus *bus, int devfn);
 408 void usb_uhci_piix4_init(PCIBus *bus, int devfn);
 409
 410 /* usb-ohci.c */
 411 void usb_ohci_init_pci(struct PCIBus *bus, int devfn);
 412
 413 /* prep_pci.c */
 414 PCIBus *pci_prep_init(qemu_irq *pic);
 415
 416 /* apb_pci.c */
 417 PCIBus *pci_apb_init(target_phys_addr_t special_base,
 418                      target_phys_addr_t mem_base,
 419                      qemu_irq *pic, PCIBus **bus2, PCIBus **bus3);
 420
 421 /* sh_pci.c */
 422 PCIBus *sh_pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
 423                             void *pic, int devfn_min, int nirq);
 424
 425 #endif