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Fix 32-bit overflow in parallels image support
[qemu-kvm/fedora.git] / kvm / bios / rombios32.c
blob0b3556cbafcf32b9b259d6e0d02b3e0fc73d2cc7
1 /////////////////////////////////////////////////////////////////////////
2 // $Id: rombios32.c,v 1.11 2007/08/03 13:56:13 vruppert Exp $
3 /////////////////////////////////////////////////////////////////////////
4 //
5 // 32 bit Bochs BIOS init code
6 // Copyright (C) 2006 Fabrice Bellard
7 //
8 // This library is free software; you can redistribute it and/or
9 // modify it under the terms of the GNU Lesser General Public
10 // License as published by the Free Software Foundation; either
11 // version 2 of the License, or (at your option) any later version.
12 //
13 // This library is distributed in the hope that it will be useful,
14 // but WITHOUT ANY WARRANTY; without even the implied warranty of
15 // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 // Lesser General Public License for more details.
17 //
18 // You should have received a copy of the GNU Lesser General Public
19 // License along with this library; if not, write to the Free Software
20 // Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
21 #include <stdarg.h>
22 #include <stddef.h>
23
24 #include "rombios.h"
25
26 typedef signed char int8_t;
27 typedef short int16_t;
28 typedef int int32_t;
29 typedef long long int64_t;
30 typedef unsigned char uint8_t;
31 typedef unsigned short uint16_t;
32 typedef unsigned int uint32_t;
33 typedef unsigned long long uint64_t;
34
35 /* if true, put the MP float table and ACPI RSDT in EBDA and the MP
36 table in RAM. Unfortunately, Linux has bugs with that, so we prefer
37 to modify the BIOS in shadow RAM */
38 //#define BX_USE_EBDA_TABLES
39
40 /* define it if the (emulated) hardware supports SMM mode */
41 //#define BX_USE_SMM
42
43 #define cpuid(index, eax, ebx, ecx, edx) \
44 asm volatile ("cpuid" \
45 : "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx) \
46 : "0" (index))
47
48 #define wbinvd() asm volatile("wbinvd")
49
50 #define CPUID_MSR (1 << 5)
51 #define CPUID_APIC (1 << 9)
52 #define CPUID_MTRR (1 << 12)
53
54 #define APIC_BASE ((uint8_t *)0xfee00000)
55 #define APIC_ICR_LOW 0x300
56 #define APIC_SVR 0x0F0
57 #define APIC_ID 0x020
58 #define APIC_LVT3 0x370
59
60 /* IRQs 5,9,10,11 */
61 #define PCI_ISA_IRQ_MASK 0x0e20U
62
63 #define APIC_ENABLED 0x0100
64
65 #define AP_BOOT_ADDR 0x9f000
66
67 #define MPTABLE_MAX_SIZE 0x00002000
68 #define SMI_CMD_IO_ADDR 0xb2
69
70 #define BIOS_TMP_STORAGE 0x00030000 /* 64 KB used to copy the BIOS to shadow RAM */
71
72 #define MSR_MTRRcap 0x000000fe
73 #define MSR_MTRRfix64K_00000 0x00000250
74 #define MSR_MTRRfix16K_80000 0x00000258
75 #define MSR_MTRRfix16K_A0000 0x00000259
76 #define MSR_MTRRfix4K_C0000 0x00000268
77 #define MSR_MTRRfix4K_C8000 0x00000269
78 #define MSR_MTRRfix4K_D0000 0x0000026a
79 #define MSR_MTRRfix4K_D8000 0x0000026b
80 #define MSR_MTRRfix4K_E0000 0x0000026c
81 #define MSR_MTRRfix4K_E8000 0x0000026d
82 #define MSR_MTRRfix4K_F0000 0x0000026e
83 #define MSR_MTRRfix4K_F8000 0x0000026f
84 #define MSR_MTRRdefType 0x000002ff
85
86 #define MTRRphysBase_MSR(reg) (0x200 + 2 * (reg))
87 #define MTRRphysMask_MSR(reg) (0x200 + 2 * (reg) + 1)
88
89 #define MAX_INT_OVERRIDES 16
90
91 static inline void outl(int addr, int val)
92 {
93 asm volatile ("outl %1, %w0" : : "d" (addr), "a" (val));
94 }
95
96 static inline void outw(int addr, int val)
97 {
98 asm volatile ("outw %w1, %w0" : : "d" (addr), "a" (val));
99 }
100
101 static inline void outb(int addr, int val)
102 {
103 asm volatile ("outb %b1, %w0" : : "d" (addr), "a" (val));
104 }
105
106 static inline uint32_t inl(int addr)
107 {
108 uint32_t val;
109 asm volatile ("inl %w1, %0" : "=a" (val) : "d" (addr));
110 return val;
111 }
112
113 static inline uint16_t inw(int addr)
114 {
115 uint16_t val;
116 asm volatile ("inw %w1, %w0" : "=a" (val) : "d" (addr));
117 return val;
118 }
119
120 static inline uint8_t inb(int addr)
121 {
122 uint8_t val;
123 asm volatile ("inb %w1, %b0" : "=a" (val) : "d" (addr));
124 return val;
125 }
126
127 static inline void writel(void *addr, uint32_t val)
128 {
129 *(volatile uint32_t *)addr = val;
130 }
131
132 static inline void writew(void *addr, uint16_t val)
133 {
134 *(volatile uint16_t *)addr = val;
135 }
136
137 static inline void writeb(void *addr, uint8_t val)
138 {
139 *(volatile uint8_t *)addr = val;
140 }
141
142 static inline uint32_t readl(const void *addr)
143 {
144 return *(volatile const uint32_t *)addr;
145 }
146
147 static inline uint16_t readw(const void *addr)
148 {
149 return *(volatile const uint16_t *)addr;
150 }
151
152 static inline uint8_t readb(const void *addr)
153 {
154 return *(volatile const uint8_t *)addr;
155 }
156
157 static inline void putc(int c)
158 {
159 outb(INFO_PORT, c);
160 }
161
162 static uint64_t rdmsr(unsigned index)
163 {
164 unsigned long long ret;
165
166 asm ("rdmsr" : "=A"(ret) : "c"(index));
167 return ret;
168 }
169
170 static void wrmsr(unsigned index, uint64_t val)
171 {
172 asm volatile ("wrmsr" : : "c"(index), "A"(val));
173 }
174
175 static inline int isdigit(int c)
176 {
177 return c >= '0' && c <= '9';
178 }
179
180 void *memset(void *d1, int val, size_t len)
181 {
182 uint8_t *d = d1;
183
184 while (len--) {
185 *d++ = val;
186 }
187 return d1;
188 }
189
190 void *memcpy(void *d1, const void *s1, size_t len)
191 {
192 uint8_t *d = d1;
193 const uint8_t *s = s1;
194
195 while (len--) {
196 *d++ = *s++;
197 }
198 return d1;
199 }
200
201 void *memmove(void *d1, const void *s1, size_t len)
202 {
203 uint8_t *d = d1;
204 const uint8_t *s = s1;
205
206 if (d <= s) {
207 while (len--) {
208 *d++ = *s++;
209 }
210 } else {
211 d += len;
212 s += len;
213 while (len--) {
214 *--d = *--s;
215 }
216 }
217 return d1;
218 }
219
220 int memcmp(const void *s1, const void *s2, size_t len)
221 {
222 const int8_t *p1 = s1;
223 const int8_t *p2 = s2;
224
225 while (len--) {
226 int r = *p1++ - *p2++;
227 if(r)
228 return r;
229 }
230
231 return 0;
232 }
233
234 size_t strlen(const char *s)
235 {
236 const char *s1;
237 for(s1 = s; *s1 != '\0'; s1++);
238 return s1 - s;
239 }
240
241 /* from BSD ppp sources */
242 int vsnprintf(char *buf, int buflen, const char *fmt, va_list args)
243 {
244 int c, i, n;
245 int width, prec, fillch;
246 int base, len, neg;
247 unsigned long val = 0;
248 const char *f;
249 char *str, *buf0;
250 char num[32];
251 static const char hexchars[] = "0123456789abcdef";
252
253 buf0 = buf;
254 --buflen;
255 while (buflen > 0) {
256 for (f = fmt; *f != '%' && *f != 0; ++f)
257 ;
258 if (f > fmt) {
259 len = f - fmt;
260 if (len > buflen)
261 len = buflen;
262 memcpy(buf, fmt, len);
263 buf += len;
264 buflen -= len;
265 fmt = f;
266 }
267 if (*fmt == 0)
268 break;
269 c = *++fmt;
270 width = prec = 0;
271 fillch = ' ';
272 if (c == '0') {
273 fillch = '0';
274 c = *++fmt;
275 }
276 if (c == '*') {
277 width = va_arg(args, int);
278 c = *++fmt;
279 } else {
280 while (isdigit(c)) {
281 width = width * 10 + c - '0';
282 c = *++fmt;
283 }
284 }
285 if (c == '.') {
286 c = *++fmt;
287 if (c == '*') {
288 prec = va_arg(args, int);
289 c = *++fmt;
290 } else {
291 while (isdigit(c)) {
292 prec = prec * 10 + c - '0';
293 c = *++fmt;
294 }
295 }
296 }
297 /* modifiers */
298 switch(c) {
299 case 'l':
300 c = *++fmt;
301 break;
302 default:
303 break;
304 }
305 str = 0;
306 base = 0;
307 neg = 0;
308 ++fmt;
309 switch (c) {
310 case 'd':
311 i = va_arg(args, int);
312 if (i < 0) {
313 neg = 1;
314 val = -i;
315 } else
316 val = i;
317 base = 10;
318 break;
319 case 'o':
320 val = va_arg(args, unsigned int);
321 base = 8;
322 break;
323 case 'x':
324 case 'X':
325 val = va_arg(args, unsigned int);
326 base = 16;
327 break;
328 case 'p':
329 val = (unsigned long) va_arg(args, void *);
330 base = 16;
331 neg = 2;
332 break;
333 case 's':
334 str = va_arg(args, char *);
335 break;
336 case 'c':
337 num[0] = va_arg(args, int);
338 num[1] = 0;
339 str = num;
340 break;
341 default:
342 *buf++ = '%';
343 if (c != '%')
344 --fmt; /* so %z outputs %z etc. */
345 --buflen;
346 continue;
347 }
348 if (base != 0) {
349 str = num + sizeof(num);
350 *--str = 0;
351 while (str > num + neg) {
352 *--str = hexchars[val % base];
353 val = val / base;
354 if (--prec <= 0 && val == 0)
355 break;
356 }
357 switch (neg) {
358 case 1:
359 *--str = '-';
360 break;
361 case 2:
362 *--str = 'x';
363 *--str = '0';
364 break;
365 }
366 len = num + sizeof(num) - 1 - str;
367 } else {
368 len = strlen(str);
369 if (prec > 0 && len > prec)
370 len = prec;
371 }
372 if (width > 0) {
373 if (width > buflen)
374 width = buflen;
375 if ((n = width - len) > 0) {
376 buflen -= n;
377 for (; n > 0; --n)
378 *buf++ = fillch;
379 }
380 }
381 if (len > buflen)
382 len = buflen;
383 memcpy(buf, str, len);
384 buf += len;
385 buflen -= len;
386 }
387 *buf = 0;
388 return buf - buf0;
389 }
390
391 int snprintf(char * buf, size_t size, const char *fmt, ...)
392 {
393 va_list args;
394 int i;
395
396 va_start(args, fmt);
397 i=vsnprintf(buf,size,fmt,args);
398 va_end(args);
399 return i;
400 }
401
402 void bios_printf(int flags, const char *fmt, ...)
403 {
404 va_list ap;
405 char buf[1024];
406 const char *s;
407
408 if ((flags & BIOS_PRINTF_DEBHALT) == BIOS_PRINTF_DEBHALT)
409 outb(PANIC_PORT2, 0x00);
410
411 va_start(ap, fmt);
412 vsnprintf(buf, sizeof(buf), fmt, ap);
413 s = buf;
414 while (*s)
415 putc(*s++);
416 va_end(ap);
417 }
418
419 void delay_ms(int n)
420 {
421 int i, j;
422 for(i = 0; i < n; i++) {
423 #ifdef BX_QEMU
424 /* approximative ! */
425 for(j = 0; j < 1000000; j++);
426 #else
427 {
428 int r1, r2;
429 j = 66;
430 r1 = inb(0x61) & 0x10;
431 do {
432 r2 = inb(0x61) & 0x10;
433 if (r1 != r2) {
434 j--;
435 r1 = r2;
436 }
437 } while (j > 0);
438 }
439 #endif
440 }
441 }
442
443 uint16_t smp_cpus;
444 uint32_t cpuid_signature;
445 uint32_t cpuid_features;
446 uint32_t cpuid_ext_features;
447 unsigned long ram_size;
448 uint64_t ram_end;
449 #ifdef BX_QEMU
450 uint8_t irq0_override;
451 #endif
452 #ifdef BX_USE_EBDA_TABLES
453 unsigned long ebda_cur_addr;
454 #endif
455 int acpi_enabled;
456 uint32_t pm_io_base, smb_io_base;
457 int pm_sci_int;
458 unsigned long bios_table_cur_addr;
459 unsigned long bios_table_end_addr;
460
461 void init_smp_msrs(void)
462 {
463 *(uint32_t *)SMP_MSR_ADDR = 0;
464 }
465
466 static inline uint64_t le64_to_cpu(uint64_t x)
467 {
468 return x;
469 }
470
471 void wrmsr_smp(uint32_t index, uint64_t val)
472 {
473 static struct { uint32_t ecx, eax, edx; } *p = (void *)SMP_MSR_ADDR;
474
475 wrmsr(index, val);
476 p->ecx = index;
477 p->eax = val;
478 p->edx = val >> 32;
479 ++p;
480 p->ecx = 0;
481 }
482
483 #ifdef BX_QEMU
484
485 int qemu_cfg_port;
486
487 void qemu_cfg_select(int f)
488 {
489 outw(QEMU_CFG_CTL_PORT, f);
490 }
491
492 int qemu_cfg_port_probe()
493 {
494 char *sig = "QEMU";
495 int i;
496
497 qemu_cfg_select(QEMU_CFG_SIGNATURE);
498
499 for (i = 0; i < 4; i++)
500 if (inb(QEMU_CFG_DATA_PORT) != sig[i])
501 return 0;
502
503 return 1;
504 }
505
506 void qemu_cfg_read(uint8_t *buf, int len)
507 {
508 while (len--)
509 *(buf++) = inb(QEMU_CFG_DATA_PORT);
510 }
511
512 static uint16_t acpi_additional_tables(void)
513 {
514 uint16_t cnt;
515
516 qemu_cfg_select(QEMU_CFG_ACPI_TABLES);
517 qemu_cfg_read((uint8_t*)&cnt, sizeof(cnt));
518
519 return cnt;
520 }
521
522 static int acpi_load_table(int i, uint32_t addr, uint16_t *len)
523 {
524 qemu_cfg_read((uint8_t*)len, sizeof(*len));
525
526 if (!*len)
527 return -1;
528
529 qemu_cfg_read((uint8_t*)addr, *len);
530 return 0;
531 }
532
533 static uint16_t smbios_entries(void)
534 {
535 uint16_t cnt;
536
537 qemu_cfg_select(QEMU_CFG_SMBIOS_ENTRIES);
538 qemu_cfg_read((uint8_t*)&cnt, sizeof(cnt));
539
540 return cnt;
541 }
542
543 uint64_t qemu_cfg_get64 (void)
544 {
545 uint64_t ret;
546
547 qemu_cfg_read((uint8_t*)&ret, 8);
548 return le64_to_cpu(ret);
549 }
550 #endif
551
552 #ifdef BX_QEMU
553 void irq0_override_probe(void)
554 {
555 if(qemu_cfg_port) {
556 qemu_cfg_select(QEMU_CFG_IRQ0_OVERRIDE);
557 qemu_cfg_read(&irq0_override, 1);
558 }
559 }
560 #endif
561
562 void cpu_probe(void)
563 {
564 uint32_t eax, ebx, ecx, edx;
565 cpuid(1, eax, ebx, ecx, edx);
566 cpuid_signature = eax;
567 cpuid_features = edx;
568 cpuid_ext_features = ecx;
569 }
570
571 static int cmos_readb(int addr)
572 {
573 outb(0x70, addr);
574 return inb(0x71);
575 }
576
577 void setup_mtrr(void)
578 {
579 int i, vcnt, fix, wc;
580 uint32_t mtrr_cap;
581 union {
582 uint8_t valb[8];
583 uint64_t val;
584 } u;
585
586 if (!(cpuid_features & CPUID_MTRR))
587 return;
588
589 if (!(cpuid_features & CPUID_MSR))
590 return;
591
592 mtrr_cap = rdmsr(MSR_MTRRcap);
593 vcnt = mtrr_cap & 0xff;
594 fix = mtrr_cap & 0x100;
595 wc = mtrr_cap & 0x400;
596 if (!vcnt || !fix)
597 return;
598
599 u.val = 0;
600 for (i = 0; i < 8; ++i)
601 if (ram_size >= 65536 * (i + 1))
602 u.valb[i] = 6;
603 wrmsr_smp(MSR_MTRRfix64K_00000, u.val);
604 u.val = 0;
605 for (i = 0; i < 8; ++i)
606 if (ram_size >= 65536 * 8 + 16384 * (i + 1))
607 u.valb[i] = 6;
608 wrmsr_smp(MSR_MTRRfix16K_80000, u.val);
609 wrmsr_smp(MSR_MTRRfix16K_A0000, 0);
610 wrmsr_smp(MSR_MTRRfix4K_C0000, 0);
611 wrmsr_smp(MSR_MTRRfix4K_C8000, 0);
612 wrmsr_smp(MSR_MTRRfix4K_D0000, 0);
613 wrmsr_smp(MSR_MTRRfix4K_D8000, 0);
614 wrmsr_smp(MSR_MTRRfix4K_E0000, 0);
615 wrmsr_smp(MSR_MTRRfix4K_E8000, 0);
616 wrmsr_smp(MSR_MTRRfix4K_F0000, 0);
617 wrmsr_smp(MSR_MTRRfix4K_F8000, 0);
618 /* Mark 3.5-4GB as UC, anything not specified defaults to WB */
619 wrmsr_smp(MTRRphysBase_MSR(0), 0xe0000000ull | 0);
620 wrmsr_smp(MTRRphysMask_MSR(0), ~(0x20000000ull - 1) | 0x800);
621 wrmsr_smp(MSR_MTRRdefType, 0xc06);
622 }
623
624 void ram_probe(void)
625 {
626 if (cmos_readb(0x34) | cmos_readb(0x35))
627 ram_size = (cmos_readb(0x34) | (cmos_readb(0x35) << 8)) * 65536 +
628 16 * 1024 * 1024;
629 else
630 ram_size = (cmos_readb(0x17) | (cmos_readb(0x18) << 8)) * 1024;
631
632 if (cmos_readb(0x5b) | cmos_readb(0x5c) | cmos_readb(0x5d))
633 ram_end = (((uint64_t)cmos_readb(0x5b) << 16) |
634 ((uint64_t)cmos_readb(0x5c) << 24) |
635 ((uint64_t)cmos_readb(0x5d) << 32)) + (1ull << 32);
636 else
637 ram_end = ram_size;
638
639 BX_INFO("end of ram=%ldMB\n", ram_end >> 20);
640
641 BX_INFO("ram_size=0x%08lx\n", ram_size);
642 #ifdef BX_USE_EBDA_TABLES
643 ebda_cur_addr = ((*(uint16_t *)(0x40e)) << 4) + 0x380;
644 BX_INFO("ebda_cur_addr: 0x%08lx\n", ebda_cur_addr);
645 #endif
646 }
647
648 /****************************************************/
649 /* SMP probe */
650
651 extern uint8_t smp_ap_boot_code_start;
652 extern uint8_t smp_ap_boot_code_end;
653
654 /* find the number of CPUs by launching a SIPI to them */
655 void smp_probe(void)
656 {
657 uint32_t val, sipi_vector;
658
659 writew(&smp_cpus, 1);
660 if (cpuid_features & CPUID_APIC) {
661
662 /* enable local APIC */
663 val = readl(APIC_BASE + APIC_SVR);
664 val |= APIC_ENABLED;
665 writel(APIC_BASE + APIC_SVR, val);
666
667 /* copy AP boot code */
668 memcpy((void *)AP_BOOT_ADDR, &smp_ap_boot_code_start,
669 &smp_ap_boot_code_end - &smp_ap_boot_code_start);
670
671 /* broadcast SIPI */
672 writel(APIC_BASE + APIC_ICR_LOW, 0x000C4500);
673 sipi_vector = AP_BOOT_ADDR >> 12;
674 writel(APIC_BASE + APIC_ICR_LOW, 0x000C4600 | sipi_vector);
675
676 #ifndef BX_QEMU
677 delay_ms(10);
678 #else
679 while (cmos_readb(0x5f) + 1 != readw(&smp_cpus))
680 ;
681 #endif
682 }
683 BX_INFO("Found %d cpu(s)\n", readw(&smp_cpus));
684 }
685
686 /****************************************************/
687 /* PCI init */
688
689 #define PCI_ADDRESS_SPACE_MEM 0x00
690 #define PCI_ADDRESS_SPACE_IO 0x01
691 #define PCI_ADDRESS_SPACE_MEM_PREFETCH 0x08
692
693 #define PCI_ROM_SLOT 6
694 #define PCI_NUM_REGIONS 7
695
696 #define PCI_DEVICES_MAX 64
697
698 #define PCI_VENDOR_ID 0x00 /* 16 bits */
699 #define PCI_DEVICE_ID 0x02 /* 16 bits */
700 #define PCI_COMMAND 0x04 /* 16 bits */
701 #define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
702 #define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
703 #define PCI_CLASS_DEVICE 0x0a /* Device class */
704 #define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
705 #define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
706 #define PCI_MIN_GNT 0x3e /* 8 bits */
707 #define PCI_MAX_LAT 0x3f /* 8 bits */
708
709 #define PCI_VENDOR_ID_INTEL 0x8086
710 #define PCI_DEVICE_ID_INTEL_82441 0x1237
711 #define PCI_DEVICE_ID_INTEL_82371SB_0 0x7000
712 #define PCI_DEVICE_ID_INTEL_82371SB_1 0x7010
713 #define PCI_DEVICE_ID_INTEL_82371AB_0 0x7110
714 #define PCI_DEVICE_ID_INTEL_82371AB 0x7111
715 #define PCI_DEVICE_ID_INTEL_82371AB_3 0x7113
716
717 #define PCI_VENDOR_ID_IBM 0x1014
718 #define PCI_VENDOR_ID_APPLE 0x106b
719
720 typedef struct PCIDevice {
721 int bus;
722 int devfn;
723 } PCIDevice;
724
725 static uint32_t pci_bios_io_addr;
726 static uint32_t pci_bios_mem_addr;
727 static uint32_t pci_bios_bigmem_addr;
728 /* host irqs corresponding to PCI irqs A-D */
729 static uint8_t pci_irqs[4] = { 10, 10, 11, 11 };
730 static PCIDevice i440_pcidev;
731
732 static void pci_config_writel(PCIDevice *d, uint32_t addr, uint32_t val)
733 {
734 outl(0xcf8, 0x80000000 | (d->bus << 16) | (d->devfn << 8) | (addr & 0xfc));
735 outl(0xcfc, val);
736 }
737
738 static void pci_config_writew(PCIDevice *d, uint32_t addr, uint32_t val)
739 {
740 outl(0xcf8, 0x80000000 | (d->bus << 16) | (d->devfn << 8) | (addr & 0xfc));
741 outw(0xcfc + (addr & 2), val);
742 }
743
744 static void pci_config_writeb(PCIDevice *d, uint32_t addr, uint32_t val)
745 {
746 outl(0xcf8, 0x80000000 | (d->bus << 16) | (d->devfn << 8) | (addr & 0xfc));
747 outb(0xcfc + (addr & 3), val);
748 }
749
750 static uint32_t pci_config_readl(PCIDevice *d, uint32_t addr)
751 {
752 outl(0xcf8, 0x80000000 | (d->bus << 16) | (d->devfn << 8) | (addr & 0xfc));
753 return inl(0xcfc);
754 }
755
756 static uint32_t pci_config_readw(PCIDevice *d, uint32_t addr)
757 {
758 outl(0xcf8, 0x80000000 | (d->bus << 16) | (d->devfn << 8) | (addr & 0xfc));
759 return inw(0xcfc + (addr & 2));
760 }
761
762 static uint32_t pci_config_readb(PCIDevice *d, uint32_t addr)
763 {
764 outl(0xcf8, 0x80000000 | (d->bus << 16) | (d->devfn << 8) | (addr & 0xfc));
765 return inb(0xcfc + (addr & 3));
766 }
767
768 static void pci_set_io_region_addr(PCIDevice *d, int region_num, uint32_t addr)
769 {
770 uint16_t cmd;
771 uint32_t ofs, old_addr;
772
773 if ( region_num == PCI_ROM_SLOT ) {
774 ofs = 0x30;
775 }else{
776 ofs = 0x10 + region_num * 4;
777 }
778
779 old_addr = pci_config_readl(d, ofs);
780
781 pci_config_writel(d, ofs, addr);
782 BX_INFO("region %d: 0x%08x\n", region_num, addr);
783
784 /* enable memory mappings */
785 cmd = pci_config_readw(d, PCI_COMMAND);
786 if ( region_num == PCI_ROM_SLOT )
787 cmd |= 2;
788 else if (old_addr & PCI_ADDRESS_SPACE_IO)
789 cmd |= 1;
790 else
791 cmd |= 2;
792 pci_config_writew(d, PCI_COMMAND, cmd);
793 }
794
795 /* return the global irq number corresponding to a given device irq
796 pin. We could also use the bus number to have a more precise
797 mapping. */
798 static int pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num)
799 {
800 int slot_addend;
801 slot_addend = (pci_dev->devfn >> 3) - 1;
802 return (irq_num + slot_addend) & 3;
803 }
804
805 static void find_bios_table_area(void)
806 {
807 unsigned long addr;
808 for(addr = 0xf0000; addr < 0x100000; addr += 16) {
809 if (*(uint32_t *)addr == 0xaafb4442) {
810 bios_table_cur_addr = addr + 8;
811 bios_table_end_addr = bios_table_cur_addr + *(uint32_t *)(addr + 4);
812 BX_INFO("bios_table_addr: 0x%08lx end=0x%08lx\n",
813 bios_table_cur_addr, bios_table_end_addr);
814 return;
815 }
816 }
817 return;
818 }
819
820 static void bios_shadow_init(PCIDevice *d)
821 {
822 int v;
823
824 if (bios_table_cur_addr == 0)
825 return;
826
827 /* remap the BIOS to shadow RAM an keep it read/write while we
828 are writing tables */
829 v = pci_config_readb(d, 0x59);
830 v &= 0xcf;
831 pci_config_writeb(d, 0x59, v);
832 memcpy((void *)BIOS_TMP_STORAGE, (void *)0x000f0000, 0x10000);
833 v |= 0x30;
834 pci_config_writeb(d, 0x59, v);
835 memcpy((void *)0x000f0000, (void *)BIOS_TMP_STORAGE, 0x10000);
836
837 i440_pcidev = *d;
838 }
839
840 static void bios_lock_shadow_ram(void)
841 {
842 PCIDevice *d = &i440_pcidev;
843 int v;
844
845 wbinvd();
846 v = pci_config_readb(d, 0x59);
847 v = (v & 0x0f) | (0x10);
848 pci_config_writeb(d, 0x59, v);
849 }
850
851 static void pci_bios_init_bridges(PCIDevice *d)
852 {
853 uint16_t vendor_id, device_id;
854
855 vendor_id = pci_config_readw(d, PCI_VENDOR_ID);
856 device_id = pci_config_readw(d, PCI_DEVICE_ID);
857
858 if (vendor_id == PCI_VENDOR_ID_INTEL &&
859 (device_id == PCI_DEVICE_ID_INTEL_82371SB_0 ||
860 device_id == PCI_DEVICE_ID_INTEL_82371AB_0)) {
861 int i, irq;
862 uint8_t elcr[2];
863
864 /* PIIX3/PIIX4 PCI to ISA bridge */
865
866 elcr[0] = 0x00;
867 elcr[1] = 0x00;
868 for(i = 0; i < 4; i++) {
869 irq = pci_irqs[i];
870 /* set to trigger level */
871 elcr[irq >> 3] |= (1 << (irq & 7));
872 /* activate irq remapping in PIIX */
873 pci_config_writeb(d, 0x60 + i, irq);
874 }
875 outb(0x4d0, elcr[0]);
876 outb(0x4d1, elcr[1]);
877 BX_INFO("PIIX3/PIIX4 init: elcr=%02x %02x\n",
878 elcr[0], elcr[1]);
879 } else if (vendor_id == PCI_VENDOR_ID_INTEL && device_id == PCI_DEVICE_ID_INTEL_82441) {
880 /* i440 PCI bridge */
881 bios_shadow_init(d);
882 }
883 }
884
885 extern uint8_t smm_relocation_start, smm_relocation_end;
886 extern uint8_t smm_code_start, smm_code_end;
887
888 #ifdef BX_USE_SMM
889 static void smm_init(PCIDevice *d)
890 {
891 uint32_t value;
892
893 /* check if SMM init is already done */
894 value = pci_config_readl(d, 0x58);
895 if ((value & (1 << 25)) == 0) {
896
897 /* enable the SMM memory window */
898 pci_config_writeb(&i440_pcidev, 0x72, 0x02 | 0x48);
899
900 /* save original memory content */
901 memcpy((void *)0xa8000, (void *)0x38000, 0x8000);
902
903 /* copy the SMM relocation code */
904 memcpy((void *)0x38000, &smm_relocation_start,
905 &smm_relocation_end - &smm_relocation_start);
906
907 /* enable SMI generation when writing to the APMC register */
908 pci_config_writel(d, 0x58, value | (1 << 25));
909
910 /* init APM status port */
911 outb(0xb3, 0x01);
912
913 /* raise an SMI interrupt */
914 outb(0xb2, 0x00);
915
916 /* wait until SMM code executed */
917 while (inb(0xb3) != 0x00);
918
919 /* restore original memory content */
920 memcpy((void *)0x38000, (void *)0xa8000, 0x8000);
921
922 /* copy the SMM code */
923 memcpy((void *)0xa8000, &smm_code_start,
924 &smm_code_end - &smm_code_start);
925 wbinvd();
926
927 /* close the SMM memory window and enable normal SMM */
928 pci_config_writeb(&i440_pcidev, 0x72, 0x02 | 0x08);
929 }
930 }
931 #endif
932
933 static void piix4_pm_enable(PCIDevice *d)
934 {
935 /* PIIX4 Power Management device (for ACPI) */
936 pci_config_writel(d, 0x40, PM_IO_BASE | 1);
937 pci_config_writeb(d, 0x80, 0x01); /* enable PM io space */
938 pci_config_writel(d, 0x90, SMB_IO_BASE | 1);
939 pci_config_writeb(d, 0xd2, 0x09); /* enable SMBus io space */
940 #ifdef BX_USE_SMM
941 smm_init(d);
942 #endif
943 }
944
945 static void pci_bios_init_device(PCIDevice *d)
946 {
947 int class;
948 uint32_t *paddr;
949 int i, pin, pic_irq, vendor_id, device_id;
950
951 class = pci_config_readw(d, PCI_CLASS_DEVICE);
952 vendor_id = pci_config_readw(d, PCI_VENDOR_ID);
953 device_id = pci_config_readw(d, PCI_DEVICE_ID);
954 BX_INFO("PCI: bus=%d devfn=0x%02x: vendor_id=0x%04x device_id=0x%04x class=0x%04x\n",
955 d->bus, d->devfn, vendor_id, device_id, class);
956 switch(class) {
957 case 0x0101: /* Mass storage controller - IDE interface */
958 if (vendor_id == PCI_VENDOR_ID_INTEL &&
959 (device_id == PCI_DEVICE_ID_INTEL_82371SB_1 ||
960 device_id == PCI_DEVICE_ID_INTEL_82371AB)) {
961 /* PIIX3/PIIX4 IDE */
962 pci_config_writew(d, 0x40, 0x8000); // enable IDE0
963 pci_config_writew(d, 0x42, 0x8000); // enable IDE1
964 goto default_map;
965 } else {
966 /* IDE: we map it as in ISA mode */
967 pci_set_io_region_addr(d, 0, 0x1f0);
968 pci_set_io_region_addr(d, 1, 0x3f4);
969 pci_set_io_region_addr(d, 2, 0x170);
970 pci_set_io_region_addr(d, 3, 0x374);
971 }
972 break;
973 case 0x0300: /* Display controller - VGA compatible controller */
974 if (vendor_id != 0x1234)
975 goto default_map;
976 /* VGA: map frame buffer to default Bochs VBE address */
977 pci_set_io_region_addr(d, 0, 0xE0000000);
978 break;
979 case 0x0800: /* Generic system peripheral - PIC */
980 if (vendor_id == PCI_VENDOR_ID_IBM) {
981 /* IBM */
982 if (device_id == 0x0046 || device_id == 0xFFFF) {
983 /* MPIC & MPIC2 */
984 pci_set_io_region_addr(d, 0, 0x80800000 + 0x00040000);
985 }
986 }
987 break;
988 case 0xff00:
989 if (vendor_id == PCI_VENDOR_ID_APPLE &&
990 (device_id == 0x0017 || device_id == 0x0022)) {
991 /* macio bridge */
992 pci_set_io_region_addr(d, 0, 0x80800000);
993 }
994 break;
995 default:
996 default_map:
997 /* default memory mappings */
998 for(i = 0; i < PCI_NUM_REGIONS; i++) {
999 int ofs;
1000 uint32_t val, size ;
1001
1002 if (i == PCI_ROM_SLOT)
1003 ofs = 0x30;
1004 else
1005 ofs = 0x10 + i * 4;
1006 pci_config_writel(d, ofs, 0xffffffff);
1007 val = pci_config_readl(d, ofs);
1008 if (val != 0) {
1009 size = (~(val & ~0xf)) + 1;
1010 if (val & PCI_ADDRESS_SPACE_IO)
1011 paddr = &pci_bios_io_addr;
1012 else if (size >= 0x04000000)
1013 paddr = &pci_bios_bigmem_addr;
1014 else
1015 paddr = &pci_bios_mem_addr;
1016 *paddr = (*paddr + size - 1) & ~(size - 1);
1017 pci_set_io_region_addr(d, i, *paddr);
1018 *paddr += size;
1019 /* make memory address page aligned */
1020 if (!(val & PCI_ADDRESS_SPACE_IO))
1021 *paddr = (*paddr + 0xfff) & 0xfffff000;
1022 }
1023 }
1024 break;
1025 }
1026
1027 /* map the interrupt */
1028 pin = pci_config_readb(d, PCI_INTERRUPT_PIN);
1029 if (pin != 0) {
1030 pin = pci_slot_get_pirq(d, pin - 1);
1031 pic_irq = pci_irqs[pin];
1032 pci_config_writeb(d, PCI_INTERRUPT_LINE, pic_irq);
1033 }
1034
1035 if (vendor_id == PCI_VENDOR_ID_INTEL && device_id == PCI_DEVICE_ID_INTEL_82371AB_3) {
1036 /* PIIX4 Power Management device (for ACPI) */
1037
1038 // acpi sci is hardwired to 9
1039 pci_config_writeb(d, PCI_INTERRUPT_LINE, 9);
1040
1041 pm_io_base = PM_IO_BASE;
1042 smb_io_base = SMB_IO_BASE;
1043 pm_sci_int = pci_config_readb(d, PCI_INTERRUPT_LINE);
1044 piix4_pm_enable(d);
1045 acpi_enabled = 1;
1046 }
1047 }
1048
1049 void pci_for_each_device(void (*init_func)(PCIDevice *d))
1050 {
1051 PCIDevice d1, *d = &d1;
1052 int bus, devfn;
1053 uint16_t vendor_id, device_id;
1054
1055 for(bus = 0; bus < 1; bus++) {
1056 for(devfn = 0; devfn < 256; devfn++) {
1057 d->bus = bus;
1058 d->devfn = devfn;
1059 vendor_id = pci_config_readw(d, PCI_VENDOR_ID);
1060 device_id = pci_config_readw(d, PCI_DEVICE_ID);
1061 if (vendor_id != 0xffff || device_id != 0xffff) {
1062 init_func(d);
1063 }
1064 }
1065 }
1066 }
1067
1068 void pci_bios_init(void)
1069 {
1070 pci_bios_io_addr = 0xc000;
1071 pci_bios_mem_addr = 0xf0000000;
1072 pci_bios_bigmem_addr = ram_size;
1073 if (pci_bios_bigmem_addr < 0x90000000)
1074 pci_bios_bigmem_addr = 0x90000000;
1075
1076 pci_for_each_device(pci_bios_init_bridges);
1077
1078 pci_for_each_device(pci_bios_init_device);
1079 }
1080
1081 /****************************************************/
1082 /* Multi Processor table init */
1083
1084 static void putb(uint8_t **pp, int val)
1085 {
1086 uint8_t *q;
1087 q = *pp;
1088 *q++ = val;
1089 *pp = q;
1090 }
1091
1092 static void putstr(uint8_t **pp, const char *str)
1093 {
1094 uint8_t *q;
1095 q = *pp;
1096 while (*str)
1097 *q++ = *str++;
1098 *pp = q;
1099 }
1100
1101 static void putle16(uint8_t **pp, int val)
1102 {
1103 uint8_t *q;
1104 q = *pp;
1105 *q++ = val;
1106 *q++ = val >> 8;
1107 *pp = q;
1108 }
1109
1110 static void putle32(uint8_t **pp, int val)
1111 {
1112 uint8_t *q;
1113 q = *pp;
1114 *q++ = val;
1115 *q++ = val >> 8;
1116 *q++ = val >> 16;
1117 *q++ = val >> 24;
1118 *pp = q;
1119 }
1120
1121 static int mpf_checksum(const uint8_t *data, int len)
1122 {
1123 int sum, i;
1124 sum = 0;
1125 for(i = 0; i < len; i++)
1126 sum += data[i];
1127 return sum & 0xff;
1128 }
1129
1130 static unsigned long align(unsigned long addr, unsigned long v)
1131 {
1132 return (addr + v - 1) & ~(v - 1);
1133 }
1134
1135 static void mptable_init(void)
1136 {
1137 uint8_t *mp_config_table, *q, *float_pointer_struct;
1138 int ioapic_id, i, len;
1139 int mp_config_table_size;
1140
1141 #ifdef BX_USE_EBDA_TABLES
1142 mp_config_table = (uint8_t *)(ram_size - ACPI_DATA_SIZE - MPTABLE_MAX_SIZE);
1143 #else
1144 bios_table_cur_addr = align(bios_table_cur_addr, 16);
1145 mp_config_table = (uint8_t *)bios_table_cur_addr;
1146 #endif
1147 q = mp_config_table;
1148 putstr(&q, "PCMP"); /* "PCMP signature */
1149 putle16(&q, 0); /* table length (patched later) */
1150 putb(&q, 4); /* spec rev */
1151 putb(&q, 0); /* checksum (patched later) */
1152 #ifdef BX_QEMU
1153 putstr(&q, "QEMUCPU "); /* OEM id */
1154 #else
1155 putstr(&q, "BOCHSCPU");
1156 #endif
1157 putstr(&q, "0.1 "); /* vendor id */
1158 putle32(&q, 0); /* OEM table ptr */
1159 putle16(&q, 0); /* OEM table size */
1160 #ifdef BX_QEMU
1161 if (irq0_override)
1162 putle16(&q, MAX_CPUS + 17); /* entry count */
1163 else
1164 putle16(&q, MAX_CPUS + 18); /* entry count */
1165 #else
1166 putle16(&q, MAX_CPUS + 18); /* entry count */
1167 #endif
1168 putle32(&q, 0xfee00000); /* local APIC addr */
1169 putle16(&q, 0); /* ext table length */
1170 putb(&q, 0); /* ext table checksum */
1171 putb(&q, 0); /* reserved */
1172
1173 for(i = 0; i < MAX_CPUS ; i++) {
1174 putb(&q, 0); /* entry type = processor */
1175 putb(&q, i); /* APIC id */
1176 putb(&q, 0x11); /* local APIC version number */
1177 if (i == 0)
1178 putb(&q, 3); /* cpu flags: enabled, bootstrap cpu */
1179 else if ( i < smp_cpus)
1180 putb(&q, 1); /* cpu flags: enabled */
1181 else
1182 putb(&q, 0); /* cpu flags: disabled */
1183 putb(&q, 0); /* cpu signature */
1184 putb(&q, 6);
1185 putb(&q, 0);
1186 putb(&q, 0);
1187 putle16(&q, 0x201); /* feature flags */
1188 putle16(&q, 0);
1189
1190 putle16(&q, 0); /* reserved */
1191 putle16(&q, 0);
1192 putle16(&q, 0);
1193 putle16(&q, 0);
1194 }
1195
1196 /* isa bus */
1197 putb(&q, 1); /* entry type = bus */
1198 putb(&q, 0); /* bus ID */
1199 putstr(&q, "ISA ");
1200
1201 /* ioapic */
1202 ioapic_id = smp_cpus;
1203 putb(&q, 2); /* entry type = I/O APIC */
1204 putb(&q, ioapic_id); /* apic ID */
1205 putb(&q, 0x11); /* I/O APIC version number */
1206 putb(&q, 1); /* enable */
1207 putle32(&q, 0xfec00000); /* I/O APIC addr */
1208
1209 /* irqs */
1210 for(i = 0; i < 16; i++) {
1211 #ifdef BX_QEMU
1212 /* One entry per ioapic interrupt destination. Destination 2 is covered
1213 * by irq0->inti2 override (i == 0). Source IRQ 2 is unused
1214 */
1215 if (irq0_override && i == 2)
1216 continue;
1217 #endif
1218 putb(&q, 3); /* entry type = I/O interrupt */
1219 putb(&q, 0); /* interrupt type = vectored interrupt */
1220 putb(&q, 0); /* flags: po=0, el=0 */
1221 putb(&q, 0);
1222 putb(&q, 0); /* source bus ID = ISA */
1223 putb(&q, i); /* source bus IRQ */
1224 putb(&q, ioapic_id); /* dest I/O APIC ID */
1225 #ifdef BX_QEMU
1226 if (irq0_override && i == 0)
1227 putb(&q, 2); /* dest I/O APIC interrupt in */
1228 else
1229 #endif
1230 putb(&q, i); /* dest I/O APIC interrupt in */
1231 }
1232 /* patch length */
1233 len = q - mp_config_table;
1234 mp_config_table[4] = len;
1235 mp_config_table[5] = len >> 8;
1236
1237 mp_config_table[7] = -mpf_checksum(mp_config_table, q - mp_config_table);
1238
1239 mp_config_table_size = q - mp_config_table;
1240
1241 #ifndef BX_USE_EBDA_TABLES
1242 bios_table_cur_addr += mp_config_table_size;
1243 #endif
1244
1245 /* floating pointer structure */
1246 #ifdef BX_USE_EBDA_TABLES
1247 ebda_cur_addr = align(ebda_cur_addr, 16);
1248 float_pointer_struct = (uint8_t *)ebda_cur_addr;
1249 #else
1250 bios_table_cur_addr = align(bios_table_cur_addr, 16);
1251 float_pointer_struct = (uint8_t *)bios_table_cur_addr;
1252 #endif
1253 q = float_pointer_struct;
1254 putstr(&q, "_MP_");
1255 /* pointer to MP config table */
1256 putle32(&q, (unsigned long)mp_config_table);
1257
1258 putb(&q, 1); /* length in 16 byte units */
1259 putb(&q, 4); /* MP spec revision */
1260 putb(&q, 0); /* checksum (patched later) */
1261 putb(&q, 0); /* MP feature byte 1 */
1262
1263 putb(&q, 0);
1264 putb(&q, 0);
1265 putb(&q, 0);
1266 putb(&q, 0);
1267 float_pointer_struct[10] =
1268 -mpf_checksum(float_pointer_struct, q - float_pointer_struct);
1269 #ifdef BX_USE_EBDA_TABLES
1270 ebda_cur_addr += (q - float_pointer_struct);
1271 #else
1272 bios_table_cur_addr += (q - float_pointer_struct);
1273 #endif
1274 BX_INFO("MP table addr=0x%08lx MPC table addr=0x%08lx size=0x%x\n",
1275 (unsigned long)float_pointer_struct,
1276 (unsigned long)mp_config_table,
1277 mp_config_table_size);
1278 }
1279
1280 /****************************************************/
1281 /* ACPI tables init */
1282
1283 /* Table structure from Linux kernel (the ACPI tables are under the
1284 BSD license) */
1285
1286 /*
1287 * All tables must be byte-packed to match the ACPI specification, since
1288 * the tables are provided by the system BIOS.
1289 */
1290
1291 #define ACPI_TABLE_HEADER_DEF /* ACPI common table header */ \
1292 uint8_t signature [4]; /* ACPI signature (4 ASCII characters) */\
1293 uint32_t length; /* Length of table, in bytes, including header */\
1294 uint8_t revision; /* ACPI Specification minor version # */\
1295 uint8_t checksum; /* To make sum of entire table == 0 */\
1296 uint8_t oem_id [6]; /* OEM identification */\
1297 uint8_t oem_table_id [8]; /* OEM table identification */\
1298 uint32_t oem_revision; /* OEM revision number */\
1299 uint8_t asl_compiler_id [4]; /* ASL compiler vendor ID */\
1300 uint32_t asl_compiler_revision; /* ASL compiler revision number */
1301
1302
1303 struct acpi_table_header /* ACPI common table header */
1304 {
1305 ACPI_TABLE_HEADER_DEF
1306 } __attribute__((__packed__));
1307
1308 struct rsdp_descriptor /* Root System Descriptor Pointer */
1309 {
1310 uint8_t signature [8]; /* ACPI signature, contains "RSD PTR " */
1311 uint8_t checksum; /* To make sum of struct == 0 */
1312 uint8_t oem_id [6]; /* OEM identification */
1313 uint8_t revision; /* Must be 0 for 1.0, 2 for 2.0 */
1314 uint32_t rsdt_physical_address; /* 32-bit physical address of RSDT */
1315 uint32_t length; /* XSDT Length in bytes including hdr */
1316 uint64_t xsdt_physical_address; /* 64-bit physical address of XSDT */
1317 uint8_t extended_checksum; /* Checksum of entire table */
1318 uint8_t reserved [3]; /* Reserved field must be 0 */
1319 } __attribute__((__packed__));
1320
1321 #define MAX_RSDT_ENTRIES 100
1322
1323 /*
1324 * ACPI 1.0 Root System Description Table (RSDT)
1325 */
1326 struct rsdt_descriptor_rev1
1327 {
1328 ACPI_TABLE_HEADER_DEF /* ACPI common table header */
1329 uint32_t table_offset_entry [MAX_RSDT_ENTRIES]; /* Array of pointers to other */
1330 /* ACPI tables */
1331 } __attribute__((__packed__));
1332
1333 /*
1334 * ACPI 1.0 Firmware ACPI Control Structure (FACS)
1335 */
1336 struct facs_descriptor_rev1
1337 {
1338 uint8_t signature[4]; /* ACPI Signature */
1339 uint32_t length; /* Length of structure, in bytes */
1340 uint32_t hardware_signature; /* Hardware configuration signature */
1341 uint32_t firmware_waking_vector; /* ACPI OS waking vector */
1342 uint32_t global_lock; /* Global Lock */
1343 uint32_t S4bios_f : 1; /* Indicates if S4BIOS support is present */
1344 uint32_t reserved1 : 31; /* Must be 0 */
1345 uint8_t resverved3 [40]; /* Reserved - must be zero */
1346 } __attribute__((__packed__));
1347
1348
1349 /*
1350 * ACPI 1.0 Fixed ACPI Description Table (FADT)
1351 */
1352 struct fadt_descriptor_rev1
1353 {
1354 ACPI_TABLE_HEADER_DEF /* ACPI common table header */
1355 uint32_t firmware_ctrl; /* Physical address of FACS */
1356 uint32_t dsdt; /* Physical address of DSDT */
1357 uint8_t model; /* System Interrupt Model */
1358 uint8_t reserved1; /* Reserved */
1359 uint16_t sci_int; /* System vector of SCI interrupt */
1360 uint32_t smi_cmd; /* Port address of SMI command port */
1361 uint8_t acpi_enable; /* Value to write to smi_cmd to enable ACPI */
1362 uint8_t acpi_disable; /* Value to write to smi_cmd to disable ACPI */
1363 uint8_t S4bios_req; /* Value to write to SMI CMD to enter S4BIOS state */
1364 uint8_t reserved2; /* Reserved - must be zero */
1365 uint32_t pm1a_evt_blk; /* Port address of Power Mgt 1a acpi_event Reg Blk */
1366 uint32_t pm1b_evt_blk; /* Port address of Power Mgt 1b acpi_event Reg Blk */
1367 uint32_t pm1a_cnt_blk; /* Port address of Power Mgt 1a Control Reg Blk */
1368 uint32_t pm1b_cnt_blk; /* Port address of Power Mgt 1b Control Reg Blk */
1369 uint32_t pm2_cnt_blk; /* Port address of Power Mgt 2 Control Reg Blk */
1370 uint32_t pm_tmr_blk; /* Port address of Power Mgt Timer Ctrl Reg Blk */
1371 uint32_t gpe0_blk; /* Port addr of General Purpose acpi_event 0 Reg Blk */
1372 uint32_t gpe1_blk; /* Port addr of General Purpose acpi_event 1 Reg Blk */
1373 uint8_t pm1_evt_len; /* Byte length of ports at pm1_x_evt_blk */
1374 uint8_t pm1_cnt_len; /* Byte length of ports at pm1_x_cnt_blk */
1375 uint8_t pm2_cnt_len; /* Byte Length of ports at pm2_cnt_blk */
1376 uint8_t pm_tmr_len; /* Byte Length of ports at pm_tm_blk */
1377 uint8_t gpe0_blk_len; /* Byte Length of ports at gpe0_blk */
1378 uint8_t gpe1_blk_len; /* Byte Length of ports at gpe1_blk */
1379 uint8_t gpe1_base; /* Offset in gpe model where gpe1 events start */
1380 uint8_t reserved3; /* Reserved */
1381 uint16_t plvl2_lat; /* Worst case HW latency to enter/exit C2 state */
1382 uint16_t plvl3_lat; /* Worst case HW latency to enter/exit C3 state */
1383 uint16_t flush_size; /* Size of area read to flush caches */
1384 uint16_t flush_stride; /* Stride used in flushing caches */
1385 uint8_t duty_offset; /* Bit location of duty cycle field in p_cnt reg */
1386 uint8_t duty_width; /* Bit width of duty cycle field in p_cnt reg */
1387 uint8_t day_alrm; /* Index to day-of-month alarm in RTC CMOS RAM */
1388 uint8_t mon_alrm; /* Index to month-of-year alarm in RTC CMOS RAM */
1389 uint8_t century; /* Index to century in RTC CMOS RAM */
1390 uint8_t reserved4; /* Reserved */
1391 uint8_t reserved4a; /* Reserved */
1392 uint8_t reserved4b; /* Reserved */
1393 #if 0
1394 uint32_t wb_invd : 1; /* The wbinvd instruction works properly */
1395 uint32_t wb_invd_flush : 1; /* The wbinvd flushes but does not invalidate */
1396 uint32_t proc_c1 : 1; /* All processors support C1 state */
1397 uint32_t plvl2_up : 1; /* C2 state works on MP system */
1398 uint32_t pwr_button : 1; /* Power button is handled as a generic feature */
1399 uint32_t sleep_button : 1; /* Sleep button is handled as a generic feature, or not present */
1400 uint32_t fixed_rTC : 1; /* RTC wakeup stat not in fixed register space */
1401 uint32_t rtcs4 : 1; /* RTC wakeup stat not possible from S4 */
1402 uint32_t tmr_val_ext : 1; /* The tmr_val width is 32 bits (0 = 24 bits) */
1403 uint32_t reserved5 : 23; /* Reserved - must be zero */
1404 #else
1405 uint32_t flags;
1406 #endif
1407 } __attribute__((__packed__));
1408
1409 /*
1410 * MADT values and structures
1411 */
1412
1413 /* Values for MADT PCATCompat */
1414
1415 #define DUAL_PIC 0
1416 #define MULTIPLE_APIC 1
1417
1418
1419 /* Master MADT */
1420
1421 struct multiple_apic_table
1422 {
1423 ACPI_TABLE_HEADER_DEF /* ACPI common table header */
1424 uint32_t local_apic_address; /* Physical address of local APIC */
1425 #if 0
1426 uint32_t PCATcompat : 1; /* A one indicates system also has dual 8259s */
1427 uint32_t reserved1 : 31;
1428 #else
1429 uint32_t flags;
1430 #endif
1431 } __attribute__((__packed__));
1432
1433
1434 /* Values for Type in APIC sub-headers */
1435
1436 #define APIC_PROCESSOR 0
1437 #define APIC_IO 1
1438 #define APIC_XRUPT_OVERRIDE 2
1439 #define APIC_NMI 3
1440 #define APIC_LOCAL_NMI 4
1441 #define APIC_ADDRESS_OVERRIDE 5
1442 #define APIC_IO_SAPIC 6
1443 #define APIC_LOCAL_SAPIC 7
1444 #define APIC_XRUPT_SOURCE 8
1445 #define APIC_RESERVED 9 /* 9 and greater are reserved */
1446
1447 #define ACPI_SUB_HEADER_DEF /* Common ACPI sub-structure header */\
1448 uint8_t type; \
1449 uint8_t length;
1450
1451 /*
1452 * MADT sub-structures (Follow MULTIPLE_APIC_DESCRIPTION_TABLE)
1453 */
1454 /* Sub-structures for MADT */
1455
1456 struct madt_processor_apic
1457 {
1458 ACPI_SUB_HEADER_DEF
1459 uint8_t processor_id; /* ACPI processor id */
1460 uint8_t local_apic_id; /* Processor's local APIC id */
1461 #if 0
1462 uint32_t processor_enabled: 1; /* Processor is usable if set */
1463 uint32_t reserved2 : 31; /* Reserved, must be zero */
1464 #else
1465 uint32_t flags;
1466 #endif
1467 } __attribute__((__packed__));
1468
1469 /*
1470 * SRAT (NUMA topology description) table
1471 */
1472
1473 #define SRAT_PROCESSOR 0
1474 #define SRAT_MEMORY 1
1475
1476 struct system_resource_affinity_table
1477 {
1478 ACPI_TABLE_HEADER_DEF
1479 uint32_t reserved1;
1480 uint32_t reserved2[2];
1481 };
1482
1483 struct srat_processor_affinity
1484 {
1485 ACPI_SUB_HEADER_DEF
1486 uint8_t proximity_lo;
1487 uint8_t local_apic_id;
1488 uint32_t flags;
1489 uint8_t local_sapic_eid;
1490 uint8_t proximity_hi[3];
1491 uint32_t reserved;
1492 };
1493
1494 struct srat_memory_affinity
1495 {
1496 ACPI_SUB_HEADER_DEF
1497 uint8_t proximity[4];
1498 uint16_t reserved1;
1499 uint32_t base_addr_low,base_addr_high;
1500 uint32_t length_low,length_high;
1501 uint32_t reserved2;
1502 uint32_t flags;
1503 uint32_t reserved3[2];
1504 };
1505
1506 #ifdef BX_QEMU
1507 /*
1508 * * ACPI 2.0 Generic Address Space definition.
1509 * */
1510 struct acpi_20_generic_address {
1511 uint8_t address_space_id;
1512 uint8_t register_bit_width;
1513 uint8_t register_bit_offset;
1514 uint8_t reserved;
1515 uint64_t address;
1516 } __attribute__((__packed__));
1517
1518 /*
1519 * HPET Description Table
1520 */
1521 struct acpi_20_hpet {
1522 ACPI_TABLE_HEADER_DEF /* ACPI common table header */
1523 uint32_t timer_block_id;
1524 struct acpi_20_generic_address addr;
1525 uint8_t hpet_number;
1526 uint16_t min_tick;
1527 uint8_t page_protect;
1528 } __attribute__((__packed__));
1529 #define ACPI_HPET_ADDRESS 0xFED00000UL
1530 #endif
1531
1532 struct madt_io_apic
1533 {
1534 ACPI_SUB_HEADER_DEF
1535 uint8_t io_apic_id; /* I/O APIC ID */
1536 uint8_t reserved; /* Reserved - must be zero */
1537 uint32_t address; /* APIC physical address */
1538 uint32_t interrupt; /* Global system interrupt where INTI
1539 * lines start */
1540 } __attribute__((__packed__));
1541
1542 #ifdef BX_QEMU
1543 struct madt_int_override
1544 {
1545 ACPI_SUB_HEADER_DEF
1546 uint8_t bus; /* Identifies ISA Bus */
1547 uint8_t source; /* Bus-relative interrupt source */
1548 uint32_t gsi; /* GSI that source will signal */
1549 uint16_t flags; /* MPS INTI flags */
1550 } __attribute__((__packed__));
1551 #endif
1552
1553 #include "acpi-dsdt.hex"
1554 #include "acpi-ssdt.hex"
1555
1556 static inline uint16_t cpu_to_le16(uint16_t x)
1557 {
1558 return x;
1559 }
1560
1561 static inline uint32_t cpu_to_le32(uint32_t x)
1562 {
1563 return x;
1564 }
1565
1566 static int acpi_checksum(const uint8_t *data, int len)
1567 {
1568 int sum, i;
1569 sum = 0;
1570 for(i = 0; i < len; i++)
1571 sum += data[i];
1572 return (-sum) & 0xff;
1573 }
1574
1575 static void acpi_build_table_header(struct acpi_table_header *h,
1576 char *sig, int len, uint8_t rev)
1577 {
1578 memcpy(h->signature, sig, 4);
1579 h->length = cpu_to_le32(len);
1580 h->revision = rev;
1581 #ifdef BX_QEMU
1582 memcpy(h->oem_id, "QEMU ", 6);
1583 memcpy(h->oem_table_id, "QEMU", 4);
1584 #else
1585 memcpy(h->oem_id, "BOCHS ", 6);
1586 memcpy(h->oem_table_id, "BXPC", 4);
1587 #endif
1588 memcpy(h->oem_table_id + 4, sig, 4);
1589 h->oem_revision = cpu_to_le32(1);
1590 #ifdef BX_QEMU
1591 memcpy(h->asl_compiler_id, "QEMU", 4);
1592 #else
1593 memcpy(h->asl_compiler_id, "BXPC", 4);
1594 #endif
1595 h->asl_compiler_revision = cpu_to_le32(1);
1596 h->checksum = acpi_checksum((void *)h, len);
1597 }
1598
1599 static void acpi_build_srat_memory(struct srat_memory_affinity *numamem,
1600 uint64_t base, uint64_t len, int node, int enabled)
1601 {
1602 numamem->type = SRAT_MEMORY;
1603 numamem->length = sizeof(*numamem);
1604 memset (numamem->proximity, 0 ,4);
1605 numamem->proximity[0] = node;
1606 numamem->flags = cpu_to_le32(!!enabled);
1607 numamem->base_addr_low = base & 0xFFFFFFFF;
1608 numamem->base_addr_high = base >> 32;
1609 numamem->length_low = len & 0xFFFFFFFF;
1610 numamem->length_high = len >> 32;
1611 return;
1612 }
1613
1614 /* base_addr must be a multiple of 4KB */
1615 void acpi_bios_init(void)
1616 {
1617 struct rsdp_descriptor *rsdp;
1618 struct rsdt_descriptor_rev1 *rsdt;
1619 struct fadt_descriptor_rev1 *fadt;
1620 struct facs_descriptor_rev1 *facs;
1621 struct multiple_apic_table *madt;
1622 uint8_t *dsdt, *ssdt;
1623 #ifdef BX_QEMU
1624 struct system_resource_affinity_table *srat;
1625 struct acpi_20_hpet *hpet;
1626 uint32_t hpet_addr;
1627 #endif
1628 uint32_t base_addr, rsdt_addr, fadt_addr, addr, facs_addr, dsdt_addr, ssdt_addr;
1629 uint32_t acpi_tables_size, madt_addr, madt_size, rsdt_size, madt_end, rsdt_end;
1630 uint32_t srat_addr,srat_size;
1631 uint16_t i, external_tables;
1632 int nb_numa_nodes;
1633 int nb_rsdt_entries = 0;
1634
1635 /* reserve memory space for tables */
1636 #ifdef BX_USE_EBDA_TABLES
1637 ebda_cur_addr = align(ebda_cur_addr, 16);
1638 rsdp = (void *)(ebda_cur_addr);
1639 ebda_cur_addr += sizeof(*rsdp);
1640 #else
1641 bios_table_cur_addr = align(bios_table_cur_addr, 16);
1642 rsdp = (void *)(bios_table_cur_addr);
1643 bios_table_cur_addr += sizeof(*rsdp);
1644 #endif
1645
1646 #ifdef BX_QEMU
1647 external_tables = acpi_additional_tables();
1648 #else
1649 external_tables = 0;
1650 #endif
1651
1652 addr = base_addr = ram_size - ACPI_DATA_SIZE;
1653 rsdt_addr = addr;
1654 rsdt = (void *)(addr);
1655 rsdt_size = sizeof(*rsdt);
1656 addr += rsdt_size;
1657
1658 fadt_addr = addr;
1659 fadt = (void *)(addr);
1660 addr += sizeof(*fadt);
1661
1662 /* XXX: FACS should be in RAM */
1663 addr = (addr + 63) & ~63; /* 64 byte alignment for FACS */
1664 facs_addr = addr;
1665 facs = (void *)(addr);
1666 addr += sizeof(*facs);
1667
1668 dsdt_addr = addr;
1669 dsdt = (void *)(addr);
1670 addr += sizeof(DSDTCode);
1671
1672 ssdt_addr = addr;
1673 ssdt = (void *)(addr);
1674 addr += sizeof(SSDTCode);
1675
1676 #ifdef BX_QEMU
1677 qemu_cfg_select(QEMU_CFG_NUMA);
1678 nb_numa_nodes = qemu_cfg_get64();
1679 #else
1680 nb_numa_nodes = 0;
1681 #endif
1682 if (nb_numa_nodes > 0) {
1683 addr = (addr + 7) & ~7;
1684 srat_addr = addr;
1685 srat_size = sizeof(*srat) +
1686 sizeof(struct srat_processor_affinity) * smp_cpus +
1687 sizeof(struct srat_memory_affinity) * (nb_numa_nodes + 2);
1688 srat = (void *)(addr);
1689 addr += srat_size;
1690 } else {
1691 srat_addr = addr;
1692 srat = (void*)(addr);
1693 srat_size = 0;
1694 }
1695
1696 addr = (addr + 7) & ~7;
1697 madt_addr = addr;
1698 madt_size = sizeof(*madt) +
1699 sizeof(struct madt_processor_apic) * MAX_CPUS +
1700 #ifdef BX_QEMU
1701 sizeof(struct madt_io_apic) + sizeof(struct madt_int_override) * MAX_INT_OVERRIDES;
1702 #else
1703 sizeof(struct madt_io_apic);
1704 #endif
1705 madt = (void *)(addr);
1706 addr += madt_size;
1707
1708 #ifdef BX_QEMU
1709 addr = (addr + 7) & ~7;
1710 hpet_addr = addr;
1711 hpet = (void *)(addr);
1712 addr += sizeof(*hpet);
1713 #endif
1714
1715 /* RSDP */
1716 memset(rsdp, 0, sizeof(*rsdp));
1717 memcpy(rsdp->signature, "RSD PTR ", 8);
1718 #ifdef BX_QEMU
1719 memcpy(rsdp->oem_id, "QEMU ", 6);
1720 #else
1721 memcpy(rsdp->oem_id, "BOCHS ", 6);
1722 #endif
1723 rsdp->rsdt_physical_address = cpu_to_le32(rsdt_addr);
1724 rsdp->checksum = acpi_checksum((void *)rsdp, 20);
1725
1726 /* FADT */
1727 memset(fadt, 0, sizeof(*fadt));
1728 fadt->firmware_ctrl = cpu_to_le32(facs_addr);
1729 fadt->dsdt = cpu_to_le32(dsdt_addr);
1730 fadt->model = 1;
1731 fadt->reserved1 = 0;
1732 fadt->sci_int = cpu_to_le16(pm_sci_int);
1733 fadt->smi_cmd = cpu_to_le32(SMI_CMD_IO_ADDR);
1734 fadt->acpi_enable = 0xf1;
1735 fadt->acpi_disable = 0xf0;
1736 fadt->pm1a_evt_blk = cpu_to_le32(pm_io_base);
1737 fadt->pm1a_cnt_blk = cpu_to_le32(pm_io_base + 0x04);
1738 fadt->pm_tmr_blk = cpu_to_le32(pm_io_base + 0x08);
1739 fadt->pm1_evt_len = 4;
1740 fadt->pm1_cnt_len = 2;
1741 fadt->pm_tmr_len = 4;
1742 fadt->plvl2_lat = cpu_to_le16(0xfff); // C2 state not supported
1743 fadt->plvl3_lat = cpu_to_le16(0xfff); // C3 state not supported
1744 fadt->gpe0_blk = cpu_to_le32(0xafe0);
1745 fadt->gpe0_blk_len = 4;
1746 /* WBINVD + PROC_C1 + SLP_BUTTON + FIX_RTC */
1747 fadt->flags = cpu_to_le32((1 << 0) | (1 << 2) | (1 << 5) | (1 << 6));
1748 acpi_build_table_header((struct acpi_table_header *)fadt, "FACP",
1749 sizeof(*fadt), 1);
1750
1751 /* FACS */
1752 memset(facs, 0, sizeof(*facs));
1753 memcpy(facs->signature, "FACS", 4);
1754 facs->length = cpu_to_le32(sizeof(*facs));
1755 BX_INFO("Firmware waking vector %p\n", &facs->firmware_waking_vector);
1756
1757 /* DSDT */
1758 memcpy(dsdt, DSDTCode, sizeof(DSDTCode));
1759
1760 /* SSDT */
1761 memcpy(ssdt, SSDTCode, sizeof(SSDTCode));
1762
1763 /* MADT */
1764 {
1765 struct madt_processor_apic *apic;
1766 struct madt_io_apic *io_apic;
1767 #ifdef BX_QEMU
1768 struct madt_int_override *int_override;
1769 #endif
1770
1771 memset(madt, 0, madt_size);
1772 madt->local_apic_address = cpu_to_le32(0xfee00000);
1773 madt->flags = cpu_to_le32(1);
1774 *(uint32_t*)APIC_MADT_PTR = apic = (void *)(madt + 1);
1775 for(i=0;i<MAX_CPUS;i++) {
1776 apic->type = APIC_PROCESSOR;
1777 apic->length = sizeof(*apic);
1778 apic->processor_id = i;
1779 apic->local_apic_id = i;
1780 if (i < smp_cpus)
1781 apic->flags = cpu_to_le32(1);
1782 else
1783 apic->flags = 0;
1784 apic++;
1785 }
1786 io_apic = (void *)apic;
1787 io_apic->type = APIC_IO;
1788 io_apic->length = sizeof(*io_apic);
1789 io_apic->io_apic_id = smp_cpus;
1790 io_apic->address = cpu_to_le32(0xfec00000);
1791 io_apic->interrupt = cpu_to_le32(0);
1792 io_apic++;
1793 int_override = (struct madt_int_override*)(io_apic);
1794 #ifdef BX_QEMU
1795 if (irq0_override) {
1796 memset(int_override, 0, sizeof(*int_override));
1797 int_override->type = APIC_XRUPT_OVERRIDE;
1798 int_override->length = sizeof(*int_override);
1799 int_override->source = 0;
1800 int_override->gsi = 2;
1801 int_override->flags = 0; /* conforms to bus specifications */
1802 int_override++;
1803 }
1804 #endif
1805 for (i = 0; i < 16; i++) {
1806 if (PCI_ISA_IRQ_MASK & (1U << i)) {
1807 memset(int_override, 0, sizeof(*int_override));
1808 int_override->type = APIC_XRUPT_OVERRIDE;
1809 int_override->length = sizeof(*int_override);
1810 int_override->source = i;
1811 int_override->gsi = i;
1812 int_override->flags = 0xd; /* active high, level triggered */
1813 } else {
1814 /* No need for a INT source override structure. */
1815 continue;
1816 }
1817 int_override++;
1818 }
1819 madt_end = (uint32_t)int_override;
1820 madt_size = madt_end - madt_addr;
1821 acpi_build_table_header((struct acpi_table_header *)madt,
1822 "APIC", madt_size, 1);
1823 }
1824
1825 memset(rsdt, 0, rsdt_size);
1826 #ifdef BX_QEMU
1827 /* SRAT */
1828 if (nb_numa_nodes > 0) {
1829 struct srat_processor_affinity *core;
1830 struct srat_memory_affinity *numamem;
1831 int slots;
1832 uint64_t mem_len, mem_base, next_base = 0, curnode;
1833
1834 qemu_cfg_select(QEMU_CFG_NUMA);
1835 qemu_cfg_get64();
1836 memset (srat, 0 , srat_size);
1837 srat->reserved1=1;
1838
1839 core = (void*)(srat + 1);
1840 for (i = 0; i < smp_cpus; ++i) {
1841 core->type = SRAT_PROCESSOR;
1842 core->length = sizeof(*core);
1843 core->local_apic_id = i;
1844 curnode = qemu_cfg_get64();
1845 core->proximity_lo = curnode;
1846 memset (core->proximity_hi, 0, 3);
1847 core->local_sapic_eid = 0;
1848 if (i < smp_cpus)
1849 core->flags = cpu_to_le32(1);
1850 else
1851 core->flags = 0;
1852 core++;
1853 }
1854
1855 /* the memory map is a bit tricky, it contains at least one hole
1856 * from 640k-1M and possibly another one from 3.5G-4G.
1857 */
1858 numamem = (void*)core; slots = 0;
1859 acpi_build_srat_memory(numamem, 0, 640*1024, 0, 1);
1860 next_base = 1024 * 1024; numamem++;slots++;
1861 for (i = 1; i < nb_numa_nodes + 1; ++i) {
1862 mem_base = next_base;
1863 mem_len = qemu_cfg_get64();
1864 if (i == 1) mem_len -= 1024 * 1024;
1865 next_base = mem_base + mem_len;
1866
1867 /* Cut out the PCI hole */
1868 if (mem_base <= ram_size && next_base > ram_size) {
1869 mem_len -= next_base - ram_size;
1870 if (mem_len > 0) {
1871 acpi_build_srat_memory(numamem, mem_base, mem_len, i-1, 1);
1872 numamem++; slots++;
1873 }
1874 mem_base = 1ULL << 32;
1875 mem_len = next_base - ram_size;
1876 next_base += (1ULL << 32) - ram_size;
1877 }
1878 acpi_build_srat_memory(numamem, mem_base, mem_len, i-1, 1);
1879 numamem++; slots++;
1880 }
1881 for (; slots < nb_numa_nodes + 2; slots++) {
1882 acpi_build_srat_memory(numamem, 0, 0, 0, 0);
1883 numamem++;
1884 }
1885
1886 acpi_build_table_header((struct acpi_table_header *)srat,
1887 "SRAT", srat_size, 1);
1888 }
1889
1890 /* HPET */
1891 memset(hpet, 0, sizeof(*hpet));
1892 /* Note timer_block_id value must be kept in sync with value advertised by
1893 * emulated hpet
1894 */
1895 hpet->timer_block_id = cpu_to_le32(0x8086a201);
1896 hpet->addr.address = cpu_to_le32(ACPI_HPET_ADDRESS);
1897 acpi_build_table_header((struct acpi_table_header *)hpet,
1898 "HPET", sizeof(*hpet), 1);
1899
1900 #endif
1901
1902 /* RSDT */
1903 rsdt->table_offset_entry[nb_rsdt_entries++] = cpu_to_le32(fadt_addr);
1904 /* On real hardware the SSDT seems to come before the MADT (APIC) */
1905 rsdt->table_offset_entry[nb_rsdt_entries++] = cpu_to_le32(ssdt_addr);
1906 rsdt->table_offset_entry[nb_rsdt_entries++] = cpu_to_le32(madt_addr);
1907 #ifdef BX_QEMU
1908 rsdt->table_offset_entry[nb_rsdt_entries++] = cpu_to_le32(hpet_addr);
1909 if (nb_numa_nodes > 0)
1910 rsdt->table_offset_entry[nb_rsdt_entries++] = cpu_to_le32(srat_addr);
1911 acpi_additional_tables(); /* resets cfg to required entry */
1912 for(i = 0; i < external_tables; i++) {
1913 uint16_t len;
1914 if(acpi_load_table(i, addr, &len) < 0)
1915 BX_PANIC("Failed to load ACPI table from QEMU\n");
1916 rsdt->table_offset_entry[nb_rsdt_entries++] = cpu_to_le32(addr);
1917 addr += len;
1918 if ((addr >= ram_size) || (nb_rsdt_entries > MAX_RSDT_ENTRIES))
1919 BX_PANIC("ACPI table overflow\n");
1920 }
1921 #endif
1922 rsdt_end = (uint32_t)(&rsdt->table_offset_entry[nb_rsdt_entries]);
1923 rsdt_size = rsdt_end - rsdt_addr;
1924 acpi_build_table_header((struct acpi_table_header *)rsdt, "RSDT",
1925 rsdt_size, 1);
1926
1927 acpi_tables_size = addr - base_addr;
1928
1929 BX_INFO("ACPI tables: RSDP addr=0x%08lx ACPI DATA addr=0x%08lx size=0x%x\n",
1930 (unsigned long)rsdp,
1931 (unsigned long)rsdt, acpi_tables_size);
1932
1933 }
1934
1935 /* SMBIOS entry point -- must be written to a 16-bit aligned address
1936 between 0xf0000 and 0xfffff.
1937 */
1938 struct smbios_entry_point {
1939 char anchor_string[4];
1940 uint8_t checksum;
1941 uint8_t length;
1942 uint8_t smbios_major_version;
1943 uint8_t smbios_minor_version;
1944 uint16_t max_structure_size;
1945 uint8_t entry_point_revision;
1946 uint8_t formatted_area[5];
1947 char intermediate_anchor_string[5];
1948 uint8_t intermediate_checksum;
1949 uint16_t structure_table_length;
1950 uint32_t structure_table_address;
1951 uint16_t number_of_structures;
1952 uint8_t smbios_bcd_revision;
1953 } __attribute__((__packed__));
1954
1955 /* This goes at the beginning of every SMBIOS structure. */
1956 struct smbios_structure_header {
1957 uint8_t type;
1958 uint8_t length;
1959 uint16_t handle;
1960 } __attribute__((__packed__));
1961
1962 /* SMBIOS type 0 - BIOS Information */
1963 struct smbios_type_0 {
1964 struct smbios_structure_header header;
1965 uint8_t vendor_str;
1966 uint8_t bios_version_str;
1967 uint16_t bios_starting_address_segment;
1968 uint8_t bios_release_date_str;
1969 uint8_t bios_rom_size;
1970 uint8_t bios_characteristics[8];
1971 uint8_t bios_characteristics_extension_bytes[2];
1972 uint8_t system_bios_major_release;
1973 uint8_t system_bios_minor_release;
1974 uint8_t embedded_controller_major_release;
1975 uint8_t embedded_controller_minor_release;
1976 } __attribute__((__packed__));
1977
1978 /* SMBIOS type 1 - System Information */
1979 struct smbios_type_1 {
1980 struct smbios_structure_header header;
1981 uint8_t manufacturer_str;
1982 uint8_t product_name_str;
1983 uint8_t version_str;
1984 uint8_t serial_number_str;
1985 uint8_t uuid[16];
1986 uint8_t wake_up_type;
1987 uint8_t sku_number_str;
1988 uint8_t family_str;
1989 } __attribute__((__packed__));
1990
1991 /* SMBIOS type 3 - System Enclosure (v2.3) */
1992 struct smbios_type_3 {
1993 struct smbios_structure_header header;
1994 uint8_t manufacturer_str;
1995 uint8_t type;
1996 uint8_t version_str;
1997 uint8_t serial_number_str;
1998 uint8_t asset_tag_number_str;
1999 uint8_t boot_up_state;
2000 uint8_t power_supply_state;
2001 uint8_t thermal_state;
2002 uint8_t security_status;
2003 uint32_t oem_defined;
2004 uint8_t height;
2005 uint8_t number_of_power_cords;
2006 uint8_t contained_element_count;
2007 // contained elements follow
2008 } __attribute__((__packed__));
2009
2010 /* SMBIOS type 4 - Processor Information (v2.0) */
2011 struct smbios_type_4 {
2012 struct smbios_structure_header header;
2013 uint8_t socket_designation_str;
2014 uint8_t processor_type;
2015 uint8_t processor_family;
2016 uint8_t processor_manufacturer_str;
2017 uint32_t processor_id[2];
2018 uint8_t processor_version_str;
2019 uint8_t voltage;
2020 uint16_t external_clock;
2021 uint16_t max_speed;
2022 uint16_t current_speed;
2023 uint8_t status;
2024 uint8_t processor_upgrade;
2025 uint16_t l1_cache_handle;
2026 uint16_t l2_cache_handle;
2027 uint16_t l3_cache_handle;
2028 } __attribute__((__packed__));
2029
2030 /* SMBIOS type 16 - Physical Memory Array
2031 * Associated with one type 17 (Memory Device).
2032 */
2033 struct smbios_type_16 {
2034 struct smbios_structure_header header;
2035 uint8_t location;
2036 uint8_t use;
2037 uint8_t error_correction;
2038 uint32_t maximum_capacity;
2039 uint16_t memory_error_information_handle;
2040 uint16_t number_of_memory_devices;
2041 } __attribute__((__packed__));
2042
2043 /* SMBIOS type 17 - Memory Device
2044 * Associated with one type 19
2045 */
2046 struct smbios_type_17 {
2047 struct smbios_structure_header header;
2048 uint16_t physical_memory_array_handle;
2049 uint16_t memory_error_information_handle;
2050 uint16_t total_width;
2051 uint16_t data_width;
2052 uint16_t size;
2053 uint8_t form_factor;
2054 uint8_t device_set;
2055 uint8_t device_locator_str;
2056 uint8_t bank_locator_str;
2057 uint8_t memory_type;
2058 uint16_t type_detail;
2059 } __attribute__((__packed__));
2060
2061 /* SMBIOS type 19 - Memory Array Mapped Address */
2062 struct smbios_type_19 {
2063 struct smbios_structure_header header;
2064 uint32_t starting_address;
2065 uint32_t ending_address;
2066 uint16_t memory_array_handle;
2067 uint8_t partition_width;
2068 } __attribute__((__packed__));
2069
2070 /* SMBIOS type 20 - Memory Device Mapped Address */
2071 struct smbios_type_20 {
2072 struct smbios_structure_header header;
2073 uint32_t starting_address;
2074 uint32_t ending_address;
2075 uint16_t memory_device_handle;
2076 uint16_t memory_array_mapped_address_handle;
2077 uint8_t partition_row_position;
2078 uint8_t interleave_position;
2079 uint8_t interleaved_data_depth;
2080 } __attribute__((__packed__));
2081
2082 /* SMBIOS type 32 - System Boot Information */
2083 struct smbios_type_32 {
2084 struct smbios_structure_header header;
2085 uint8_t reserved[6];
2086 uint8_t boot_status;
2087 } __attribute__((__packed__));
2088
2089 /* SMBIOS type 127 -- End-of-table */
2090 struct smbios_type_127 {
2091 struct smbios_structure_header header;
2092 } __attribute__((__packed__));
2093
2094 static void
2095 smbios_entry_point_init(void *start,
2096 uint16_t max_structure_size,
2097 uint16_t structure_table_length,
2098 uint32_t structure_table_address,
2099 uint16_t number_of_structures)
2100 {
2101 uint8_t sum;
2102 int i;
2103 struct smbios_entry_point *ep = (struct smbios_entry_point *)start;
2104
2105 memcpy(ep->anchor_string, "_SM_", 4);
2106 ep->length = 0x1f;
2107 ep->smbios_major_version = 2;
2108 ep->smbios_minor_version = 4;
2109 ep->max_structure_size = max_structure_size;
2110 ep->entry_point_revision = 0;
2111 memset(ep->formatted_area, 0, 5);
2112 memcpy(ep->intermediate_anchor_string, "_DMI_", 5);
2113
2114 ep->structure_table_length = structure_table_length;
2115 ep->structure_table_address = structure_table_address;
2116 ep->number_of_structures = number_of_structures;
2117 ep->smbios_bcd_revision = 0x24;
2118
2119 ep->checksum = 0;
2120 ep->intermediate_checksum = 0;
2121
2122 sum = 0;
2123 for (i = 0; i < 0x10; i++)
2124 sum += ((int8_t *)start)[i];
2125 ep->checksum = -sum;
2126
2127 sum = 0;
2128 for (i = 0x10; i < ep->length; i++)
2129 sum += ((int8_t *)start)[i];
2130 ep->intermediate_checksum = -sum;
2131 }
2132
2133 struct smbios_header {
2134 uint16_t length;
2135 uint8_t type;
2136 } __attribute__((__packed__));
2137
2138 struct smbios_field {
2139 struct smbios_header header;
2140 uint8_t type;
2141 uint16_t offset;
2142 uint8_t data[];
2143 } __attribute__((__packed__));
2144
2145 struct smbios_table {
2146 struct smbios_header header;
2147 uint8_t data[];
2148 } __attribute__((__packed__));
2149
2150 #define SMBIOS_FIELD_ENTRY 0
2151 #define SMBIOS_TABLE_ENTRY 1
2152
2153 static size_t
2154 smbios_load_field(int type, size_t offset, void *addr)
2155 {
2156 #ifdef BX_QEMU
2157 int i;
2158
2159 for (i = smbios_entries(); i > 0; i--) {
2160 struct smbios_field field;
2161
2162 qemu_cfg_read((uint8_t *)&field, sizeof(struct smbios_header));
2163 field.header.length -= sizeof(struct smbios_header);
2164
2165 if (field.header.type != SMBIOS_FIELD_ENTRY) {
2166 while (field.header.length--)
2167 inb(QEMU_CFG_DATA_PORT);
2168 continue;
2169 }
2170
2171 qemu_cfg_read((uint8_t *)&field.type,
2172 sizeof(field) - sizeof(struct smbios_header));
2173 field.header.length -= sizeof(field) - sizeof(struct smbios_header);
2174
2175 if (field.type != type || field.offset != offset) {
2176 while (field.header.length--)
2177 inb(QEMU_CFG_DATA_PORT);
2178 continue;
2179 }
2180
2181 qemu_cfg_read(addr, field.header.length);
2182 return (size_t)field.header.length;
2183 }
2184 #endif
2185 return 0;
2186 }
2187
2188 #define load_str_field_with_default(type, field, def) do { \
2189 size = smbios_load_field(type, offsetof(struct smbios_type_##type, \
2190 field), end); \
2191 if (size > 0) { \
2192 end += size; \
2193 } else { \
2194 memcpy(end, def, sizeof(def)); \
2195 end += sizeof(def); \
2196 } \
2197 p->field = ++str_index; \
2198 } while (0)
2199
2200 #define load_str_field_or_skip(type, field) do { \
2201 size = smbios_load_field(type, offsetof(struct smbios_type_##type, \
2202 field), end); \
2203 if (size > 0) { \
2204 end += size; \
2205 p->field = ++str_index; \
2206 } else { \
2207 p->field = 0; \
2208 } \
2209 } while (0)
2210
2211 /* Type 0 -- BIOS Information */
2212 #define RELEASE_DATE_STR "01/01/2007"
2213 static void *
2214 smbios_init_type_0(void *start)
2215 {
2216 struct smbios_type_0 *p = (struct smbios_type_0 *)start;
2217 char *end = (char *)start + sizeof(struct smbios_type_0);
2218 size_t size;
2219 int str_index = 0;
2220
2221 p->header.type = 0;
2222 p->header.length = sizeof(struct smbios_type_0);
2223 p->header.handle = 0;
2224
2225 load_str_field_with_default(0, vendor_str, BX_APPNAME);
2226 load_str_field_with_default(0, bios_version_str, BX_APPNAME);
2227
2228 p->bios_starting_address_segment = 0xe800;
2229
2230 load_str_field_with_default(0, bios_release_date_str, RELEASE_DATE_STR);
2231
2232 p->bios_rom_size = 0; /* FIXME */
2233
2234 memset(p->bios_characteristics, 0, 8);
2235 p->bios_characteristics[0] = 0x08; /* BIOS characteristics not supported */
2236 p->bios_characteristics_extension_bytes[0] = 0;
2237 p->bios_characteristics_extension_bytes[1] = 0;
2238
2239 if (!smbios_load_field(0, offsetof(struct smbios_type_0,
2240 system_bios_major_release),
2241 &p->system_bios_major_release))
2242 p->system_bios_major_release = 1;
2243
2244 if (!smbios_load_field(0, offsetof(struct smbios_type_0,
2245 system_bios_minor_release),
2246 &p->system_bios_minor_release))
2247 p->system_bios_minor_release = 0;
2248
2249 p->embedded_controller_major_release = 0xff;
2250 p->embedded_controller_minor_release = 0xff;
2251
2252 *end = 0;
2253 end++;
2254
2255 return end;
2256 }
2257
2258 /* Type 1 -- System Information */
2259 static void *
2260 smbios_init_type_1(void *start)
2261 {
2262 struct smbios_type_1 *p = (struct smbios_type_1 *)start;
2263 char *end = (char *)start + sizeof(struct smbios_type_1);
2264 size_t size;
2265 int str_index = 0;
2266
2267 p->header.type = 1;
2268 p->header.length = sizeof(struct smbios_type_1);
2269 p->header.handle = 0x100;
2270
2271 load_str_field_or_skip(1, manufacturer_str);
2272 load_str_field_or_skip(1, product_name_str);
2273 load_str_field_or_skip(1, version_str);
2274 load_str_field_or_skip(1, serial_number_str);
2275
2276 size = smbios_load_field(1, offsetof(struct smbios_type_1,
2277 uuid), &p->uuid);
2278 if (size == 0)
2279 memset(p->uuid, 0, 16);
2280
2281 p->wake_up_type = 0x06; /* power switch */
2282
2283 load_str_field_or_skip(1, sku_number_str);
2284 load_str_field_or_skip(1, family_str);
2285
2286 *end = 0;
2287 end++;
2288 if (!str_index) {
2289 *end = 0;
2290 end++;
2291 }
2292
2293 return end;
2294 }
2295
2296 /* Type 3 -- System Enclosure */
2297 static void *
2298 smbios_init_type_3(void *start)
2299 {
2300 struct smbios_type_3 *p = (struct smbios_type_3 *)start;
2301
2302 p->header.type = 3;
2303 p->header.length = sizeof(struct smbios_type_3);
2304 p->header.handle = 0x300;
2305
2306 p->manufacturer_str = 0;
2307 p->type = 0x01; /* other */
2308 p->version_str = 0;
2309 p->serial_number_str = 0;
2310 p->asset_tag_number_str = 0;
2311 p->boot_up_state = 0x03; /* safe */
2312 p->power_supply_state = 0x03; /* safe */
2313 p->thermal_state = 0x03; /* safe */
2314 p->security_status = 0x02; /* unknown */
2315 p->oem_defined = 0;
2316 p->height = 0;
2317 p->number_of_power_cords = 0;
2318 p->contained_element_count = 0;
2319
2320 start += sizeof(struct smbios_type_3);
2321 *((uint16_t *)start) = 0;
2322
2323 return start+2;
2324 }
2325
2326 /* Type 4 -- Processor Information */
2327 static void *
2328 smbios_init_type_4(void *start, unsigned int cpu_number)
2329 {
2330 struct smbios_type_4 *p = (struct smbios_type_4 *)start;
2331
2332 p->header.type = 4;
2333 p->header.length = sizeof(struct smbios_type_4);
2334 p->header.handle = 0x400 + cpu_number;
2335
2336 p->socket_designation_str = 1;
2337 p->processor_type = 0x03; /* CPU */
2338 p->processor_family = 0x01; /* other */
2339 p->processor_manufacturer_str = 0;
2340
2341 p->processor_id[0] = cpuid_signature;
2342 p->processor_id[1] = cpuid_features;
2343
2344 p->processor_version_str = 0;
2345 p->voltage = 0;
2346 p->external_clock = 0;
2347
2348 p->max_speed = 0; /* unknown */
2349 p->current_speed = 0; /* unknown */
2350
2351 p->status = 0x41; /* socket populated, CPU enabled */
2352 p->processor_upgrade = 0x01; /* other */
2353
2354 p->l1_cache_handle = 0xffff; /* cache information structure not provided */
2355 p->l2_cache_handle = 0xffff;
2356 p->l3_cache_handle = 0xffff;
2357
2358 start += sizeof(struct smbios_type_4);
2359
2360 memcpy((char *)start, "CPU " "\0" "" "\0" "", 7);
2361 ((char *)start)[4] = cpu_number + '0';
2362
2363 return start+7;
2364 }
2365
2366 /* Type 16 -- Physical Memory Array */
2367 static void *
2368 smbios_init_type_16(void *start, uint32_t memsize, int nr_mem_devs)
2369 {
2370 struct smbios_type_16 *p = (struct smbios_type_16*)start;
2371
2372 p->header.type = 16;
2373 p->header.length = sizeof(struct smbios_type_16);
2374 p->header.handle = 0x1000;
2375
2376 p->location = 0x01; /* other */
2377 p->use = 0x03; /* system memory */
2378 p->error_correction = 0x01; /* other */
2379 p->maximum_capacity = memsize * 1024;
2380 p->memory_error_information_handle = 0xfffe; /* none provided */
2381 p->number_of_memory_devices = nr_mem_devs;
2382
2383 start += sizeof(struct smbios_type_16);
2384 *((uint16_t *)start) = 0;
2385
2386 return start + 2;
2387 }
2388
2389 /* Type 17 -- Memory Device */
2390 static void *
2391 smbios_init_type_17(void *start, uint32_t memory_size_mb, int instance)
2392 {
2393 struct smbios_type_17 *p = (struct smbios_type_17 *)start;
2394
2395 p->header.type = 17;
2396 p->header.length = sizeof(struct smbios_type_17);
2397 p->header.handle = 0x1100 + instance;
2398
2399 p->physical_memory_array_handle = 0x1000;
2400 p->total_width = 64;
2401 p->data_width = 64;
2402 /* TODO: should assert in case something is wrong ASSERT((memory_size_mb & ~0x7fff) == 0); */
2403 p->size = memory_size_mb;
2404 p->form_factor = 0x09; /* DIMM */
2405 p->device_set = 0;
2406 p->device_locator_str = 1;
2407 p->bank_locator_str = 0;
2408 p->memory_type = 0x07; /* RAM */
2409 p->type_detail = 0;
2410
2411 start += sizeof(struct smbios_type_17);
2412 snprintf(start, 8, "DIMM %d", instance);
2413 start += strlen(start) + 1;
2414 *((uint8_t *)start) = 0;
2415
2416 return start+1;
2417 }
2418
2419 /* Type 19 -- Memory Array Mapped Address */
2420 static void *
2421 smbios_init_type_19(void *start, uint32_t memory_size_mb, int instance)
2422 {
2423 struct smbios_type_19 *p = (struct smbios_type_19 *)start;
2424
2425 p->header.type = 19;
2426 p->header.length = sizeof(struct smbios_type_19);
2427 p->header.handle = 0x1300 + instance;
2428
2429 p->starting_address = instance << 24;
2430 p->ending_address = p->starting_address + (memory_size_mb << 10) - 1;
2431 p->memory_array_handle = 0x1000;
2432 p->partition_width = 1;
2433
2434 start += sizeof(struct smbios_type_19);
2435 *((uint16_t *)start) = 0;
2436
2437 return start + 2;
2438 }
2439
2440 /* Type 20 -- Memory Device Mapped Address */
2441 static void *
2442 smbios_init_type_20(void *start, uint32_t memory_size_mb, int instance)
2443 {
2444 struct smbios_type_20 *p = (struct smbios_type_20 *)start;
2445
2446 p->header.type = 20;
2447 p->header.length = sizeof(struct smbios_type_20);
2448 p->header.handle = 0x1400 + instance;
2449
2450 p->starting_address = instance << 24;
2451 p->ending_address = p->starting_address + (memory_size_mb << 10) - 1;
2452 p->memory_device_handle = 0x1100 + instance;
2453 p->memory_array_mapped_address_handle = 0x1300 + instance;
2454 p->partition_row_position = 1;
2455 p->interleave_position = 0;
2456 p->interleaved_data_depth = 0;
2457
2458 start += sizeof(struct smbios_type_20);
2459
2460 *((uint16_t *)start) = 0;
2461 return start+2;
2462 }
2463
2464 /* Type 32 -- System Boot Information */
2465 static void *
2466 smbios_init_type_32(void *start)
2467 {
2468 struct smbios_type_32 *p = (struct smbios_type_32 *)start;
2469
2470 p->header.type = 32;
2471 p->header.length = sizeof(struct smbios_type_32);
2472 p->header.handle = 0x2000;
2473 memset(p->reserved, 0, 6);
2474 p->boot_status = 0; /* no errors detected */
2475
2476 start += sizeof(struct smbios_type_32);
2477 *((uint16_t *)start) = 0;
2478
2479 return start+2;
2480 }
2481
2482 /* Type 127 -- End of Table */
2483 static void *
2484 smbios_init_type_127(void *start)
2485 {
2486 struct smbios_type_127 *p = (struct smbios_type_127 *)start;
2487
2488 p->header.type = 127;
2489 p->header.length = sizeof(struct smbios_type_127);
2490 p->header.handle = 0x7f00;
2491
2492 start += sizeof(struct smbios_type_127);
2493 *((uint16_t *)start) = 0;
2494
2495 return start + 2;
2496 }
2497
2498 static int
2499 smbios_load_external(int type, char **p, unsigned *nr_structs,
2500 unsigned *max_struct_size)
2501 {
2502 #ifdef BX_QEMU
2503 static uint64_t used_bitmap[4] = { 0 };
2504 char *start = *p;
2505 int i;
2506
2507 /* Check if we've already reported these tables */
2508 if (used_bitmap[(type >> 6) & 0x3] & (1ULL << (type & 0x3f)))
2509 return 1;
2510
2511 /* Don't introduce spurious end markers */
2512 if (type == 127)
2513 return 0;
2514
2515 for (i = smbios_entries(); i > 0; i--) {
2516 struct smbios_table table;
2517 struct smbios_structure_header *header = (void *)*p;
2518 int string;
2519
2520 qemu_cfg_read((uint8_t *)&table, sizeof(struct smbios_header));
2521 table.header.length -= sizeof(struct smbios_header);
2522
2523 if (table.header.type != SMBIOS_TABLE_ENTRY) {
2524 while (table.header.length--)
2525 inb(QEMU_CFG_DATA_PORT);
2526 continue;
2527 }
2528
2529 qemu_cfg_read((uint8_t *)*p, sizeof(struct smbios_structure_header));
2530 table.header.length -= sizeof(struct smbios_structure_header);
2531
2532 if (header->type != type) {
2533 while (table.header.length--)
2534 inb(QEMU_CFG_DATA_PORT);
2535 continue;
2536 }
2537
2538 *p += sizeof(struct smbios_structure_header);
2539
2540 /* Entries end with a double NULL char, if there's a string at
2541 * the end (length is greater than formatted length), the string
2542 * terminator provides the first NULL. */
2543 string = header->length < table.header.length +
2544 sizeof(struct smbios_structure_header);
2545
2546 /* Read the rest and terminate the entry */
2547 qemu_cfg_read((uint8_t *)*p, table.header.length);
2548 *p += table.header.length;
2549 *((uint8_t*)*p) = 0;
2550 (*p)++;
2551 if (!string) {
2552 *((uint8_t*)*p) = 0;
2553 (*p)++;
2554 }
2555
2556 (*nr_structs)++;
2557 if (*p - (char *)header > *max_struct_size)
2558 *max_struct_size = *p - (char *)header;
2559 }
2560
2561 if (start != *p) {
2562 /* Mark that we've reported on this type */
2563 used_bitmap[(type >> 6) & 0x3] |= (1ULL << (type & 0x3f));
2564 return 1;
2565 }
2566
2567 #endif /* !BX_QEMU */
2568 return 0;
2569 }
2570
2571 void smbios_init(void)
2572 {
2573 unsigned cpu_num, nr_structs = 0, max_struct_size = 0;
2574 char *start, *p, *q;
2575 int memsize = (ram_end == ram_size) ? ram_size / (1024 * 1024) :
2576 (ram_end - (1ull << 32) + ram_size) / (1024 * 1024);
2577 int i, nr_mem_devs;
2578
2579 #ifdef BX_USE_EBDA_TABLES
2580 ebda_cur_addr = align(ebda_cur_addr, 16);
2581 start = (void *)(ebda_cur_addr);
2582 #else
2583 bios_table_cur_addr = align(bios_table_cur_addr, 16);
2584 start = (void *)(bios_table_cur_addr);
2585 #endif
2586
2587 p = (char *)start + sizeof(struct smbios_entry_point);
2588
2589 #define add_struct(type, args...) do { \
2590 if (!smbios_load_external(type, &p, &nr_structs, &max_struct_size)) { \
2591 q = smbios_init_type_##type(args); \
2592 nr_structs++; \
2593 if ((q - p) > max_struct_size) \
2594 max_struct_size = q - p; \
2595 p = q; \
2596 } \
2597 } while (0)
2598
2599 add_struct(0, p);
2600 add_struct(1, p);
2601 add_struct(3, p);
2602 for (cpu_num = 1; cpu_num <= smp_cpus; cpu_num++)
2603 add_struct(4, p, cpu_num);
2604
2605 /* Each 'memory device' covers up to 16GB of address space. */
2606 nr_mem_devs = (memsize + 0x3fff) >> 14;
2607 add_struct(16, p, memsize, nr_mem_devs);
2608 for ( i = 0; i < nr_mem_devs; i++ )
2609 {
2610 uint32_t dev_memsize = ((i == (nr_mem_devs - 1))
2611 ? (((memsize-1) & 0x3fff)+1) : 0x4000);
2612 add_struct(17, p, dev_memsize, i);
2613 add_struct(19, p, dev_memsize, i);
2614 add_struct(20, p, dev_memsize, i);
2615 }
2616
2617 add_struct(32, p);
2618 /* Add any remaining provided entries before the end marker */
2619 for (i = 0; i < 256; i++)
2620 smbios_load_external(i, &p, &nr_structs, &max_struct_size);
2621 add_struct(127, p);
2622
2623 #undef add_struct
2624
2625 smbios_entry_point_init(
2626 start, max_struct_size,
2627 (p - (char *)start) - sizeof(struct smbios_entry_point),
2628 (uint32_t)(start + sizeof(struct smbios_entry_point)),
2629 nr_structs);
2630
2631 #ifdef BX_USE_EBDA_TABLES
2632 ebda_cur_addr += (p - (char *)start);
2633 #else
2634 bios_table_cur_addr += (p - (char *)start);
2635 #endif
2636
2637 BX_INFO("SMBIOS table addr=0x%08lx\n", (unsigned long)start);
2638 }
2639
2640 static uint32_t find_resume_vector(void)
2641 {
2642 unsigned long addr, start, end;
2643
2644 #ifdef BX_USE_EBDA_TABLES
2645 start = align(ebda_cur_addr, 16);
2646 end = 0xa000 << 4;
2647 #else
2648 if (bios_table_cur_addr == 0)
2649 return 0;
2650 start = align(bios_table_cur_addr, 16);
2651 end = bios_table_end_addr;
2652 #endif
2653
2654 for (addr = start; addr < end; addr += 16) {
2655 if (!memcmp((void*)addr, "RSD PTR ", 8)) {
2656 struct rsdp_descriptor *rsdp = (void*)addr;
2657 struct rsdt_descriptor_rev1 *rsdt = (void*)rsdp->rsdt_physical_address;
2658 struct fadt_descriptor_rev1 *fadt = (void*)rsdt->table_offset_entry[0];
2659 struct facs_descriptor_rev1 *facs = (void*)fadt->firmware_ctrl;
2660 return facs->firmware_waking_vector;
2661 }
2662 }
2663
2664 return 0;
2665 }
2666
2667 static void find_440fx(PCIDevice *d)
2668 {
2669 uint16_t vendor_id, device_id;
2670
2671 vendor_id = pci_config_readw(d, PCI_VENDOR_ID);
2672 device_id = pci_config_readw(d, PCI_DEVICE_ID);
2673
2674 if (vendor_id == PCI_VENDOR_ID_INTEL && device_id == PCI_DEVICE_ID_INTEL_82441)
2675 i440_pcidev = *d;
2676 }
2677
2678 static void reinit_piix4_pm(PCIDevice *d)
2679 {
2680 uint16_t vendor_id, device_id;
2681
2682 vendor_id = pci_config_readw(d, PCI_VENDOR_ID);
2683 device_id = pci_config_readw(d, PCI_DEVICE_ID);
2684
2685 if (vendor_id == PCI_VENDOR_ID_INTEL && device_id == PCI_DEVICE_ID_INTEL_82371AB_3)
2686 piix4_pm_enable(d);
2687 }
2688
2689 void rombios32_init(uint32_t *s3_resume_vector, uint8_t *shutdown_flag)
2690 {
2691 BX_INFO("Starting rombios32\n");
2692 BX_INFO("Shutdown flag %x\n", *shutdown_flag);
2693
2694 #ifdef BX_QEMU
2695 qemu_cfg_port = qemu_cfg_port_probe();
2696 #endif
2697
2698 init_smp_msrs();
2699
2700 ram_probe();
2701
2702 cpu_probe();
2703
2704 setup_mtrr();
2705
2706 smp_probe();
2707
2708 find_bios_table_area();
2709
2710 if (*shutdown_flag == 0xfe) {
2711 /* redirect bios read access to RAM */
2712 pci_for_each_device(find_440fx);
2713 bios_lock_shadow_ram(); /* bios is already copied */
2714 *s3_resume_vector = find_resume_vector();
2715 if (!*s3_resume_vector) {
2716 BX_INFO("This is S3 resume but wakeup vector is NULL\n");
2717 } else {
2718 BX_INFO("S3 resume vector %p\n", *s3_resume_vector);
2719 pci_for_each_device(reinit_piix4_pm);
2720 }
2721 return;
2722 }
2723
2724 pci_bios_init();
2725
2726 if (bios_table_cur_addr != 0) {
2727
2728 #ifdef BX_QEMU
2729 irq0_override_probe();
2730 #endif
2731 mptable_init();
2732
2733 smbios_init();
2734
2735 if (acpi_enabled)
2736 acpi_bios_init();
2737
2738 bios_lock_shadow_ram();
2739
2740 BX_INFO("bios_table_cur_addr: 0x%08lx\n", bios_table_cur_addr);
2741 if (bios_table_cur_addr > bios_table_end_addr)
2742 BX_PANIC("bios_table_end_addr overflow!\n");
2743 #ifdef BX_USE_EBDA_TABLES
2744 BX_INFO("ebda_cur_addr: 0x%08lx\n", ebda_cur_addr);
2745 if (ebda_cur_addr > 0xA0000)
2746 BX_PANIC("ebda_cur_addr overflow!\n");
2747 #endif
2748 }
2749 }
Patches shipped by Fedora