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virtio-net: replace custom io thread notify with qemu one
[qemu-kvm/fedora.git] / qemu-kvm-x86.c
blobd2c8abe1fd36d741abc1a7a19e2e16e19c45bac1
1 /*
2 * qemu/kvm integration, x86 specific code
3 *
4 * Copyright (C) 2006-2008 Qumranet Technologies
5 *
6 * Licensed under the terms of the GNU GPL version 2 or higher.
7 */
8
9 #include "config.h"
10 #include "config-host.h"
11
12 #include <string.h>
13 #include "hw/hw.h"
14 #include "gdbstub.h"
15 #include <sys/io.h>
16
17 #include "qemu-kvm.h"
18 #include "libkvm.h"
19 #include <pthread.h>
20 #include <sys/utsname.h>
21 #include <linux/kvm_para.h>
22 #include <sys/ioctl.h>
23
24 #include "kvm.h"
25 #include "hw/pc.h"
26
27 #define MSR_IA32_TSC 0x10
28
29 static struct kvm_msr_list *kvm_msr_list;
30 extern unsigned int kvm_shadow_memory;
31 static int kvm_has_msr_star;
32 static int kvm_has_vm_hsave_pa;
33
34 static int lm_capable_kernel;
35
36 int kvm_set_tss_addr(kvm_context_t kvm, unsigned long addr)
37 {
38 #ifdef KVM_CAP_SET_TSS_ADDR
39 int r;
40
41 r = ioctl(kvm->fd, KVM_CHECK_EXTENSION, KVM_CAP_SET_TSS_ADDR);
42 if (r > 0) {
43 r = ioctl(kvm->vm_fd, KVM_SET_TSS_ADDR, addr);
44 if (r == -1) {
45 fprintf(stderr, "kvm_set_tss_addr: %m\n");
46 return -errno;
47 }
48 return 0;
49 }
50 #endif
51 return -ENOSYS;
52 }
53
54 static int kvm_init_tss(kvm_context_t kvm)
55 {
56 #ifdef KVM_CAP_SET_TSS_ADDR
57 int r;
58
59 r = ioctl(kvm->fd, KVM_CHECK_EXTENSION, KVM_CAP_SET_TSS_ADDR);
60 if (r > 0) {
61 /*
62 * this address is 3 pages before the bios, and the bios should present
63 * as unavaible memory
64 */
65 r = kvm_set_tss_addr(kvm, 0xfffbd000);
66 if (r < 0) {
67 fprintf(stderr, "kvm_init_tss: unable to set tss addr\n");
68 return r;
69 }
70
71 }
72 #endif
73 return 0;
74 }
75
76 static int kvm_set_identity_map_addr(kvm_context_t kvm, unsigned long addr)
77 {
78 #ifdef KVM_CAP_SET_IDENTITY_MAP_ADDR
79 int r;
80
81 r = ioctl(kvm->fd, KVM_CHECK_EXTENSION, KVM_CAP_SET_IDENTITY_MAP_ADDR);
82 if (r > 0) {
83 r = ioctl(kvm->vm_fd, KVM_SET_IDENTITY_MAP_ADDR, &addr);
84 if (r == -1) {
85 fprintf(stderr, "kvm_set_identity_map_addr: %m\n");
86 return -errno;
87 }
88 return 0;
89 }
90 #endif
91 return -ENOSYS;
92 }
93
94 static int kvm_init_identity_map_page(kvm_context_t kvm)
95 {
96 #ifdef KVM_CAP_SET_IDENTITY_MAP_ADDR
97 int r;
98
99 r = ioctl(kvm->fd, KVM_CHECK_EXTENSION, KVM_CAP_SET_IDENTITY_MAP_ADDR);
100 if (r > 0) {
101 /*
102 * this address is 4 pages before the bios, and the bios should present
103 * as unavaible memory
104 */
105 r = kvm_set_identity_map_addr(kvm, 0xfffbc000);
106 if (r < 0) {
107 fprintf(stderr, "kvm_init_identity_map_page: "
108 "unable to set identity mapping addr\n");
109 return r;
110 }
111
112 }
113 #endif
114 return 0;
115 }
116
117 static int kvm_create_pit(kvm_context_t kvm)
118 {
119 #ifdef KVM_CAP_PIT
120 int r;
121
122 kvm->pit_in_kernel = 0;
123 if (!kvm->no_pit_creation) {
124 r = ioctl(kvm->fd, KVM_CHECK_EXTENSION, KVM_CAP_PIT);
125 if (r > 0) {
126 r = ioctl(kvm->vm_fd, KVM_CREATE_PIT);
127 if (r >= 0)
128 kvm->pit_in_kernel = 1;
129 else {
130 fprintf(stderr, "Create kernel PIC irqchip failed\n");
131 return r;
132 }
133 }
134 }
135 #endif
136 return 0;
137 }
138
139 int kvm_arch_create(kvm_context_t kvm, unsigned long phys_mem_bytes,
140 void **vm_mem)
141 {
142 int r = 0;
143
144 r = kvm_init_tss(kvm);
145 if (r < 0)
146 return r;
147
148 r = kvm_init_identity_map_page(kvm);
149 if (r < 0)
150 return r;
151
152 r = kvm_create_pit(kvm);
153 if (r < 0)
154 return r;
155
156 r = kvm_init_coalesced_mmio(kvm);
157 if (r < 0)
158 return r;
159
160 return 0;
161 }
162
163 #ifdef KVM_EXIT_TPR_ACCESS
164
165 static int kvm_handle_tpr_access(kvm_vcpu_context_t vcpu)
166 {
167 struct kvm_run *run = vcpu->run;
168 kvm_tpr_access_report(cpu_single_env,
169 run->tpr_access.rip,
170 run->tpr_access.is_write);
171 return 0;
172 }
173
174
175 int kvm_enable_vapic(kvm_vcpu_context_t vcpu, uint64_t vapic)
176 {
177 int r;
178 struct kvm_vapic_addr va = {
179 .vapic_addr = vapic,
180 };
181
182 r = ioctl(vcpu->fd, KVM_SET_VAPIC_ADDR, &va);
183 if (r == -1) {
184 r = -errno;
185 perror("kvm_enable_vapic");
186 return r;
187 }
188 return 0;
189 }
190
191 #endif
192
193 int kvm_arch_run(kvm_vcpu_context_t vcpu)
194 {
195 int r = 0;
196 struct kvm_run *run = vcpu->run;
197
198
199 switch (run->exit_reason) {
200 #ifdef KVM_EXIT_SET_TPR
201 case KVM_EXIT_SET_TPR:
202 break;
203 #endif
204 #ifdef KVM_EXIT_TPR_ACCESS
205 case KVM_EXIT_TPR_ACCESS:
206 r = kvm_handle_tpr_access(vcpu);
207 break;
208 #endif
209 default:
210 r = 1;
211 break;
212 }
213
214 return r;
215 }
216
217 #define MAX_ALIAS_SLOTS 4
218 static struct {
219 uint64_t start;
220 uint64_t len;
221 } kvm_aliases[MAX_ALIAS_SLOTS];
222
223 static int get_alias_slot(uint64_t start)
224 {
225 int i;
226
227 for (i=0; i<MAX_ALIAS_SLOTS; i++)
228 if (kvm_aliases[i].start == start)
229 return i;
230 return -1;
231 }
232 static int get_free_alias_slot(void)
233 {
234 int i;
235
236 for (i=0; i<MAX_ALIAS_SLOTS; i++)
237 if (kvm_aliases[i].len == 0)
238 return i;
239 return -1;
240 }
241
242 static void register_alias(int slot, uint64_t start, uint64_t len)
243 {
244 kvm_aliases[slot].start = start;
245 kvm_aliases[slot].len = len;
246 }
247
248 int kvm_create_memory_alias(kvm_context_t kvm,
249 uint64_t phys_start,
250 uint64_t len,
251 uint64_t target_phys)
252 {
253 struct kvm_memory_alias alias = {
254 .flags = 0,
255 .guest_phys_addr = phys_start,
256 .memory_size = len,
257 .target_phys_addr = target_phys,
258 };
259 int fd = kvm->vm_fd;
260 int r;
261 int slot;
262
263 slot = get_alias_slot(phys_start);
264 if (slot < 0)
265 slot = get_free_alias_slot();
266 if (slot < 0)
267 return -EBUSY;
268 alias.slot = slot;
269
270 r = ioctl(fd, KVM_SET_MEMORY_ALIAS, &alias);
271 if (r == -1)
272 return -errno;
273
274 register_alias(slot, phys_start, len);
275 return 0;
276 }
277
278 int kvm_destroy_memory_alias(kvm_context_t kvm, uint64_t phys_start)
279 {
280 return kvm_create_memory_alias(kvm, phys_start, 0, 0);
281 }
282
283 #ifdef KVM_CAP_IRQCHIP
284
285 int kvm_get_lapic(kvm_vcpu_context_t vcpu, struct kvm_lapic_state *s)
286 {
287 int r;
288 if (!kvm_irqchip_in_kernel(vcpu->kvm))
289 return 0;
290 r = ioctl(vcpu->fd, KVM_GET_LAPIC, s);
291 if (r == -1) {
292 r = -errno;
293 perror("kvm_get_lapic");
294 }
295 return r;
296 }
297
298 int kvm_set_lapic(kvm_vcpu_context_t vcpu, struct kvm_lapic_state *s)
299 {
300 int r;
301 if (!kvm_irqchip_in_kernel(vcpu->kvm))
302 return 0;
303 r = ioctl(vcpu->fd, KVM_SET_LAPIC, s);
304 if (r == -1) {
305 r = -errno;
306 perror("kvm_set_lapic");
307 }
308 return r;
309 }
310
311 #endif
312
313 #ifdef KVM_CAP_PIT
314
315 int kvm_get_pit(kvm_context_t kvm, struct kvm_pit_state *s)
316 {
317 int r;
318 if (!kvm->pit_in_kernel)
319 return 0;
320 r = ioctl(kvm->vm_fd, KVM_GET_PIT, s);
321 if (r == -1) {
322 r = -errno;
323 perror("kvm_get_pit");
324 }
325 return r;
326 }
327
328 int kvm_set_pit(kvm_context_t kvm, struct kvm_pit_state *s)
329 {
330 int r;
331 if (!kvm->pit_in_kernel)
332 return 0;
333 r = ioctl(kvm->vm_fd, KVM_SET_PIT, s);
334 if (r == -1) {
335 r = -errno;
336 perror("kvm_set_pit");
337 }
338 return r;
339 }
340
341 #ifdef KVM_CAP_PIT_STATE2
342 int kvm_get_pit2(kvm_context_t kvm, struct kvm_pit_state2 *ps2)
343 {
344 int r;
345 if (!kvm->pit_in_kernel)
346 return 0;
347 r = ioctl(kvm->vm_fd, KVM_GET_PIT2, ps2);
348 if (r == -1) {
349 r = -errno;
350 perror("kvm_get_pit2");
351 }
352 return r;
353 }
354
355 int kvm_set_pit2(kvm_context_t kvm, struct kvm_pit_state2 *ps2)
356 {
357 int r;
358 if (!kvm->pit_in_kernel)
359 return 0;
360 r = ioctl(kvm->vm_fd, KVM_SET_PIT2, ps2);
361 if (r == -1) {
362 r = -errno;
363 perror("kvm_set_pit2");
364 }
365 return r;
366 }
367
368 #endif
369 #endif
370
371 int kvm_has_pit_state2(kvm_context_t kvm)
372 {
373 int r = 0;
374
375 #ifdef KVM_CAP_PIT_STATE2
376 r = kvm_check_extension(kvm, KVM_CAP_PIT_STATE2);
377 #endif
378 return r;
379 }
380
381 void kvm_show_code(kvm_vcpu_context_t vcpu)
382 {
383 #define SHOW_CODE_LEN 50
384 int fd = vcpu->fd;
385 struct kvm_regs regs;
386 struct kvm_sregs sregs;
387 int r, n;
388 int back_offset;
389 unsigned char code;
390 char code_str[SHOW_CODE_LEN * 3 + 1];
391 unsigned long rip;
392 kvm_context_t kvm = vcpu->kvm;
393
394 r = ioctl(fd, KVM_GET_SREGS, &sregs);
395 if (r == -1) {
396 perror("KVM_GET_SREGS");
397 return;
398 }
399 r = ioctl(fd, KVM_GET_REGS, &regs);
400 if (r == -1) {
401 perror("KVM_GET_REGS");
402 return;
403 }
404 rip = sregs.cs.base + regs.rip;
405 back_offset = regs.rip;
406 if (back_offset > 20)
407 back_offset = 20;
408 *code_str = 0;
409 for (n = -back_offset; n < SHOW_CODE_LEN-back_offset; ++n) {
410 if (n == 0)
411 strcat(code_str, " -->");
412 r = kvm_mmio_read(kvm->opaque, rip + n, &code, 1);
413 if (r < 0) {
414 strcat(code_str, " xx");
415 continue;
416 }
417 sprintf(code_str + strlen(code_str), " %02x", code);
418 }
419 fprintf(stderr, "code:%s\n", code_str);
420 }
421
422
423 /*
424 * Returns available msr list. User must free.
425 */
426 struct kvm_msr_list *kvm_get_msr_list(kvm_context_t kvm)
427 {
428 struct kvm_msr_list sizer, *msrs;
429 int r, e;
430
431 sizer.nmsrs = 0;
432 r = ioctl(kvm->fd, KVM_GET_MSR_INDEX_LIST, &sizer);
433 if (r == -1 && errno != E2BIG)
434 return NULL;
435 /* Old kernel modules had a bug and could write beyond the provided
436 memory. Allocate at least a safe amount of 1K. */
437 msrs = qemu_malloc(MAX(1024, sizeof(*msrs) +
438 sizer.nmsrs * sizeof(*msrs->indices)));
439
440 msrs->nmsrs = sizer.nmsrs;
441 r = ioctl(kvm->fd, KVM_GET_MSR_INDEX_LIST, msrs);
442 if (r == -1) {
443 e = errno;
444 free(msrs);
445 errno = e;
446 return NULL;
447 }
448 return msrs;
449 }
450
451 int kvm_get_msrs(kvm_vcpu_context_t vcpu, struct kvm_msr_entry *msrs, int n)
452 {
453 struct kvm_msrs *kmsrs = qemu_malloc(sizeof *kmsrs + n * sizeof *msrs);
454 int r, e;
455
456 kmsrs->nmsrs = n;
457 memcpy(kmsrs->entries, msrs, n * sizeof *msrs);
458 r = ioctl(vcpu->fd, KVM_GET_MSRS, kmsrs);
459 e = errno;
460 memcpy(msrs, kmsrs->entries, n * sizeof *msrs);
461 free(kmsrs);
462 errno = e;
463 return r;
464 }
465
466 int kvm_set_msrs(kvm_vcpu_context_t vcpu, struct kvm_msr_entry *msrs, int n)
467 {
468 struct kvm_msrs *kmsrs = qemu_malloc(sizeof *kmsrs + n * sizeof *msrs);
469 int r, e;
470
471 kmsrs->nmsrs = n;
472 memcpy(kmsrs->entries, msrs, n * sizeof *msrs);
473 r = ioctl(vcpu->fd, KVM_SET_MSRS, kmsrs);
474 e = errno;
475 free(kmsrs);
476 errno = e;
477 return r;
478 }
479
480 int kvm_get_mce_cap_supported(kvm_context_t kvm, uint64_t *mce_cap,
481 int *max_banks)
482 {
483 #ifdef KVM_CAP_MCE
484 int r;
485
486 r = ioctl(kvm->fd, KVM_CHECK_EXTENSION, KVM_CAP_MCE);
487 if (r > 0) {
488 *max_banks = r;
489 return ioctl(kvm->fd, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);
490 }
491 #endif
492 return -ENOSYS;
493 }
494
495 int kvm_setup_mce(kvm_vcpu_context_t vcpu, uint64_t *mcg_cap)
496 {
497 #ifdef KVM_CAP_MCE
498 return ioctl(vcpu->fd, KVM_X86_SETUP_MCE, mcg_cap);
499 #else
500 return -ENOSYS;
501 #endif
502 }
503
504 int kvm_set_mce(kvm_vcpu_context_t vcpu, struct kvm_x86_mce *m)
505 {
506 #ifdef KVM_CAP_MCE
507 return ioctl(vcpu->fd, KVM_X86_SET_MCE, m);
508 #else
509 return -ENOSYS;
510 #endif
511 }
512
513 static void print_seg(FILE *file, const char *name, struct kvm_segment *seg)
514 {
515 fprintf(stderr,
516 "%s %04x (%08llx/%08x p %d dpl %d db %d s %d type %x l %d"
517 " g %d avl %d)\n",
518 name, seg->selector, seg->base, seg->limit, seg->present,
519 seg->dpl, seg->db, seg->s, seg->type, seg->l, seg->g,
520 seg->avl);
521 }
522
523 static void print_dt(FILE *file, const char *name, struct kvm_dtable *dt)
524 {
525 fprintf(stderr, "%s %llx/%x\n", name, dt->base, dt->limit);
526 }
527
528 void kvm_show_regs(kvm_vcpu_context_t vcpu)
529 {
530 int fd = vcpu->fd;
531 struct kvm_regs regs;
532 struct kvm_sregs sregs;
533 int r;
534
535 r = ioctl(fd, KVM_GET_REGS, &regs);
536 if (r == -1) {
537 perror("KVM_GET_REGS");
538 return;
539 }
540 fprintf(stderr,
541 "rax %016llx rbx %016llx rcx %016llx rdx %016llx\n"
542 "rsi %016llx rdi %016llx rsp %016llx rbp %016llx\n"
543 "r8 %016llx r9 %016llx r10 %016llx r11 %016llx\n"
544 "r12 %016llx r13 %016llx r14 %016llx r15 %016llx\n"
545 "rip %016llx rflags %08llx\n",
546 regs.rax, regs.rbx, regs.rcx, regs.rdx,
547 regs.rsi, regs.rdi, regs.rsp, regs.rbp,
548 regs.r8, regs.r9, regs.r10, regs.r11,
549 regs.r12, regs.r13, regs.r14, regs.r15,
550 regs.rip, regs.rflags);
551 r = ioctl(fd, KVM_GET_SREGS, &sregs);
552 if (r == -1) {
553 perror("KVM_GET_SREGS");
554 return;
555 }
556 print_seg(stderr, "cs", &sregs.cs);
557 print_seg(stderr, "ds", &sregs.ds);
558 print_seg(stderr, "es", &sregs.es);
559 print_seg(stderr, "ss", &sregs.ss);
560 print_seg(stderr, "fs", &sregs.fs);
561 print_seg(stderr, "gs", &sregs.gs);
562 print_seg(stderr, "tr", &sregs.tr);
563 print_seg(stderr, "ldt", &sregs.ldt);
564 print_dt(stderr, "gdt", &sregs.gdt);
565 print_dt(stderr, "idt", &sregs.idt);
566 fprintf(stderr, "cr0 %llx cr2 %llx cr3 %llx cr4 %llx cr8 %llx"
567 " efer %llx\n",
568 sregs.cr0, sregs.cr2, sregs.cr3, sregs.cr4, sregs.cr8,
569 sregs.efer);
570 }
571
572 uint64_t kvm_get_apic_base(kvm_vcpu_context_t vcpu)
573 {
574 return vcpu->run->apic_base;
575 }
576
577 void kvm_set_cr8(kvm_vcpu_context_t vcpu, uint64_t cr8)
578 {
579 vcpu->run->cr8 = cr8;
580 }
581
582 __u64 kvm_get_cr8(kvm_vcpu_context_t vcpu)
583 {
584 return vcpu->run->cr8;
585 }
586
587 int kvm_setup_cpuid(kvm_vcpu_context_t vcpu, int nent,
588 struct kvm_cpuid_entry *entries)
589 {
590 struct kvm_cpuid *cpuid;
591 int r;
592
593 cpuid = qemu_malloc(sizeof(*cpuid) + nent * sizeof(*entries));
594
595 cpuid->nent = nent;
596 memcpy(cpuid->entries, entries, nent * sizeof(*entries));
597 r = ioctl(vcpu->fd, KVM_SET_CPUID, cpuid);
598
599 free(cpuid);
600 return r;
601 }
602
603 int kvm_setup_cpuid2(kvm_vcpu_context_t vcpu, int nent,
604 struct kvm_cpuid_entry2 *entries)
605 {
606 struct kvm_cpuid2 *cpuid;
607 int r;
608
609 cpuid = qemu_malloc(sizeof(*cpuid) + nent * sizeof(*entries));
610
611 cpuid->nent = nent;
612 memcpy(cpuid->entries, entries, nent * sizeof(*entries));
613 r = ioctl(vcpu->fd, KVM_SET_CPUID2, cpuid);
614 if (r == -1) {
615 fprintf(stderr, "kvm_setup_cpuid2: %m\n");
616 r = -errno;
617 }
618 free(cpuid);
619 return r;
620 }
621
622 int kvm_set_shadow_pages(kvm_context_t kvm, unsigned int nrshadow_pages)
623 {
624 #ifdef KVM_CAP_MMU_SHADOW_CACHE_CONTROL
625 int r;
626
627 r = ioctl(kvm->fd, KVM_CHECK_EXTENSION,
628 KVM_CAP_MMU_SHADOW_CACHE_CONTROL);
629 if (r > 0) {
630 r = ioctl(kvm->vm_fd, KVM_SET_NR_MMU_PAGES, nrshadow_pages);
631 if (r == -1) {
632 fprintf(stderr, "kvm_set_shadow_pages: %m\n");
633 return -errno;
634 }
635 return 0;
636 }
637 #endif
638 return -1;
639 }
640
641 int kvm_get_shadow_pages(kvm_context_t kvm, unsigned int *nrshadow_pages)
642 {
643 #ifdef KVM_CAP_MMU_SHADOW_CACHE_CONTROL
644 int r;
645
646 r = ioctl(kvm->fd, KVM_CHECK_EXTENSION,
647 KVM_CAP_MMU_SHADOW_CACHE_CONTROL);
648 if (r > 0) {
649 *nrshadow_pages = ioctl(kvm->vm_fd, KVM_GET_NR_MMU_PAGES);
650 return 0;
651 }
652 #endif
653 return -1;
654 }
655
656 #ifdef KVM_CAP_VAPIC
657
658 static int tpr_access_reporting(kvm_vcpu_context_t vcpu, int enabled)
659 {
660 int r;
661 struct kvm_tpr_access_ctl tac = {
662 .enabled = enabled,
663 };
664
665 r = ioctl(vcpu->kvm->fd, KVM_CHECK_EXTENSION, KVM_CAP_VAPIC);
666 if (r == -1 || r == 0)
667 return -ENOSYS;
668 r = ioctl(vcpu->fd, KVM_TPR_ACCESS_REPORTING, &tac);
669 if (r == -1) {
670 r = -errno;
671 perror("KVM_TPR_ACCESS_REPORTING");
672 return r;
673 }
674 return 0;
675 }
676
677 int kvm_enable_tpr_access_reporting(kvm_vcpu_context_t vcpu)
678 {
679 return tpr_access_reporting(vcpu, 1);
680 }
681
682 int kvm_disable_tpr_access_reporting(kvm_vcpu_context_t vcpu)
683 {
684 return tpr_access_reporting(vcpu, 0);
685 }
686
687 #endif
688
689 #ifdef KVM_CAP_EXT_CPUID
690
691 static struct kvm_cpuid2 *try_get_cpuid(kvm_context_t kvm, int max)
692 {
693 struct kvm_cpuid2 *cpuid;
694 int r, size;
695
696 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
697 cpuid = qemu_malloc(size);
698 cpuid->nent = max;
699 r = ioctl(kvm->fd, KVM_GET_SUPPORTED_CPUID, cpuid);
700 if (r == -1)
701 r = -errno;
702 else if (r == 0 && cpuid->nent >= max)
703 r = -E2BIG;
704 if (r < 0) {
705 if (r == -E2BIG) {
706 free(cpuid);
707 return NULL;
708 } else {
709 fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
710 strerror(-r));
711 exit(1);
712 }
713 }
714 return cpuid;
715 }
716
717 #define R_EAX 0
718 #define R_ECX 1
719 #define R_EDX 2
720 #define R_EBX 3
721 #define R_ESP 4
722 #define R_EBP 5
723 #define R_ESI 6
724 #define R_EDI 7
725
726 uint32_t kvm_get_supported_cpuid(kvm_context_t kvm, uint32_t function, int reg)
727 {
728 struct kvm_cpuid2 *cpuid;
729 int i, max;
730 uint32_t ret = 0;
731 uint32_t cpuid_1_edx;
732
733 if (!kvm_check_extension(kvm, KVM_CAP_EXT_CPUID)) {
734 return -1U;
735 }
736
737 max = 1;
738 while ((cpuid = try_get_cpuid(kvm, max)) == NULL) {
739 max *= 2;
740 }
741
742 for (i = 0; i < cpuid->nent; ++i) {
743 if (cpuid->entries[i].function == function) {
744 switch (reg) {
745 case R_EAX:
746 ret = cpuid->entries[i].eax;
747 break;
748 case R_EBX:
749 ret = cpuid->entries[i].ebx;
750 break;
751 case R_ECX:
752 ret = cpuid->entries[i].ecx;
753 break;
754 case R_EDX:
755 ret = cpuid->entries[i].edx;
756 if (function == 1) {
757 /* kvm misreports the following features
758 */
759 ret |= 1 << 12; /* MTRR */
760 ret |= 1 << 16; /* PAT */
761 ret |= 1 << 7; /* MCE */
762 ret |= 1 << 14; /* MCA */
763 }
764
765 /* On Intel, kvm returns cpuid according to
766 * the Intel spec, so add missing bits
767 * according to the AMD spec:
768 */
769 if (function == 0x80000001) {
770 cpuid_1_edx = kvm_get_supported_cpuid(kvm, 1, R_EDX);
771 ret |= cpuid_1_edx & 0xdfeff7ff;
772 }
773 break;
774 }
775 }
776 }
777
778 free(cpuid);
779
780 return ret;
781 }
782
783 #else
784
785 uint32_t kvm_get_supported_cpuid(kvm_context_t kvm, uint32_t function, int reg)
786 {
787 return -1U;
788 }
789
790 #endif
791 int kvm_qemu_create_memory_alias(uint64_t phys_start,
792 uint64_t len,
793 uint64_t target_phys)
794 {
795 return kvm_create_memory_alias(kvm_context, phys_start, len, target_phys);
796 }
797
798 int kvm_qemu_destroy_memory_alias(uint64_t phys_start)
799 {
800 return kvm_destroy_memory_alias(kvm_context, phys_start);
801 }
802
803 int kvm_arch_qemu_create_context(void)
804 {
805 int i;
806 struct utsname utsname;
807
808 uname(&utsname);
809 lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
810
811 if (kvm_shadow_memory)
812 kvm_set_shadow_pages(kvm_context, kvm_shadow_memory);
813
814 kvm_msr_list = kvm_get_msr_list(kvm_context);
815 if (!kvm_msr_list)
816 return -1;
817 for (i = 0; i < kvm_msr_list->nmsrs; ++i) {
818 if (kvm_msr_list->indices[i] == MSR_STAR)
819 kvm_has_msr_star = 1;
820 if (kvm_msr_list->indices[i] == MSR_VM_HSAVE_PA)
821 kvm_has_vm_hsave_pa = 1;
822 }
823
824 return 0;
825 }
826
827 static void set_msr_entry(struct kvm_msr_entry *entry, uint32_t index,
828 uint64_t data)
829 {
830 entry->index = index;
831 entry->data = data;
832 }
833
834 /* returns 0 on success, non-0 on failure */
835 static int get_msr_entry(struct kvm_msr_entry *entry, CPUState *env)
836 {
837 switch (entry->index) {
838 case MSR_IA32_SYSENTER_CS:
839 env->sysenter_cs = entry->data;
840 break;
841 case MSR_IA32_SYSENTER_ESP:
842 env->sysenter_esp = entry->data;
843 break;
844 case MSR_IA32_SYSENTER_EIP:
845 env->sysenter_eip = entry->data;
846 break;
847 case MSR_STAR:
848 env->star = entry->data;
849 break;
850 #ifdef TARGET_X86_64
851 case MSR_CSTAR:
852 env->cstar = entry->data;
853 break;
854 case MSR_KERNELGSBASE:
855 env->kernelgsbase = entry->data;
856 break;
857 case MSR_FMASK:
858 env->fmask = entry->data;
859 break;
860 case MSR_LSTAR:
861 env->lstar = entry->data;
862 break;
863 #endif
864 case MSR_IA32_TSC:
865 env->tsc = entry->data;
866 break;
867 case MSR_VM_HSAVE_PA:
868 env->vm_hsave = entry->data;
869 break;
870 default:
871 printf("Warning unknown msr index 0x%x\n", entry->index);
872 return 1;
873 }
874 return 0;
875 }
876
877 #ifdef TARGET_X86_64
878 #define MSR_COUNT 9
879 #else
880 #define MSR_COUNT 5
881 #endif
882
883 static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
884 {
885 lhs->selector = rhs->selector;
886 lhs->base = rhs->base;
887 lhs->limit = rhs->limit;
888 lhs->type = 3;
889 lhs->present = 1;
890 lhs->dpl = 3;
891 lhs->db = 0;
892 lhs->s = 1;
893 lhs->l = 0;
894 lhs->g = 0;
895 lhs->avl = 0;
896 lhs->unusable = 0;
897 }
898
899 static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
900 {
901 unsigned flags = rhs->flags;
902 lhs->selector = rhs->selector;
903 lhs->base = rhs->base;
904 lhs->limit = rhs->limit;
905 lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
906 lhs->present = (flags & DESC_P_MASK) != 0;
907 lhs->dpl = rhs->selector & 3;
908 lhs->db = (flags >> DESC_B_SHIFT) & 1;
909 lhs->s = (flags & DESC_S_MASK) != 0;
910 lhs->l = (flags >> DESC_L_SHIFT) & 1;
911 lhs->g = (flags & DESC_G_MASK) != 0;
912 lhs->avl = (flags & DESC_AVL_MASK) != 0;
913 lhs->unusable = 0;
914 }
915
916 static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
917 {
918 lhs->selector = rhs->selector;
919 lhs->base = rhs->base;
920 lhs->limit = rhs->limit;
921 lhs->flags =
922 (rhs->type << DESC_TYPE_SHIFT)
923 | (rhs->present * DESC_P_MASK)
924 | (rhs->dpl << DESC_DPL_SHIFT)
925 | (rhs->db << DESC_B_SHIFT)
926 | (rhs->s * DESC_S_MASK)
927 | (rhs->l << DESC_L_SHIFT)
928 | (rhs->g * DESC_G_MASK)
929 | (rhs->avl * DESC_AVL_MASK);
930 }
931
932 void kvm_arch_load_regs(CPUState *env)
933 {
934 struct kvm_regs regs;
935 struct kvm_fpu fpu;
936 struct kvm_sregs sregs;
937 struct kvm_msr_entry msrs[MSR_COUNT];
938 int rc, n, i;
939
940 regs.rax = env->regs[R_EAX];
941 regs.rbx = env->regs[R_EBX];
942 regs.rcx = env->regs[R_ECX];
943 regs.rdx = env->regs[R_EDX];
944 regs.rsi = env->regs[R_ESI];
945 regs.rdi = env->regs[R_EDI];
946 regs.rsp = env->regs[R_ESP];
947 regs.rbp = env->regs[R_EBP];
948 #ifdef TARGET_X86_64
949 regs.r8 = env->regs[8];
950 regs.r9 = env->regs[9];
951 regs.r10 = env->regs[10];
952 regs.r11 = env->regs[11];
953 regs.r12 = env->regs[12];
954 regs.r13 = env->regs[13];
955 regs.r14 = env->regs[14];
956 regs.r15 = env->regs[15];
957 #endif
958
959 regs.rflags = env->eflags;
960 regs.rip = env->eip;
961
962 kvm_set_regs(env->kvm_cpu_state.vcpu_ctx, &regs);
963
964 memset(&fpu, 0, sizeof fpu);
965 fpu.fsw = env->fpus & ~(7 << 11);
966 fpu.fsw |= (env->fpstt & 7) << 11;
967 fpu.fcw = env->fpuc;
968 for (i = 0; i < 8; ++i)
969 fpu.ftwx |= (!env->fptags[i]) << i;
970 memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
971 memcpy(fpu.xmm, env->xmm_regs, sizeof env->xmm_regs);
972 fpu.mxcsr = env->mxcsr;
973 kvm_set_fpu(env->kvm_cpu_state.vcpu_ctx, &fpu);
974
975 memcpy(sregs.interrupt_bitmap, env->interrupt_bitmap, sizeof(sregs.interrupt_bitmap));
976
977 if ((env->eflags & VM_MASK)) {
978 set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
979 set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
980 set_v8086_seg(&sregs.es, &env->segs[R_ES]);
981 set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
982 set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
983 set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
984 } else {
985 set_seg(&sregs.cs, &env->segs[R_CS]);
986 set_seg(&sregs.ds, &env->segs[R_DS]);
987 set_seg(&sregs.es, &env->segs[R_ES]);
988 set_seg(&sregs.fs, &env->segs[R_FS]);
989 set_seg(&sregs.gs, &env->segs[R_GS]);
990 set_seg(&sregs.ss, &env->segs[R_SS]);
991
992 if (env->cr[0] & CR0_PE_MASK) {
993 /* force ss cpl to cs cpl */
994 sregs.ss.selector = (sregs.ss.selector & ~3) |
995 (sregs.cs.selector & 3);
996 sregs.ss.dpl = sregs.ss.selector & 3;
997 }
998 }
999
1000 set_seg(&sregs.tr, &env->tr);
1001 set_seg(&sregs.ldt, &env->ldt);
1002
1003 sregs.idt.limit = env->idt.limit;
1004 sregs.idt.base = env->idt.base;
1005 sregs.gdt.limit = env->gdt.limit;
1006 sregs.gdt.base = env->gdt.base;
1007
1008 sregs.cr0 = env->cr[0];
1009 sregs.cr2 = env->cr[2];
1010 sregs.cr3 = env->cr[3];
1011 sregs.cr4 = env->cr[4];
1012
1013 sregs.cr8 = cpu_get_apic_tpr(env);
1014 sregs.apic_base = cpu_get_apic_base(env);
1015
1016 sregs.efer = env->efer;
1017
1018 kvm_set_sregs(env->kvm_cpu_state.vcpu_ctx, &sregs);
1019
1020 /* msrs */
1021 n = 0;
1022 set_msr_entry(&msrs[n++], MSR_IA32_SYSENTER_CS, env->sysenter_cs);
1023 set_msr_entry(&msrs[n++], MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
1024 set_msr_entry(&msrs[n++], MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
1025 if (kvm_has_msr_star)
1026 set_msr_entry(&msrs[n++], MSR_STAR, env->star);
1027 if (kvm_has_vm_hsave_pa)
1028 set_msr_entry(&msrs[n++], MSR_VM_HSAVE_PA, env->vm_hsave);
1029 #ifdef TARGET_X86_64
1030 if (lm_capable_kernel) {
1031 set_msr_entry(&msrs[n++], MSR_CSTAR, env->cstar);
1032 set_msr_entry(&msrs[n++], MSR_KERNELGSBASE, env->kernelgsbase);
1033 set_msr_entry(&msrs[n++], MSR_FMASK, env->fmask);
1034 set_msr_entry(&msrs[n++], MSR_LSTAR , env->lstar);
1035 }
1036 #endif
1037
1038 rc = kvm_set_msrs(env->kvm_cpu_state.vcpu_ctx, msrs, n);
1039 if (rc == -1)
1040 perror("kvm_set_msrs FAILED");
1041 }
1042
1043 void kvm_load_tsc(CPUState *env)
1044 {
1045 int rc;
1046 struct kvm_msr_entry msr;
1047
1048 set_msr_entry(&msr, MSR_IA32_TSC, env->tsc);
1049
1050 rc = kvm_set_msrs(env->kvm_cpu_state.vcpu_ctx, &msr, 1);
1051 if (rc == -1)
1052 perror("kvm_set_tsc FAILED.\n");
1053 }
1054
1055 void kvm_arch_save_mpstate(CPUState *env)
1056 {
1057 #ifdef KVM_CAP_MP_STATE
1058 int r;
1059 struct kvm_mp_state mp_state;
1060
1061 r = kvm_get_mpstate(env->kvm_cpu_state.vcpu_ctx, &mp_state);
1062 if (r < 0)
1063 env->mp_state = -1;
1064 else
1065 env->mp_state = mp_state.mp_state;
1066 #endif
1067 }
1068
1069 void kvm_arch_load_mpstate(CPUState *env)
1070 {
1071 #ifdef KVM_CAP_MP_STATE
1072 struct kvm_mp_state mp_state = { .mp_state = env->mp_state };
1073
1074 /*
1075 * -1 indicates that the host did not support GET_MP_STATE ioctl,
1076 * so don't touch it.
1077 */
1078 if (env->mp_state != -1)
1079 kvm_set_mpstate(env->kvm_cpu_state.vcpu_ctx, &mp_state);
1080 #endif
1081 }
1082
1083 void kvm_arch_save_regs(CPUState *env)
1084 {
1085 struct kvm_regs regs;
1086 struct kvm_fpu fpu;
1087 struct kvm_sregs sregs;
1088 struct kvm_msr_entry msrs[MSR_COUNT];
1089 uint32_t hflags;
1090 uint32_t i, n, rc;
1091
1092 kvm_get_regs(env->kvm_cpu_state.vcpu_ctx, &regs);
1093
1094 env->regs[R_EAX] = regs.rax;
1095 env->regs[R_EBX] = regs.rbx;
1096 env->regs[R_ECX] = regs.rcx;
1097 env->regs[R_EDX] = regs.rdx;
1098 env->regs[R_ESI] = regs.rsi;
1099 env->regs[R_EDI] = regs.rdi;
1100 env->regs[R_ESP] = regs.rsp;
1101 env->regs[R_EBP] = regs.rbp;
1102 #ifdef TARGET_X86_64
1103 env->regs[8] = regs.r8;
1104 env->regs[9] = regs.r9;
1105 env->regs[10] = regs.r10;
1106 env->regs[11] = regs.r11;
1107 env->regs[12] = regs.r12;
1108 env->regs[13] = regs.r13;
1109 env->regs[14] = regs.r14;
1110 env->regs[15] = regs.r15;
1111 #endif
1112
1113 env->eflags = regs.rflags;
1114 env->eip = regs.rip;
1115
1116 kvm_get_fpu(env->kvm_cpu_state.vcpu_ctx, &fpu);
1117 env->fpstt = (fpu.fsw >> 11) & 7;
1118 env->fpus = fpu.fsw;
1119 env->fpuc = fpu.fcw;
1120 for (i = 0; i < 8; ++i)
1121 env->fptags[i] = !((fpu.ftwx >> i) & 1);
1122 memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
1123 memcpy(env->xmm_regs, fpu.xmm, sizeof env->xmm_regs);
1124 env->mxcsr = fpu.mxcsr;
1125
1126 kvm_get_sregs(env->kvm_cpu_state.vcpu_ctx, &sregs);
1127
1128 memcpy(env->interrupt_bitmap, sregs.interrupt_bitmap, sizeof(env->interrupt_bitmap));
1129
1130 get_seg(&env->segs[R_CS], &sregs.cs);
1131 get_seg(&env->segs[R_DS], &sregs.ds);
1132 get_seg(&env->segs[R_ES], &sregs.es);
1133 get_seg(&env->segs[R_FS], &sregs.fs);
1134 get_seg(&env->segs[R_GS], &sregs.gs);
1135 get_seg(&env->segs[R_SS], &sregs.ss);
1136
1137 get_seg(&env->tr, &sregs.tr);
1138 get_seg(&env->ldt, &sregs.ldt);
1139
1140 env->idt.limit = sregs.idt.limit;
1141 env->idt.base = sregs.idt.base;
1142 env->gdt.limit = sregs.gdt.limit;
1143 env->gdt.base = sregs.gdt.base;
1144
1145 env->cr[0] = sregs.cr0;
1146 env->cr[2] = sregs.cr2;
1147 env->cr[3] = sregs.cr3;
1148 env->cr[4] = sregs.cr4;
1149
1150 cpu_set_apic_base(env, sregs.apic_base);
1151
1152 env->efer = sregs.efer;
1153 //cpu_set_apic_tpr(env, sregs.cr8);
1154
1155 #define HFLAG_COPY_MASK ~( \
1156 HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
1157 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
1158 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
1159 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
1160
1161
1162
1163 hflags = (env->segs[R_CS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
1164 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
1165 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
1166 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
1167 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
1168 hflags |= (env->cr[4] & CR4_OSFXSR_MASK) <<
1169 (HF_OSFXSR_SHIFT - CR4_OSFXSR_SHIFT);
1170
1171 if (env->efer & MSR_EFER_LMA) {
1172 hflags |= HF_LMA_MASK;
1173 }
1174
1175 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
1176 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
1177 } else {
1178 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
1179 (DESC_B_SHIFT - HF_CS32_SHIFT);
1180 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
1181 (DESC_B_SHIFT - HF_SS32_SHIFT);
1182 if (!(env->cr[0] & CR0_PE_MASK) ||
1183 (env->eflags & VM_MASK) ||
1184 !(hflags & HF_CS32_MASK)) {
1185 hflags |= HF_ADDSEG_MASK;
1186 } else {
1187 hflags |= ((env->segs[R_DS].base |
1188 env->segs[R_ES].base |
1189 env->segs[R_SS].base) != 0) <<
1190 HF_ADDSEG_SHIFT;
1191 }
1192 }
1193 env->hflags = (env->hflags & HFLAG_COPY_MASK) | hflags;
1194
1195 /* msrs */
1196 n = 0;
1197 msrs[n++].index = MSR_IA32_SYSENTER_CS;
1198 msrs[n++].index = MSR_IA32_SYSENTER_ESP;
1199 msrs[n++].index = MSR_IA32_SYSENTER_EIP;
1200 if (kvm_has_msr_star)
1201 msrs[n++].index = MSR_STAR;
1202 msrs[n++].index = MSR_IA32_TSC;
1203 if (kvm_has_vm_hsave_pa)
1204 msrs[n++].index = MSR_VM_HSAVE_PA;
1205 #ifdef TARGET_X86_64
1206 if (lm_capable_kernel) {
1207 msrs[n++].index = MSR_CSTAR;
1208 msrs[n++].index = MSR_KERNELGSBASE;
1209 msrs[n++].index = MSR_FMASK;
1210 msrs[n++].index = MSR_LSTAR;
1211 }
1212 #endif
1213 rc = kvm_get_msrs(env->kvm_cpu_state.vcpu_ctx, msrs, n);
1214 if (rc == -1) {
1215 perror("kvm_get_msrs FAILED");
1216 }
1217 else {
1218 n = rc; /* actual number of MSRs */
1219 for (i=0 ; i<n; i++) {
1220 if (get_msr_entry(&msrs[i], env))
1221 return;
1222 }
1223 }
1224 }
1225
1226 static void do_cpuid_ent(struct kvm_cpuid_entry2 *e, uint32_t function,
1227 uint32_t count, CPUState *env)
1228 {
1229 env->regs[R_EAX] = function;
1230 env->regs[R_ECX] = count;
1231 qemu_kvm_cpuid_on_env(env);
1232 e->function = function;
1233 e->flags = 0;
1234 e->index = 0;
1235 e->eax = env->regs[R_EAX];
1236 e->ebx = env->regs[R_EBX];
1237 e->ecx = env->regs[R_ECX];
1238 e->edx = env->regs[R_EDX];
1239 }
1240
1241 struct kvm_para_features {
1242 int cap;
1243 int feature;
1244 } para_features[] = {
1245 #ifdef KVM_CAP_CLOCKSOURCE
1246 { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
1247 #endif
1248 #ifdef KVM_CAP_NOP_IO_DELAY
1249 { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
1250 #endif
1251 #ifdef KVM_CAP_PV_MMU
1252 { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
1253 #endif
1254 #ifdef KVM_CAP_CR3_CACHE
1255 { KVM_CAP_CR3_CACHE, KVM_FEATURE_CR3_CACHE },
1256 #endif
1257 { -1, -1 }
1258 };
1259
1260 static int get_para_features(kvm_context_t kvm_context)
1261 {
1262 int i, features = 0;
1263
1264 for (i = 0; i < ARRAY_SIZE(para_features)-1; i++) {
1265 if (kvm_check_extension(kvm_context, para_features[i].cap))
1266 features |= (1 << para_features[i].feature);
1267 }
1268
1269 return features;
1270 }
1271
1272 static void kvm_trim_features(uint32_t *features, uint32_t supported)
1273 {
1274 int i;
1275 uint32_t mask;
1276
1277 for (i = 0; i < 32; ++i) {
1278 mask = 1U << i;
1279 if ((*features & mask) && !(supported & mask)) {
1280 *features &= ~mask;
1281 }
1282 }
1283 }
1284
1285 int kvm_arch_qemu_init_env(CPUState *cenv)
1286 {
1287 struct kvm_cpuid_entry2 cpuid_ent[100];
1288 #ifdef KVM_CPUID_SIGNATURE
1289 struct kvm_cpuid_entry2 *pv_ent;
1290 uint32_t signature[3];
1291 #endif
1292 int cpuid_nent = 0;
1293 CPUState copy;
1294 uint32_t i, j, limit;
1295
1296 qemu_kvm_load_lapic(cenv);
1297
1298
1299 #ifdef KVM_CPUID_SIGNATURE
1300 /* Paravirtualization CPUIDs */
1301 memcpy(signature, "KVMKVMKVM\0\0\0", 12);
1302 pv_ent = &cpuid_ent[cpuid_nent++];
1303 memset(pv_ent, 0, sizeof(*pv_ent));
1304 pv_ent->function = KVM_CPUID_SIGNATURE;
1305 pv_ent->eax = 0;
1306 pv_ent->ebx = signature[0];
1307 pv_ent->ecx = signature[1];
1308 pv_ent->edx = signature[2];
1309
1310 pv_ent = &cpuid_ent[cpuid_nent++];
1311 memset(pv_ent, 0, sizeof(*pv_ent));
1312 pv_ent->function = KVM_CPUID_FEATURES;
1313 pv_ent->eax = get_para_features(kvm_context);
1314 #endif
1315
1316 kvm_trim_features(&cenv->cpuid_features,
1317 kvm_arch_get_supported_cpuid(cenv, 1, R_EDX));
1318
1319 /* prevent the hypervisor bit from being cleared by the kernel */
1320 i = cenv->cpuid_ext_features & CPUID_EXT_HYPERVISOR;
1321 kvm_trim_features(&cenv->cpuid_ext_features,
1322 kvm_arch_get_supported_cpuid(cenv, 1, R_ECX));
1323 cenv->cpuid_ext_features |= i;
1324
1325 kvm_trim_features(&cenv->cpuid_ext2_features,
1326 kvm_arch_get_supported_cpuid(cenv, 0x80000001, R_EDX));
1327 kvm_trim_features(&cenv->cpuid_ext3_features,
1328 kvm_arch_get_supported_cpuid(cenv, 0x80000001, R_ECX));
1329
1330 copy = *cenv;
1331
1332 copy.regs[R_EAX] = 0;
1333 qemu_kvm_cpuid_on_env(&copy);
1334 limit = copy.regs[R_EAX];
1335
1336 for (i = 0; i <= limit; ++i) {
1337 if (i == 4 || i == 0xb || i == 0xd) {
1338 for (j = 0; ; ++j) {
1339 do_cpuid_ent(&cpuid_ent[cpuid_nent], i, j, &copy);
1340
1341 cpuid_ent[cpuid_nent].flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1342 cpuid_ent[cpuid_nent].index = j;
1343
1344 cpuid_nent++;
1345
1346 if (i == 4 && copy.regs[R_EAX] == 0)
1347 break;
1348 if (i == 0xb && !(copy.regs[R_ECX] & 0xff00))
1349 break;
1350 if (i == 0xd && copy.regs[R_EAX] == 0)
1351 break;
1352 }
1353 } else
1354 do_cpuid_ent(&cpuid_ent[cpuid_nent++], i, 0, &copy);
1355 }
1356
1357 copy.regs[R_EAX] = 0x80000000;
1358 qemu_kvm_cpuid_on_env(&copy);
1359 limit = copy.regs[R_EAX];
1360
1361 for (i = 0x80000000; i <= limit; ++i)
1362 do_cpuid_ent(&cpuid_ent[cpuid_nent++], i, 0, &copy);
1363
1364 kvm_setup_cpuid2(cenv->kvm_cpu_state.vcpu_ctx, cpuid_nent, cpuid_ent);
1365
1366 #ifdef KVM_CAP_MCE
1367 if (((cenv->cpuid_version >> 8)&0xF) >= 6
1368 && (cenv->cpuid_features&(CPUID_MCE|CPUID_MCA)) == (CPUID_MCE|CPUID_MCA)
1369 && kvm_check_extension(kvm_context, KVM_CAP_MCE) > 0) {
1370 uint64_t mcg_cap;
1371 int banks;
1372
1373 if (kvm_get_mce_cap_supported(kvm_context, &mcg_cap, &banks))
1374 perror("kvm_get_mce_cap_supported FAILED");
1375 else {
1376 if (banks > MCE_BANKS_DEF)
1377 banks = MCE_BANKS_DEF;
1378 mcg_cap &= MCE_CAP_DEF;
1379 mcg_cap |= banks;
1380 if (kvm_setup_mce(cenv->kvm_cpu_state.vcpu_ctx, &mcg_cap))
1381 perror("kvm_setup_mce FAILED");
1382 else
1383 cenv->mcg_cap = mcg_cap;
1384 }
1385 }
1386 #endif
1387
1388 return 0;
1389 }
1390
1391 int kvm_arch_halt(void *opaque, kvm_vcpu_context_t vcpu)
1392 {
1393 CPUState *env = cpu_single_env;
1394
1395 if (!((env->interrupt_request & CPU_INTERRUPT_HARD) &&
1396 (env->eflags & IF_MASK)) &&
1397 !(env->interrupt_request & CPU_INTERRUPT_NMI)) {
1398 env->halted = 1;
1399 }
1400 return 1;
1401 }
1402
1403 void kvm_arch_pre_kvm_run(void *opaque, CPUState *env)
1404 {
1405 if (!kvm_irqchip_in_kernel(kvm_context))
1406 kvm_set_cr8(env->kvm_cpu_state.vcpu_ctx, cpu_get_apic_tpr(env));
1407 }
1408
1409 void kvm_arch_post_kvm_run(void *opaque, CPUState *env)
1410 {
1411 cpu_single_env = env;
1412
1413 env->eflags = kvm_get_interrupt_flag(env->kvm_cpu_state.vcpu_ctx)
1414 ? env->eflags | IF_MASK : env->eflags & ~IF_MASK;
1415
1416 cpu_set_apic_tpr(env, kvm_get_cr8(env->kvm_cpu_state.vcpu_ctx));
1417 cpu_set_apic_base(env, kvm_get_apic_base(env->kvm_cpu_state.vcpu_ctx));
1418 }
1419
1420 int kvm_arch_has_work(CPUState *env)
1421 {
1422 if (((env->interrupt_request & CPU_INTERRUPT_HARD) &&
1423 (env->eflags & IF_MASK)) ||
1424 (env->interrupt_request & CPU_INTERRUPT_NMI))
1425 return 1;
1426 return 0;
1427 }
1428
1429 int kvm_arch_try_push_interrupts(void *opaque)
1430 {
1431 CPUState *env = cpu_single_env;
1432 int r, irq;
1433
1434 if (kvm_is_ready_for_interrupt_injection(env->kvm_cpu_state.vcpu_ctx) &&
1435 (env->interrupt_request & CPU_INTERRUPT_HARD) &&
1436 (env->eflags & IF_MASK)) {
1437 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
1438 irq = cpu_get_pic_interrupt(env);
1439 if (irq >= 0) {
1440 r = kvm_inject_irq(env->kvm_cpu_state.vcpu_ctx, irq);
1441 if (r < 0)
1442 printf("cpu %d fail inject %x\n", env->cpu_index, irq);
1443 }
1444 }
1445
1446 return (env->interrupt_request & CPU_INTERRUPT_HARD) != 0;
1447 }
1448
1449 #ifdef KVM_CAP_USER_NMI
1450 void kvm_arch_push_nmi(void *opaque)
1451 {
1452 CPUState *env = cpu_single_env;
1453 int r;
1454
1455 if (likely(!(env->interrupt_request & CPU_INTERRUPT_NMI)))
1456 return;
1457
1458 env->interrupt_request &= ~CPU_INTERRUPT_NMI;
1459 r = kvm_inject_nmi(env->kvm_cpu_state.vcpu_ctx);
1460 if (r < 0)
1461 printf("cpu %d fail inject NMI\n", env->cpu_index);
1462 }
1463 #endif /* KVM_CAP_USER_NMI */
1464
1465 void kvm_arch_update_regs_for_sipi(CPUState *env)
1466 {
1467 SegmentCache cs = env->segs[R_CS];
1468
1469 kvm_arch_save_regs(env);
1470 env->segs[R_CS] = cs;
1471 env->eip = 0;
1472 kvm_arch_load_regs(env);
1473 }
1474
1475 void kvm_arch_cpu_reset(CPUState *env)
1476 {
1477 kvm_arch_load_regs(env);
1478 if (!cpu_is_bsp(env)) {
1479 if (kvm_irqchip_in_kernel(kvm_context)) {
1480 #ifdef KVM_CAP_MP_STATE
1481 kvm_reset_mpstate(env->kvm_cpu_state.vcpu_ctx);
1482 #endif
1483 } else {
1484 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
1485 env->halted = 1;
1486 }
1487 }
1488 }
1489
1490 int kvm_arch_insert_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp)
1491 {
1492 uint8_t int3 = 0xcc;
1493
1494 if (cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
1495 cpu_memory_rw_debug(env, bp->pc, &int3, 1, 1))
1496 return -EINVAL;
1497 return 0;
1498 }
1499
1500 int kvm_arch_remove_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp)
1501 {
1502 uint8_t int3;
1503
1504 if (cpu_memory_rw_debug(env, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
1505 cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1))
1506 return -EINVAL;
1507 return 0;
1508 }
1509
1510 #ifdef KVM_CAP_SET_GUEST_DEBUG
1511 static struct {
1512 target_ulong addr;
1513 int len;
1514 int type;
1515 } hw_breakpoint[4];
1516
1517 static int nb_hw_breakpoint;
1518
1519 static int find_hw_breakpoint(target_ulong addr, int len, int type)
1520 {
1521 int n;
1522
1523 for (n = 0; n < nb_hw_breakpoint; n++)
1524 if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
1525 (hw_breakpoint[n].len == len || len == -1))
1526 return n;
1527 return -1;
1528 }
1529
1530 int kvm_arch_insert_hw_breakpoint(target_ulong addr,
1531 target_ulong len, int type)
1532 {
1533 switch (type) {
1534 case GDB_BREAKPOINT_HW:
1535 len = 1;
1536 break;
1537 case GDB_WATCHPOINT_WRITE:
1538 case GDB_WATCHPOINT_ACCESS:
1539 switch (len) {
1540 case 1:
1541 break;
1542 case 2:
1543 case 4:
1544 case 8:
1545 if (addr & (len - 1))
1546 return -EINVAL;
1547 break;
1548 default:
1549 return -EINVAL;
1550 }
1551 break;
1552 default:
1553 return -ENOSYS;
1554 }
1555
1556 if (nb_hw_breakpoint == 4)
1557 return -ENOBUFS;
1558
1559 if (find_hw_breakpoint(addr, len, type) >= 0)
1560 return -EEXIST;
1561
1562 hw_breakpoint[nb_hw_breakpoint].addr = addr;
1563 hw_breakpoint[nb_hw_breakpoint].len = len;
1564 hw_breakpoint[nb_hw_breakpoint].type = type;
1565 nb_hw_breakpoint++;
1566
1567 return 0;
1568 }
1569
1570 int kvm_arch_remove_hw_breakpoint(target_ulong addr,
1571 target_ulong len, int type)
1572 {
1573 int n;
1574
1575 n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
1576 if (n < 0)
1577 return -ENOENT;
1578
1579 nb_hw_breakpoint--;
1580 hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
1581
1582 return 0;
1583 }
1584
1585 void kvm_arch_remove_all_hw_breakpoints(void)
1586 {
1587 nb_hw_breakpoint = 0;
1588 }
1589
1590 static CPUWatchpoint hw_watchpoint;
1591
1592 int kvm_arch_debug(struct kvm_debug_exit_arch *arch_info)
1593 {
1594 int handle = 0;
1595 int n;
1596
1597 if (arch_info->exception == 1) {
1598 if (arch_info->dr6 & (1 << 14)) {
1599 if (cpu_single_env->singlestep_enabled)
1600 handle = 1;
1601 } else {
1602 for (n = 0; n < 4; n++)
1603 if (arch_info->dr6 & (1 << n))
1604 switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
1605 case 0x0:
1606 handle = 1;
1607 break;
1608 case 0x1:
1609 handle = 1;
1610 cpu_single_env->watchpoint_hit = &hw_watchpoint;
1611 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
1612 hw_watchpoint.flags = BP_MEM_WRITE;
1613 break;
1614 case 0x3:
1615 handle = 1;
1616 cpu_single_env->watchpoint_hit = &hw_watchpoint;
1617 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
1618 hw_watchpoint.flags = BP_MEM_ACCESS;
1619 break;
1620 }
1621 }
1622 } else if (kvm_find_sw_breakpoint(cpu_single_env, arch_info->pc))
1623 handle = 1;
1624
1625 if (!handle)
1626 kvm_update_guest_debug(cpu_single_env,
1627 (arch_info->exception == 1) ?
1628 KVM_GUESTDBG_INJECT_DB : KVM_GUESTDBG_INJECT_BP);
1629
1630 return handle;
1631 }
1632
1633 void kvm_arch_update_guest_debug(CPUState *env, struct kvm_guest_debug *dbg)
1634 {
1635 const uint8_t type_code[] = {
1636 [GDB_BREAKPOINT_HW] = 0x0,
1637 [GDB_WATCHPOINT_WRITE] = 0x1,
1638 [GDB_WATCHPOINT_ACCESS] = 0x3
1639 };
1640 const uint8_t len_code[] = {
1641 [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
1642 };
1643 int n;
1644
1645 if (kvm_sw_breakpoints_active(env))
1646 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
1647
1648 if (nb_hw_breakpoint > 0) {
1649 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
1650 dbg->arch.debugreg[7] = 0x0600;
1651 for (n = 0; n < nb_hw_breakpoint; n++) {
1652 dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
1653 dbg->arch.debugreg[7] |= (2 << (n * 2)) |
1654 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
1655 (len_code[hw_breakpoint[n].len] << (18 + n*4));
1656 }
1657 }
1658 }
1659 #endif
1660
1661 void kvm_arch_do_ioperm(void *_data)
1662 {
1663 struct ioperm_data *data = _data;
1664 ioperm(data->start_port, data->num, data->turn_on);
1665 }
1666
1667 /*
1668 * Setup x86 specific IRQ routing
1669 */
1670 int kvm_arch_init_irq_routing(void)
1671 {
1672 int i, r;
1673
1674 if (kvm_irqchip && kvm_has_gsi_routing(kvm_context)) {
1675 kvm_clear_gsi_routes(kvm_context);
1676 for (i = 0; i < 8; ++i) {
1677 if (i == 2)
1678 continue;
1679 r = kvm_add_irq_route(kvm_context, i, KVM_IRQCHIP_PIC_MASTER, i);
1680 if (r < 0)
1681 return r;
1682 }
1683 for (i = 8; i < 16; ++i) {
1684 r = kvm_add_irq_route(kvm_context, i, KVM_IRQCHIP_PIC_SLAVE, i - 8);
1685 if (r < 0)
1686 return r;
1687 }
1688 for (i = 0; i < 24; ++i) {
1689 if (i == 0) {
1690 r = kvm_add_irq_route(kvm_context, i, KVM_IRQCHIP_IOAPIC, 2);
1691 } else if (i != 2) {
1692 r = kvm_add_irq_route(kvm_context, i, KVM_IRQCHIP_IOAPIC, i);
1693 }
1694 if (r < 0)
1695 return r;
1696 }
1697 kvm_commit_irq_routes(kvm_context);
1698 }
1699 return 0;
1700 }
1701
1702 uint32_t kvm_arch_get_supported_cpuid(CPUState *env, uint32_t function,
1703 int reg)
1704 {
1705 return kvm_get_supported_cpuid(kvm_context, function, reg);
1706 }
1707
1708 void kvm_arch_process_irqchip_events(CPUState *env)
1709 {
1710 kvm_arch_save_regs(env);
1711 if (env->interrupt_request & CPU_INTERRUPT_INIT)
1712 do_cpu_init(env);
1713 if (env->interrupt_request & CPU_INTERRUPT_SIPI)
1714 do_cpu_sipi(env);
1715 kvm_arch_load_regs(env);
1716 }
Patches shipped by Fedora