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Sparc32: convert cs4231 to qdev
[qemu-kvm/fedora.git] / hw / sun4m.c
blob5d23f31ac218c3e9be36f8fe2ffa39a9b81c9872
1 /*
2 * QEMU Sun4m & Sun4d & Sun4c System Emulator
3 *
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "sysbus.h"
25 #include "qemu-timer.h"
26 #include "sun4m.h"
27 #include "nvram.h"
28 #include "sparc32_dma.h"
29 #include "fdc.h"
30 #include "sysemu.h"
31 #include "net.h"
32 #include "boards.h"
33 #include "firmware_abi.h"
34 #include "scsi.h"
35 #include "pc.h"
36 #include "isa.h"
37 #include "fw_cfg.h"
38 #include "escc.h"
39
40 //#define DEBUG_IRQ
41
42 /*
43 * Sun4m architecture was used in the following machines:
44 *
45 * SPARCserver 6xxMP/xx
46 * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15),
47 * SPARCclassic X (4/10)
48 * SPARCstation LX/ZX (4/30)
49 * SPARCstation Voyager
50 * SPARCstation 10/xx, SPARCserver 10/xx
51 * SPARCstation 5, SPARCserver 5
52 * SPARCstation 20/xx, SPARCserver 20
53 * SPARCstation 4
54 *
55 * Sun4d architecture was used in the following machines:
56 *
57 * SPARCcenter 2000
58 * SPARCserver 1000
59 *
60 * Sun4c architecture was used in the following machines:
61 * SPARCstation 1/1+, SPARCserver 1/1+
62 * SPARCstation SLC
63 * SPARCstation IPC
64 * SPARCstation ELC
65 * SPARCstation IPX
66 *
67 * See for example: http://www.sunhelp.org/faq/sunref1.html
68 */
69
70 #ifdef DEBUG_IRQ
71 #define DPRINTF(fmt, ...) \
72 do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0)
73 #else
74 #define DPRINTF(fmt, ...)
75 #endif
76
77 #define KERNEL_LOAD_ADDR 0x00004000
78 #define CMDLINE_ADDR 0x007ff000
79 #define INITRD_LOAD_ADDR 0x00800000
80 #define PROM_SIZE_MAX (1024 * 1024)
81 #define PROM_VADDR 0xffd00000
82 #define PROM_FILENAME "openbios-sparc32"
83 #define CFG_ADDR 0xd00000510ULL
84 #define FW_CFG_SUN4M_DEPTH (FW_CFG_ARCH_LOCAL + 0x00)
85
86 #define MAX_CPUS 16
87 #define MAX_PILS 16
88
89 #define ESCC_CLOCK 4915200
90
91 struct sun4m_hwdef {
92 target_phys_addr_t iommu_base, slavio_base;
93 target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base;
94 target_phys_addr_t serial_base, fd_base;
95 target_phys_addr_t idreg_base, dma_base, esp_base, le_base;
96 target_phys_addr_t tcx_base, cs_base, apc_base, aux1_base, aux2_base;
97 target_phys_addr_t ecc_base;
98 uint32_t ecc_version;
99 long vram_size, nvram_size;
100 // IRQ numbers are not PIL ones, but master interrupt controller
101 // register bit numbers
102 int esp_irq, le_irq, clock_irq, clock1_irq;
103 int ser_irq, ms_kb_irq, fd_irq, me_irq, cs_irq, ecc_irq;
104 uint8_t nvram_machine_id;
105 uint16_t machine_id;
106 uint32_t iommu_version;
107 uint32_t intbit_to_level[32];
108 uint64_t max_mem;
109 const char * const default_cpu_model;
110 };
111
112 #define MAX_IOUNITS 5
113
114 struct sun4d_hwdef {
115 target_phys_addr_t iounit_bases[MAX_IOUNITS], slavio_base;
116 target_phys_addr_t counter_base, nvram_base, ms_kb_base;
117 target_phys_addr_t serial_base;
118 target_phys_addr_t espdma_base, esp_base;
119 target_phys_addr_t ledma_base, le_base;
120 target_phys_addr_t tcx_base;
121 target_phys_addr_t sbi_base;
122 unsigned long vram_size, nvram_size;
123 // IRQ numbers are not PIL ones, but SBI register bit numbers
124 int esp_irq, le_irq, clock_irq, clock1_irq;
125 int ser_irq, ms_kb_irq, me_irq;
126 uint8_t nvram_machine_id;
127 uint16_t machine_id;
128 uint32_t iounit_version;
129 uint64_t max_mem;
130 const char * const default_cpu_model;
131 };
132
133 struct sun4c_hwdef {
134 target_phys_addr_t iommu_base, slavio_base;
135 target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base;
136 target_phys_addr_t serial_base, fd_base;
137 target_phys_addr_t idreg_base, dma_base, esp_base, le_base;
138 target_phys_addr_t tcx_base, aux1_base;
139 long vram_size, nvram_size;
140 // IRQ numbers are not PIL ones, but master interrupt controller
141 // register bit numbers
142 int esp_irq, le_irq, clock_irq, clock1_irq;
143 int ser_irq, ms_kb_irq, fd_irq, me_irq;
144 uint8_t nvram_machine_id;
145 uint16_t machine_id;
146 uint32_t iommu_version;
147 uint32_t intbit_to_level[32];
148 uint64_t max_mem;
149 const char * const default_cpu_model;
150 };
151
152 int DMA_get_channel_mode (int nchan)
153 {
154 return 0;
155 }
156 int DMA_read_memory (int nchan, void *buf, int pos, int size)
157 {
158 return 0;
159 }
160 int DMA_write_memory (int nchan, void *buf, int pos, int size)
161 {
162 return 0;
163 }
164 void DMA_hold_DREQ (int nchan) {}
165 void DMA_release_DREQ (int nchan) {}
166 void DMA_schedule(int nchan) {}
167 void DMA_init (int high_page_enable) {}
168 void DMA_register_channel (int nchan,
169 DMA_transfer_handler transfer_handler,
170 void *opaque)
171 {
172 }
173
174 static int fw_cfg_boot_set(void *opaque, const char *boot_device)
175 {
176 fw_cfg_add_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
177 return 0;
178 }
179
180 static void nvram_init(m48t59_t *nvram, uint8_t *macaddr, const char *cmdline,
181 const char *boot_devices, ram_addr_t RAM_size,
182 uint32_t kernel_size,
183 int width, int height, int depth,
184 int nvram_machine_id, const char *arch)
185 {
186 unsigned int i;
187 uint32_t start, end;
188 uint8_t image[0x1ff0];
189 struct OpenBIOS_nvpart_v1 *part_header;
190
191 memset(image, '\0', sizeof(image));
192
193 start = 0;
194
195 // OpenBIOS nvram variables
196 // Variable partition
197 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
198 part_header->signature = OPENBIOS_PART_SYSTEM;
199 pstrcpy(part_header->name, sizeof(part_header->name), "system");
200
201 end = start + sizeof(struct OpenBIOS_nvpart_v1);
202 for (i = 0; i < nb_prom_envs; i++)
203 end = OpenBIOS_set_var(image, end, prom_envs[i]);
204
205 // End marker
206 image[end++] = '\0';
207
208 end = start + ((end - start + 15) & ~15);
209 OpenBIOS_finish_partition(part_header, end - start);
210
211 // free partition
212 start = end;
213 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
214 part_header->signature = OPENBIOS_PART_FREE;
215 pstrcpy(part_header->name, sizeof(part_header->name), "free");
216
217 end = 0x1fd0;
218 OpenBIOS_finish_partition(part_header, end - start);
219
220 Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr,
221 nvram_machine_id);
222
223 for (i = 0; i < sizeof(image); i++)
224 m48t59_write(nvram, i, image[i]);
225 }
226
227 static void *slavio_intctl;
228
229 void pic_info(Monitor *mon)
230 {
231 if (slavio_intctl)
232 slavio_pic_info(mon, slavio_intctl);
233 }
234
235 void irq_info(Monitor *mon)
236 {
237 if (slavio_intctl)
238 slavio_irq_info(mon, slavio_intctl);
239 }
240
241 void cpu_check_irqs(CPUState *env)
242 {
243 if (env->pil_in && (env->interrupt_index == 0 ||
244 (env->interrupt_index & ~15) == TT_EXTINT)) {
245 unsigned int i;
246
247 for (i = 15; i > 0; i--) {
248 if (env->pil_in & (1 << i)) {
249 int old_interrupt = env->interrupt_index;
250
251 env->interrupt_index = TT_EXTINT | i;
252 if (old_interrupt != env->interrupt_index) {
253 DPRINTF("Set CPU IRQ %d\n", i);
254 cpu_interrupt(env, CPU_INTERRUPT_HARD);
255 }
256 break;
257 }
258 }
259 } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) {
260 DPRINTF("Reset CPU IRQ %d\n", env->interrupt_index & 15);
261 env->interrupt_index = 0;
262 cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
263 }
264 }
265
266 static void cpu_set_irq(void *opaque, int irq, int level)
267 {
268 CPUState *env = opaque;
269
270 if (level) {
271 DPRINTF("Raise CPU IRQ %d\n", irq);
272 env->halted = 0;
273 env->pil_in |= 1 << irq;
274 cpu_check_irqs(env);
275 } else {
276 DPRINTF("Lower CPU IRQ %d\n", irq);
277 env->pil_in &= ~(1 << irq);
278 cpu_check_irqs(env);
279 }
280 }
281
282 static void dummy_cpu_set_irq(void *opaque, int irq, int level)
283 {
284 }
285
286 static void *slavio_misc;
287
288 void qemu_system_powerdown(void)
289 {
290 slavio_set_power_fail(slavio_misc, 1);
291 }
292
293 static void main_cpu_reset(void *opaque)
294 {
295 CPUState *env = opaque;
296
297 cpu_reset(env);
298 env->halted = 0;
299 }
300
301 static void secondary_cpu_reset(void *opaque)
302 {
303 CPUState *env = opaque;
304
305 cpu_reset(env);
306 env->halted = 1;
307 }
308
309 static void cpu_halt_signal(void *opaque, int irq, int level)
310 {
311 if (level && cpu_single_env)
312 cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HALT);
313 }
314
315 static unsigned long sun4m_load_kernel(const char *kernel_filename,
316 const char *initrd_filename,
317 ram_addr_t RAM_size)
318 {
319 int linux_boot;
320 unsigned int i;
321 long initrd_size, kernel_size;
322
323 linux_boot = (kernel_filename != NULL);
324
325 kernel_size = 0;
326 if (linux_boot) {
327 kernel_size = load_elf(kernel_filename, -0xf0000000ULL, NULL, NULL,
328 NULL);
329 if (kernel_size < 0)
330 kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR,
331 RAM_size - KERNEL_LOAD_ADDR);
332 if (kernel_size < 0)
333 kernel_size = load_image_targphys(kernel_filename,
334 KERNEL_LOAD_ADDR,
335 RAM_size - KERNEL_LOAD_ADDR);
336 if (kernel_size < 0) {
337 fprintf(stderr, "qemu: could not load kernel '%s'\n",
338 kernel_filename);
339 exit(1);
340 }
341
342 /* load initrd */
343 initrd_size = 0;
344 if (initrd_filename) {
345 initrd_size = load_image_targphys(initrd_filename,
346 INITRD_LOAD_ADDR,
347 RAM_size - INITRD_LOAD_ADDR);
348 if (initrd_size < 0) {
349 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
350 initrd_filename);
351 exit(1);
352 }
353 }
354 if (initrd_size > 0) {
355 for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
356 if (ldl_phys(KERNEL_LOAD_ADDR + i) == 0x48647253) { // HdrS
357 stl_phys(KERNEL_LOAD_ADDR + i + 16, INITRD_LOAD_ADDR);
358 stl_phys(KERNEL_LOAD_ADDR + i + 20, initrd_size);
359 break;
360 }
361 }
362 }
363 }
364 return kernel_size;
365 }
366
367 static void lance_init(NICInfo *nd, target_phys_addr_t leaddr,
368 void *dma_opaque, qemu_irq irq, qemu_irq *reset)
369 {
370 DeviceState *dev;
371 SysBusDevice *s;
372
373 qemu_check_nic_model(&nd_table[0], "lance");
374
375 dev = qdev_create(NULL, "lance");
376 qdev_set_netdev(dev, nd);
377 qdev_set_prop_ptr(dev, "dma", dma_opaque);
378 qdev_init(dev);
379 s = sysbus_from_qdev(dev);
380 sysbus_mmio_map(s, 0, leaddr);
381 sysbus_connect_irq(s, 0, irq);
382 *reset = qdev_get_gpio_in(dev, 0);
383 }
384
385 /* NCR89C100/MACIO Internal ID register */
386 static const uint8_t idreg_data[] = { 0xfe, 0x81, 0x01, 0x03 };
387
388 static void idreg_init(target_phys_addr_t addr)
389 {
390 DeviceState *dev;
391 SysBusDevice *s;
392
393 dev = qdev_create(NULL, "macio_idreg");
394 qdev_init(dev);
395 s = sysbus_from_qdev(dev);
396
397 sysbus_mmio_map(s, 0, addr);
398 cpu_physical_memory_write_rom(addr, idreg_data, sizeof(idreg_data));
399 }
400
401 static void idreg_init1(SysBusDevice *dev)
402 {
403 ram_addr_t idreg_offset;
404
405 idreg_offset = qemu_ram_alloc(sizeof(idreg_data));
406 sysbus_init_mmio(dev, sizeof(idreg_data), idreg_offset | IO_MEM_ROM);
407 }
408
409 static SysBusDeviceInfo idreg_info = {
410 .init = idreg_init1,
411 .qdev.name = "macio_idreg",
412 .qdev.size = sizeof(SysBusDevice),
413 .qdev.props = (DevicePropList[]) {
414 {.name = NULL}
415 }
416 };
417
418 static void idreg_register_devices(void)
419 {
420 sysbus_register_withprop(&idreg_info);
421 }
422
423 device_init(idreg_register_devices);
424
425 static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, ram_addr_t RAM_size,
426 const char *boot_device,
427 const char *kernel_filename,
428 const char *kernel_cmdline,
429 const char *initrd_filename, const char *cpu_model)
430
431 {
432 CPUState *env, *envs[MAX_CPUS];
433 unsigned int i;
434 void *iommu, *espdma, *ledma, *nvram;
435 qemu_irq *cpu_irqs[MAX_CPUS], *slavio_irq, *slavio_cpu_irq,
436 espdma_irq, ledma_irq;
437 qemu_irq *esp_reset, *le_reset;
438 qemu_irq fdc_tc;
439 qemu_irq *cpu_halt;
440 ram_addr_t ram_offset, prom_offset;
441 unsigned long kernel_size;
442 int ret;
443 char *filename;
444 BlockDriverState *fd[MAX_FD];
445 int drive_index;
446 void *fw_cfg;
447
448 /* init CPUs */
449 if (!cpu_model)
450 cpu_model = hwdef->default_cpu_model;
451
452 for(i = 0; i < smp_cpus; i++) {
453 env = cpu_init(cpu_model);
454 if (!env) {
455 fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
456 exit(1);
457 }
458 cpu_sparc_set_id(env, i);
459 envs[i] = env;
460 if (i == 0) {
461 qemu_register_reset(main_cpu_reset, env);
462 } else {
463 qemu_register_reset(secondary_cpu_reset, env);
464 env->halted = 1;
465 }
466 cpu_irqs[i] = qemu_allocate_irqs(cpu_set_irq, envs[i], MAX_PILS);
467 env->prom_addr = hwdef->slavio_base;
468 }
469
470 for (i = smp_cpus; i < MAX_CPUS; i++)
471 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
472
473
474 /* allocate RAM */
475 if ((uint64_t)RAM_size > hwdef->max_mem) {
476 fprintf(stderr,
477 "qemu: Too much memory for this machine: %d, maximum %d\n",
478 (unsigned int)(RAM_size / (1024 * 1024)),
479 (unsigned int)(hwdef->max_mem / (1024 * 1024)));
480 exit(1);
481 }
482 ram_offset = qemu_ram_alloc(RAM_size);
483 cpu_register_physical_memory(0, RAM_size, ram_offset);
484
485 /* load boot prom */
486 prom_offset = qemu_ram_alloc(PROM_SIZE_MAX);
487 cpu_register_physical_memory(hwdef->slavio_base,
488 (PROM_SIZE_MAX + TARGET_PAGE_SIZE - 1) &
489 TARGET_PAGE_MASK,
490 prom_offset | IO_MEM_ROM);
491
492 if (bios_name == NULL)
493 bios_name = PROM_FILENAME;
494 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
495 if (filename) {
496 ret = load_elf(filename, hwdef->slavio_base - PROM_VADDR,
497 NULL, NULL, NULL);
498 if (ret < 0 || ret > PROM_SIZE_MAX)
499 ret = load_image_targphys(filename, hwdef->slavio_base,
500 PROM_SIZE_MAX);
501 qemu_free(filename);
502 } else {
503 ret = -1;
504 }
505 if (ret < 0 || ret > PROM_SIZE_MAX) {
506 fprintf(stderr, "qemu: could not load prom '%s'\n",
507 bios_name);
508 exit(1);
509 }
510
511 /* set up devices */
512 slavio_intctl = slavio_intctl_init(hwdef->intctl_base,
513 hwdef->intctl_base + 0x10000ULL,
514 &hwdef->intbit_to_level[0],
515 &slavio_irq, &slavio_cpu_irq,
516 cpu_irqs,
517 hwdef->clock_irq);
518
519 if (hwdef->idreg_base) {
520 idreg_init(hwdef->idreg_base);
521 }
522
523 iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version,
524 slavio_irq[hwdef->me_irq]);
525
526 espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[hwdef->esp_irq],
527 iommu, &espdma_irq, &esp_reset);
528
529 ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
530 slavio_irq[hwdef->le_irq], iommu, &ledma_irq,
531 &le_reset);
532
533 if (graphic_depth != 8 && graphic_depth != 24) {
534 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
535 exit (1);
536 }
537 tcx_init(hwdef->tcx_base, hwdef->vram_size, graphic_width, graphic_height,
538 graphic_depth);
539
540 lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq, le_reset);
541
542 nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0,
543 hwdef->nvram_size, 8);
544
545 slavio_timer_init_all(hwdef->counter_base, slavio_irq[hwdef->clock1_irq],
546 slavio_cpu_irq, smp_cpus);
547
548 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[hwdef->ms_kb_irq],
549 display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
550 // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
551 // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
552 escc_init(hwdef->serial_base, slavio_irq[hwdef->ser_irq], slavio_irq[hwdef->ser_irq],
553 serial_hds[0], serial_hds[1], ESCC_CLOCK, 1);
554
555 cpu_halt = qemu_allocate_irqs(cpu_halt_signal, NULL, 1);
556 slavio_misc = slavio_misc_init(hwdef->slavio_base,
557 hwdef->aux1_base, hwdef->aux2_base,
558 slavio_irq[hwdef->me_irq], fdc_tc);
559 if (hwdef->apc_base) {
560 apc_init(hwdef->apc_base, cpu_halt[0]);
561 }
562
563 if (hwdef->fd_base) {
564 /* there is zero or one floppy drive */
565 memset(fd, 0, sizeof(fd));
566 drive_index = drive_get_index(IF_FLOPPY, 0, 0);
567 if (drive_index != -1)
568 fd[0] = drives_table[drive_index].bdrv;
569
570 sun4m_fdctrl_init(slavio_irq[hwdef->fd_irq], hwdef->fd_base, fd,
571 &fdc_tc);
572 }
573
574 if (drive_get_max_bus(IF_SCSI) > 0) {
575 fprintf(stderr, "qemu: too many SCSI bus\n");
576 exit(1);
577 }
578
579 esp_init(hwdef->esp_base, 2,
580 espdma_memory_read, espdma_memory_write,
581 espdma, espdma_irq, esp_reset);
582
583 if (hwdef->cs_base) {
584 sysbus_create_simple("SUNW,CS4231", hwdef->cs_base,
585 slavio_irq[hwdef->cs_irq]);
586 }
587
588 kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
589 RAM_size);
590
591 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
592 boot_device, RAM_size, kernel_size, graphic_width,
593 graphic_height, graphic_depth, hwdef->nvram_machine_id,
594 "Sun4m");
595
596 if (hwdef->ecc_base)
597 ecc_init(hwdef->ecc_base, slavio_irq[hwdef->ecc_irq],
598 hwdef->ecc_version);
599
600 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
601 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
602 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
603 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
604 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
605 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
606 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
607 if (kernel_cmdline) {
608 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
609 pstrcpy_targphys(CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
610 } else {
611 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
612 }
613 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
614 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
615 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
616 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
617 }
618
619 enum {
620 ss2_id = 0,
621 ss5_id = 32,
622 vger_id,
623 lx_id,
624 ss4_id,
625 scls_id,
626 sbook_id,
627 ss10_id = 64,
628 ss20_id,
629 ss600mp_id,
630 ss1000_id = 96,
631 ss2000_id,
632 };
633
634 static const struct sun4m_hwdef sun4m_hwdefs[] = {
635 /* SS-5 */
636 {
637 .iommu_base = 0x10000000,
638 .tcx_base = 0x50000000,
639 .cs_base = 0x6c000000,
640 .slavio_base = 0x70000000,
641 .ms_kb_base = 0x71000000,
642 .serial_base = 0x71100000,
643 .nvram_base = 0x71200000,
644 .fd_base = 0x71400000,
645 .counter_base = 0x71d00000,
646 .intctl_base = 0x71e00000,
647 .idreg_base = 0x78000000,
648 .dma_base = 0x78400000,
649 .esp_base = 0x78800000,
650 .le_base = 0x78c00000,
651 .apc_base = 0x6a000000,
652 .aux1_base = 0x71900000,
653 .aux2_base = 0x71910000,
654 .vram_size = 0x00100000,
655 .nvram_size = 0x2000,
656 .esp_irq = 18,
657 .le_irq = 16,
658 .clock_irq = 7,
659 .clock1_irq = 19,
660 .ms_kb_irq = 14,
661 .ser_irq = 15,
662 .fd_irq = 22,
663 .me_irq = 30,
664 .cs_irq = 5,
665 .nvram_machine_id = 0x80,
666 .machine_id = ss5_id,
667 .iommu_version = 0x05000000,
668 .intbit_to_level = {
669 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
670 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
671 },
672 .max_mem = 0x10000000,
673 .default_cpu_model = "Fujitsu MB86904",
674 },
675 /* SS-10 */
676 {
677 .iommu_base = 0xfe0000000ULL,
678 .tcx_base = 0xe20000000ULL,
679 .slavio_base = 0xff0000000ULL,
680 .ms_kb_base = 0xff1000000ULL,
681 .serial_base = 0xff1100000ULL,
682 .nvram_base = 0xff1200000ULL,
683 .fd_base = 0xff1700000ULL,
684 .counter_base = 0xff1300000ULL,
685 .intctl_base = 0xff1400000ULL,
686 .idreg_base = 0xef0000000ULL,
687 .dma_base = 0xef0400000ULL,
688 .esp_base = 0xef0800000ULL,
689 .le_base = 0xef0c00000ULL,
690 .apc_base = 0xefa000000ULL, // XXX should not exist
691 .aux1_base = 0xff1800000ULL,
692 .aux2_base = 0xff1a01000ULL,
693 .ecc_base = 0xf00000000ULL,
694 .ecc_version = 0x10000000, // version 0, implementation 1
695 .vram_size = 0x00100000,
696 .nvram_size = 0x2000,
697 .esp_irq = 18,
698 .le_irq = 16,
699 .clock_irq = 7,
700 .clock1_irq = 19,
701 .ms_kb_irq = 14,
702 .ser_irq = 15,
703 .fd_irq = 22,
704 .me_irq = 30,
705 .ecc_irq = 28,
706 .nvram_machine_id = 0x72,
707 .machine_id = ss10_id,
708 .iommu_version = 0x03000000,
709 .intbit_to_level = {
710 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
711 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
712 },
713 .max_mem = 0xf00000000ULL,
714 .default_cpu_model = "TI SuperSparc II",
715 },
716 /* SS-600MP */
717 {
718 .iommu_base = 0xfe0000000ULL,
719 .tcx_base = 0xe20000000ULL,
720 .slavio_base = 0xff0000000ULL,
721 .ms_kb_base = 0xff1000000ULL,
722 .serial_base = 0xff1100000ULL,
723 .nvram_base = 0xff1200000ULL,
724 .counter_base = 0xff1300000ULL,
725 .intctl_base = 0xff1400000ULL,
726 .dma_base = 0xef0081000ULL,
727 .esp_base = 0xef0080000ULL,
728 .le_base = 0xef0060000ULL,
729 .apc_base = 0xefa000000ULL, // XXX should not exist
730 .aux1_base = 0xff1800000ULL,
731 .aux2_base = 0xff1a01000ULL, // XXX should not exist
732 .ecc_base = 0xf00000000ULL,
733 .ecc_version = 0x00000000, // version 0, implementation 0
734 .vram_size = 0x00100000,
735 .nvram_size = 0x2000,
736 .esp_irq = 18,
737 .le_irq = 16,
738 .clock_irq = 7,
739 .clock1_irq = 19,
740 .ms_kb_irq = 14,
741 .ser_irq = 15,
742 .fd_irq = 22,
743 .me_irq = 30,
744 .ecc_irq = 28,
745 .nvram_machine_id = 0x71,
746 .machine_id = ss600mp_id,
747 .iommu_version = 0x01000000,
748 .intbit_to_level = {
749 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
750 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
751 },
752 .max_mem = 0xf00000000ULL,
753 .default_cpu_model = "TI SuperSparc II",
754 },
755 /* SS-20 */
756 {
757 .iommu_base = 0xfe0000000ULL,
758 .tcx_base = 0xe20000000ULL,
759 .slavio_base = 0xff0000000ULL,
760 .ms_kb_base = 0xff1000000ULL,
761 .serial_base = 0xff1100000ULL,
762 .nvram_base = 0xff1200000ULL,
763 .fd_base = 0xff1700000ULL,
764 .counter_base = 0xff1300000ULL,
765 .intctl_base = 0xff1400000ULL,
766 .idreg_base = 0xef0000000ULL,
767 .dma_base = 0xef0400000ULL,
768 .esp_base = 0xef0800000ULL,
769 .le_base = 0xef0c00000ULL,
770 .apc_base = 0xefa000000ULL, // XXX should not exist
771 .aux1_base = 0xff1800000ULL,
772 .aux2_base = 0xff1a01000ULL,
773 .ecc_base = 0xf00000000ULL,
774 .ecc_version = 0x20000000, // version 0, implementation 2
775 .vram_size = 0x00100000,
776 .nvram_size = 0x2000,
777 .esp_irq = 18,
778 .le_irq = 16,
779 .clock_irq = 7,
780 .clock1_irq = 19,
781 .ms_kb_irq = 14,
782 .ser_irq = 15,
783 .fd_irq = 22,
784 .me_irq = 30,
785 .ecc_irq = 28,
786 .nvram_machine_id = 0x72,
787 .machine_id = ss20_id,
788 .iommu_version = 0x13000000,
789 .intbit_to_level = {
790 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
791 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
792 },
793 .max_mem = 0xf00000000ULL,
794 .default_cpu_model = "TI SuperSparc II",
795 },
796 /* Voyager */
797 {
798 .iommu_base = 0x10000000,
799 .tcx_base = 0x50000000,
800 .slavio_base = 0x70000000,
801 .ms_kb_base = 0x71000000,
802 .serial_base = 0x71100000,
803 .nvram_base = 0x71200000,
804 .fd_base = 0x71400000,
805 .counter_base = 0x71d00000,
806 .intctl_base = 0x71e00000,
807 .idreg_base = 0x78000000,
808 .dma_base = 0x78400000,
809 .esp_base = 0x78800000,
810 .le_base = 0x78c00000,
811 .apc_base = 0x71300000, // pmc
812 .aux1_base = 0x71900000,
813 .aux2_base = 0x71910000,
814 .vram_size = 0x00100000,
815 .nvram_size = 0x2000,
816 .esp_irq = 18,
817 .le_irq = 16,
818 .clock_irq = 7,
819 .clock1_irq = 19,
820 .ms_kb_irq = 14,
821 .ser_irq = 15,
822 .fd_irq = 22,
823 .me_irq = 30,
824 .nvram_machine_id = 0x80,
825 .machine_id = vger_id,
826 .iommu_version = 0x05000000,
827 .intbit_to_level = {
828 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
829 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
830 },
831 .max_mem = 0x10000000,
832 .default_cpu_model = "Fujitsu MB86904",
833 },
834 /* LX */
835 {
836 .iommu_base = 0x10000000,
837 .tcx_base = 0x50000000,
838 .slavio_base = 0x70000000,
839 .ms_kb_base = 0x71000000,
840 .serial_base = 0x71100000,
841 .nvram_base = 0x71200000,
842 .fd_base = 0x71400000,
843 .counter_base = 0x71d00000,
844 .intctl_base = 0x71e00000,
845 .idreg_base = 0x78000000,
846 .dma_base = 0x78400000,
847 .esp_base = 0x78800000,
848 .le_base = 0x78c00000,
849 .aux1_base = 0x71900000,
850 .aux2_base = 0x71910000,
851 .vram_size = 0x00100000,
852 .nvram_size = 0x2000,
853 .esp_irq = 18,
854 .le_irq = 16,
855 .clock_irq = 7,
856 .clock1_irq = 19,
857 .ms_kb_irq = 14,
858 .ser_irq = 15,
859 .fd_irq = 22,
860 .me_irq = 30,
861 .nvram_machine_id = 0x80,
862 .machine_id = lx_id,
863 .iommu_version = 0x04000000,
864 .intbit_to_level = {
865 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
866 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
867 },
868 .max_mem = 0x10000000,
869 .default_cpu_model = "TI MicroSparc I",
870 },
871 /* SS-4 */
872 {
873 .iommu_base = 0x10000000,
874 .tcx_base = 0x50000000,
875 .cs_base = 0x6c000000,
876 .slavio_base = 0x70000000,
877 .ms_kb_base = 0x71000000,
878 .serial_base = 0x71100000,
879 .nvram_base = 0x71200000,
880 .fd_base = 0x71400000,
881 .counter_base = 0x71d00000,
882 .intctl_base = 0x71e00000,
883 .idreg_base = 0x78000000,
884 .dma_base = 0x78400000,
885 .esp_base = 0x78800000,
886 .le_base = 0x78c00000,
887 .apc_base = 0x6a000000,
888 .aux1_base = 0x71900000,
889 .aux2_base = 0x71910000,
890 .vram_size = 0x00100000,
891 .nvram_size = 0x2000,
892 .esp_irq = 18,
893 .le_irq = 16,
894 .clock_irq = 7,
895 .clock1_irq = 19,
896 .ms_kb_irq = 14,
897 .ser_irq = 15,
898 .fd_irq = 22,
899 .me_irq = 30,
900 .cs_irq = 5,
901 .nvram_machine_id = 0x80,
902 .machine_id = ss4_id,
903 .iommu_version = 0x05000000,
904 .intbit_to_level = {
905 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
906 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
907 },
908 .max_mem = 0x10000000,
909 .default_cpu_model = "Fujitsu MB86904",
910 },
911 /* SPARCClassic */
912 {
913 .iommu_base = 0x10000000,
914 .tcx_base = 0x50000000,
915 .slavio_base = 0x70000000,
916 .ms_kb_base = 0x71000000,
917 .serial_base = 0x71100000,
918 .nvram_base = 0x71200000,
919 .fd_base = 0x71400000,
920 .counter_base = 0x71d00000,
921 .intctl_base = 0x71e00000,
922 .idreg_base = 0x78000000,
923 .dma_base = 0x78400000,
924 .esp_base = 0x78800000,
925 .le_base = 0x78c00000,
926 .apc_base = 0x6a000000,
927 .aux1_base = 0x71900000,
928 .aux2_base = 0x71910000,
929 .vram_size = 0x00100000,
930 .nvram_size = 0x2000,
931 .esp_irq = 18,
932 .le_irq = 16,
933 .clock_irq = 7,
934 .clock1_irq = 19,
935 .ms_kb_irq = 14,
936 .ser_irq = 15,
937 .fd_irq = 22,
938 .me_irq = 30,
939 .nvram_machine_id = 0x80,
940 .machine_id = scls_id,
941 .iommu_version = 0x05000000,
942 .intbit_to_level = {
943 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
944 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
945 },
946 .max_mem = 0x10000000,
947 .default_cpu_model = "TI MicroSparc I",
948 },
949 /* SPARCbook */
950 {
951 .iommu_base = 0x10000000,
952 .tcx_base = 0x50000000, // XXX
953 .slavio_base = 0x70000000,
954 .ms_kb_base = 0x71000000,
955 .serial_base = 0x71100000,
956 .nvram_base = 0x71200000,
957 .fd_base = 0x71400000,
958 .counter_base = 0x71d00000,
959 .intctl_base = 0x71e00000,
960 .idreg_base = 0x78000000,
961 .dma_base = 0x78400000,
962 .esp_base = 0x78800000,
963 .le_base = 0x78c00000,
964 .apc_base = 0x6a000000,
965 .aux1_base = 0x71900000,
966 .aux2_base = 0x71910000,
967 .vram_size = 0x00100000,
968 .nvram_size = 0x2000,
969 .esp_irq = 18,
970 .le_irq = 16,
971 .clock_irq = 7,
972 .clock1_irq = 19,
973 .ms_kb_irq = 14,
974 .ser_irq = 15,
975 .fd_irq = 22,
976 .me_irq = 30,
977 .nvram_machine_id = 0x80,
978 .machine_id = sbook_id,
979 .iommu_version = 0x05000000,
980 .intbit_to_level = {
981 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
982 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
983 },
984 .max_mem = 0x10000000,
985 .default_cpu_model = "TI MicroSparc I",
986 },
987 };
988
989 /* SPARCstation 5 hardware initialisation */
990 static void ss5_init(ram_addr_t RAM_size,
991 const char *boot_device,
992 const char *kernel_filename, const char *kernel_cmdline,
993 const char *initrd_filename, const char *cpu_model)
994 {
995 sun4m_hw_init(&sun4m_hwdefs[0], RAM_size, boot_device, kernel_filename,
996 kernel_cmdline, initrd_filename, cpu_model);
997 }
998
999 /* SPARCstation 10 hardware initialisation */
1000 static void ss10_init(ram_addr_t RAM_size,
1001 const char *boot_device,
1002 const char *kernel_filename, const char *kernel_cmdline,
1003 const char *initrd_filename, const char *cpu_model)
1004 {
1005 sun4m_hw_init(&sun4m_hwdefs[1], RAM_size, boot_device, kernel_filename,
1006 kernel_cmdline, initrd_filename, cpu_model);
1007 }
1008
1009 /* SPARCserver 600MP hardware initialisation */
1010 static void ss600mp_init(ram_addr_t RAM_size,
1011 const char *boot_device,
1012 const char *kernel_filename,
1013 const char *kernel_cmdline,
1014 const char *initrd_filename, const char *cpu_model)
1015 {
1016 sun4m_hw_init(&sun4m_hwdefs[2], RAM_size, boot_device, kernel_filename,
1017 kernel_cmdline, initrd_filename, cpu_model);
1018 }
1019
1020 /* SPARCstation 20 hardware initialisation */
1021 static void ss20_init(ram_addr_t RAM_size,
1022 const char *boot_device,
1023 const char *kernel_filename, const char *kernel_cmdline,
1024 const char *initrd_filename, const char *cpu_model)
1025 {
1026 sun4m_hw_init(&sun4m_hwdefs[3], RAM_size, boot_device, kernel_filename,
1027 kernel_cmdline, initrd_filename, cpu_model);
1028 }
1029
1030 /* SPARCstation Voyager hardware initialisation */
1031 static void vger_init(ram_addr_t RAM_size,
1032 const char *boot_device,
1033 const char *kernel_filename, const char *kernel_cmdline,
1034 const char *initrd_filename, const char *cpu_model)
1035 {
1036 sun4m_hw_init(&sun4m_hwdefs[4], RAM_size, boot_device, kernel_filename,
1037 kernel_cmdline, initrd_filename, cpu_model);
1038 }
1039
1040 /* SPARCstation LX hardware initialisation */
1041 static void ss_lx_init(ram_addr_t RAM_size,
1042 const char *boot_device,
1043 const char *kernel_filename, const char *kernel_cmdline,
1044 const char *initrd_filename, const char *cpu_model)
1045 {
1046 sun4m_hw_init(&sun4m_hwdefs[5], RAM_size, boot_device, kernel_filename,
1047 kernel_cmdline, initrd_filename, cpu_model);
1048 }
1049
1050 /* SPARCstation 4 hardware initialisation */
1051 static void ss4_init(ram_addr_t RAM_size,
1052 const char *boot_device,
1053 const char *kernel_filename, const char *kernel_cmdline,
1054 const char *initrd_filename, const char *cpu_model)
1055 {
1056 sun4m_hw_init(&sun4m_hwdefs[6], RAM_size, boot_device, kernel_filename,
1057 kernel_cmdline, initrd_filename, cpu_model);
1058 }
1059
1060 /* SPARCClassic hardware initialisation */
1061 static void scls_init(ram_addr_t RAM_size,
1062 const char *boot_device,
1063 const char *kernel_filename, const char *kernel_cmdline,
1064 const char *initrd_filename, const char *cpu_model)
1065 {
1066 sun4m_hw_init(&sun4m_hwdefs[7], RAM_size, boot_device, kernel_filename,
1067 kernel_cmdline, initrd_filename, cpu_model);
1068 }
1069
1070 /* SPARCbook hardware initialisation */
1071 static void sbook_init(ram_addr_t RAM_size,
1072 const char *boot_device,
1073 const char *kernel_filename, const char *kernel_cmdline,
1074 const char *initrd_filename, const char *cpu_model)
1075 {
1076 sun4m_hw_init(&sun4m_hwdefs[8], RAM_size, boot_device, kernel_filename,
1077 kernel_cmdline, initrd_filename, cpu_model);
1078 }
1079
1080 static QEMUMachine ss5_machine = {
1081 .name = "SS-5",
1082 .desc = "Sun4m platform, SPARCstation 5",
1083 .init = ss5_init,
1084 .use_scsi = 1,
1085 .is_default = 1,
1086 };
1087
1088 static QEMUMachine ss10_machine = {
1089 .name = "SS-10",
1090 .desc = "Sun4m platform, SPARCstation 10",
1091 .init = ss10_init,
1092 .use_scsi = 1,
1093 .max_cpus = 4,
1094 };
1095
1096 static QEMUMachine ss600mp_machine = {
1097 .name = "SS-600MP",
1098 .desc = "Sun4m platform, SPARCserver 600MP",
1099 .init = ss600mp_init,
1100 .use_scsi = 1,
1101 .max_cpus = 4,
1102 };
1103
1104 static QEMUMachine ss20_machine = {
1105 .name = "SS-20",
1106 .desc = "Sun4m platform, SPARCstation 20",
1107 .init = ss20_init,
1108 .use_scsi = 1,
1109 .max_cpus = 4,
1110 };
1111
1112 static QEMUMachine voyager_machine = {
1113 .name = "Voyager",
1114 .desc = "Sun4m platform, SPARCstation Voyager",
1115 .init = vger_init,
1116 .use_scsi = 1,
1117 };
1118
1119 static QEMUMachine ss_lx_machine = {
1120 .name = "LX",
1121 .desc = "Sun4m platform, SPARCstation LX",
1122 .init = ss_lx_init,
1123 .use_scsi = 1,
1124 };
1125
1126 static QEMUMachine ss4_machine = {
1127 .name = "SS-4",
1128 .desc = "Sun4m platform, SPARCstation 4",
1129 .init = ss4_init,
1130 .use_scsi = 1,
1131 };
1132
1133 static QEMUMachine scls_machine = {
1134 .name = "SPARCClassic",
1135 .desc = "Sun4m platform, SPARCClassic",
1136 .init = scls_init,
1137 .use_scsi = 1,
1138 };
1139
1140 static QEMUMachine sbook_machine = {
1141 .name = "SPARCbook",
1142 .desc = "Sun4m platform, SPARCbook",
1143 .init = sbook_init,
1144 .use_scsi = 1,
1145 };
1146
1147 static const struct sun4d_hwdef sun4d_hwdefs[] = {
1148 /* SS-1000 */
1149 {
1150 .iounit_bases = {
1151 0xfe0200000ULL,
1152 0xfe1200000ULL,
1153 0xfe2200000ULL,
1154 0xfe3200000ULL,
1155 -1,
1156 },
1157 .tcx_base = 0x820000000ULL,
1158 .slavio_base = 0xf00000000ULL,
1159 .ms_kb_base = 0xf00240000ULL,
1160 .serial_base = 0xf00200000ULL,
1161 .nvram_base = 0xf00280000ULL,
1162 .counter_base = 0xf00300000ULL,
1163 .espdma_base = 0x800081000ULL,
1164 .esp_base = 0x800080000ULL,
1165 .ledma_base = 0x800040000ULL,
1166 .le_base = 0x800060000ULL,
1167 .sbi_base = 0xf02800000ULL,
1168 .vram_size = 0x00100000,
1169 .nvram_size = 0x2000,
1170 .esp_irq = 3,
1171 .le_irq = 4,
1172 .clock_irq = 14,
1173 .clock1_irq = 10,
1174 .ms_kb_irq = 12,
1175 .ser_irq = 12,
1176 .nvram_machine_id = 0x80,
1177 .machine_id = ss1000_id,
1178 .iounit_version = 0x03000000,
1179 .max_mem = 0xf00000000ULL,
1180 .default_cpu_model = "TI SuperSparc II",
1181 },
1182 /* SS-2000 */
1183 {
1184 .iounit_bases = {
1185 0xfe0200000ULL,
1186 0xfe1200000ULL,
1187 0xfe2200000ULL,
1188 0xfe3200000ULL,
1189 0xfe4200000ULL,
1190 },
1191 .tcx_base = 0x820000000ULL,
1192 .slavio_base = 0xf00000000ULL,
1193 .ms_kb_base = 0xf00240000ULL,
1194 .serial_base = 0xf00200000ULL,
1195 .nvram_base = 0xf00280000ULL,
1196 .counter_base = 0xf00300000ULL,
1197 .espdma_base = 0x800081000ULL,
1198 .esp_base = 0x800080000ULL,
1199 .ledma_base = 0x800040000ULL,
1200 .le_base = 0x800060000ULL,
1201 .sbi_base = 0xf02800000ULL,
1202 .vram_size = 0x00100000,
1203 .nvram_size = 0x2000,
1204 .esp_irq = 3,
1205 .le_irq = 4,
1206 .clock_irq = 14,
1207 .clock1_irq = 10,
1208 .ms_kb_irq = 12,
1209 .ser_irq = 12,
1210 .nvram_machine_id = 0x80,
1211 .machine_id = ss2000_id,
1212 .iounit_version = 0x03000000,
1213 .max_mem = 0xf00000000ULL,
1214 .default_cpu_model = "TI SuperSparc II",
1215 },
1216 };
1217
1218 static void sun4d_hw_init(const struct sun4d_hwdef *hwdef, ram_addr_t RAM_size,
1219 const char *boot_device,
1220 const char *kernel_filename,
1221 const char *kernel_cmdline,
1222 const char *initrd_filename, const char *cpu_model)
1223 {
1224 CPUState *env, *envs[MAX_CPUS];
1225 unsigned int i;
1226 void *iounits[MAX_IOUNITS], *espdma, *ledma, *nvram, *sbi;
1227 qemu_irq *cpu_irqs[MAX_CPUS], *sbi_irq, *sbi_cpu_irq,
1228 espdma_irq, ledma_irq;
1229 qemu_irq *esp_reset, *le_reset;
1230 ram_addr_t ram_offset, prom_offset;
1231 unsigned long kernel_size;
1232 int ret;
1233 char *filename;
1234 void *fw_cfg;
1235
1236 /* init CPUs */
1237 if (!cpu_model)
1238 cpu_model = hwdef->default_cpu_model;
1239
1240 for (i = 0; i < smp_cpus; i++) {
1241 env = cpu_init(cpu_model);
1242 if (!env) {
1243 fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
1244 exit(1);
1245 }
1246 cpu_sparc_set_id(env, i);
1247 envs[i] = env;
1248 if (i == 0) {
1249 qemu_register_reset(main_cpu_reset, env);
1250 } else {
1251 qemu_register_reset(secondary_cpu_reset, env);
1252 env->halted = 1;
1253 }
1254 cpu_irqs[i] = qemu_allocate_irqs(cpu_set_irq, envs[i], MAX_PILS);
1255 env->prom_addr = hwdef->slavio_base;
1256 }
1257
1258 for (i = smp_cpus; i < MAX_CPUS; i++)
1259 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
1260
1261 /* allocate RAM */
1262 if ((uint64_t)RAM_size > hwdef->max_mem) {
1263 fprintf(stderr,
1264 "qemu: Too much memory for this machine: %d, maximum %d\n",
1265 (unsigned int)(RAM_size / (1024 * 1024)),
1266 (unsigned int)(hwdef->max_mem / (1024 * 1024)));
1267 exit(1);
1268 }
1269 ram_offset = qemu_ram_alloc(RAM_size);
1270 cpu_register_physical_memory(0, RAM_size, ram_offset);
1271
1272 /* load boot prom */
1273 prom_offset = qemu_ram_alloc(PROM_SIZE_MAX);
1274 cpu_register_physical_memory(hwdef->slavio_base,
1275 (PROM_SIZE_MAX + TARGET_PAGE_SIZE - 1) &
1276 TARGET_PAGE_MASK,
1277 prom_offset | IO_MEM_ROM);
1278
1279 if (bios_name == NULL)
1280 bios_name = PROM_FILENAME;
1281 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
1282 if (filename) {
1283 ret = load_elf(filename, hwdef->slavio_base - PROM_VADDR,
1284 NULL, NULL, NULL);
1285 if (ret < 0 || ret > PROM_SIZE_MAX)
1286 ret = load_image_targphys(filename, hwdef->slavio_base,
1287 PROM_SIZE_MAX);
1288 qemu_free(filename);
1289 } else {
1290 ret = -1;
1291 }
1292 if (ret < 0 || ret > PROM_SIZE_MAX) {
1293 fprintf(stderr, "qemu: could not load prom '%s'\n",
1294 bios_name);
1295 exit(1);
1296 }
1297
1298 /* set up devices */
1299 sbi = sbi_init(hwdef->sbi_base, &sbi_irq, &sbi_cpu_irq, cpu_irqs);
1300
1301 for (i = 0; i < MAX_IOUNITS; i++)
1302 if (hwdef->iounit_bases[i] != (target_phys_addr_t)-1)
1303 iounits[i] = iommu_init(hwdef->iounit_bases[i],
1304 hwdef->iounit_version,
1305 sbi_irq[hwdef->me_irq]);
1306
1307 espdma = sparc32_dma_init(hwdef->espdma_base, sbi_irq[hwdef->esp_irq],
1308 iounits[0], &espdma_irq, &esp_reset);
1309
1310 ledma = sparc32_dma_init(hwdef->ledma_base, sbi_irq[hwdef->le_irq],
1311 iounits[0], &ledma_irq, &le_reset);
1312
1313 if (graphic_depth != 8 && graphic_depth != 24) {
1314 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
1315 exit (1);
1316 }
1317 tcx_init(hwdef->tcx_base, hwdef->vram_size, graphic_width, graphic_height,
1318 graphic_depth);
1319
1320 lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq, le_reset);
1321
1322 nvram = m48t59_init(sbi_irq[0], hwdef->nvram_base, 0,
1323 hwdef->nvram_size, 8);
1324
1325 slavio_timer_init_all(hwdef->counter_base, sbi_irq[hwdef->clock1_irq],
1326 sbi_cpu_irq, smp_cpus);
1327
1328 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, sbi_irq[hwdef->ms_kb_irq],
1329 display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
1330 // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
1331 // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
1332 escc_init(hwdef->serial_base, sbi_irq[hwdef->ser_irq], sbi_irq[hwdef->ser_irq],
1333 serial_hds[0], serial_hds[1], ESCC_CLOCK, 1);
1334
1335 if (drive_get_max_bus(IF_SCSI) > 0) {
1336 fprintf(stderr, "qemu: too many SCSI bus\n");
1337 exit(1);
1338 }
1339
1340 esp_init(hwdef->esp_base, 2,
1341 espdma_memory_read, espdma_memory_write,
1342 espdma, espdma_irq, esp_reset);
1343
1344 kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
1345 RAM_size);
1346
1347 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
1348 boot_device, RAM_size, kernel_size, graphic_width,
1349 graphic_height, graphic_depth, hwdef->nvram_machine_id,
1350 "Sun4d");
1351
1352 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
1353 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
1354 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
1355 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
1356 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
1357 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
1358 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
1359 if (kernel_cmdline) {
1360 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
1361 pstrcpy_targphys(CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
1362 } else {
1363 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
1364 }
1365 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
1366 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
1367 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
1368 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
1369 }
1370
1371 /* SPARCserver 1000 hardware initialisation */
1372 static void ss1000_init(ram_addr_t RAM_size,
1373 const char *boot_device,
1374 const char *kernel_filename, const char *kernel_cmdline,
1375 const char *initrd_filename, const char *cpu_model)
1376 {
1377 sun4d_hw_init(&sun4d_hwdefs[0], RAM_size, boot_device, kernel_filename,
1378 kernel_cmdline, initrd_filename, cpu_model);
1379 }
1380
1381 /* SPARCcenter 2000 hardware initialisation */
1382 static void ss2000_init(ram_addr_t RAM_size,
1383 const char *boot_device,
1384 const char *kernel_filename, const char *kernel_cmdline,
1385 const char *initrd_filename, const char *cpu_model)
1386 {
1387 sun4d_hw_init(&sun4d_hwdefs[1], RAM_size, boot_device, kernel_filename,
1388 kernel_cmdline, initrd_filename, cpu_model);
1389 }
1390
1391 static QEMUMachine ss1000_machine = {
1392 .name = "SS-1000",
1393 .desc = "Sun4d platform, SPARCserver 1000",
1394 .init = ss1000_init,
1395 .use_scsi = 1,
1396 .max_cpus = 8,
1397 };
1398
1399 static QEMUMachine ss2000_machine = {
1400 .name = "SS-2000",
1401 .desc = "Sun4d platform, SPARCcenter 2000",
1402 .init = ss2000_init,
1403 .use_scsi = 1,
1404 .max_cpus = 20,
1405 };
1406
1407 static const struct sun4c_hwdef sun4c_hwdefs[] = {
1408 /* SS-2 */
1409 {
1410 .iommu_base = 0xf8000000,
1411 .tcx_base = 0xfe000000,
1412 .slavio_base = 0xf6000000,
1413 .intctl_base = 0xf5000000,
1414 .counter_base = 0xf3000000,
1415 .ms_kb_base = 0xf0000000,
1416 .serial_base = 0xf1000000,
1417 .nvram_base = 0xf2000000,
1418 .fd_base = 0xf7200000,
1419 .dma_base = 0xf8400000,
1420 .esp_base = 0xf8800000,
1421 .le_base = 0xf8c00000,
1422 .aux1_base = 0xf7400003,
1423 .vram_size = 0x00100000,
1424 .nvram_size = 0x800,
1425 .esp_irq = 2,
1426 .le_irq = 3,
1427 .clock_irq = 5,
1428 .clock1_irq = 7,
1429 .ms_kb_irq = 1,
1430 .ser_irq = 1,
1431 .fd_irq = 1,
1432 .me_irq = 1,
1433 .nvram_machine_id = 0x55,
1434 .machine_id = ss2_id,
1435 .max_mem = 0x10000000,
1436 .default_cpu_model = "Cypress CY7C601",
1437 },
1438 };
1439
1440 static void sun4c_hw_init(const struct sun4c_hwdef *hwdef, ram_addr_t RAM_size,
1441 const char *boot_device,
1442 const char *kernel_filename,
1443 const char *kernel_cmdline,
1444 const char *initrd_filename, const char *cpu_model)
1445 {
1446 CPUState *env;
1447 void *iommu, *espdma, *ledma, *nvram;
1448 qemu_irq *cpu_irqs, *slavio_irq, espdma_irq, ledma_irq;
1449 qemu_irq *esp_reset, *le_reset;
1450 qemu_irq fdc_tc;
1451 ram_addr_t ram_offset, prom_offset;
1452 unsigned long kernel_size;
1453 int ret;
1454 char *filename;
1455 BlockDriverState *fd[MAX_FD];
1456 int drive_index;
1457 void *fw_cfg;
1458
1459 /* init CPU */
1460 if (!cpu_model)
1461 cpu_model = hwdef->default_cpu_model;
1462
1463 env = cpu_init(cpu_model);
1464 if (!env) {
1465 fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
1466 exit(1);
1467 }
1468
1469 cpu_sparc_set_id(env, 0);
1470
1471 qemu_register_reset(main_cpu_reset, env);
1472 cpu_irqs = qemu_allocate_irqs(cpu_set_irq, env, MAX_PILS);
1473 env->prom_addr = hwdef->slavio_base;
1474
1475 /* allocate RAM */
1476 if ((uint64_t)RAM_size > hwdef->max_mem) {
1477 fprintf(stderr,
1478 "qemu: Too much memory for this machine: %d, maximum %d\n",
1479 (unsigned int)(RAM_size / (1024 * 1024)),
1480 (unsigned int)(hwdef->max_mem / (1024 * 1024)));
1481 exit(1);
1482 }
1483 ram_offset = qemu_ram_alloc(RAM_size);
1484 cpu_register_physical_memory(0, RAM_size, ram_offset);
1485
1486 /* load boot prom */
1487 prom_offset = qemu_ram_alloc(PROM_SIZE_MAX);
1488 cpu_register_physical_memory(hwdef->slavio_base,
1489 (PROM_SIZE_MAX + TARGET_PAGE_SIZE - 1) &
1490 TARGET_PAGE_MASK,
1491 prom_offset | IO_MEM_ROM);
1492
1493 if (bios_name == NULL)
1494 bios_name = PROM_FILENAME;
1495 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
1496 if (filename) {
1497 ret = load_elf(filename, hwdef->slavio_base - PROM_VADDR,
1498 NULL, NULL, NULL);
1499 if (ret < 0 || ret > PROM_SIZE_MAX)
1500 ret = load_image_targphys(filename, hwdef->slavio_base,
1501 PROM_SIZE_MAX);
1502 qemu_free(filename);
1503 } else {
1504 ret = -1;
1505 }
1506 if (ret < 0 || ret > PROM_SIZE_MAX) {
1507 fprintf(stderr, "qemu: could not load prom '%s'\n",
1508 filename);
1509 exit(1);
1510 }
1511
1512 /* set up devices */
1513 slavio_intctl = sun4c_intctl_init(hwdef->intctl_base,
1514 &slavio_irq, cpu_irqs);
1515
1516 iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version,
1517 slavio_irq[hwdef->me_irq]);
1518
1519 espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[hwdef->esp_irq],
1520 iommu, &espdma_irq, &esp_reset);
1521
1522 ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
1523 slavio_irq[hwdef->le_irq], iommu, &ledma_irq,
1524 &le_reset);
1525
1526 if (graphic_depth != 8 && graphic_depth != 24) {
1527 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
1528 exit (1);
1529 }
1530 tcx_init(hwdef->tcx_base, hwdef->vram_size, graphic_width, graphic_height,
1531 graphic_depth);
1532
1533 lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq, le_reset);
1534
1535 nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0,
1536 hwdef->nvram_size, 2);
1537
1538 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[hwdef->ms_kb_irq],
1539 display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
1540 // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
1541 // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
1542 escc_init(hwdef->serial_base, slavio_irq[hwdef->ser_irq],
1543 slavio_irq[hwdef->ser_irq], serial_hds[0], serial_hds[1],
1544 ESCC_CLOCK, 1);
1545
1546 slavio_misc = slavio_misc_init(0, hwdef->aux1_base, 0,
1547 slavio_irq[hwdef->me_irq], fdc_tc);
1548
1549 if (hwdef->fd_base != (target_phys_addr_t)-1) {
1550 /* there is zero or one floppy drive */
1551 memset(fd, 0, sizeof(fd));
1552 drive_index = drive_get_index(IF_FLOPPY, 0, 0);
1553 if (drive_index != -1)
1554 fd[0] = drives_table[drive_index].bdrv;
1555
1556 sun4m_fdctrl_init(slavio_irq[hwdef->fd_irq], hwdef->fd_base, fd,
1557 &fdc_tc);
1558 }
1559
1560 if (drive_get_max_bus(IF_SCSI) > 0) {
1561 fprintf(stderr, "qemu: too many SCSI bus\n");
1562 exit(1);
1563 }
1564
1565 esp_init(hwdef->esp_base, 2,
1566 espdma_memory_read, espdma_memory_write,
1567 espdma, espdma_irq, esp_reset);
1568
1569 kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
1570 RAM_size);
1571
1572 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
1573 boot_device, RAM_size, kernel_size, graphic_width,
1574 graphic_height, graphic_depth, hwdef->nvram_machine_id,
1575 "Sun4c");
1576
1577 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
1578 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
1579 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
1580 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
1581 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
1582 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
1583 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
1584 if (kernel_cmdline) {
1585 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
1586 pstrcpy_targphys(CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
1587 } else {
1588 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
1589 }
1590 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
1591 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
1592 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
1593 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
1594 }
1595
1596 /* SPARCstation 2 hardware initialisation */
1597 static void ss2_init(ram_addr_t RAM_size,
1598 const char *boot_device,
1599 const char *kernel_filename, const char *kernel_cmdline,
1600 const char *initrd_filename, const char *cpu_model)
1601 {
1602 sun4c_hw_init(&sun4c_hwdefs[0], RAM_size, boot_device, kernel_filename,
1603 kernel_cmdline, initrd_filename, cpu_model);
1604 }
1605
1606 static QEMUMachine ss2_machine = {
1607 .name = "SS-2",
1608 .desc = "Sun4c platform, SPARCstation 2",
1609 .init = ss2_init,
1610 .use_scsi = 1,
1611 };
1612
1613 static void ss2_machine_init(void)
1614 {
1615 qemu_register_machine(&ss5_machine);
1616 qemu_register_machine(&ss10_machine);
1617 qemu_register_machine(&ss600mp_machine);
1618 qemu_register_machine(&ss20_machine);
1619 qemu_register_machine(&voyager_machine);
1620 qemu_register_machine(&ss_lx_machine);
1621 qemu_register_machine(&ss4_machine);
1622 qemu_register_machine(&scls_machine);
1623 qemu_register_machine(&sbook_machine);
1624 qemu_register_machine(&ss1000_machine);
1625 qemu_register_machine(&ss2000_machine);
1626 qemu_register_machine(&ss2_machine);
1627 }
1628
1629 machine_init(ss2_machine_init);
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