target-i386/cpu.h

   1 /*
   2  * i386 virtual CPU header
   3  *
   4  *  Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  19  */
  20 #ifndef CPU_I386_H
  21 #define CPU_I386_H
  22
  23 #include "config.h"
  24
  25 #ifdef TARGET_X86_64
  26 #define TARGET_LONG_BITS 64
  27 #else
  28 #define TARGET_LONG_BITS 32
  29 #endif
  30
  31 /* target supports implicit self modifying code */
  32 #define TARGET_HAS_SMC
  33 /* support for self modifying code even if the modified instruction is
  34    close to the modifying instruction */
  35 #define TARGET_HAS_PRECISE_SMC
  36
  37 #define TARGET_HAS_ICE 1
  38
  39 #ifdef TARGET_X86_64
  40 #define ELF_MACHINE     EM_X86_64
  41 #else
  42 #define ELF_MACHINE     EM_386
  43 #endif
  44
  45 #include "cpu-defs.h"
  46
  47 #include "softfloat.h"
  48
  49 #define R_EAX 0
  50 #define R_ECX 1
  51 #define R_EDX 2
  52 #define R_EBX 3
  53 #define R_ESP 4
  54 #define R_EBP 5
  55 #define R_ESI 6
  56 #define R_EDI 7
  57
  58 #define R_AL 0
  59 #define R_CL 1
  60 #define R_DL 2
  61 #define R_BL 3
  62 #define R_AH 4
  63 #define R_CH 5
  64 #define R_DH 6
  65 #define R_BH 7
  66
  67 #define R_ES 0
  68 #define R_CS 1
  69 #define R_SS 2
  70 #define R_DS 3
  71 #define R_FS 4
  72 #define R_GS 5
  73
  74 /* segment descriptor fields */
  75 #define DESC_G_MASK     (1 << 23)
  76 #define DESC_B_SHIFT    22
  77 #define DESC_B_MASK     (1 << DESC_B_SHIFT)
  78 #define DESC_L_SHIFT    21 /* x86_64 only : 64 bit code segment */
  79 #define DESC_L_MASK     (1 << DESC_L_SHIFT)
  80 #define DESC_AVL_MASK   (1 << 20)
  81 #define DESC_P_MASK     (1 << 15)
  82 #define DESC_DPL_SHIFT  13
  83 #define DESC_DPL_MASK   (1 << DESC_DPL_SHIFT)
  84 #define DESC_S_MASK     (1 << 12)
  85 #define DESC_TYPE_SHIFT 8
  86 #define DESC_A_MASK     (1 << 8)
  87
  88 #define DESC_CS_MASK    (1 << 11) /* 1=code segment 0=data segment */
  89 #define DESC_C_MASK     (1 << 10) /* code: conforming */
  90 #define DESC_R_MASK     (1 << 9)  /* code: readable */
  91
  92 #define DESC_E_MASK     (1 << 10) /* data: expansion direction */
  93 #define DESC_W_MASK     (1 << 9)  /* data: writable */
  94
  95 #define DESC_TSS_BUSY_MASK (1 << 9)
  96
  97 /* eflags masks */
  98 #define CC_C    0x0001
  99 #define CC_P    0x0004
 100 #define CC_A    0x0010
 101 #define CC_Z    0x0040
 102 #define CC_S    0x0080
 103 #define CC_O    0x0800
 104
 105 #define TF_SHIFT   8
 106 #define IOPL_SHIFT 12
 107 #define VM_SHIFT   17
 108
 109 #define TF_MASK                 0x00000100
 110 #define IF_MASK                 0x00000200
 111 #define DF_MASK                 0x00000400
 112 #define IOPL_MASK               0x00003000
 113 #define NT_MASK                 0x00004000
 114 #define RF_MASK                 0x00010000
 115 #define VM_MASK                 0x00020000
 116 #define AC_MASK                 0x00040000
 117 #define VIF_MASK                0x00080000
 118 #define VIP_MASK                0x00100000
 119 #define ID_MASK                 0x00200000
 120
 121 /* hidden flags - used internally by qemu to represent additional cpu
 122    states. Only the CPL, INHIBIT_IRQ and HALTED are not redundant. We avoid
 123    using the IOPL_MASK, TF_MASK and VM_MASK bit position to ease oring
 124    with eflags. */
 125 /* current cpl */
 126 #define HF_CPL_SHIFT         0
 127 /* true if soft mmu is being used */
 128 #define HF_SOFTMMU_SHIFT     2
 129 /* true if hardware interrupts must be disabled for next instruction */
 130 #define HF_INHIBIT_IRQ_SHIFT 3
 131 /* 16 or 32 segments */
 132 #define HF_CS32_SHIFT        4
 133 #define HF_SS32_SHIFT        5
 134 /* zero base for DS, ES and SS : can be '0' only in 32 bit CS segment */
 135 #define HF_ADDSEG_SHIFT      6
 136 /* copy of CR0.PE (protected mode) */
 137 #define HF_PE_SHIFT          7
 138 #define HF_TF_SHIFT          8 /* must be same as eflags */
 139 #define HF_MP_SHIFT          9 /* the order must be MP, EM, TS */
 140 #define HF_EM_SHIFT         10
 141 #define HF_TS_SHIFT         11
 142 #define HF_IOPL_SHIFT       12 /* must be same as eflags */
 143 #define HF_LMA_SHIFT        14 /* only used on x86_64: long mode active */
 144 #define HF_CS64_SHIFT       15 /* only used on x86_64: 64 bit code segment  */
 145 #define HF_OSFXSR_SHIFT     16 /* CR4.OSFXSR */
 146 #define HF_VM_SHIFT         17 /* must be same as eflags */
 147 #define HF_HALTED_SHIFT     18 /* CPU halted */
 148 #define HF_SMM_SHIFT        19 /* CPU in SMM mode */
 149 #define HF_GIF_SHIFT        20 /* if set CPU takes interrupts */
 150 #define HF_HIF_SHIFT        21 /* shadow copy of IF_MASK when in SVM */
 151
 152 #define HF_CPL_MASK          (3 << HF_CPL_SHIFT)
 153 #define HF_SOFTMMU_MASK      (1 << HF_SOFTMMU_SHIFT)
 154 #define HF_INHIBIT_IRQ_MASK  (1 << HF_INHIBIT_IRQ_SHIFT)
 155 #define HF_CS32_MASK         (1 << HF_CS32_SHIFT)
 156 #define HF_SS32_MASK         (1 << HF_SS32_SHIFT)
 157 #define HF_ADDSEG_MASK       (1 << HF_ADDSEG_SHIFT)
 158 #define HF_PE_MASK           (1 << HF_PE_SHIFT)
 159 #define HF_TF_MASK           (1 << HF_TF_SHIFT)
 160 #define HF_MP_MASK           (1 << HF_MP_SHIFT)
 161 #define HF_EM_MASK           (1 << HF_EM_SHIFT)
 162 #define HF_TS_MASK           (1 << HF_TS_SHIFT)
 163 #define HF_IOPL_MASK         (3 << HF_IOPL_SHIFT)
 164 #define HF_LMA_MASK          (1 << HF_LMA_SHIFT)
 165 #define HF_CS64_MASK         (1 << HF_CS64_SHIFT)
 166 #define HF_OSFXSR_MASK       (1 << HF_OSFXSR_SHIFT)
 167 #define HF_VM_MASK           (1 << HF_VM_SHIFT)
 168 #define HF_HALTED_MASK       (1 << HF_HALTED_SHIFT)
 169 #define HF_SMM_MASK          (1 << HF_SMM_SHIFT)
 170 #define HF_GIF_MASK          (1 << HF_GIF_SHIFT)
 171 #define HF_HIF_MASK          (1 << HF_HIF_SHIFT)
 172
 173 #define CR0_PE_SHIFT 0
 174 #define CR0_MP_SHIFT 1
 175
 176 #define CR0_PE_MASK  (1 << 0)
 177 #define CR0_MP_MASK  (1 << 1)
 178 #define CR0_EM_MASK  (1 << 2)
 179 #define CR0_TS_MASK  (1 << 3)
 180 #define CR0_ET_MASK  (1 << 4)
 181 #define CR0_NE_MASK  (1 << 5)
 182 #define CR0_WP_MASK  (1 << 16)
 183 #define CR0_AM_MASK  (1 << 18)
 184 #define CR0_PG_MASK  (1 << 31)
 185
 186 #define CR4_VME_MASK  (1 << 0)
 187 #define CR4_PVI_MASK  (1 << 1)
 188 #define CR4_TSD_MASK  (1 << 2)
 189 #define CR4_DE_MASK   (1 << 3)
 190 #define CR4_PSE_MASK  (1 << 4)
 191 #define CR4_PAE_MASK  (1 << 5)
 192 #define CR4_PGE_MASK  (1 << 7)
 193 #define CR4_PCE_MASK  (1 << 8)
 194 #define CR4_OSFXSR_SHIFT 9
 195 #define CR4_OSFXSR_MASK (1 << CR4_OSFXSR_SHIFT)
 196 #define CR4_OSXMMEXCPT_MASK  (1 << 10)
 197
 198 #define PG_PRESENT_BIT  0
 199 #define PG_RW_BIT       1
 200 #define PG_USER_BIT     2
 201 #define PG_PWT_BIT      3
 202 #define PG_PCD_BIT      4
 203 #define PG_ACCESSED_BIT 5
 204 #define PG_DIRTY_BIT    6
 205 #define PG_PSE_BIT      7
 206 #define PG_GLOBAL_BIT   8
 207 #define PG_NX_BIT       63
 208
 209 #define PG_PRESENT_MASK  (1 << PG_PRESENT_BIT)
 210 #define PG_RW_MASK       (1 << PG_RW_BIT)
 211 #define PG_USER_MASK     (1 << PG_USER_BIT)
 212 #define PG_PWT_MASK      (1 << PG_PWT_BIT)
 213 #define PG_PCD_MASK      (1 << PG_PCD_BIT)
 214 #define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT)
 215 #define PG_DIRTY_MASK    (1 << PG_DIRTY_BIT)
 216 #define PG_PSE_MASK      (1 << PG_PSE_BIT)
 217 #define PG_GLOBAL_MASK   (1 << PG_GLOBAL_BIT)
 218 #define PG_NX_MASK       (1LL << PG_NX_BIT)
 219
 220 #define PG_ERROR_W_BIT     1
 221
 222 #define PG_ERROR_P_MASK    0x01
 223 #define PG_ERROR_W_MASK    (1 << PG_ERROR_W_BIT)
 224 #define PG_ERROR_U_MASK    0x04
 225 #define PG_ERROR_RSVD_MASK 0x08
 226 #define PG_ERROR_I_D_MASK  0x10
 227
 228 #define MSR_IA32_APICBASE               0x1b
 229 #define MSR_IA32_APICBASE_BSP           (1<<8)
 230 #define MSR_IA32_APICBASE_ENABLE        (1<<11)
 231 #define MSR_IA32_APICBASE_BASE          (0xfffff<<12)
 232
 233 #define MSR_IA32_SYSENTER_CS            0x174
 234 #define MSR_IA32_SYSENTER_ESP           0x175
 235 #define MSR_IA32_SYSENTER_EIP           0x176
 236
 237 #define MSR_MCG_CAP                     0x179
 238 #define MSR_MCG_STATUS                  0x17a
 239 #define MSR_MCG_CTL                     0x17b
 240
 241 #define MSR_PAT                         0x277
 242
 243 #define MSR_EFER                        0xc0000080
 244
 245 #define MSR_EFER_SCE   (1 << 0)
 246 #define MSR_EFER_LME   (1 << 8)
 247 #define MSR_EFER_LMA   (1 << 10)
 248 #define MSR_EFER_NXE   (1 << 11)
 249 #define MSR_EFER_FFXSR (1 << 14)
 250
 251 #define MSR_STAR                        0xc0000081
 252 #define MSR_LSTAR                       0xc0000082
 253 #define MSR_CSTAR                       0xc0000083
 254 #define MSR_FMASK                       0xc0000084
 255 #define MSR_FSBASE                      0xc0000100
 256 #define MSR_GSBASE                      0xc0000101
 257 #define MSR_KERNELGSBASE                0xc0000102
 258
 259 #define MSR_VM_HSAVE_PA                 0xc0010117
 260
 261 /* cpuid_features bits */
 262 #define CPUID_FP87 (1 << 0)
 263 #define CPUID_VME  (1 << 1)
 264 #define CPUID_DE   (1 << 2)
 265 #define CPUID_PSE  (1 << 3)
 266 #define CPUID_TSC  (1 << 4)
 267 #define CPUID_MSR  (1 << 5)
 268 #define CPUID_PAE  (1 << 6)
 269 #define CPUID_MCE  (1 << 7)
 270 #define CPUID_CX8  (1 << 8)
 271 #define CPUID_APIC (1 << 9)
 272 #define CPUID_SEP  (1 << 11) /* sysenter/sysexit */
 273 #define CPUID_MTRR (1 << 12)
 274 #define CPUID_PGE  (1 << 13)
 275 #define CPUID_MCA  (1 << 14)
 276 #define CPUID_CMOV (1 << 15)
 277 #define CPUID_PAT  (1 << 16)
 278 #define CPUID_PSE36   (1 << 17)
 279 #define CPUID_PN   (1 << 18)
 280 #define CPUID_CLFLUSH (1 << 19)
 281 #define CPUID_DTS (1 << 21)
 282 #define CPUID_ACPI (1 << 22)
 283 #define CPUID_MMX  (1 << 23)
 284 #define CPUID_FXSR (1 << 24)
 285 #define CPUID_SSE  (1 << 25)
 286 #define CPUID_SSE2 (1 << 26)
 287 #define CPUID_SS (1 << 27)
 288 #define CPUID_HT (1 << 28)
 289 #define CPUID_TM (1 << 29)
 290 #define CPUID_IA64 (1 << 30)
 291 #define CPUID_PBE (1 << 31)
 292
 293 #define CPUID_EXT_SSE3     (1 << 0)
 294 #define CPUID_EXT_MONITOR  (1 << 3)
 295 #define CPUID_EXT_DSCPL    (1 << 4)
 296 #define CPUID_EXT_VMX      (1 << 5)
 297 #define CPUID_EXT_SMX      (1 << 6)
 298 #define CPUID_EXT_EST      (1 << 7)
 299 #define CPUID_EXT_TM2      (1 << 8)
 300 #define CPUID_EXT_SSSE3    (1 << 9)
 301 #define CPUID_EXT_CID      (1 << 10)
 302 #define CPUID_EXT_CX16     (1 << 13)
 303 #define CPUID_EXT_XTPR     (1 << 14)
 304 #define CPUID_EXT_DCA      (1 << 17)
 305 #define CPUID_EXT_POPCNT   (1 << 22)
 306
 307 #define CPUID_EXT2_SYSCALL (1 << 11)
 308 #define CPUID_EXT2_MP      (1 << 19)
 309 #define CPUID_EXT2_NX      (1 << 20)
 310 #define CPUID_EXT2_MMXEXT  (1 << 22)
 311 #define CPUID_EXT2_FFXSR   (1 << 25)
 312 #define CPUID_EXT2_PDPE1GB (1 << 26)
 313 #define CPUID_EXT2_RDTSCP  (1 << 27)
 314 #define CPUID_EXT2_LM      (1 << 29)
 315 #define CPUID_EXT2_3DNOWEXT (1 << 30)
 316 #define CPUID_EXT2_3DNOW   (1 << 31)
 317
 318 #define CPUID_EXT3_LAHF_LM (1 << 0)
 319 #define CPUID_EXT3_CMP_LEG (1 << 1)
 320 #define CPUID_EXT3_SVM     (1 << 2)
 321 #define CPUID_EXT3_EXTAPIC (1 << 3)
 322 #define CPUID_EXT3_CR8LEG  (1 << 4)
 323 #define CPUID_EXT3_ABM     (1 << 5)
 324 #define CPUID_EXT3_SSE4A   (1 << 6)
 325 #define CPUID_EXT3_MISALIGNSSE (1 << 7)
 326 #define CPUID_EXT3_3DNOWPREFETCH (1 << 8)
 327 #define CPUID_EXT3_OSVW    (1 << 9)
 328 #define CPUID_EXT3_IBS     (1 << 10)
 329
 330 #define EXCP00_DIVZ     0
 331 #define EXCP01_SSTP     1
 332 #define EXCP02_NMI      2
 333 #define EXCP03_INT3     3
 334 #define EXCP04_INTO     4
 335 #define EXCP05_BOUND    5
 336 #define EXCP06_ILLOP    6
 337 #define EXCP07_PREX     7
 338 #define EXCP08_DBLE     8
 339 #define EXCP09_XERR     9
 340 #define EXCP0A_TSS      10
 341 #define EXCP0B_NOSEG    11
 342 #define EXCP0C_STACK    12
 343 #define EXCP0D_GPF      13
 344 #define EXCP0E_PAGE     14
 345 #define EXCP10_COPR     16
 346 #define EXCP11_ALGN     17
 347 #define EXCP12_MCHK     18
 348
 349 #define EXCP_SYSCALL    0x100 /* only happens in user only emulation
 350                                  for syscall instruction */
 351
 352 enum {
 353     CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */
 354     CC_OP_EFLAGS,  /* all cc are explicitely computed, CC_SRC = flags */
 355
 356     CC_OP_MULB, /* modify all flags, C, O = (CC_SRC != 0) */
 357     CC_OP_MULW,
 358     CC_OP_MULL,
 359     CC_OP_MULQ,
 360
 361     CC_OP_ADDB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
 362     CC_OP_ADDW,
 363     CC_OP_ADDL,
 364     CC_OP_ADDQ,
 365
 366     CC_OP_ADCB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
 367     CC_OP_ADCW,
 368     CC_OP_ADCL,
 369     CC_OP_ADCQ,
 370
 371     CC_OP_SUBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
 372     CC_OP_SUBW,
 373     CC_OP_SUBL,
 374     CC_OP_SUBQ,
 375
 376     CC_OP_SBBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
 377     CC_OP_SBBW,
 378     CC_OP_SBBL,
 379     CC_OP_SBBQ,
 380
 381     CC_OP_LOGICB, /* modify all flags, CC_DST = res */
 382     CC_OP_LOGICW,
 383     CC_OP_LOGICL,
 384     CC_OP_LOGICQ,
 385
 386     CC_OP_INCB, /* modify all flags except, CC_DST = res, CC_SRC = C */
 387     CC_OP_INCW,
 388     CC_OP_INCL,
 389     CC_OP_INCQ,
 390
 391     CC_OP_DECB, /* modify all flags except, CC_DST = res, CC_SRC = C  */
 392     CC_OP_DECW,
 393     CC_OP_DECL,
 394     CC_OP_DECQ,
 395
 396     CC_OP_SHLB, /* modify all flags, CC_DST = res, CC_SRC.msb = C */
 397     CC_OP_SHLW,
 398     CC_OP_SHLL,
 399     CC_OP_SHLQ,
 400
 401     CC_OP_SARB, /* modify all flags, CC_DST = res, CC_SRC.lsb = C */
 402     CC_OP_SARW,
 403     CC_OP_SARL,
 404     CC_OP_SARQ,
 405
 406     CC_OP_NB,
 407 };
 408
 409 #ifdef FLOATX80
 410 #define USE_X86LDOUBLE
 411 #endif
 412
 413 #ifdef USE_X86LDOUBLE
 414 typedef floatx80 CPU86_LDouble;
 415 #else
 416 typedef float64 CPU86_LDouble;
 417 #endif
 418
 419 typedef struct SegmentCache {
 420     uint32_t selector;
 421     target_ulong base;
 422     uint32_t limit;
 423     uint32_t flags;
 424 } SegmentCache;
 425
 426 typedef union {
 427     uint8_t _b[16];
 428     uint16_t _w[8];
 429     uint32_t _l[4];
 430     uint64_t _q[2];
 431     float32 _s[4];
 432     float64 _d[2];
 433 } XMMReg;
 434
 435 typedef union {
 436     uint8_t _b[8];
 437     uint16_t _w[2];
 438     uint32_t _l[1];
 439     uint64_t q;
 440 } MMXReg;
 441
 442 #ifdef WORDS_BIGENDIAN
 443 #define XMM_B(n) _b[15 - (n)]
 444 #define XMM_W(n) _w[7 - (n)]
 445 #define XMM_L(n) _l[3 - (n)]
 446 #define XMM_S(n) _s[3 - (n)]
 447 #define XMM_Q(n) _q[1 - (n)]
 448 #define XMM_D(n) _d[1 - (n)]
 449
 450 #define MMX_B(n) _b[7 - (n)]
 451 #define MMX_W(n) _w[3 - (n)]
 452 #define MMX_L(n) _l[1 - (n)]
 453 #else
 454 #define XMM_B(n) _b[n]
 455 #define XMM_W(n) _w[n]
 456 #define XMM_L(n) _l[n]
 457 #define XMM_S(n) _s[n]
 458 #define XMM_Q(n) _q[n]
 459 #define XMM_D(n) _d[n]
 460
 461 #define MMX_B(n) _b[n]
 462 #define MMX_W(n) _w[n]
 463 #define MMX_L(n) _l[n]
 464 #endif
 465 #define MMX_Q(n) q
 466
 467 #ifdef TARGET_X86_64
 468 #define CPU_NB_REGS 16
 469 #else
 470 #define CPU_NB_REGS 8
 471 #endif
 472
 473 #define NB_MMU_MODES 2
 474
 475 typedef struct CPUX86State {
 476 #if TARGET_LONG_BITS > HOST_LONG_BITS
 477     /* temporaries if we cannot store them in host registers */
 478     target_ulong t0, t1, t2;
 479 #endif
 480
 481     /* standard registers */
 482     target_ulong regs[CPU_NB_REGS];
 483     target_ulong eip;
 484     target_ulong eflags; /* eflags register. During CPU emulation, CC
 485                         flags and DF are set to zero because they are
 486                         stored elsewhere */
 487
 488     /* emulator internal eflags handling */
 489     target_ulong cc_src;
 490     target_ulong cc_dst;
 491     uint32_t cc_op;
 492     int32_t df; /* D flag : 1 if D = 0, -1 if D = 1 */
 493     uint32_t hflags; /* hidden flags, see HF_xxx constants */
 494
 495     /* segments */
 496     SegmentCache segs[6]; /* selector values */
 497     SegmentCache ldt;
 498     SegmentCache tr;
 499     SegmentCache gdt; /* only base and limit are used */
 500     SegmentCache idt; /* only base and limit are used */
 501
 502     target_ulong cr[5]; /* NOTE: cr1 is unused */
 503     uint32_t a20_mask;
 504
 505     /* FPU state */
 506     unsigned int fpstt; /* top of stack index */
 507     unsigned int fpus;
 508     unsigned int fpuc;
 509     uint8_t fptags[8];   /* 0 = valid, 1 = empty */
 510     union {
 511 #ifdef USE_X86LDOUBLE
 512         CPU86_LDouble d __attribute__((aligned(16)));
 513 #else
 514         CPU86_LDouble d;
 515 #endif
 516         MMXReg mmx;
 517     } fpregs[8];
 518
 519     /* emulator internal variables */
 520     float_status fp_status;
 521     CPU86_LDouble ft0;
 522     union {
 523         float f;
 524         double d;
 525         int i32;
 526         int64_t i64;
 527     } fp_convert;
 528
 529     float_status sse_status;
 530     uint32_t mxcsr;
 531     XMMReg xmm_regs[CPU_NB_REGS];
 532     XMMReg xmm_t0;
 533     MMXReg mmx_t0;
 534
 535     /* sysenter registers */
 536     uint32_t sysenter_cs;
 537     uint32_t sysenter_esp;
 538     uint32_t sysenter_eip;
 539     uint64_t efer;
 540     uint64_t star;
 541
 542     target_phys_addr_t vm_hsave;
 543     target_phys_addr_t vm_vmcb;
 544     uint64_t intercept;
 545     uint16_t intercept_cr_read;
 546     uint16_t intercept_cr_write;
 547     uint16_t intercept_dr_read;
 548     uint16_t intercept_dr_write;
 549     uint32_t intercept_exceptions;
 550
 551 #ifdef TARGET_X86_64
 552     target_ulong lstar;
 553     target_ulong cstar;
 554     target_ulong fmask;
 555     target_ulong kernelgsbase;
 556 #endif
 557
 558     uint64_t tsc; /* time stamp counter */
 559     uint8_t ready_for_interrupt_injection;
 560     uint64_t pat;
 561
 562     /* exception/interrupt handling */
 563     jmp_buf jmp_env;
 564     int exception_index;
 565     int error_code;
 566     int exception_is_int;
 567     target_ulong exception_next_eip;
 568     target_ulong dr[8]; /* debug registers */
 569     uint32_t smbase;
 570     int interrupt_request;
 571     int user_mode_only; /* user mode only simulation */
 572     int old_exception;  /* exception in flight */
 573
 574     CPU_COMMON
 575
 576     /* processor features (e.g. for CPUID insn) */
 577     uint32_t cpuid_level;
 578     uint32_t cpuid_vendor1;
 579     uint32_t cpuid_vendor2;
 580     uint32_t cpuid_vendor3;
 581     uint32_t cpuid_version;
 582     uint32_t cpuid_features;
 583     uint32_t cpuid_ext_features;
 584     uint32_t cpuid_xlevel;
 585     uint32_t cpuid_model[12];
 586     uint32_t cpuid_ext2_features;
 587     uint32_t cpuid_ext3_features;
 588     uint32_t cpuid_apic_id;
 589
 590 #ifdef USE_KQEMU
 591     int kqemu_enabled;
 592     int last_io_time;
 593 #endif
 594
 595 #define BITS_PER_LONG (8 * sizeof (uint32_t))
 596 #define NR_IRQ_WORDS (256/ BITS_PER_LONG)
 597     uint32_t kvm_interrupt_bitmap[NR_IRQ_WORDS];
 598
 599     /* in order to simplify APIC support, we leave this pointer to the
 600        user */
 601     struct APICState *apic_state;
 602 } CPUX86State;
 603
 604 CPUX86State *cpu_x86_init(const char *cpu_model);
 605 int cpu_x86_exec(CPUX86State *s);
 606 void cpu_x86_close(CPUX86State *s);
 607 void x86_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt,
 608                                                  ...));
 609 int cpu_get_pic_interrupt(CPUX86State *s);
 610 /* MSDOS compatibility mode FPU exception support */
 611 void cpu_set_ferr(CPUX86State *s);
 612
 613 /* this function must always be used to load data in the segment
 614    cache: it synchronizes the hflags with the segment cache values */
 615 static inline void cpu_x86_load_seg_cache(CPUX86State *env,
 616                                           int seg_reg, unsigned int selector,
 617                                           target_ulong base,
 618                                           unsigned int limit,
 619                                           unsigned int flags)
 620 {
 621     SegmentCache *sc;
 622     unsigned int new_hflags;
 623
 624     sc = &env->segs[seg_reg];
 625     sc->selector = selector;
 626     sc->base = base;
 627     sc->limit = limit;
 628     sc->flags = flags;
 629
 630     /* update the hidden flags */
 631     {
 632         if (seg_reg == R_CS) {
 633 #ifdef TARGET_X86_64
 634             if ((env->hflags & HF_LMA_MASK) && (flags & DESC_L_MASK)) {
 635                 /* long mode */
 636                 env->hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
 637                 env->hflags &= ~(HF_ADDSEG_MASK);
 638             } else
 639 #endif
 640             {
 641                 /* legacy / compatibility case */
 642                 new_hflags = (env->segs[R_CS].flags & DESC_B_MASK)
 643                     >> (DESC_B_SHIFT - HF_CS32_SHIFT);
 644                 env->hflags = (env->hflags & ~(HF_CS32_MASK | HF_CS64_MASK)) |
 645                     new_hflags;
 646             }
 647         }
 648         new_hflags = (env->segs[R_SS].flags & DESC_B_MASK)
 649             >> (DESC_B_SHIFT - HF_SS32_SHIFT);
 650         if (env->hflags & HF_CS64_MASK) {
 651             /* zero base assumed for DS, ES and SS in long mode */
 652         } else if (!(env->cr[0] & CR0_PE_MASK) ||
 653                    (env->eflags & VM_MASK) ||
 654                    !(env->hflags & HF_CS32_MASK)) {
 655             /* XXX: try to avoid this test. The problem comes from the
 656                fact that is real mode or vm86 mode we only modify the
 657                'base' and 'selector' fields of the segment cache to go
 658                faster. A solution may be to force addseg to one in
 659                translate-i386.c. */
 660             new_hflags |= HF_ADDSEG_MASK;
 661         } else {
 662             new_hflags |= ((env->segs[R_DS].base |
 663                             env->segs[R_ES].base |
 664                             env->segs[R_SS].base) != 0) <<
 665                 HF_ADDSEG_SHIFT;
 666         }
 667         env->hflags = (env->hflags &
 668                        ~(HF_SS32_MASK | HF_ADDSEG_MASK)) | new_hflags;
 669     }
 670 }
 671
 672 /* wrapper, just in case memory mappings must be changed */
 673 static inline void cpu_x86_set_cpl(CPUX86State *s, int cpl)
 674 {
 675 #if HF_CPL_MASK == 3
 676     s->hflags = (s->hflags & ~HF_CPL_MASK) | cpl;
 677 #else
 678 #error HF_CPL_MASK is hardcoded
 679 #endif
 680 }
 681
 682 /* used for debug or cpu save/restore */
 683 void cpu_get_fp80(uint64_t *pmant, uint16_t *pexp, CPU86_LDouble f);
 684 CPU86_LDouble cpu_set_fp80(uint64_t mant, uint16_t upper);
 685
 686 /* the following helpers are only usable in user mode simulation as
 687    they can trigger unexpected exceptions */
 688 void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector);
 689 void cpu_x86_fsave(CPUX86State *s, target_ulong ptr, int data32);
 690 void cpu_x86_frstor(CPUX86State *s, target_ulong ptr, int data32);
 691
 692 /* you can call this signal handler from your SIGBUS and SIGSEGV
 693    signal handlers to inform the virtual CPU of exceptions. non zero
 694    is returned if the signal was handled by the virtual CPU.  */
 695 int cpu_x86_signal_handler(int host_signum, void *pinfo,
 696                            void *puc);
 697 void cpu_x86_set_a20(CPUX86State *env, int a20_state);
 698
 699 uint64_t cpu_get_tsc(CPUX86State *env);
 700
 701 void cpu_set_apic_base(CPUX86State *env, uint64_t val);
 702 uint64_t cpu_get_apic_base(CPUX86State *env);
 703 void cpu_set_apic_tpr(CPUX86State *env, uint8_t val);
 704 #ifndef NO_CPU_IO_DEFS
 705 uint8_t cpu_get_apic_tpr(CPUX86State *env);
 706 #endif
 707 void cpu_smm_update(CPUX86State *env);
 708
 709 /* will be suppressed */
 710 void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0);
 711
 712 /* used to debug */
 713 #define X86_DUMP_FPU  0x0001 /* dump FPU state too */
 714 #define X86_DUMP_CCOP 0x0002 /* dump qemu flag cache */
 715
 716 #ifdef USE_KQEMU
 717 static inline int cpu_get_time_fast(void)
 718 {
 719     int low, high;
 720     asm volatile("rdtsc" : "=a" (low), "=d" (high));
 721     return low;
 722 }
 723 #endif
 724
 725 #define TARGET_PAGE_BITS 12
 726
 727 #define CPUState CPUX86State
 728 #define cpu_init cpu_x86_init
 729 #define cpu_exec cpu_x86_exec
 730 #define cpu_gen_code cpu_x86_gen_code
 731 #define cpu_signal_handler cpu_x86_signal_handler
 732 #define cpu_list x86_cpu_list
 733
 734 /* MMU modes definitions */
 735 #define MMU_MODE0_SUFFIX _kernel
 736 #define MMU_MODE1_SUFFIX _user
 737 #define MMU_USER_IDX 1
 738 static inline int cpu_mmu_index (CPUState *env)
 739 {
 740     return (env->hflags & HF_CPL_MASK) == 3 ? 1 : 0;
 741 }
 742
 743 #include "cpu-all.h"
 744
 745 #include "svm.h"
 746
 747 #endif /* CPU_I386_H */