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Fix timer rearm fallout from last qemu merge
[qemu-kvm/fedora.git] / cris-dis.c
blob3b09f2767648ac76374842e23cb0ee00786091ec
1 /* Disassembler code for CRIS.
2 Copyright 2000, 2001, 2002, 2004, 2005, 2006 Free Software Foundation, Inc.
3 Contributed by Axis Communications AB, Lund, Sweden.
4 Written by Hans-Peter Nilsson.
5
6 This file is part of the GNU binutils and GDB, the GNU debugger.
7
8 This program is free software; you can redistribute it and/or modify it
9 under the terms of the GNU General Public License as published by the
10 Free Software Foundation; either version 2, or (at your option) any later
11 version.
12
13 This program is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
21 MA 02110-1301, USA. */
22
23 #include "dis-asm.h"
24 //#include "sysdep.h"
25 #include "target-cris/opcode-cris.h"
26 //#include "libiberty.h"
27 \f
28
29 #define FALSE 0
30 #define TRUE 1
31 #define CONST_STRNEQ(STR1,STR2) (strncmp ((STR1), (STR2), sizeof (STR2) - 1) == 0)
32
33 /* cris-opc.c -- Table of opcodes for the CRIS processor.
34 Copyright 2000, 2001, 2004 Free Software Foundation, Inc.
35 Contributed by Axis Communications AB, Lund, Sweden.
36 Originally written for GAS 1.38.1 by Mikael Asker.
37 Reorganized by Hans-Peter Nilsson.
38
39 This file is part of GAS, GDB and the GNU binutils.
40
41 GAS, GDB, and GNU binutils is free software; you can redistribute it
42 and/or modify it under the terms of the GNU General Public License as
43 published by the Free Software Foundation; either version 2, or (at your
44 option) any later version.
45
46 GAS, GDB, and GNU binutils are distributed in the hope that they will be
47 useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
48 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
49 GNU General Public License for more details.
50
51 You should have received a copy of the GNU General Public License
52 along with this program; if not, write to the Free Software
53 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
54
55 #ifndef NULL
56 #define NULL (0)
57 #endif
58
59 /* This table isn't used for CRISv32 and the size of immediate operands. */
60 const struct cris_spec_reg
61 cris_spec_regs[] =
62 {
63 {"bz", 0, 1, cris_ver_v32p, NULL},
64 {"p0", 0, 1, 0, NULL},
65 {"vr", 1, 1, 0, NULL},
66 {"p1", 1, 1, 0, NULL},
67 {"pid", 2, 1, cris_ver_v32p, NULL},
68 {"p2", 2, 1, cris_ver_v32p, NULL},
69 {"p2", 2, 1, cris_ver_warning, NULL},
70 {"srs", 3, 1, cris_ver_v32p, NULL},
71 {"p3", 3, 1, cris_ver_v32p, NULL},
72 {"p3", 3, 1, cris_ver_warning, NULL},
73 {"wz", 4, 2, cris_ver_v32p, NULL},
74 {"p4", 4, 2, 0, NULL},
75 {"ccr", 5, 2, cris_ver_v0_10, NULL},
76 {"exs", 5, 4, cris_ver_v32p, NULL},
77 {"p5", 5, 2, cris_ver_v0_10, NULL},
78 {"p5", 5, 4, cris_ver_v32p, NULL},
79 {"dcr0",6, 2, cris_ver_v0_3, NULL},
80 {"eda", 6, 4, cris_ver_v32p, NULL},
81 {"p6", 6, 2, cris_ver_v0_3, NULL},
82 {"p6", 6, 4, cris_ver_v32p, NULL},
83 {"dcr1/mof", 7, 4, cris_ver_v10p,
84 "Register `dcr1/mof' with ambiguous size specified. Guessing 4 bytes"},
85 {"dcr1/mof", 7, 2, cris_ver_v0_3,
86 "Register `dcr1/mof' with ambiguous size specified. Guessing 2 bytes"},
87 {"mof", 7, 4, cris_ver_v10p, NULL},
88 {"dcr1",7, 2, cris_ver_v0_3, NULL},
89 {"p7", 7, 4, cris_ver_v10p, NULL},
90 {"p7", 7, 2, cris_ver_v0_3, NULL},
91 {"dz", 8, 4, cris_ver_v32p, NULL},
92 {"p8", 8, 4, 0, NULL},
93 {"ibr", 9, 4, cris_ver_v0_10, NULL},
94 {"ebp", 9, 4, cris_ver_v32p, NULL},
95 {"p9", 9, 4, 0, NULL},
96 {"irp", 10, 4, cris_ver_v0_10, NULL},
97 {"erp", 10, 4, cris_ver_v32p, NULL},
98 {"p10", 10, 4, 0, NULL},
99 {"srp", 11, 4, 0, NULL},
100 {"p11", 11, 4, 0, NULL},
101 /* For disassembly use only. Accept at assembly with a warning. */
102 {"bar/dtp0", 12, 4, cris_ver_warning,
103 "Ambiguous register `bar/dtp0' specified"},
104 {"nrp", 12, 4, cris_ver_v32p, NULL},
105 {"bar", 12, 4, cris_ver_v8_10, NULL},
106 {"dtp0",12, 4, cris_ver_v0_3, NULL},
107 {"p12", 12, 4, 0, NULL},
108 /* For disassembly use only. Accept at assembly with a warning. */
109 {"dccr/dtp1",13, 4, cris_ver_warning,
110 "Ambiguous register `dccr/dtp1' specified"},
111 {"ccs", 13, 4, cris_ver_v32p, NULL},
112 {"dccr",13, 4, cris_ver_v8_10, NULL},
113 {"dtp1",13, 4, cris_ver_v0_3, NULL},
114 {"p13", 13, 4, 0, NULL},
115 {"brp", 14, 4, cris_ver_v3_10, NULL},
116 {"usp", 14, 4, cris_ver_v32p, NULL},
117 {"p14", 14, 4, cris_ver_v3p, NULL},
118 {"usp", 15, 4, cris_ver_v10, NULL},
119 {"spc", 15, 4, cris_ver_v32p, NULL},
120 {"p15", 15, 4, cris_ver_v10p, NULL},
121 {NULL, 0, 0, cris_ver_version_all, NULL}
122 };
123
124 /* Add version specifiers to this table when necessary.
125 The (now) regular coding of register names suggests a simpler
126 implementation. */
127 const struct cris_support_reg cris_support_regs[] =
128 {
129 {"s0", 0},
130 {"s1", 1},
131 {"s2", 2},
132 {"s3", 3},
133 {"s4", 4},
134 {"s5", 5},
135 {"s6", 6},
136 {"s7", 7},
137 {"s8", 8},
138 {"s9", 9},
139 {"s10", 10},
140 {"s11", 11},
141 {"s12", 12},
142 {"s13", 13},
143 {"s14", 14},
144 {"s15", 15},
145 {NULL, 0}
146 };
147
148 /* All CRIS opcodes are 16 bits.
149
150 - The match component is a mask saying which bits must match a
151 particular opcode in order for an instruction to be an instance
152 of that opcode.
153
154 - The args component is a string containing characters symbolically
155 matching the operands of an instruction. Used for both assembly
156 and disassembly.
157
158 Operand-matching characters:
159 [ ] , space
160 Verbatim.
161 A The string "ACR" (case-insensitive).
162 B Not really an operand. It causes a "BDAP -size,SP" prefix to be
163 output for the PUSH alias-instructions and recognizes a push-
164 prefix at disassembly. This letter isn't recognized for v32.
165 Must be followed by a R or P letter.
166 ! Non-match pattern, will not match if there's a prefix insn.
167 b Non-matching operand, used for branches with 16-bit
168 displacement. Only recognized by the disassembler.
169 c 5-bit unsigned immediate in bits <4:0>.
170 C 4-bit unsigned immediate in bits <3:0>.
171 d At assembly, optionally (as in put other cases before this one)
172 ".d" or ".D" at the start of the operands, followed by one space
173 character. At disassembly, nothing.
174 D General register in bits <15:12> and <3:0>.
175 f List of flags in bits <15:12> and <3:0>.
176 i 6-bit signed immediate in bits <5:0>.
177 I 6-bit unsigned immediate in bits <5:0>.
178 M Size modifier (B, W or D) for CLEAR instructions.
179 m Size modifier (B, W or D) in bits <5:4>
180 N A 32-bit dword, like in the difference between s and y.
181 This has no effect on bits in the opcode. Can also be expressed
182 as "[pc+]" in input.
183 n As N, but PC-relative (to the start of the instruction).
184 o [-128..127] word offset in bits <7:1> and <0>. Used by 8-bit
185 branch instructions.
186 O [-128..127] offset in bits <7:0>. Also matches a comma and a
187 general register after the expression, in bits <15:12>. Used
188 only for the BDAP prefix insn (in v32 the ADDOQ insn; same opcode).
189 P Special register in bits <15:12>.
190 p Indicates that the insn is a prefix insn. Must be first
191 character.
192 Q As O, but don't relax; force an 8-bit offset.
193 R General register in bits <15:12>.
194 r General register in bits <3:0>.
195 S Source operand in bit <10> and a prefix; a 3-operand prefix
196 without side-effect.
197 s Source operand in bits <10> and <3:0>, optionally with a
198 side-effect prefix, except [pc] (the name, not R15 as in ACR)
199 isn't allowed for v32 and higher.
200 T Support register in bits <15:12>.
201 u 4-bit (PC-relative) unsigned immediate word offset in bits <3:0>.
202 U Relaxes to either u or n, instruction is assumed LAPCQ or LAPC.
203 Not recognized at disassembly.
204 x Register-dot-modifier, for example "r5.w" in bits <15:12> and <5:4>.
205 y Like 's' but do not allow an integer at assembly.
206 Y The difference s-y; only an integer is allowed.
207 z Size modifier (B or W) in bit <4>. */
208
209
210 /* Please note the order of the opcodes in this table is significant.
211 The assembler requires that all instances of the same mnemonic must
212 be consecutive. If they aren't, the assembler might not recognize
213 them, or may indicate an internal error.
214
215 The disassembler should not normally care about the order of the
216 opcodes, but will prefer an earlier alternative if the "match-score"
217 (see cris-dis.c) is computed as equal.
218
219 It should not be significant for proper execution that this table is
220 in alphabetical order, but please follow that convention for an easy
221 overview. */
222
223 const struct cris_opcode
224 cris_opcodes[] =
225 {
226 {"abs", 0x06B0, 0x0940, "r,R", 0, SIZE_NONE, 0,
227 cris_abs_op},
228
229 {"add", 0x0600, 0x09c0, "m r,R", 0, SIZE_NONE, 0,
230 cris_reg_mode_add_sub_cmp_and_or_move_op},
231
232 {"add", 0x0A00, 0x01c0, "m s,R", 0, SIZE_FIELD, 0,
233 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
234
235 {"add", 0x0A00, 0x01c0, "m S,D", 0, SIZE_NONE,
236 cris_ver_v0_10,
237 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
238
239 {"add", 0x0a00, 0x05c0, "m S,R,r", 0, SIZE_NONE,
240 cris_ver_v0_10,
241 cris_three_operand_add_sub_cmp_and_or_op},
242
243 {"add", 0x0A00, 0x01c0, "m s,R", 0, SIZE_FIELD,
244 cris_ver_v32p,
245 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
246
247 {"addc", 0x0570, 0x0A80, "r,R", 0, SIZE_FIX_32,
248 cris_ver_v32p,
249 cris_not_implemented_op},
250
251 {"addc", 0x09A0, 0x0250, "s,R", 0, SIZE_FIX_32,
252 cris_ver_v32p,
253 cris_not_implemented_op},
254
255 {"addi", 0x0540, 0x0A80, "x,r,A", 0, SIZE_NONE,
256 cris_ver_v32p,
257 cris_addi_op},
258
259 {"addi", 0x0500, 0x0Ac0, "x,r", 0, SIZE_NONE, 0,
260 cris_addi_op},
261
262 /* This collates after "addo", but we want to disassemble as "addoq",
263 not "addo". */
264 {"addoq", 0x0100, 0x0E00, "Q,A", 0, SIZE_NONE,
265 cris_ver_v32p,
266 cris_not_implemented_op},
267
268 {"addo", 0x0940, 0x0280, "m s,R,A", 0, SIZE_FIELD_SIGNED,
269 cris_ver_v32p,
270 cris_not_implemented_op},
271
272 /* This must be located after the insn above, lest we misinterpret
273 "addo.b -1,r0,acr" as "addo .b-1,r0,acr". FIXME: Sounds like a
274 parser bug. */
275 {"addo", 0x0100, 0x0E00, "O,A", 0, SIZE_NONE,
276 cris_ver_v32p,
277 cris_not_implemented_op},
278
279 {"addq", 0x0200, 0x0Dc0, "I,R", 0, SIZE_NONE, 0,
280 cris_quick_mode_add_sub_op},
281
282 {"adds", 0x0420, 0x0Bc0, "z r,R", 0, SIZE_NONE, 0,
283 cris_reg_mode_add_sub_cmp_and_or_move_op},
284
285 /* FIXME: SIZE_FIELD_SIGNED and all necessary changes. */
286 {"adds", 0x0820, 0x03c0, "z s,R", 0, SIZE_FIELD, 0,
287 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
288
289 {"adds", 0x0820, 0x03c0, "z S,D", 0, SIZE_NONE,
290 cris_ver_v0_10,
291 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
292
293 {"adds", 0x0820, 0x07c0, "z S,R,r", 0, SIZE_NONE,
294 cris_ver_v0_10,
295 cris_three_operand_add_sub_cmp_and_or_op},
296
297 {"addu", 0x0400, 0x0be0, "z r,R", 0, SIZE_NONE, 0,
298 cris_reg_mode_add_sub_cmp_and_or_move_op},
299
300 /* FIXME: SIZE_FIELD_UNSIGNED and all necessary changes. */
301 {"addu", 0x0800, 0x03e0, "z s,R", 0, SIZE_FIELD, 0,
302 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
303
304 {"addu", 0x0800, 0x03e0, "z S,D", 0, SIZE_NONE,
305 cris_ver_v0_10,
306 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
307
308 {"addu", 0x0800, 0x07e0, "z S,R,r", 0, SIZE_NONE,
309 cris_ver_v0_10,
310 cris_three_operand_add_sub_cmp_and_or_op},
311
312 {"and", 0x0700, 0x08C0, "m r,R", 0, SIZE_NONE, 0,
313 cris_reg_mode_add_sub_cmp_and_or_move_op},
314
315 {"and", 0x0B00, 0x00C0, "m s,R", 0, SIZE_FIELD, 0,
316 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
317
318 {"and", 0x0B00, 0x00C0, "m S,D", 0, SIZE_NONE,
319 cris_ver_v0_10,
320 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
321
322 {"and", 0x0B00, 0x04C0, "m S,R,r", 0, SIZE_NONE,
323 cris_ver_v0_10,
324 cris_three_operand_add_sub_cmp_and_or_op},
325
326 {"andq", 0x0300, 0x0CC0, "i,R", 0, SIZE_NONE, 0,
327 cris_quick_mode_and_cmp_move_or_op},
328
329 {"asr", 0x0780, 0x0840, "m r,R", 0, SIZE_NONE, 0,
330 cris_asr_op},
331
332 {"asrq", 0x03a0, 0x0c40, "c,R", 0, SIZE_NONE, 0,
333 cris_asrq_op},
334
335 {"ax", 0x15B0, 0xEA4F, "", 0, SIZE_NONE, 0,
336 cris_ax_ei_setf_op},
337
338 /* FIXME: Should use branch #defines. */
339 {"b", 0x0dff, 0x0200, "b", 1, SIZE_NONE, 0,
340 cris_sixteen_bit_offset_branch_op},
341
342 {"ba",
343 BA_QUICK_OPCODE,
344 0x0F00+(0xF-CC_A)*0x1000, "o", 1, SIZE_NONE, 0,
345 cris_eight_bit_offset_branch_op},
346
347 /* Needs to come after the usual "ba o", which might be relaxed to
348 this one. */
349 {"ba", BA_DWORD_OPCODE,
350 0xffff & (~BA_DWORD_OPCODE), "n", 0, SIZE_FIX_32,
351 cris_ver_v32p,
352 cris_none_reg_mode_jump_op},
353
354 {"bas", 0x0EBF, 0x0140, "n,P", 0, SIZE_FIX_32,
355 cris_ver_v32p,
356 cris_none_reg_mode_jump_op},
357
358 {"basc", 0x0EFF, 0x0100, "n,P", 0, SIZE_FIX_32,
359 cris_ver_v32p,
360 cris_none_reg_mode_jump_op},
361
362 {"bcc",
363 BRANCH_QUICK_OPCODE+CC_CC*0x1000,
364 0x0f00+(0xF-CC_CC)*0x1000, "o", 1, SIZE_NONE, 0,
365 cris_eight_bit_offset_branch_op},
366
367 {"bcs",
368 BRANCH_QUICK_OPCODE+CC_CS*0x1000,
369 0x0f00+(0xF-CC_CS)*0x1000, "o", 1, SIZE_NONE, 0,
370 cris_eight_bit_offset_branch_op},
371
372 {"bdap",
373 BDAP_INDIR_OPCODE, BDAP_INDIR_Z_BITS, "pm s,R", 0, SIZE_FIELD_SIGNED,
374 cris_ver_v0_10,
375 cris_bdap_prefix},
376
377 {"bdap",
378 BDAP_QUICK_OPCODE, BDAP_QUICK_Z_BITS, "pO", 0, SIZE_NONE,
379 cris_ver_v0_10,
380 cris_quick_mode_bdap_prefix},
381
382 {"beq",
383 BRANCH_QUICK_OPCODE+CC_EQ*0x1000,
384 0x0f00+(0xF-CC_EQ)*0x1000, "o", 1, SIZE_NONE, 0,
385 cris_eight_bit_offset_branch_op},
386
387 /* This is deliberately put before "bext" to trump it, even though not
388 in alphabetical order, since we don't do excluding version checks
389 for v0..v10. */
390 {"bwf",
391 BRANCH_QUICK_OPCODE+CC_EXT*0x1000,
392 0x0f00+(0xF-CC_EXT)*0x1000, "o", 1, SIZE_NONE,
393 cris_ver_v10,
394 cris_eight_bit_offset_branch_op},
395
396 {"bext",
397 BRANCH_QUICK_OPCODE+CC_EXT*0x1000,
398 0x0f00+(0xF-CC_EXT)*0x1000, "o", 1, SIZE_NONE,
399 cris_ver_v0_3,
400 cris_eight_bit_offset_branch_op},
401
402 {"bge",
403 BRANCH_QUICK_OPCODE+CC_GE*0x1000,
404 0x0f00+(0xF-CC_GE)*0x1000, "o", 1, SIZE_NONE, 0,
405 cris_eight_bit_offset_branch_op},
406
407 {"bgt",
408 BRANCH_QUICK_OPCODE+CC_GT*0x1000,
409 0x0f00+(0xF-CC_GT)*0x1000, "o", 1, SIZE_NONE, 0,
410 cris_eight_bit_offset_branch_op},
411
412 {"bhi",
413 BRANCH_QUICK_OPCODE+CC_HI*0x1000,
414 0x0f00+(0xF-CC_HI)*0x1000, "o", 1, SIZE_NONE, 0,
415 cris_eight_bit_offset_branch_op},
416
417 {"bhs",
418 BRANCH_QUICK_OPCODE+CC_HS*0x1000,
419 0x0f00+(0xF-CC_HS)*0x1000, "o", 1, SIZE_NONE, 0,
420 cris_eight_bit_offset_branch_op},
421
422 {"biap", BIAP_OPCODE, BIAP_Z_BITS, "pm r,R", 0, SIZE_NONE,
423 cris_ver_v0_10,
424 cris_biap_prefix},
425
426 {"ble",
427 BRANCH_QUICK_OPCODE+CC_LE*0x1000,
428 0x0f00+(0xF-CC_LE)*0x1000, "o", 1, SIZE_NONE, 0,
429 cris_eight_bit_offset_branch_op},
430
431 {"blo",
432 BRANCH_QUICK_OPCODE+CC_LO*0x1000,
433 0x0f00+(0xF-CC_LO)*0x1000, "o", 1, SIZE_NONE, 0,
434 cris_eight_bit_offset_branch_op},
435
436 {"bls",
437 BRANCH_QUICK_OPCODE+CC_LS*0x1000,
438 0x0f00+(0xF-CC_LS)*0x1000, "o", 1, SIZE_NONE, 0,
439 cris_eight_bit_offset_branch_op},
440
441 {"blt",
442 BRANCH_QUICK_OPCODE+CC_LT*0x1000,
443 0x0f00+(0xF-CC_LT)*0x1000, "o", 1, SIZE_NONE, 0,
444 cris_eight_bit_offset_branch_op},
445
446 {"bmi",
447 BRANCH_QUICK_OPCODE+CC_MI*0x1000,
448 0x0f00+(0xF-CC_MI)*0x1000, "o", 1, SIZE_NONE, 0,
449 cris_eight_bit_offset_branch_op},
450
451 {"bmod", 0x0ab0, 0x0140, "s,R", 0, SIZE_FIX_32,
452 cris_ver_sim_v0_10,
453 cris_not_implemented_op},
454
455 {"bmod", 0x0ab0, 0x0140, "S,D", 0, SIZE_NONE,
456 cris_ver_sim_v0_10,
457 cris_not_implemented_op},
458
459 {"bmod", 0x0ab0, 0x0540, "S,R,r", 0, SIZE_NONE,
460 cris_ver_sim_v0_10,
461 cris_not_implemented_op},
462
463 {"bne",
464 BRANCH_QUICK_OPCODE+CC_NE*0x1000,
465 0x0f00+(0xF-CC_NE)*0x1000, "o", 1, SIZE_NONE, 0,
466 cris_eight_bit_offset_branch_op},
467
468 {"bound", 0x05c0, 0x0A00, "m r,R", 0, SIZE_NONE, 0,
469 cris_two_operand_bound_op},
470 /* FIXME: SIZE_FIELD_UNSIGNED and all necessary changes. */
471 {"bound", 0x09c0, 0x0200, "m s,R", 0, SIZE_FIELD,
472 cris_ver_v0_10,
473 cris_two_operand_bound_op},
474 /* FIXME: SIZE_FIELD_UNSIGNED and all necessary changes. */
475 {"bound", 0x0dcf, 0x0200, "m Y,R", 0, SIZE_FIELD, 0,
476 cris_two_operand_bound_op},
477 {"bound", 0x09c0, 0x0200, "m S,D", 0, SIZE_NONE,
478 cris_ver_v0_10,
479 cris_two_operand_bound_op},
480 {"bound", 0x09c0, 0x0600, "m S,R,r", 0, SIZE_NONE,
481 cris_ver_v0_10,
482 cris_three_operand_bound_op},
483
484 {"bpl",
485 BRANCH_QUICK_OPCODE+CC_PL*0x1000,
486 0x0f00+(0xF-CC_PL)*0x1000, "o", 1, SIZE_NONE, 0,
487 cris_eight_bit_offset_branch_op},
488
489 {"break", 0xe930, 0x16c0, "C", 0, SIZE_NONE,
490 cris_ver_v3p,
491 cris_break_op},
492
493 {"bsb",
494 BRANCH_QUICK_OPCODE+CC_EXT*0x1000,
495 0x0f00+(0xF-CC_EXT)*0x1000, "o", 1, SIZE_NONE,
496 cris_ver_v32p,
497 cris_eight_bit_offset_branch_op},
498
499 {"bsr", 0xBEBF, 0x4140, "n", 0, SIZE_FIX_32,
500 cris_ver_v32p,
501 cris_none_reg_mode_jump_op},
502
503 {"bsrc", 0xBEFF, 0x4100, "n", 0, SIZE_FIX_32,
504 cris_ver_v32p,
505 cris_none_reg_mode_jump_op},
506
507 {"bstore", 0x0af0, 0x0100, "s,R", 0, SIZE_FIX_32,
508 cris_ver_warning,
509 cris_not_implemented_op},
510
511 {"bstore", 0x0af0, 0x0100, "S,D", 0, SIZE_NONE,
512 cris_ver_warning,
513 cris_not_implemented_op},
514
515 {"bstore", 0x0af0, 0x0500, "S,R,r", 0, SIZE_NONE,
516 cris_ver_warning,
517 cris_not_implemented_op},
518
519 {"btst", 0x04F0, 0x0B00, "r,R", 0, SIZE_NONE, 0,
520 cris_btst_nop_op},
521 {"btstq", 0x0380, 0x0C60, "c,R", 0, SIZE_NONE, 0,
522 cris_btst_nop_op},
523
524 {"bvc",
525 BRANCH_QUICK_OPCODE+CC_VC*0x1000,
526 0x0f00+(0xF-CC_VC)*0x1000, "o", 1, SIZE_NONE, 0,
527 cris_eight_bit_offset_branch_op},
528
529 {"bvs",
530 BRANCH_QUICK_OPCODE+CC_VS*0x1000,
531 0x0f00+(0xF-CC_VS)*0x1000, "o", 1, SIZE_NONE, 0,
532 cris_eight_bit_offset_branch_op},
533
534 {"clear", 0x0670, 0x3980, "M r", 0, SIZE_NONE, 0,
535 cris_reg_mode_clear_op},
536
537 {"clear", 0x0A70, 0x3180, "M y", 0, SIZE_NONE, 0,
538 cris_none_reg_mode_clear_test_op},
539
540 {"clear", 0x0A70, 0x3180, "M S", 0, SIZE_NONE,
541 cris_ver_v0_10,
542 cris_none_reg_mode_clear_test_op},
543
544 {"clearf", 0x05F0, 0x0A00, "f", 0, SIZE_NONE, 0,
545 cris_clearf_di_op},
546
547 {"cmp", 0x06C0, 0x0900, "m r,R", 0, SIZE_NONE, 0,
548 cris_reg_mode_add_sub_cmp_and_or_move_op},
549
550 {"cmp", 0x0Ac0, 0x0100, "m s,R", 0, SIZE_FIELD, 0,
551 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
552
553 {"cmp", 0x0Ac0, 0x0100, "m S,D", 0, SIZE_NONE,
554 cris_ver_v0_10,
555 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
556
557 {"cmpq", 0x02C0, 0x0D00, "i,R", 0, SIZE_NONE, 0,
558 cris_quick_mode_and_cmp_move_or_op},
559
560 /* FIXME: SIZE_FIELD_SIGNED and all necessary changes. */
561 {"cmps", 0x08e0, 0x0300, "z s,R", 0, SIZE_FIELD, 0,
562 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
563
564 {"cmps", 0x08e0, 0x0300, "z S,D", 0, SIZE_NONE,
565 cris_ver_v0_10,
566 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
567
568 /* FIXME: SIZE_FIELD_UNSIGNED and all necessary changes. */
569 {"cmpu", 0x08c0, 0x0320, "z s,R" , 0, SIZE_FIELD, 0,
570 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
571
572 {"cmpu", 0x08c0, 0x0320, "z S,D", 0, SIZE_NONE,
573 cris_ver_v0_10,
574 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
575
576 {"di", 0x25F0, 0xDA0F, "", 0, SIZE_NONE, 0,
577 cris_clearf_di_op},
578
579 {"dip", DIP_OPCODE, DIP_Z_BITS, "ps", 0, SIZE_FIX_32,
580 cris_ver_v0_10,
581 cris_dip_prefix},
582
583 {"div", 0x0980, 0x0640, "m R,r", 0, SIZE_FIELD, 0,
584 cris_not_implemented_op},
585
586 {"dstep", 0x06f0, 0x0900, "r,R", 0, SIZE_NONE, 0,
587 cris_dstep_logshift_mstep_neg_not_op},
588
589 {"ei", 0x25B0, 0xDA4F, "", 0, SIZE_NONE, 0,
590 cris_ax_ei_setf_op},
591
592 {"fidxd", 0x0ab0, 0xf540, "[r]", 0, SIZE_NONE,
593 cris_ver_v32p,
594 cris_not_implemented_op},
595
596 {"fidxi", 0x0d30, 0xF2C0, "[r]", 0, SIZE_NONE,
597 cris_ver_v32p,
598 cris_not_implemented_op},
599
600 {"ftagd", 0x1AB0, 0xE540, "[r]", 0, SIZE_NONE,
601 cris_ver_v32p,
602 cris_not_implemented_op},
603
604 {"ftagi", 0x1D30, 0xE2C0, "[r]", 0, SIZE_NONE,
605 cris_ver_v32p,
606 cris_not_implemented_op},
607
608 {"halt", 0xF930, 0x06CF, "", 0, SIZE_NONE,
609 cris_ver_v32p,
610 cris_not_implemented_op},
611
612 {"jas", 0x09B0, 0x0640, "r,P", 0, SIZE_NONE,
613 cris_ver_v32p,
614 cris_reg_mode_jump_op},
615
616 {"jas", 0x0DBF, 0x0240, "N,P", 0, SIZE_FIX_32,
617 cris_ver_v32p,
618 cris_reg_mode_jump_op},
619
620 {"jasc", 0x0B30, 0x04C0, "r,P", 0, SIZE_NONE,
621 cris_ver_v32p,
622 cris_reg_mode_jump_op},
623
624 {"jasc", 0x0F3F, 0x00C0, "N,P", 0, SIZE_FIX_32,
625 cris_ver_v32p,
626 cris_reg_mode_jump_op},
627
628 {"jbrc", 0x69b0, 0x9640, "r", 0, SIZE_NONE,
629 cris_ver_v8_10,
630 cris_reg_mode_jump_op},
631
632 {"jbrc", 0x6930, 0x92c0, "s", 0, SIZE_FIX_32,
633 cris_ver_v8_10,
634 cris_none_reg_mode_jump_op},
635
636 {"jbrc", 0x6930, 0x92c0, "S", 0, SIZE_NONE,
637 cris_ver_v8_10,
638 cris_none_reg_mode_jump_op},
639
640 {"jir", 0xA9b0, 0x5640, "r", 0, SIZE_NONE,
641 cris_ver_v8_10,
642 cris_reg_mode_jump_op},
643
644 {"jir", 0xA930, 0x52c0, "s", 0, SIZE_FIX_32,
645 cris_ver_v8_10,
646 cris_none_reg_mode_jump_op},
647
648 {"jir", 0xA930, 0x52c0, "S", 0, SIZE_NONE,
649 cris_ver_v8_10,
650 cris_none_reg_mode_jump_op},
651
652 {"jirc", 0x29b0, 0xd640, "r", 0, SIZE_NONE,
653 cris_ver_v8_10,
654 cris_reg_mode_jump_op},
655
656 {"jirc", 0x2930, 0xd2c0, "s", 0, SIZE_FIX_32,
657 cris_ver_v8_10,
658 cris_none_reg_mode_jump_op},
659
660 {"jirc", 0x2930, 0xd2c0, "S", 0, SIZE_NONE,
661 cris_ver_v8_10,
662 cris_none_reg_mode_jump_op},
663
664 {"jsr", 0xB9b0, 0x4640, "r", 0, SIZE_NONE, 0,
665 cris_reg_mode_jump_op},
666
667 {"jsr", 0xB930, 0x42c0, "s", 0, SIZE_FIX_32,
668 cris_ver_v0_10,
669 cris_none_reg_mode_jump_op},
670
671 {"jsr", 0xBDBF, 0x4240, "N", 0, SIZE_FIX_32,
672 cris_ver_v32p,
673 cris_none_reg_mode_jump_op},
674
675 {"jsr", 0xB930, 0x42c0, "S", 0, SIZE_NONE,
676 cris_ver_v0_10,
677 cris_none_reg_mode_jump_op},
678
679 {"jsrc", 0x39b0, 0xc640, "r", 0, SIZE_NONE,
680 cris_ver_v8_10,
681 cris_reg_mode_jump_op},
682
683 {"jsrc", 0x3930, 0xc2c0, "s", 0, SIZE_FIX_32,
684 cris_ver_v8_10,
685 cris_none_reg_mode_jump_op},
686
687 {"jsrc", 0x3930, 0xc2c0, "S", 0, SIZE_NONE,
688 cris_ver_v8_10,
689 cris_none_reg_mode_jump_op},
690
691 {"jsrc", 0xBB30, 0x44C0, "r", 0, SIZE_NONE,
692 cris_ver_v32p,
693 cris_reg_mode_jump_op},
694
695 {"jsrc", 0xBF3F, 0x40C0, "N", 0, SIZE_FIX_32,
696 cris_ver_v32p,
697 cris_reg_mode_jump_op},
698
699 {"jump", 0x09b0, 0xF640, "r", 0, SIZE_NONE, 0,
700 cris_reg_mode_jump_op},
701
702 {"jump",
703 JUMP_INDIR_OPCODE, JUMP_INDIR_Z_BITS, "s", 0, SIZE_FIX_32,
704 cris_ver_v0_10,
705 cris_none_reg_mode_jump_op},
706
707 {"jump",
708 JUMP_INDIR_OPCODE, JUMP_INDIR_Z_BITS, "S", 0, SIZE_NONE,
709 cris_ver_v0_10,
710 cris_none_reg_mode_jump_op},
711
712 {"jump", 0x09F0, 0x060F, "P", 0, SIZE_NONE,
713 cris_ver_v32p,
714 cris_none_reg_mode_jump_op},
715
716 {"jump",
717 JUMP_PC_INCR_OPCODE_V32,
718 (0xffff & ~JUMP_PC_INCR_OPCODE_V32), "N", 0, SIZE_FIX_32,
719 cris_ver_v32p,
720 cris_none_reg_mode_jump_op},
721
722 {"jmpu", 0x8930, 0x72c0, "s", 0, SIZE_FIX_32,
723 cris_ver_v10,
724 cris_none_reg_mode_jump_op},
725
726 {"jmpu", 0x8930, 0x72c0, "S", 0, SIZE_NONE,
727 cris_ver_v10,
728 cris_none_reg_mode_jump_op},
729
730 {"lapc", 0x0970, 0x0680, "U,R", 0, SIZE_NONE,
731 cris_ver_v32p,
732 cris_not_implemented_op},
733
734 {"lapc", 0x0D7F, 0x0280, "dn,R", 0, SIZE_FIX_32,
735 cris_ver_v32p,
736 cris_not_implemented_op},
737
738 {"lapcq", 0x0970, 0x0680, "u,R", 0, SIZE_NONE,
739 cris_ver_v32p,
740 cris_addi_op},
741
742 {"lsl", 0x04C0, 0x0B00, "m r,R", 0, SIZE_NONE, 0,
743 cris_dstep_logshift_mstep_neg_not_op},
744
745 {"lslq", 0x03c0, 0x0C20, "c,R", 0, SIZE_NONE, 0,
746 cris_dstep_logshift_mstep_neg_not_op},
747
748 {"lsr", 0x07C0, 0x0800, "m r,R", 0, SIZE_NONE, 0,
749 cris_dstep_logshift_mstep_neg_not_op},
750
751 {"lsrq", 0x03e0, 0x0C00, "c,R", 0, SIZE_NONE, 0,
752 cris_dstep_logshift_mstep_neg_not_op},
753
754 {"lz", 0x0730, 0x08C0, "r,R", 0, SIZE_NONE,
755 cris_ver_v3p,
756 cris_not_implemented_op},
757
758 {"mcp", 0x07f0, 0x0800, "P,r", 0, SIZE_NONE,
759 cris_ver_v32p,
760 cris_not_implemented_op},
761
762 {"move", 0x0640, 0x0980, "m r,R", 0, SIZE_NONE, 0,
763 cris_reg_mode_add_sub_cmp_and_or_move_op},
764
765 {"move", 0x0A40, 0x0180, "m s,R", 0, SIZE_FIELD, 0,
766 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
767
768 {"move", 0x0A40, 0x0180, "m S,D", 0, SIZE_NONE,
769 cris_ver_v0_10,
770 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
771
772 {"move", 0x0630, 0x09c0, "r,P", 0, SIZE_NONE, 0,
773 cris_move_to_preg_op},
774
775 {"move", 0x0670, 0x0980, "P,r", 0, SIZE_NONE, 0,
776 cris_reg_mode_move_from_preg_op},
777
778 {"move", 0x0BC0, 0x0000, "m R,y", 0, SIZE_FIELD, 0,
779 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
780
781 {"move", 0x0BC0, 0x0000, "m D,S", 0, SIZE_NONE,
782 cris_ver_v0_10,
783 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
784
785 {"move",
786 MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS,
787 "s,P", 0, SIZE_SPEC_REG, 0,
788 cris_move_to_preg_op},
789
790 {"move", 0x0A30, 0x01c0, "S,P", 0, SIZE_NONE,
791 cris_ver_v0_10,
792 cris_move_to_preg_op},
793
794 {"move", 0x0A70, 0x0180, "P,y", 0, SIZE_SPEC_REG, 0,
795 cris_none_reg_mode_move_from_preg_op},
796
797 {"move", 0x0A70, 0x0180, "P,S", 0, SIZE_NONE,
798 cris_ver_v0_10,
799 cris_none_reg_mode_move_from_preg_op},
800
801 {"move", 0x0B70, 0x0480, "r,T", 0, SIZE_NONE,
802 cris_ver_v32p,
803 cris_not_implemented_op},
804
805 {"move", 0x0F70, 0x0080, "T,r", 0, SIZE_NONE,
806 cris_ver_v32p,
807 cris_not_implemented_op},
808
809 {"movem", 0x0BF0, 0x0000, "R,y", 0, SIZE_FIX_32, 0,
810 cris_move_reg_to_mem_movem_op},
811
812 {"movem", 0x0BF0, 0x0000, "D,S", 0, SIZE_NONE,
813 cris_ver_v0_10,
814 cris_move_reg_to_mem_movem_op},
815
816 {"movem", 0x0BB0, 0x0040, "s,R", 0, SIZE_FIX_32, 0,
817 cris_move_mem_to_reg_movem_op},
818
819 {"movem", 0x0BB0, 0x0040, "S,D", 0, SIZE_NONE,
820 cris_ver_v0_10,
821 cris_move_mem_to_reg_movem_op},
822
823 {"moveq", 0x0240, 0x0D80, "i,R", 0, SIZE_NONE, 0,
824 cris_quick_mode_and_cmp_move_or_op},
825
826 {"movs", 0x0460, 0x0B80, "z r,R", 0, SIZE_NONE, 0,
827 cris_reg_mode_add_sub_cmp_and_or_move_op},
828
829 /* FIXME: SIZE_FIELD_SIGNED and all necessary changes. */
830 {"movs", 0x0860, 0x0380, "z s,R", 0, SIZE_FIELD, 0,
831 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
832
833 {"movs", 0x0860, 0x0380, "z S,D", 0, SIZE_NONE,
834 cris_ver_v0_10,
835 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
836
837 {"movu", 0x0440, 0x0Ba0, "z r,R", 0, SIZE_NONE, 0,
838 cris_reg_mode_add_sub_cmp_and_or_move_op},
839
840 /* FIXME: SIZE_FIELD_UNSIGNED and all necessary changes. */
841 {"movu", 0x0840, 0x03a0, "z s,R", 0, SIZE_FIELD, 0,
842 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
843
844 {"movu", 0x0840, 0x03a0, "z S,D", 0, SIZE_NONE,
845 cris_ver_v0_10,
846 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
847
848 {"mstep", 0x07f0, 0x0800, "r,R", 0, SIZE_NONE,
849 cris_ver_v0_10,
850 cris_dstep_logshift_mstep_neg_not_op},
851
852 {"muls", 0x0d00, 0x02c0, "m r,R", 0, SIZE_NONE,
853 cris_ver_v10p,
854 cris_muls_op},
855
856 {"mulu", 0x0900, 0x06c0, "m r,R", 0, SIZE_NONE,
857 cris_ver_v10p,
858 cris_mulu_op},
859
860 {"neg", 0x0580, 0x0A40, "m r,R", 0, SIZE_NONE, 0,
861 cris_dstep_logshift_mstep_neg_not_op},
862
863 {"nop", NOP_OPCODE, NOP_Z_BITS, "", 0, SIZE_NONE,
864 cris_ver_v0_10,
865 cris_btst_nop_op},
866
867 {"nop", NOP_OPCODE_V32, NOP_Z_BITS_V32, "", 0, SIZE_NONE,
868 cris_ver_v32p,
869 cris_btst_nop_op},
870
871 {"not", 0x8770, 0x7880, "r", 0, SIZE_NONE, 0,
872 cris_dstep_logshift_mstep_neg_not_op},
873
874 {"or", 0x0740, 0x0880, "m r,R", 0, SIZE_NONE, 0,
875 cris_reg_mode_add_sub_cmp_and_or_move_op},
876
877 {"or", 0x0B40, 0x0080, "m s,R", 0, SIZE_FIELD, 0,
878 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
879
880 {"or", 0x0B40, 0x0080, "m S,D", 0, SIZE_NONE,
881 cris_ver_v0_10,
882 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
883
884 {"or", 0x0B40, 0x0480, "m S,R,r", 0, SIZE_NONE,
885 cris_ver_v0_10,
886 cris_three_operand_add_sub_cmp_and_or_op},
887
888 {"orq", 0x0340, 0x0C80, "i,R", 0, SIZE_NONE, 0,
889 cris_quick_mode_and_cmp_move_or_op},
890
891 {"pop", 0x0E6E, 0x0191, "!R", 0, SIZE_NONE,
892 cris_ver_v0_10,
893 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
894
895 {"pop", 0x0e3e, 0x01c1, "!P", 0, SIZE_NONE,
896 cris_ver_v0_10,
897 cris_none_reg_mode_move_from_preg_op},
898
899 {"push", 0x0FEE, 0x0011, "BR", 0, SIZE_NONE,
900 cris_ver_v0_10,
901 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
902
903 {"push", 0x0E7E, 0x0181, "BP", 0, SIZE_NONE,
904 cris_ver_v0_10,
905 cris_move_to_preg_op},
906
907 {"rbf", 0x3b30, 0xc0c0, "y", 0, SIZE_NONE,
908 cris_ver_v10,
909 cris_not_implemented_op},
910
911 {"rbf", 0x3b30, 0xc0c0, "S", 0, SIZE_NONE,
912 cris_ver_v10,
913 cris_not_implemented_op},
914
915 {"rfe", 0x2930, 0xD6CF, "", 0, SIZE_NONE,
916 cris_ver_v32p,
917 cris_not_implemented_op},
918
919 {"rfg", 0x4930, 0xB6CF, "", 0, SIZE_NONE,
920 cris_ver_v32p,
921 cris_not_implemented_op},
922
923 {"rfn", 0x5930, 0xA6CF, "", 0, SIZE_NONE,
924 cris_ver_v32p,
925 cris_not_implemented_op},
926
927 {"ret", 0xB67F, 0x4980, "", 1, SIZE_NONE,
928 cris_ver_v0_10,
929 cris_reg_mode_move_from_preg_op},
930
931 {"ret", 0xB9F0, 0x460F, "", 1, SIZE_NONE,
932 cris_ver_v32p,
933 cris_reg_mode_move_from_preg_op},
934
935 {"retb", 0xe67f, 0x1980, "", 1, SIZE_NONE,
936 cris_ver_v0_10,
937 cris_reg_mode_move_from_preg_op},
938
939 {"rete", 0xA9F0, 0x560F, "", 1, SIZE_NONE,
940 cris_ver_v32p,
941 cris_reg_mode_move_from_preg_op},
942
943 {"reti", 0xA67F, 0x5980, "", 1, SIZE_NONE,
944 cris_ver_v0_10,
945 cris_reg_mode_move_from_preg_op},
946
947 {"retn", 0xC9F0, 0x360F, "", 1, SIZE_NONE,
948 cris_ver_v32p,
949 cris_reg_mode_move_from_preg_op},
950
951 {"sbfs", 0x3b70, 0xc080, "y", 0, SIZE_NONE,
952 cris_ver_v10,
953 cris_not_implemented_op},
954
955 {"sbfs", 0x3b70, 0xc080, "S", 0, SIZE_NONE,
956 cris_ver_v10,
957 cris_not_implemented_op},
958
959 {"sa",
960 0x0530+CC_A*0x1000,
961 0x0AC0+(0xf-CC_A)*0x1000, "r", 0, SIZE_NONE, 0,
962 cris_scc_op},
963
964 {"ssb",
965 0x0530+CC_EXT*0x1000,
966 0x0AC0+(0xf-CC_EXT)*0x1000, "r", 0, SIZE_NONE,
967 cris_ver_v32p,
968 cris_scc_op},
969
970 {"scc",
971 0x0530+CC_CC*0x1000,
972 0x0AC0+(0xf-CC_CC)*0x1000, "r", 0, SIZE_NONE, 0,
973 cris_scc_op},
974
975 {"scs",
976 0x0530+CC_CS*0x1000,
977 0x0AC0+(0xf-CC_CS)*0x1000, "r", 0, SIZE_NONE, 0,
978 cris_scc_op},
979
980 {"seq",
981 0x0530+CC_EQ*0x1000,
982 0x0AC0+(0xf-CC_EQ)*0x1000, "r", 0, SIZE_NONE, 0,
983 cris_scc_op},
984
985 {"setf", 0x05b0, 0x0A40, "f", 0, SIZE_NONE, 0,
986 cris_ax_ei_setf_op},
987
988 {"sfe", 0x3930, 0xC6CF, "", 0, SIZE_NONE,
989 cris_ver_v32p,
990 cris_not_implemented_op},
991
992 /* Need to have "swf" in front of "sext" so it is the one displayed in
993 disassembly. */
994 {"swf",
995 0x0530+CC_EXT*0x1000,
996 0x0AC0+(0xf-CC_EXT)*0x1000, "r", 0, SIZE_NONE,
997 cris_ver_v10,
998 cris_scc_op},
999
1000 {"sext",
1001 0x0530+CC_EXT*0x1000,
1002 0x0AC0+(0xf-CC_EXT)*0x1000, "r", 0, SIZE_NONE,
1003 cris_ver_v0_3,
1004 cris_scc_op},
1005
1006 {"sge",
1007 0x0530+CC_GE*0x1000,
1008 0x0AC0+(0xf-CC_GE)*0x1000, "r", 0, SIZE_NONE, 0,
1009 cris_scc_op},
1010
1011 {"sgt",
1012 0x0530+CC_GT*0x1000,
1013 0x0AC0+(0xf-CC_GT)*0x1000, "r", 0, SIZE_NONE, 0,
1014 cris_scc_op},
1015
1016 {"shi",
1017 0x0530+CC_HI*0x1000,
1018 0x0AC0+(0xf-CC_HI)*0x1000, "r", 0, SIZE_NONE, 0,
1019 cris_scc_op},
1020
1021 {"shs",
1022 0x0530+CC_HS*0x1000,
1023 0x0AC0+(0xf-CC_HS)*0x1000, "r", 0, SIZE_NONE, 0,
1024 cris_scc_op},
1025
1026 {"sle",
1027 0x0530+CC_LE*0x1000,
1028 0x0AC0+(0xf-CC_LE)*0x1000, "r", 0, SIZE_NONE, 0,
1029 cris_scc_op},
1030
1031 {"slo",
1032 0x0530+CC_LO*0x1000,
1033 0x0AC0+(0xf-CC_LO)*0x1000, "r", 0, SIZE_NONE, 0,
1034 cris_scc_op},
1035
1036 {"sls",
1037 0x0530+CC_LS*0x1000,
1038 0x0AC0+(0xf-CC_LS)*0x1000, "r", 0, SIZE_NONE, 0,
1039 cris_scc_op},
1040
1041 {"slt",
1042 0x0530+CC_LT*0x1000,
1043 0x0AC0+(0xf-CC_LT)*0x1000, "r", 0, SIZE_NONE, 0,
1044 cris_scc_op},
1045
1046 {"smi",
1047 0x0530+CC_MI*0x1000,
1048 0x0AC0+(0xf-CC_MI)*0x1000, "r", 0, SIZE_NONE, 0,
1049 cris_scc_op},
1050
1051 {"sne",
1052 0x0530+CC_NE*0x1000,
1053 0x0AC0+(0xf-CC_NE)*0x1000, "r", 0, SIZE_NONE, 0,
1054 cris_scc_op},
1055
1056 {"spl",
1057 0x0530+CC_PL*0x1000,
1058 0x0AC0+(0xf-CC_PL)*0x1000, "r", 0, SIZE_NONE, 0,
1059 cris_scc_op},
1060
1061 {"sub", 0x0680, 0x0940, "m r,R", 0, SIZE_NONE, 0,
1062 cris_reg_mode_add_sub_cmp_and_or_move_op},
1063
1064 {"sub", 0x0a80, 0x0140, "m s,R", 0, SIZE_FIELD, 0,
1065 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
1066
1067 {"sub", 0x0a80, 0x0140, "m S,D", 0, SIZE_NONE,
1068 cris_ver_v0_10,
1069 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
1070
1071 {"sub", 0x0a80, 0x0540, "m S,R,r", 0, SIZE_NONE,
1072 cris_ver_v0_10,
1073 cris_three_operand_add_sub_cmp_and_or_op},
1074
1075 {"subq", 0x0280, 0x0d40, "I,R", 0, SIZE_NONE, 0,
1076 cris_quick_mode_add_sub_op},
1077
1078 {"subs", 0x04a0, 0x0b40, "z r,R", 0, SIZE_NONE, 0,
1079 cris_reg_mode_add_sub_cmp_and_or_move_op},
1080
1081 /* FIXME: SIZE_FIELD_SIGNED and all necessary changes. */
1082 {"subs", 0x08a0, 0x0340, "z s,R", 0, SIZE_FIELD, 0,
1083 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
1084
1085 {"subs", 0x08a0, 0x0340, "z S,D", 0, SIZE_NONE,
1086 cris_ver_v0_10,
1087 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
1088
1089 {"subs", 0x08a0, 0x0740, "z S,R,r", 0, SIZE_NONE,
1090 cris_ver_v0_10,
1091 cris_three_operand_add_sub_cmp_and_or_op},
1092
1093 {"subu", 0x0480, 0x0b60, "z r,R", 0, SIZE_NONE, 0,
1094 cris_reg_mode_add_sub_cmp_and_or_move_op},
1095
1096 /* FIXME: SIZE_FIELD_UNSIGNED and all necessary changes. */
1097 {"subu", 0x0880, 0x0360, "z s,R", 0, SIZE_FIELD, 0,
1098 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
1099
1100 {"subu", 0x0880, 0x0360, "z S,D", 0, SIZE_NONE,
1101 cris_ver_v0_10,
1102 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
1103
1104 {"subu", 0x0880, 0x0760, "z S,R,r", 0, SIZE_NONE,
1105 cris_ver_v0_10,
1106 cris_three_operand_add_sub_cmp_and_or_op},
1107
1108 {"svc",
1109 0x0530+CC_VC*0x1000,
1110 0x0AC0+(0xf-CC_VC)*0x1000, "r", 0, SIZE_NONE, 0,
1111 cris_scc_op},
1112
1113 {"svs",
1114 0x0530+CC_VS*0x1000,
1115 0x0AC0+(0xf-CC_VS)*0x1000, "r", 0, SIZE_NONE, 0,
1116 cris_scc_op},
1117
1118 /* The insn "swapn" is the same as "not" and will be disassembled as
1119 such, but the swap* family of mnmonics are generally v8-and-higher
1120 only, so count it in. */
1121 {"swapn", 0x8770, 0x7880, "r", 0, SIZE_NONE,
1122 cris_ver_v8p,
1123 cris_not_implemented_op},
1124
1125 {"swapw", 0x4770, 0xb880, "r", 0, SIZE_NONE,
1126 cris_ver_v8p,
1127 cris_not_implemented_op},
1128
1129 {"swapnw", 0xc770, 0x3880, "r", 0, SIZE_NONE,
1130 cris_ver_v8p,
1131 cris_not_implemented_op},
1132
1133 {"swapb", 0x2770, 0xd880, "r", 0, SIZE_NONE,
1134 cris_ver_v8p,
1135 cris_not_implemented_op},
1136
1137 {"swapnb", 0xA770, 0x5880, "r", 0, SIZE_NONE,
1138 cris_ver_v8p,
1139 cris_not_implemented_op},
1140
1141 {"swapwb", 0x6770, 0x9880, "r", 0, SIZE_NONE,
1142 cris_ver_v8p,
1143 cris_not_implemented_op},
1144
1145 {"swapnwb", 0xE770, 0x1880, "r", 0, SIZE_NONE,
1146 cris_ver_v8p,
1147 cris_not_implemented_op},
1148
1149 {"swapr", 0x1770, 0xe880, "r", 0, SIZE_NONE,
1150 cris_ver_v8p,
1151 cris_not_implemented_op},
1152
1153 {"swapnr", 0x9770, 0x6880, "r", 0, SIZE_NONE,
1154 cris_ver_v8p,
1155 cris_not_implemented_op},
1156
1157 {"swapwr", 0x5770, 0xa880, "r", 0, SIZE_NONE,
1158 cris_ver_v8p,
1159 cris_not_implemented_op},
1160
1161 {"swapnwr", 0xd770, 0x2880, "r", 0, SIZE_NONE,
1162 cris_ver_v8p,
1163 cris_not_implemented_op},
1164
1165 {"swapbr", 0x3770, 0xc880, "r", 0, SIZE_NONE,
1166 cris_ver_v8p,
1167 cris_not_implemented_op},
1168
1169 {"swapnbr", 0xb770, 0x4880, "r", 0, SIZE_NONE,
1170 cris_ver_v8p,
1171 cris_not_implemented_op},
1172
1173 {"swapwbr", 0x7770, 0x8880, "r", 0, SIZE_NONE,
1174 cris_ver_v8p,
1175 cris_not_implemented_op},
1176
1177 {"swapnwbr", 0xf770, 0x0880, "r", 0, SIZE_NONE,
1178 cris_ver_v8p,
1179 cris_not_implemented_op},
1180
1181 {"test", 0x0640, 0x0980, "m D", 0, SIZE_NONE,
1182 cris_ver_v0_10,
1183 cris_reg_mode_test_op},
1184
1185 {"test", 0x0b80, 0xf040, "m y", 0, SIZE_FIELD, 0,
1186 cris_none_reg_mode_clear_test_op},
1187
1188 {"test", 0x0b80, 0xf040, "m S", 0, SIZE_NONE,
1189 cris_ver_v0_10,
1190 cris_none_reg_mode_clear_test_op},
1191
1192 {"xor", 0x07B0, 0x0840, "r,R", 0, SIZE_NONE, 0,
1193 cris_xor_op},
1194
1195 {NULL, 0, 0, NULL, 0, 0, 0, cris_not_implemented_op}
1196 };
1197
1198 /* Condition-names, indexed by the CC_* numbers as found in cris.h. */
1199 const char * const
1200 cris_cc_strings[] =
1201 {
1202 "hs",
1203 "lo",
1204 "ne",
1205 "eq",
1206 "vc",
1207 "vs",
1208 "pl",
1209 "mi",
1210 "ls",
1211 "hi",
1212 "ge",
1213 "lt",
1214 "gt",
1215 "le",
1216 "a",
1217 /* This is a placeholder. In v0, this would be "ext". In v32, this
1218 is "sb". See cris_conds15. */
1219 "wf"
1220 };
1221
1222 /* Different names and semantics for condition 1111 (0xf). */
1223 const struct cris_cond15 cris_cond15s[] =
1224 {
1225 /* FIXME: In what version did condition "ext" disappear? */
1226 {"ext", cris_ver_v0_3},
1227 {"wf", cris_ver_v10},
1228 {"sb", cris_ver_v32p},
1229 {NULL, 0}
1230 };
1231
1232
1233 /*
1234 * Local variables:
1235 * eval: (c-set-style "gnu")
1236 * indent-tabs-mode: t
1237 * End:
1238 */
1239
1240
1241 /* No instruction will be disassembled longer than this. In theory, and
1242 in silicon, address prefixes can be cascaded. In practice, cascading
1243 is not used by GCC, and not supported by the assembler. */
1244 #ifndef MAX_BYTES_PER_CRIS_INSN
1245 #define MAX_BYTES_PER_CRIS_INSN 8
1246 #endif
1247
1248 /* Whether or not to decode prefixes, folding it into the following
1249 instruction. FIXME: Make this optional later. */
1250 #ifndef PARSE_PREFIX
1251 #define PARSE_PREFIX 1
1252 #endif
1253
1254 /* Sometimes we prefix all registers with this character. */
1255 #define REGISTER_PREFIX_CHAR '$'
1256
1257 /* Whether or not to trace the following sequence:
1258 sub* X,r%d
1259 bound* Y,r%d
1260 adds.w [pc+r%d.w],pc
1261
1262 This is the assembly form of a switch-statement in C.
1263 The "sub is optional. If there is none, then X will be zero.
1264 X is the value of the first case,
1265 Y is the number of cases (including default).
1266
1267 This results in case offsets printed on the form:
1268 case N: -> case_address
1269 where N is an estimation on the corresponding 'case' operand in C,
1270 and case_address is where execution of that case continues after the
1271 sequence presented above.
1272
1273 The old style of output was to print the offsets as instructions,
1274 which made it hard to follow "case"-constructs in the disassembly,
1275 and caused a lot of annoying warnings about undefined instructions.
1276
1277 FIXME: Make this optional later. */
1278 #ifndef TRACE_CASE
1279 #define TRACE_CASE (disdata->trace_case)
1280 #endif
1281
1282 enum cris_disass_family
1283 { cris_dis_v0_v10, cris_dis_common_v10_v32, cris_dis_v32 };
1284
1285 /* Stored in the disasm_info->private_data member. */
1286 struct cris_disasm_data
1287 {
1288 /* Whether to print something less confusing if we find something
1289 matching a switch-construct. */
1290 bfd_boolean trace_case;
1291
1292 /* Whether this code is flagged as crisv32. FIXME: Should be an enum
1293 that includes "compatible". */
1294 enum cris_disass_family distype;
1295 };
1296
1297 /* Value of first element in switch. */
1298 static long case_offset = 0;
1299
1300 /* How many more case-offsets to print. */
1301 static long case_offset_counter = 0;
1302
1303 /* Number of case offsets. */
1304 static long no_of_case_offsets = 0;
1305
1306 /* Candidate for next case_offset. */
1307 static long last_immediate = 0;
1308
1309 static int cris_constraint
1310 (const char *, unsigned, unsigned, struct cris_disasm_data *);
1311
1312 /* Parse disassembler options and store state in info. FIXME: For the
1313 time being, we abuse static variables. */
1314
1315 static bfd_boolean
1316 cris_parse_disassembler_options (disassemble_info *info,
1317 enum cris_disass_family distype)
1318 {
1319 struct cris_disasm_data *disdata;
1320
1321 info->private_data = calloc (1, sizeof (struct cris_disasm_data));
1322 disdata = (struct cris_disasm_data *) info->private_data;
1323 if (disdata == NULL)
1324 return FALSE;
1325
1326 /* Default true. */
1327 disdata->trace_case
1328 = (info->disassembler_options == NULL
1329 || (strcmp (info->disassembler_options, "nocase") != 0));
1330
1331 disdata->distype = distype;
1332 return TRUE;
1333 }
1334
1335 static const struct cris_spec_reg *
1336 spec_reg_info (unsigned int sreg, enum cris_disass_family distype)
1337 {
1338 int i;
1339
1340 for (i = 0; cris_spec_regs[i].name != NULL; i++)
1341 {
1342 if (cris_spec_regs[i].number == sreg)
1343 {
1344 if (distype == cris_dis_v32)
1345 switch (cris_spec_regs[i].applicable_version)
1346 {
1347 case cris_ver_warning:
1348 case cris_ver_version_all:
1349 case cris_ver_v3p:
1350 case cris_ver_v8p:
1351 case cris_ver_v10p:
1352 case cris_ver_v32p:
1353 /* No ambiguous sizes or register names with CRISv32. */
1354 if (cris_spec_regs[i].warning == NULL)
1355 return &cris_spec_regs[i];
1356 default:
1357 ;
1358 }
1359 else if (cris_spec_regs[i].applicable_version != cris_ver_v32p)
1360 return &cris_spec_regs[i];
1361 }
1362 }
1363
1364 return NULL;
1365 }
1366
1367 /* Return the number of bits in the argument. */
1368
1369 static int
1370 number_of_bits (unsigned int val)
1371 {
1372 int bits;
1373
1374 for (bits = 0; val != 0; val &= val - 1)
1375 bits++;
1376
1377 return bits;
1378 }
1379
1380 /* Get an entry in the opcode-table. */
1381
1382 static const struct cris_opcode *
1383 get_opcode_entry (unsigned int insn,
1384 unsigned int prefix_insn,
1385 struct cris_disasm_data *disdata)
1386 {
1387 /* For non-prefixed insns, we keep a table of pointers, indexed by the
1388 insn code. Each entry is initialized when found to be NULL. */
1389 static const struct cris_opcode **opc_table = NULL;
1390
1391 const struct cris_opcode *max_matchedp = NULL;
1392 const struct cris_opcode **prefix_opc_table = NULL;
1393
1394 /* We hold a table for each prefix that need to be handled differently. */
1395 static const struct cris_opcode **dip_prefixes = NULL;
1396 static const struct cris_opcode **bdapq_m1_prefixes = NULL;
1397 static const struct cris_opcode **bdapq_m2_prefixes = NULL;
1398 static const struct cris_opcode **bdapq_m4_prefixes = NULL;
1399 static const struct cris_opcode **rest_prefixes = NULL;
1400
1401 /* Allocate and clear the opcode-table. */
1402 if (opc_table == NULL)
1403 {
1404 opc_table = malloc (65536 * sizeof (opc_table[0]));
1405 if (opc_table == NULL)
1406 return NULL;
1407
1408 memset (opc_table, 0, 65536 * sizeof (const struct cris_opcode *));
1409
1410 dip_prefixes
1411 = malloc (65536 * sizeof (const struct cris_opcode **));
1412 if (dip_prefixes == NULL)
1413 return NULL;
1414
1415 memset (dip_prefixes, 0, 65536 * sizeof (dip_prefixes[0]));
1416
1417 bdapq_m1_prefixes
1418 = malloc (65536 * sizeof (const struct cris_opcode **));
1419 if (bdapq_m1_prefixes == NULL)
1420 return NULL;
1421
1422 memset (bdapq_m1_prefixes, 0, 65536 * sizeof (bdapq_m1_prefixes[0]));
1423
1424 bdapq_m2_prefixes
1425 = malloc (65536 * sizeof (const struct cris_opcode **));
1426 if (bdapq_m2_prefixes == NULL)
1427 return NULL;
1428
1429 memset (bdapq_m2_prefixes, 0, 65536 * sizeof (bdapq_m2_prefixes[0]));
1430
1431 bdapq_m4_prefixes
1432 = malloc (65536 * sizeof (const struct cris_opcode **));
1433 if (bdapq_m4_prefixes == NULL)
1434 return NULL;
1435
1436 memset (bdapq_m4_prefixes, 0, 65536 * sizeof (bdapq_m4_prefixes[0]));
1437
1438 rest_prefixes
1439 = malloc (65536 * sizeof (const struct cris_opcode **));
1440 if (rest_prefixes == NULL)
1441 return NULL;
1442
1443 memset (rest_prefixes, 0, 65536 * sizeof (rest_prefixes[0]));
1444 }
1445
1446 /* Get the right table if this is a prefix.
1447 This code is connected to cris_constraints in that it knows what
1448 prefixes play a role in recognition of patterns; the necessary
1449 state is reflected by which table is used. If constraints
1450 involving match or non-match of prefix insns are changed, then this
1451 probably needs changing too. */
1452 if (prefix_insn != NO_CRIS_PREFIX)
1453 {
1454 const struct cris_opcode *popcodep
1455 = (opc_table[prefix_insn] != NULL
1456 ? opc_table[prefix_insn]
1457 : get_opcode_entry (prefix_insn, NO_CRIS_PREFIX, disdata));
1458
1459 if (popcodep == NULL)
1460 return NULL;
1461
1462 if (popcodep->match == BDAP_QUICK_OPCODE)
1463 {
1464 /* Since some offsets are recognized with "push" macros, we
1465 have to have different tables for them. */
1466 int offset = (prefix_insn & 255);
1467
1468 if (offset > 127)
1469 offset -= 256;
1470
1471 switch (offset)
1472 {
1473 case -4:
1474 prefix_opc_table = bdapq_m4_prefixes;
1475 break;
1476
1477 case -2:
1478 prefix_opc_table = bdapq_m2_prefixes;
1479 break;
1480
1481 case -1:
1482 prefix_opc_table = bdapq_m1_prefixes;
1483 break;
1484
1485 default:
1486 prefix_opc_table = rest_prefixes;
1487 break;
1488 }
1489 }
1490 else if (popcodep->match == DIP_OPCODE)
1491 /* We don't allow postincrement when the prefix is DIP, so use a
1492 different table for DIP. */
1493 prefix_opc_table = dip_prefixes;
1494 else
1495 prefix_opc_table = rest_prefixes;
1496 }
1497
1498 if (prefix_insn != NO_CRIS_PREFIX
1499 && prefix_opc_table[insn] != NULL)
1500 max_matchedp = prefix_opc_table[insn];
1501 else if (prefix_insn == NO_CRIS_PREFIX && opc_table[insn] != NULL)
1502 max_matchedp = opc_table[insn];
1503 else
1504 {
1505 const struct cris_opcode *opcodep;
1506 int max_level_of_match = -1;
1507
1508 for (opcodep = cris_opcodes;
1509 opcodep->name != NULL;
1510 opcodep++)
1511 {
1512 int level_of_match;
1513
1514 if (disdata->distype == cris_dis_v32)
1515 {
1516 switch (opcodep->applicable_version)
1517 {
1518 case cris_ver_version_all:
1519 break;
1520
1521 case cris_ver_v0_3:
1522 case cris_ver_v0_10:
1523 case cris_ver_v3_10:
1524 case cris_ver_sim_v0_10:
1525 case cris_ver_v8_10:
1526 case cris_ver_v10:
1527 case cris_ver_warning:
1528 continue;
1529
1530 case cris_ver_v3p:
1531 case cris_ver_v8p:
1532 case cris_ver_v10p:
1533 case cris_ver_v32p:
1534 break;
1535
1536 case cris_ver_v8:
1537 abort ();
1538 default:
1539 abort ();
1540 }
1541 }
1542 else
1543 {
1544 switch (opcodep->applicable_version)
1545 {
1546 case cris_ver_version_all:
1547 case cris_ver_v0_3:
1548 case cris_ver_v3p:
1549 case cris_ver_v0_10:
1550 case cris_ver_v8p:
1551 case cris_ver_v8_10:
1552 case cris_ver_v10:
1553 case cris_ver_sim_v0_10:
1554 case cris_ver_v10p:
1555 case cris_ver_warning:
1556 break;
1557
1558 case cris_ver_v32p:
1559 continue;
1560
1561 case cris_ver_v8:
1562 abort ();
1563 default:
1564 abort ();
1565 }
1566 }
1567
1568 /* We give a double lead for bits matching the template in
1569 cris_opcodes. Not even, because then "move p8,r10" would
1570 be given 2 bits lead over "clear.d r10". When there's a
1571 tie, the first entry in the table wins. This is
1572 deliberate, to avoid a more complicated recognition
1573 formula. */
1574 if ((opcodep->match & insn) == opcodep->match
1575 && (opcodep->lose & insn) == 0
1576 && ((level_of_match
1577 = cris_constraint (opcodep->args,
1578 insn,
1579 prefix_insn,
1580 disdata))
1581 >= 0)
1582 && ((level_of_match
1583 += 2 * number_of_bits (opcodep->match
1584 | opcodep->lose))
1585 > max_level_of_match))
1586 {
1587 max_matchedp = opcodep;
1588 max_level_of_match = level_of_match;
1589
1590 /* If there was a full match, never mind looking
1591 further. */
1592 if (level_of_match >= 2 * 16)
1593 break;
1594 }
1595 }
1596 /* Fill in the new entry.
1597
1598 If there are changes to the opcode-table involving prefixes, and
1599 disassembly then does not work correctly, try removing the
1600 else-clause below that fills in the prefix-table. If that
1601 helps, you need to change the prefix_opc_table setting above, or
1602 something related. */
1603 if (prefix_insn == NO_CRIS_PREFIX)
1604 opc_table[insn] = max_matchedp;
1605 else
1606 prefix_opc_table[insn] = max_matchedp;
1607 }
1608
1609 return max_matchedp;
1610 }
1611
1612 /* Return -1 if the constraints of a bitwise-matched instruction say
1613 that there is no match. Otherwise return a nonnegative number
1614 indicating the confidence in the match (higher is better). */
1615
1616 static int
1617 cris_constraint (const char *cs,
1618 unsigned int insn,
1619 unsigned int prefix_insn,
1620 struct cris_disasm_data *disdata)
1621 {
1622 int retval = 0;
1623 int tmp;
1624 int prefix_ok = 0;
1625 const char *s;
1626
1627 for (s = cs; *s; s++)
1628 switch (*s)
1629 {
1630 case '!':
1631 /* Do not recognize "pop" if there's a prefix and then only for
1632 v0..v10. */
1633 if (prefix_insn != NO_CRIS_PREFIX
1634 || disdata->distype != cris_dis_v0_v10)
1635 return -1;
1636 break;
1637
1638 case 'U':
1639 /* Not recognized at disassembly. */
1640 return -1;
1641
1642 case 'M':
1643 /* Size modifier for "clear", i.e. special register 0, 4 or 8.
1644 Check that it is one of them. Only special register 12 could
1645 be mismatched, but checking for matches is more logical than
1646 checking for mismatches when there are only a few cases. */
1647 tmp = ((insn >> 12) & 0xf);
1648 if (tmp != 0 && tmp != 4 && tmp != 8)
1649 return -1;
1650 break;
1651
1652 case 'm':
1653 if ((insn & 0x30) == 0x30)
1654 return -1;
1655 break;
1656
1657 case 'S':
1658 /* A prefix operand without side-effect. */
1659 if (prefix_insn != NO_CRIS_PREFIX && (insn & 0x400) == 0)
1660 {
1661 prefix_ok = 1;
1662 break;
1663 }
1664 else
1665 return -1;
1666
1667 case 's':
1668 case 'y':
1669 case 'Y':
1670 /* If this is a prefixed insn with postincrement (side-effect),
1671 the prefix must not be DIP. */
1672 if (prefix_insn != NO_CRIS_PREFIX)
1673 {
1674 if (insn & 0x400)
1675 {
1676 const struct cris_opcode *prefix_opcodep
1677 = get_opcode_entry (prefix_insn, NO_CRIS_PREFIX, disdata);
1678
1679 if (prefix_opcodep->match == DIP_OPCODE)
1680 return -1;
1681 }
1682
1683 prefix_ok = 1;
1684 }
1685 break;
1686
1687 case 'B':
1688 /* If we don't fall through, then the prefix is ok. */
1689 prefix_ok = 1;
1690
1691 /* A "push" prefix. Check for valid "push" size.
1692 In case of special register, it may be != 4. */
1693 if (prefix_insn != NO_CRIS_PREFIX)
1694 {
1695 /* Match the prefix insn to BDAPQ. */
1696 const struct cris_opcode *prefix_opcodep
1697 = get_opcode_entry (prefix_insn, NO_CRIS_PREFIX, disdata);
1698
1699 if (prefix_opcodep->match == BDAP_QUICK_OPCODE)
1700 {
1701 int pushsize = (prefix_insn & 255);
1702
1703 if (pushsize > 127)
1704 pushsize -= 256;
1705
1706 if (s[1] == 'P')
1707 {
1708 unsigned int spec_reg = (insn >> 12) & 15;
1709 const struct cris_spec_reg *sregp
1710 = spec_reg_info (spec_reg, disdata->distype);
1711
1712 /* For a special-register, the "prefix size" must
1713 match the size of the register. */
1714 if (sregp && sregp->reg_size == (unsigned int) -pushsize)
1715 break;
1716 }
1717 else if (s[1] == 'R')
1718 {
1719 if ((insn & 0x30) == 0x20 && pushsize == -4)
1720 break;
1721 }
1722 /* FIXME: Should abort here; next constraint letter
1723 *must* be 'P' or 'R'. */
1724 }
1725 }
1726 return -1;
1727
1728 case 'D':
1729 retval = (((insn >> 12) & 15) == (insn & 15));
1730 if (!retval)
1731 return -1;
1732 else
1733 retval += 4;
1734 break;
1735
1736 case 'P':
1737 {
1738 const struct cris_spec_reg *sregp
1739 = spec_reg_info ((insn >> 12) & 15, disdata->distype);
1740
1741 /* Since we match four bits, we will give a value of 4-1 = 3
1742 in a match. If there is a corresponding exact match of a
1743 special register in another pattern, it will get a value of
1744 4, which will be higher. This should be correct in that an
1745 exact pattern would match better than a general pattern.
1746
1747 Note that there is a reason for not returning zero; the
1748 pattern for "clear" is partly matched in the bit-pattern
1749 (the two lower bits must be zero), while the bit-pattern
1750 for a move from a special register is matched in the
1751 register constraint. */
1752
1753 if (sregp != NULL)
1754 {
1755 retval += 3;
1756 break;
1757 }
1758 else
1759 return -1;
1760 }
1761 }
1762
1763 if (prefix_insn != NO_CRIS_PREFIX && ! prefix_ok)
1764 return -1;
1765
1766 return retval;
1767 }
1768
1769 /* Format number as hex with a leading "0x" into outbuffer. */
1770
1771 static char *
1772 format_hex (unsigned long number,
1773 char *outbuffer,
1774 struct cris_disasm_data *disdata)
1775 {
1776 /* Truncate negative numbers on >32-bit hosts. */
1777 number &= 0xffffffff;
1778
1779 sprintf (outbuffer, "0x%lx", number);
1780
1781 /* Save this value for the "case" support. */
1782 if (TRACE_CASE)
1783 last_immediate = number;
1784
1785 return outbuffer + strlen (outbuffer);
1786 }
1787
1788 /* Format number as decimal into outbuffer. Parameter signedp says
1789 whether the number should be formatted as signed (!= 0) or
1790 unsigned (== 0). */
1791
1792 static char *
1793 format_dec (long number, char *outbuffer, int signedp)
1794 {
1795 last_immediate = number;
1796 sprintf (outbuffer, signedp ? "%ld" : "%lu", number);
1797
1798 return outbuffer + strlen (outbuffer);
1799 }
1800
1801 /* Format the name of the general register regno into outbuffer. */
1802
1803 static char *
1804 format_reg (struct cris_disasm_data *disdata,
1805 int regno,
1806 char *outbuffer_start,
1807 bfd_boolean with_reg_prefix)
1808 {
1809 char *outbuffer = outbuffer_start;
1810
1811 if (with_reg_prefix)
1812 *outbuffer++ = REGISTER_PREFIX_CHAR;
1813
1814 switch (regno)
1815 {
1816 case 15:
1817 /* For v32, there is no context in which we output PC. */
1818 if (disdata->distype == cris_dis_v32)
1819 strcpy (outbuffer, "acr");
1820 else
1821 strcpy (outbuffer, "pc");
1822 break;
1823
1824 case 14:
1825 strcpy (outbuffer, "sp");
1826 break;
1827
1828 default:
1829 sprintf (outbuffer, "r%d", regno);
1830 break;
1831 }
1832
1833 return outbuffer_start + strlen (outbuffer_start);
1834 }
1835
1836 /* Format the name of a support register into outbuffer. */
1837
1838 static char *
1839 format_sup_reg (unsigned int regno,
1840 char *outbuffer_start,
1841 bfd_boolean with_reg_prefix)
1842 {
1843 char *outbuffer = outbuffer_start;
1844 int i;
1845
1846 if (with_reg_prefix)
1847 *outbuffer++ = REGISTER_PREFIX_CHAR;
1848
1849 for (i = 0; cris_support_regs[i].name != NULL; i++)
1850 if (cris_support_regs[i].number == regno)
1851 {
1852 sprintf (outbuffer, "%s", cris_support_regs[i].name);
1853 return outbuffer_start + strlen (outbuffer_start);
1854 }
1855
1856 /* There's supposed to be register names covering all numbers, though
1857 some may be generic names. */
1858 sprintf (outbuffer, "format_sup_reg-BUG");
1859 return outbuffer_start + strlen (outbuffer_start);
1860 }
1861
1862 /* Return the length of an instruction. */
1863
1864 static unsigned
1865 bytes_to_skip (unsigned int insn,
1866 const struct cris_opcode *matchedp,
1867 enum cris_disass_family distype,
1868 const struct cris_opcode *prefix_matchedp)
1869 {
1870 /* Each insn is a word plus "immediate" operands. */
1871 unsigned to_skip = 2;
1872 const char *template = matchedp->args;
1873 const char *s;
1874
1875 for (s = template; *s; s++)
1876 if ((*s == 's' || *s == 'N' || *s == 'Y')
1877 && (insn & 0x400) && (insn & 15) == 15
1878 && prefix_matchedp == NULL)
1879 {
1880 /* Immediate via [pc+], so we have to check the size of the
1881 operand. */
1882 int mode_size = 1 << ((insn >> 4) & (*template == 'z' ? 1 : 3));
1883
1884 if (matchedp->imm_oprnd_size == SIZE_FIX_32)
1885 to_skip += 4;
1886 else if (matchedp->imm_oprnd_size == SIZE_SPEC_REG)
1887 {
1888 const struct cris_spec_reg *sregp
1889 = spec_reg_info ((insn >> 12) & 15, distype);
1890
1891 /* FIXME: Improve error handling; should have been caught
1892 earlier. */
1893 if (sregp == NULL)
1894 return 2;
1895
1896 /* PC is incremented by two, not one, for a byte. Except on
1897 CRISv32, where constants are always DWORD-size for
1898 special registers. */
1899 to_skip +=
1900 distype == cris_dis_v32 ? 4 : (sregp->reg_size + 1) & ~1;
1901 }
1902 else
1903 to_skip += (mode_size + 1) & ~1;
1904 }
1905 else if (*s == 'n')
1906 to_skip += 4;
1907 else if (*s == 'b')
1908 to_skip += 2;
1909
1910 return to_skip;
1911 }
1912
1913 /* Print condition code flags. */
1914
1915 static char *
1916 print_flags (struct cris_disasm_data *disdata, unsigned int insn, char *cp)
1917 {
1918 /* Use the v8 (Etrax 100) flag definitions for disassembly.
1919 The differences with v0 (Etrax 1..4) vs. Svinto are:
1920 v0 'd' <=> v8 'm'
1921 v0 'e' <=> v8 'b'.
1922 FIXME: Emit v0..v3 flag names somehow. */
1923 static const char v8_fnames[] = "cvznxibm";
1924 static const char v32_fnames[] = "cvznxiup";
1925 const char *fnames
1926 = disdata->distype == cris_dis_v32 ? v32_fnames : v8_fnames;
1927
1928 unsigned char flagbits = (((insn >> 8) & 0xf0) | (insn & 15));
1929 int i;
1930
1931 for (i = 0; i < 8; i++)
1932 if (flagbits & (1 << i))
1933 *cp++ = fnames[i];
1934
1935 return cp;
1936 }
1937
1938 /* Print out an insn with its operands, and update the info->insn_type
1939 fields. The prefix_opcodep and the rest hold a prefix insn that is
1940 supposed to be output as an address mode. */
1941
1942 static void
1943 print_with_operands (const struct cris_opcode *opcodep,
1944 unsigned int insn,
1945 unsigned char *buffer,
1946 bfd_vma addr,
1947 disassemble_info *info,
1948 /* If a prefix insn was before this insn (and is supposed
1949 to be output as an address), here is a description of
1950 it. */
1951 const struct cris_opcode *prefix_opcodep,
1952 unsigned int prefix_insn,
1953 unsigned char *prefix_buffer,
1954 bfd_boolean with_reg_prefix)
1955 {
1956 /* Get a buffer of somewhat reasonable size where we store
1957 intermediate parts of the insn. */
1958 char temp[sizeof (".d [$r13=$r12-2147483648],$r10") * 2];
1959 char *tp = temp;
1960 static const char mode_char[] = "bwd?";
1961 const char *s;
1962 const char *cs;
1963 struct cris_disasm_data *disdata
1964 = (struct cris_disasm_data *) info->private_data;
1965
1966 /* Print out the name first thing we do. */
1967 (*info->fprintf_func) (info->stream, "%s", opcodep->name);
1968
1969 cs = opcodep->args;
1970 s = cs;
1971
1972 /* Ignore any prefix indicator. */
1973 if (*s == 'p')
1974 s++;
1975
1976 if (*s == 'm' || *s == 'M' || *s == 'z')
1977 {
1978 *tp++ = '.';
1979
1980 /* Get the size-letter. */
1981 *tp++ = *s == 'M'
1982 ? (insn & 0x8000 ? 'd'
1983 : insn & 0x4000 ? 'w' : 'b')
1984 : mode_char[(insn >> 4) & (*s == 'z' ? 1 : 3)];
1985
1986 /* Ignore the size and the space character that follows. */
1987 s += 2;
1988 }
1989
1990 /* Add a space if this isn't a long-branch, because for those will add
1991 the condition part of the name later. */
1992 if (opcodep->match != (BRANCH_PC_LOW + BRANCH_INCR_HIGH * 256))
1993 *tp++ = ' ';
1994
1995 /* Fill in the insn-type if deducible from the name (and there's no
1996 better way). */
1997 if (opcodep->name[0] == 'j')
1998 {
1999 if (CONST_STRNEQ (opcodep->name, "jsr"))
2000 /* It's "jsr" or "jsrc". */
2001 info->insn_type = dis_jsr;
2002 else
2003 /* Any other jump-type insn is considered a branch. */
2004 info->insn_type = dis_branch;
2005 }
2006
2007 /* We might know some more fields right now. */
2008 info->branch_delay_insns = opcodep->delayed;
2009
2010 /* Handle operands. */
2011 for (; *s; s++)
2012 {
2013 switch (*s)
2014 {
2015 case 'T':
2016 tp = format_sup_reg ((insn >> 12) & 15, tp, with_reg_prefix);
2017 break;
2018
2019 case 'A':
2020 if (with_reg_prefix)
2021 *tp++ = REGISTER_PREFIX_CHAR;
2022 *tp++ = 'a';
2023 *tp++ = 'c';
2024 *tp++ = 'r';
2025 break;
2026
2027 case '[':
2028 case ']':
2029 case ',':
2030 *tp++ = *s;
2031 break;
2032
2033 case '!':
2034 /* Ignore at this point; used at earlier stages to avoid
2035 recognition if there's a prefix at something that in other
2036 ways looks like a "pop". */
2037 break;
2038
2039 case 'd':
2040 /* Ignore. This is an optional ".d " on the large one of
2041 relaxable insns. */
2042 break;
2043
2044 case 'B':
2045 /* This was the prefix that made this a "push". We've already
2046 handled it by recognizing it, so signal that the prefix is
2047 handled by setting it to NULL. */
2048 prefix_opcodep = NULL;
2049 break;
2050
2051 case 'D':
2052 case 'r':
2053 tp = format_reg (disdata, insn & 15, tp, with_reg_prefix);
2054 break;
2055
2056 case 'R':
2057 tp = format_reg (disdata, (insn >> 12) & 15, tp, with_reg_prefix);
2058 break;
2059
2060 case 'n':
2061 {
2062 /* Like N but pc-relative to the start of the insn. */
2063 unsigned long number
2064 = (buffer[2] + buffer[3] * 256 + buffer[4] * 65536
2065 + buffer[5] * 0x1000000 + addr);
2066
2067 /* Finish off and output previous formatted bytes. */
2068 *tp = 0;
2069 if (temp[0])
2070 (*info->fprintf_func) (info->stream, "%s", temp);
2071 tp = temp;
2072
2073 (*info->print_address_func) ((bfd_vma) number, info);
2074 }
2075 break;
2076
2077 case 'u':
2078 {
2079 /* Like n but the offset is bits <3:0> in the instruction. */
2080 unsigned long number = (buffer[0] & 0xf) * 2 + addr;
2081
2082 /* Finish off and output previous formatted bytes. */
2083 *tp = 0;
2084 if (temp[0])
2085 (*info->fprintf_func) (info->stream, "%s", temp);
2086 tp = temp;
2087
2088 (*info->print_address_func) ((bfd_vma) number, info);
2089 }
2090 break;
2091
2092 case 'N':
2093 case 'y':
2094 case 'Y':
2095 case 'S':
2096 case 's':
2097 /* Any "normal" memory operand. */
2098 if ((insn & 0x400) && (insn & 15) == 15 && prefix_opcodep == NULL)
2099 {
2100 /* We're looking at [pc+], i.e. we need to output an immediate
2101 number, where the size can depend on different things. */
2102 long number;
2103 int signedp
2104 = ((*cs == 'z' && (insn & 0x20))
2105 || opcodep->match == BDAP_QUICK_OPCODE);
2106 int nbytes;
2107
2108 if (opcodep->imm_oprnd_size == SIZE_FIX_32)
2109 nbytes = 4;
2110 else if (opcodep->imm_oprnd_size == SIZE_SPEC_REG)
2111 {
2112 const struct cris_spec_reg *sregp
2113 = spec_reg_info ((insn >> 12) & 15, disdata->distype);
2114
2115 /* A NULL return should have been as a non-match earlier,
2116 so catch it as an internal error in the error-case
2117 below. */
2118 if (sregp == NULL)
2119 /* Whatever non-valid size. */
2120 nbytes = 42;
2121 else
2122 /* PC is always incremented by a multiple of two.
2123 For CRISv32, immediates are always 4 bytes for
2124 special registers. */
2125 nbytes = disdata->distype == cris_dis_v32
2126 ? 4 : (sregp->reg_size + 1) & ~1;
2127 }
2128 else
2129 {
2130 int mode_size = 1 << ((insn >> 4) & (*cs == 'z' ? 1 : 3));
2131
2132 if (mode_size == 1)
2133 nbytes = 2;
2134 else
2135 nbytes = mode_size;
2136 }
2137
2138 switch (nbytes)
2139 {
2140 case 1:
2141 number = buffer[2];
2142 if (signedp && number > 127)
2143 number -= 256;
2144 break;
2145
2146 case 2:
2147 number = buffer[2] + buffer[3] * 256;
2148 if (signedp && number > 32767)
2149 number -= 65536;
2150 break;
2151
2152 case 4:
2153 number
2154 = buffer[2] + buffer[3] * 256 + buffer[4] * 65536
2155 + buffer[5] * 0x1000000;
2156 break;
2157
2158 default:
2159 strcpy (tp, "bug");
2160 tp += 3;
2161 number = 42;
2162 }
2163
2164 if ((*cs == 'z' && (insn & 0x20))
2165 || (opcodep->match == BDAP_QUICK_OPCODE
2166 && (nbytes <= 2 || buffer[1 + nbytes] == 0)))
2167 tp = format_dec (number, tp, signedp);
2168 else
2169 {
2170 unsigned int highbyte = (number >> 24) & 0xff;
2171
2172 /* Either output this as an address or as a number. If it's
2173 a dword with the same high-byte as the address of the
2174 insn, assume it's an address, and also if it's a non-zero
2175 non-0xff high-byte. If this is a jsr or a jump, then
2176 it's definitely an address. */
2177 if (nbytes == 4
2178 && (highbyte == ((addr >> 24) & 0xff)
2179 || (highbyte != 0 && highbyte != 0xff)
2180 || info->insn_type == dis_branch
2181 || info->insn_type == dis_jsr))
2182 {
2183 /* Finish off and output previous formatted bytes. */
2184 *tp = 0;
2185 tp = temp;
2186 if (temp[0])
2187 (*info->fprintf_func) (info->stream, "%s", temp);
2188
2189 (*info->print_address_func) ((bfd_vma) number, info);
2190
2191 info->target = number;
2192 }
2193 else
2194 tp = format_hex (number, tp, disdata);
2195 }
2196 }
2197 else
2198 {
2199 /* Not an immediate number. Then this is a (possibly
2200 prefixed) memory operand. */
2201 if (info->insn_type != dis_nonbranch)
2202 {
2203 int mode_size
2204 = 1 << ((insn >> 4)
2205 & (opcodep->args[0] == 'z' ? 1 : 3));
2206 int size;
2207 info->insn_type = dis_dref;
2208 info->flags |= CRIS_DIS_FLAG_MEMREF;
2209
2210 if (opcodep->imm_oprnd_size == SIZE_FIX_32)
2211 size = 4;
2212 else if (opcodep->imm_oprnd_size == SIZE_SPEC_REG)
2213 {
2214 const struct cris_spec_reg *sregp
2215 = spec_reg_info ((insn >> 12) & 15, disdata->distype);
2216
2217 /* FIXME: Improve error handling; should have been caught
2218 earlier. */
2219 if (sregp == NULL)
2220 size = 4;
2221 else
2222 size = sregp->reg_size;
2223 }
2224 else
2225 size = mode_size;
2226
2227 info->data_size = size;
2228 }
2229
2230 *tp++ = '[';
2231
2232 if (prefix_opcodep
2233 /* We don't match dip with a postincremented field
2234 as a side-effect address mode. */
2235 && ((insn & 0x400) == 0
2236 || prefix_opcodep->match != DIP_OPCODE))
2237 {
2238 if (insn & 0x400)
2239 {
2240 tp = format_reg (disdata, insn & 15, tp, with_reg_prefix);
2241 *tp++ = '=';
2242 }
2243
2244
2245 /* We mainly ignore the prefix format string when the
2246 address-mode syntax is output. */
2247 switch (prefix_opcodep->match)
2248 {
2249 case DIP_OPCODE:
2250 /* It's [r], [r+] or [pc+]. */
2251 if ((prefix_insn & 0x400) && (prefix_insn & 15) == 15)
2252 {
2253 /* It's [pc+]. This cannot possibly be anything
2254 but an address. */
2255 unsigned long number
2256 = prefix_buffer[2] + prefix_buffer[3] * 256
2257 + prefix_buffer[4] * 65536
2258 + prefix_buffer[5] * 0x1000000;
2259
2260 info->target = (bfd_vma) number;
2261
2262 /* Finish off and output previous formatted
2263 data. */
2264 *tp = 0;
2265 tp = temp;
2266 if (temp[0])
2267 (*info->fprintf_func) (info->stream, "%s", temp);
2268
2269 (*info->print_address_func) ((bfd_vma) number, info);
2270 }
2271 else
2272 {
2273 /* For a memref in an address, we use target2.
2274 In this case, target is zero. */
2275 info->flags
2276 |= (CRIS_DIS_FLAG_MEM_TARGET2_IS_REG
2277 | CRIS_DIS_FLAG_MEM_TARGET2_MEM);
2278
2279 info->target2 = prefix_insn & 15;
2280
2281 *tp++ = '[';
2282 tp = format_reg (disdata, prefix_insn & 15, tp,
2283 with_reg_prefix);
2284 if (prefix_insn & 0x400)
2285 *tp++ = '+';
2286 *tp++ = ']';
2287 }
2288 break;
2289
2290 case BDAP_QUICK_OPCODE:
2291 {
2292 int number;
2293
2294 number = prefix_buffer[0];
2295 if (number > 127)
2296 number -= 256;
2297
2298 /* Output "reg+num" or, if num < 0, "reg-num". */
2299 tp = format_reg (disdata, (prefix_insn >> 12) & 15, tp,
2300 with_reg_prefix);
2301 if (number >= 0)
2302 *tp++ = '+';
2303 tp = format_dec (number, tp, 1);
2304
2305 info->flags |= CRIS_DIS_FLAG_MEM_TARGET_IS_REG;
2306 info->target = (prefix_insn >> 12) & 15;
2307 info->target2 = (bfd_vma) number;
2308 break;
2309 }
2310
2311 case BIAP_OPCODE:
2312 /* Output "r+R.m". */
2313 tp = format_reg (disdata, prefix_insn & 15, tp,
2314 with_reg_prefix);
2315 *tp++ = '+';
2316 tp = format_reg (disdata, (prefix_insn >> 12) & 15, tp,
2317 with_reg_prefix);
2318 *tp++ = '.';
2319 *tp++ = mode_char[(prefix_insn >> 4) & 3];
2320
2321 info->flags
2322 |= (CRIS_DIS_FLAG_MEM_TARGET2_IS_REG
2323 | CRIS_DIS_FLAG_MEM_TARGET_IS_REG
2324
2325 | ((prefix_insn & 0x8000)
2326 ? CRIS_DIS_FLAG_MEM_TARGET2_MULT4
2327 : ((prefix_insn & 0x8000)
2328 ? CRIS_DIS_FLAG_MEM_TARGET2_MULT2 : 0)));
2329
2330 /* Is it the casejump? It's a "adds.w [pc+r%d.w],pc". */
2331 if (insn == 0xf83f && (prefix_insn & ~0xf000) == 0x55f)
2332 /* Then start interpreting data as offsets. */
2333 case_offset_counter = no_of_case_offsets;
2334 break;
2335
2336 case BDAP_INDIR_OPCODE:
2337 /* Output "r+s.m", or, if "s" is [pc+], "r+s" or
2338 "r-s". */
2339 tp = format_reg (disdata, (prefix_insn >> 12) & 15, tp,
2340 with_reg_prefix);
2341
2342 if ((prefix_insn & 0x400) && (prefix_insn & 15) == 15)
2343 {
2344 long number;
2345 unsigned int nbytes;
2346
2347 /* It's a value. Get its size. */
2348 int mode_size = 1 << ((prefix_insn >> 4) & 3);
2349
2350 if (mode_size == 1)
2351 nbytes = 2;
2352 else
2353 nbytes = mode_size;
2354
2355 switch (nbytes)
2356 {
2357 case 1:
2358 number = prefix_buffer[2];
2359 if (number > 127)
2360 number -= 256;
2361 break;
2362
2363 case 2:
2364 number = prefix_buffer[2] + prefix_buffer[3] * 256;
2365 if (number > 32767)
2366 number -= 65536;
2367 break;
2368
2369 case 4:
2370 number
2371 = prefix_buffer[2] + prefix_buffer[3] * 256
2372 + prefix_buffer[4] * 65536
2373 + prefix_buffer[5] * 0x1000000;
2374 break;
2375
2376 default:
2377 strcpy (tp, "bug");
2378 tp += 3;
2379 number = 42;
2380 }
2381
2382 info->flags |= CRIS_DIS_FLAG_MEM_TARGET_IS_REG;
2383 info->target2 = (bfd_vma) number;
2384
2385 /* If the size is dword, then assume it's an
2386 address. */
2387 if (nbytes == 4)
2388 {
2389 /* Finish off and output previous formatted
2390 bytes. */
2391 *tp++ = '+';
2392 *tp = 0;
2393 tp = temp;
2394 (*info->fprintf_func) (info->stream, "%s", temp);
2395
2396 (*info->print_address_func) ((bfd_vma) number, info);
2397 }
2398 else
2399 {
2400 if (number >= 0)
2401 *tp++ = '+';
2402 tp = format_dec (number, tp, 1);
2403 }
2404 }
2405 else
2406 {
2407 /* Output "r+[R].m" or "r+[R+].m". */
2408 *tp++ = '+';
2409 *tp++ = '[';
2410 tp = format_reg (disdata, prefix_insn & 15, tp,
2411 with_reg_prefix);
2412 if (prefix_insn & 0x400)
2413 *tp++ = '+';
2414 *tp++ = ']';
2415 *tp++ = '.';
2416 *tp++ = mode_char[(prefix_insn >> 4) & 3];
2417
2418 info->flags
2419 |= (CRIS_DIS_FLAG_MEM_TARGET2_IS_REG
2420 | CRIS_DIS_FLAG_MEM_TARGET2_MEM
2421 | CRIS_DIS_FLAG_MEM_TARGET_IS_REG
2422
2423 | (((prefix_insn >> 4) == 2)
2424 ? 0
2425 : (((prefix_insn >> 4) & 3) == 1
2426 ? CRIS_DIS_FLAG_MEM_TARGET2_MEM_WORD
2427 : CRIS_DIS_FLAG_MEM_TARGET2_MEM_BYTE)));
2428 }
2429 break;
2430
2431 default:
2432 (*info->fprintf_func) (info->stream, "?prefix-bug");
2433 }
2434
2435 /* To mark that the prefix is used, reset it. */
2436 prefix_opcodep = NULL;
2437 }
2438 else
2439 {
2440 tp = format_reg (disdata, insn & 15, tp, with_reg_prefix);
2441
2442 info->flags |= CRIS_DIS_FLAG_MEM_TARGET_IS_REG;
2443 info->target = insn & 15;
2444
2445 if (insn & 0x400)
2446 *tp++ = '+';
2447 }
2448 *tp++ = ']';
2449 }
2450 break;
2451
2452 case 'x':
2453 tp = format_reg (disdata, (insn >> 12) & 15, tp, with_reg_prefix);
2454 *tp++ = '.';
2455 *tp++ = mode_char[(insn >> 4) & 3];
2456 break;
2457
2458 case 'I':
2459 tp = format_dec (insn & 63, tp, 0);
2460 break;
2461
2462 case 'b':
2463 {
2464 int where = buffer[2] + buffer[3] * 256;
2465
2466 if (where > 32767)
2467 where -= 65536;
2468
2469 where += addr + ((disdata->distype == cris_dis_v32) ? 0 : 4);
2470
2471 if (insn == BA_PC_INCR_OPCODE)
2472 info->insn_type = dis_branch;
2473 else
2474 info->insn_type = dis_condbranch;
2475
2476 info->target = (bfd_vma) where;
2477
2478 *tp = 0;
2479 tp = temp;
2480 (*info->fprintf_func) (info->stream, "%s%s ",
2481 temp, cris_cc_strings[insn >> 12]);
2482
2483 (*info->print_address_func) ((bfd_vma) where, info);
2484 }
2485 break;
2486
2487 case 'c':
2488 tp = format_dec (insn & 31, tp, 0);
2489 break;
2490
2491 case 'C':
2492 tp = format_dec (insn & 15, tp, 0);
2493 break;
2494
2495 case 'o':
2496 {
2497 long offset = insn & 0xfe;
2498 bfd_vma target;
2499
2500 if (insn & 1)
2501 offset |= ~0xff;
2502
2503 if (opcodep->match == BA_QUICK_OPCODE)
2504 info->insn_type = dis_branch;
2505 else
2506 info->insn_type = dis_condbranch;
2507
2508 target = addr + ((disdata->distype == cris_dis_v32) ? 0 : 2) + offset;
2509 info->target = target;
2510 *tp = 0;
2511 tp = temp;
2512 (*info->fprintf_func) (info->stream, "%s", temp);
2513 (*info->print_address_func) (target, info);
2514 }
2515 break;
2516
2517 case 'Q':
2518 case 'O':
2519 {
2520 long number = buffer[0];
2521
2522 if (number > 127)
2523 number = number - 256;
2524
2525 tp = format_dec (number, tp, 1);
2526 *tp++ = ',';
2527 tp = format_reg (disdata, (insn >> 12) & 15, tp, with_reg_prefix);
2528 }
2529 break;
2530
2531 case 'f':
2532 tp = print_flags (disdata, insn, tp);
2533 break;
2534
2535 case 'i':
2536 tp = format_dec ((insn & 32) ? (insn & 31) | ~31L : insn & 31, tp, 1);
2537 break;
2538
2539 case 'P':
2540 {
2541 const struct cris_spec_reg *sregp
2542 = spec_reg_info ((insn >> 12) & 15, disdata->distype);
2543
2544 if (sregp->name == NULL)
2545 /* Should have been caught as a non-match eariler. */
2546 *tp++ = '?';
2547 else
2548 {
2549 if (with_reg_prefix)
2550 *tp++ = REGISTER_PREFIX_CHAR;
2551 strcpy (tp, sregp->name);
2552 tp += strlen (tp);
2553 }
2554 }
2555 break;
2556
2557 default:
2558 strcpy (tp, "???");
2559 tp += 3;
2560 }
2561 }
2562
2563 *tp = 0;
2564
2565 if (prefix_opcodep)
2566 (*info->fprintf_func) (info->stream, " (OOPS unused prefix \"%s: %s\")",
2567 prefix_opcodep->name, prefix_opcodep->args);
2568
2569 (*info->fprintf_func) (info->stream, "%s", temp);
2570
2571 /* Get info for matching case-tables, if we don't have any active.
2572 We assume that the last constant seen is used; either in the insn
2573 itself or in a "move.d const,rN, sub.d rN,rM"-like sequence. */
2574 if (TRACE_CASE && case_offset_counter == 0)
2575 {
2576 if (CONST_STRNEQ (opcodep->name, "sub"))
2577 case_offset = last_immediate;
2578
2579 /* It could also be an "add", if there are negative case-values. */
2580 else if (CONST_STRNEQ (opcodep->name, "add"))
2581 /* The first case is the negated operand to the add. */
2582 case_offset = -last_immediate;
2583
2584 /* A bound insn will tell us the number of cases. */
2585 else if (CONST_STRNEQ (opcodep->name, "bound"))
2586 no_of_case_offsets = last_immediate + 1;
2587
2588 /* A jump or jsr or branch breaks the chain of insns for a
2589 case-table, so assume default first-case again. */
2590 else if (info->insn_type == dis_jsr
2591 || info->insn_type == dis_branch
2592 || info->insn_type == dis_condbranch)
2593 case_offset = 0;
2594 }
2595 }
2596
2597
2598 /* Print the CRIS instruction at address memaddr on stream. Returns
2599 length of the instruction, in bytes. Prefix register names with `$' if
2600 WITH_REG_PREFIX. */
2601
2602 static int
2603 print_insn_cris_generic (bfd_vma memaddr,
2604 disassemble_info *info,
2605 bfd_boolean with_reg_prefix)
2606 {
2607 int nbytes;
2608 unsigned int insn;
2609 const struct cris_opcode *matchedp;
2610 int advance = 0;
2611 struct cris_disasm_data *disdata
2612 = (struct cris_disasm_data *) info->private_data;
2613
2614 /* No instruction will be disassembled as longer than this number of
2615 bytes; stacked prefixes will not be expanded. */
2616 unsigned char buffer[MAX_BYTES_PER_CRIS_INSN];
2617 unsigned char *bufp;
2618 int status = 0;
2619 bfd_vma addr;
2620
2621 /* There will be an "out of range" error after the last instruction.
2622 Reading pairs of bytes in decreasing number, we hope that we will get
2623 at least the amount that we will consume.
2624
2625 If we can't get any data, or we do not get enough data, we print
2626 the error message. */
2627
2628 for (nbytes = MAX_BYTES_PER_CRIS_INSN; nbytes > 0; nbytes -= 2)
2629 {
2630 status = (*info->read_memory_func) (memaddr, buffer, nbytes, info);
2631 if (status == 0)
2632 break;
2633 }
2634
2635 /* If we did not get all we asked for, then clear the rest.
2636 Hopefully this makes a reproducible result in case of errors. */
2637 if (nbytes != MAX_BYTES_PER_CRIS_INSN)
2638 memset (buffer + nbytes, 0, MAX_BYTES_PER_CRIS_INSN - nbytes);
2639
2640 addr = memaddr;
2641 bufp = buffer;
2642
2643 /* Set some defaults for the insn info. */
2644 info->insn_info_valid = 1;
2645 info->branch_delay_insns = 0;
2646 info->data_size = 0;
2647 info->insn_type = dis_nonbranch;
2648 info->flags = 0;
2649 info->target = 0;
2650 info->target2 = 0;
2651
2652 /* If we got any data, disassemble it. */
2653 if (nbytes != 0)
2654 {
2655 matchedp = NULL;
2656
2657 insn = bufp[0] + bufp[1] * 256;
2658
2659 /* If we're in a case-table, don't disassemble the offsets. */
2660 if (TRACE_CASE && case_offset_counter != 0)
2661 {
2662 info->insn_type = dis_noninsn;
2663 advance += 2;
2664
2665 /* If to print data as offsets, then shortcut here. */
2666 (*info->fprintf_func) (info->stream, "case %ld%s: -> ",
2667 case_offset + no_of_case_offsets
2668 - case_offset_counter,
2669 case_offset_counter == 1 ? "/default" :
2670 "");
2671
2672 (*info->print_address_func) ((bfd_vma)
2673 ((short) (insn)
2674 + (long) (addr
2675 - (no_of_case_offsets
2676 - case_offset_counter)
2677 * 2)), info);
2678 case_offset_counter--;
2679
2680 /* The default case start (without a "sub" or "add") must be
2681 zero. */
2682 if (case_offset_counter == 0)
2683 case_offset = 0;
2684 }
2685 else if (insn == 0)
2686 {
2687 /* We're often called to disassemble zeroes. While this is a
2688 valid "bcc .+2" insn, it is also useless enough and enough
2689 of a nuiscance that we will just output "bcc .+2" for it
2690 and signal it as a noninsn. */
2691 (*info->fprintf_func) (info->stream,
2692 disdata->distype == cris_dis_v32
2693 ? "bcc ." : "bcc .+2");
2694 info->insn_type = dis_noninsn;
2695 advance += 2;
2696 }
2697 else
2698 {
2699 const struct cris_opcode *prefix_opcodep = NULL;
2700 unsigned char *prefix_buffer = bufp;
2701 unsigned int prefix_insn = insn;
2702 int prefix_size = 0;
2703
2704 matchedp = get_opcode_entry (insn, NO_CRIS_PREFIX, disdata);
2705
2706 /* Check if we're supposed to write out prefixes as address
2707 modes and if this was a prefix. */
2708 if (matchedp != NULL && PARSE_PREFIX && matchedp->args[0] == 'p')
2709 {
2710 /* If it's a prefix, put it into the prefix vars and get the
2711 main insn. */
2712 prefix_size = bytes_to_skip (prefix_insn, matchedp,
2713 disdata->distype, NULL);
2714 prefix_opcodep = matchedp;
2715
2716 insn = bufp[prefix_size] + bufp[prefix_size + 1] * 256;
2717 matchedp = get_opcode_entry (insn, prefix_insn, disdata);
2718
2719 if (matchedp != NULL)
2720 {
2721 addr += prefix_size;
2722 bufp += prefix_size;
2723 advance += prefix_size;
2724 }
2725 else
2726 {
2727 /* The "main" insn wasn't valid, at least not when
2728 prefixed. Put back things enough to output the
2729 prefix insn only, as a normal insn. */
2730 matchedp = prefix_opcodep;
2731 insn = prefix_insn;
2732 prefix_opcodep = NULL;
2733 }
2734 }
2735
2736 if (matchedp == NULL)
2737 {
2738 (*info->fprintf_func) (info->stream, "??0x%x", insn);
2739 advance += 2;
2740
2741 info->insn_type = dis_noninsn;
2742 }
2743 else
2744 {
2745 advance
2746 += bytes_to_skip (insn, matchedp, disdata->distype,
2747 prefix_opcodep);
2748
2749 /* The info_type and assorted fields will be set according
2750 to the operands. */
2751 print_with_operands (matchedp, insn, bufp, addr, info,
2752 prefix_opcodep, prefix_insn,
2753 prefix_buffer, with_reg_prefix);
2754 }
2755 }
2756 }
2757 else
2758 info->insn_type = dis_noninsn;
2759
2760 /* If we read less than MAX_BYTES_PER_CRIS_INSN, i.e. we got an error
2761 status when reading that much, and the insn decoding indicated a
2762 length exceeding what we read, there is an error. */
2763 if (status != 0 && (nbytes == 0 || advance > nbytes))
2764 {
2765 (*info->memory_error_func) (status, memaddr, info);
2766 return -1;
2767 }
2768
2769 /* Max supported insn size with one folded prefix insn. */
2770 info->bytes_per_line = MAX_BYTES_PER_CRIS_INSN;
2771
2772 /* I would like to set this to a fixed value larger than the actual
2773 number of bytes to print in order to avoid spaces between bytes,
2774 but objdump.c (2.9.1) does not like that, so we print 16-bit
2775 chunks, which is the next choice. */
2776 info->bytes_per_chunk = 2;
2777
2778 /* Printing bytes in order of increasing addresses makes sense,
2779 especially on a little-endian target.
2780 This is completely the opposite of what you think; setting this to
2781 BFD_ENDIAN_LITTLE will print bytes in order N..0 rather than the 0..N
2782 we want. */
2783 info->display_endian = BFD_ENDIAN_BIG;
2784
2785 return advance;
2786 }
2787
2788 /* Disassemble, prefixing register names with `$'. CRIS v0..v10. */
2789 #if 0
2790 static int
2791 print_insn_cris_with_register_prefix (bfd_vma vma,
2792 disassemble_info *info)
2793 {
2794 if (info->private_data == NULL
2795 && !cris_parse_disassembler_options (info, cris_dis_v0_v10))
2796 return -1;
2797 return print_insn_cris_generic (vma, info, TRUE);
2798 }
2799 #endif
2800 /* Disassemble, prefixing register names with `$'. CRIS v32. */
2801
2802 static int
2803 print_insn_crisv32_with_register_prefix (bfd_vma vma,
2804 disassemble_info *info)
2805 {
2806 if (info->private_data == NULL
2807 && !cris_parse_disassembler_options (info, cris_dis_v32))
2808 return -1;
2809 return print_insn_cris_generic (vma, info, TRUE);
2810 }
2811
2812 #if 0
2813 /* Disassemble, prefixing register names with `$'.
2814 Common v10 and v32 subset. */
2815
2816 static int
2817 print_insn_crisv10_v32_with_register_prefix (bfd_vma vma,
2818 disassemble_info *info)
2819 {
2820 if (info->private_data == NULL
2821 && !cris_parse_disassembler_options (info, cris_dis_common_v10_v32))
2822 return -1;
2823 return print_insn_cris_generic (vma, info, TRUE);
2824 }
2825
2826 /* Disassemble, no prefixes on register names. CRIS v0..v10. */
2827
2828 static int
2829 print_insn_cris_without_register_prefix (bfd_vma vma,
2830 disassemble_info *info)
2831 {
2832 if (info->private_data == NULL
2833 && !cris_parse_disassembler_options (info, cris_dis_v0_v10))
2834 return -1;
2835 return print_insn_cris_generic (vma, info, FALSE);
2836 }
2837
2838 /* Disassemble, no prefixes on register names. CRIS v32. */
2839
2840 static int
2841 print_insn_crisv32_without_register_prefix (bfd_vma vma,
2842 disassemble_info *info)
2843 {
2844 if (info->private_data == NULL
2845 && !cris_parse_disassembler_options (info, cris_dis_v32))
2846 return -1;
2847 return print_insn_cris_generic (vma, info, FALSE);
2848 }
2849
2850 /* Disassemble, no prefixes on register names.
2851 Common v10 and v32 subset. */
2852
2853 static int
2854 print_insn_crisv10_v32_without_register_prefix (bfd_vma vma,
2855 disassemble_info *info)
2856 {
2857 if (info->private_data == NULL
2858 && !cris_parse_disassembler_options (info, cris_dis_common_v10_v32))
2859 return -1;
2860 return print_insn_cris_generic (vma, info, FALSE);
2861 }
2862 #endif
2863
2864 int
2865 print_insn_crisv32 (bfd_vma vma,
2866 disassemble_info *info)
2867 {
2868 return print_insn_crisv32_with_register_prefix(vma, info);
2869 }
2870
2871 /* Return a disassembler-function that prints registers with a `$' prefix,
2872 or one that prints registers without a prefix.
2873 FIXME: We should improve the solution to avoid the multitude of
2874 functions seen above. */
2875 #if 0
2876 disassembler_ftype
2877 cris_get_disassembler (bfd *abfd)
2878 {
2879 /* If there's no bfd in sight, we return what is valid as input in all
2880 contexts if fed back to the assembler: disassembly *with* register
2881 prefix. Unfortunately this will be totally wrong for v32. */
2882 if (abfd == NULL)
2883 return print_insn_cris_with_register_prefix;
2884
2885 if (bfd_get_symbol_leading_char (abfd) == 0)
2886 {
2887 if (bfd_get_mach (abfd) == bfd_mach_cris_v32)
2888 return print_insn_crisv32_with_register_prefix;
2889 if (bfd_get_mach (abfd) == bfd_mach_cris_v10_v32)
2890 return print_insn_crisv10_v32_with_register_prefix;
2891
2892 /* We default to v10. This may be specifically specified in the
2893 bfd mach, but is also the default setting. */
2894 return print_insn_cris_with_register_prefix;
2895 }
2896
2897 if (bfd_get_mach (abfd) == bfd_mach_cris_v32)
2898 return print_insn_crisv32_without_register_prefix;
2899 if (bfd_get_mach (abfd) == bfd_mach_cris_v10_v32)
2900 return print_insn_crisv10_v32_without_register_prefix;
2901 return print_insn_cris_without_register_prefix;
2902 }
2903 #endif
2904 /* Local variables:
2905 eval: (c-set-style "gnu")
2906 indent-tabs-mode: t
2907 End: */
Patches shipped by Fedora