hw/serial.c

   1 /*
   2  * QEMU 16450 UART emulation
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "qemu-char.h"
  26 #include "isa.h"
  27 #include "pc.h"
  28
  29 //#define DEBUG_SERIAL
  30
  31 #define UART_LCR_DLAB   0x80    /* Divisor latch access bit */
  32
  33 #define UART_IER_MSI    0x08    /* Enable Modem status interrupt */
  34 #define UART_IER_RLSI   0x04    /* Enable receiver line status interrupt */
  35 #define UART_IER_THRI   0x02    /* Enable Transmitter holding register int. */
  36 #define UART_IER_RDI    0x01    /* Enable receiver data interrupt */
  37
  38 #define UART_IIR_NO_INT 0x01    /* No interrupts pending */
  39 #define UART_IIR_ID     0x06    /* Mask for the interrupt ID */
  40
  41 #define UART_IIR_MSI    0x00    /* Modem status interrupt */
  42 #define UART_IIR_THRI   0x02    /* Transmitter holding register empty */
  43 #define UART_IIR_RDI    0x04    /* Receiver data interrupt */
  44 #define UART_IIR_RLSI   0x06    /* Receiver line status interrupt */
  45
  46 /*
  47  * These are the definitions for the Modem Control Register
  48  */
  49 #define UART_MCR_LOOP   0x10    /* Enable loopback test mode */
  50 #define UART_MCR_OUT2   0x08    /* Out2 complement */
  51 #define UART_MCR_OUT1   0x04    /* Out1 complement */
  52 #define UART_MCR_RTS    0x02    /* RTS complement */
  53 #define UART_MCR_DTR    0x01    /* DTR complement */
  54
  55 /*
  56  * These are the definitions for the Modem Status Register
  57  */
  58 #define UART_MSR_DCD    0x80    /* Data Carrier Detect */
  59 #define UART_MSR_RI     0x40    /* Ring Indicator */
  60 #define UART_MSR_DSR    0x20    /* Data Set Ready */
  61 #define UART_MSR_CTS    0x10    /* Clear to Send */
  62 #define UART_MSR_DDCD   0x08    /* Delta DCD */
  63 #define UART_MSR_TERI   0x04    /* Trailing edge ring indicator */
  64 #define UART_MSR_DDSR   0x02    /* Delta DSR */
  65 #define UART_MSR_DCTS   0x01    /* Delta CTS */
  66 #define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */
  67
  68 #define UART_LSR_TEMT   0x40    /* Transmitter empty */
  69 #define UART_LSR_THRE   0x20    /* Transmit-hold-register empty */
  70 #define UART_LSR_BI     0x10    /* Break interrupt indicator */
  71 #define UART_LSR_FE     0x08    /* Frame error indicator */
  72 #define UART_LSR_PE     0x04    /* Parity error indicator */
  73 #define UART_LSR_OE     0x02    /* Overrun error indicator */
  74 #define UART_LSR_DR     0x01    /* Receiver data ready */
  75
  76 struct SerialState {
  77     uint16_t divider;
  78     uint8_t rbr; /* receive register */
  79     uint8_t ier;
  80     uint8_t iir; /* read only */
  81     uint8_t lcr;
  82     uint8_t mcr;
  83     uint8_t lsr; /* read only */
  84     uint8_t msr; /* read only */
  85     uint8_t scr;
  86     /* NOTE: this hidden state is necessary for tx irq generation as
  87        it can be reset while reading iir */
  88     int thr_ipending;
  89     qemu_irq irq;
  90     CharDriverState *chr;
  91     int last_break_enable;
  92     target_phys_addr_t base;
  93     int it_shift;
  94 };
  95
  96 static void serial_update_irq(SerialState *s)
  97 {
  98     if ((s->lsr & UART_LSR_DR) && (s->ier & UART_IER_RDI)) {
  99         s->iir = UART_IIR_RDI;
 100     } else if (s->thr_ipending && (s->ier & UART_IER_THRI)) {
 101         s->iir = UART_IIR_THRI;
 102     } else {
 103         s->iir = UART_IIR_NO_INT;
 104     }
 105     if (s->iir != UART_IIR_NO_INT) {
 106         qemu_irq_raise(s->irq);
 107     } else {
 108         qemu_irq_lower(s->irq);
 109     }
 110 }
 111
 112 static void serial_update_parameters(SerialState *s)
 113 {
 114     int speed, parity, data_bits, stop_bits;
 115     QEMUSerialSetParams ssp;
 116
 117     if (s->lcr & 0x08) {
 118         if (s->lcr & 0x10)
 119             parity = 'E';
 120         else
 121             parity = 'O';
 122     } else {
 123             parity = 'N';
 124     }
 125     if (s->lcr & 0x04)
 126         stop_bits = 2;
 127     else
 128         stop_bits = 1;
 129     data_bits = (s->lcr & 0x03) + 5;
 130     if (s->divider == 0)
 131         return;
 132     speed = 115200 / s->divider;
 133     ssp.speed = speed;
 134     ssp.parity = parity;
 135     ssp.data_bits = data_bits;
 136     ssp.stop_bits = stop_bits;
 137     qemu_chr_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
 138 #if 0
 139     printf("speed=%d parity=%c data=%d stop=%d\n",
 140            speed, parity, data_bits, stop_bits);
 141 #endif
 142 }
 143
 144 static void serial_ioport_write(void *opaque, uint32_t addr, uint32_t val)
 145 {
 146     SerialState *s = opaque;
 147     unsigned char ch;
 148
 149     addr &= 7;
 150 #ifdef DEBUG_SERIAL
 151     printf("serial: write addr=0x%02x val=0x%02x\n", addr, val);
 152 #endif
 153     switch(addr) {
 154     default:
 155     case 0:
 156         if (s->lcr & UART_LCR_DLAB) {
 157             s->divider = (s->divider & 0xff00) | val;
 158             serial_update_parameters(s);
 159         } else {
 160             s->thr_ipending = 0;
 161             s->lsr &= ~UART_LSR_THRE;
 162             serial_update_irq(s);
 163             ch = val;
 164             qemu_chr_write(s->chr, &ch, 1);
 165             s->thr_ipending = 1;
 166             s->lsr |= UART_LSR_THRE;
 167             s->lsr |= UART_LSR_TEMT;
 168             serial_update_irq(s);
 169         }
 170         break;
 171     case 1:
 172         if (s->lcr & UART_LCR_DLAB) {
 173             s->divider = (s->divider & 0x00ff) | (val << 8);
 174             serial_update_parameters(s);
 175         } else {
 176             s->ier = val & 0x0f;
 177             if (s->lsr & UART_LSR_THRE) {
 178                 s->thr_ipending = 1;
 179             }
 180             serial_update_irq(s);
 181         }
 182         break;
 183     case 2:
 184         break;
 185     case 3:
 186         {
 187             int break_enable;
 188             s->lcr = val;
 189             serial_update_parameters(s);
 190             break_enable = (val >> 6) & 1;
 191             if (break_enable != s->last_break_enable) {
 192                 s->last_break_enable = break_enable;
 193                 qemu_chr_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_BREAK,
 194                                &break_enable);
 195             }
 196         }
 197         break;
 198     case 4:
 199         s->mcr = val & 0x1f;
 200         break;
 201     case 5:
 202         break;
 203     case 6:
 204         break;
 205     case 7:
 206         s->scr = val;
 207         break;
 208     }
 209 }
 210
 211 static uint32_t serial_ioport_read(void *opaque, uint32_t addr)
 212 {
 213     SerialState *s = opaque;
 214     uint32_t ret;
 215
 216     addr &= 7;
 217     switch(addr) {
 218     default:
 219     case 0:
 220         if (s->lcr & UART_LCR_DLAB) {
 221             ret = s->divider & 0xff;
 222         } else {
 223             ret = s->rbr;
 224             s->lsr &= ~(UART_LSR_DR | UART_LSR_BI);
 225             serial_update_irq(s);
 226             qemu_chr_accept_input(s->chr);
 227         }
 228         break;
 229     case 1:
 230         if (s->lcr & UART_LCR_DLAB) {
 231             ret = (s->divider >> 8) & 0xff;
 232         } else {
 233             ret = s->ier;
 234         }
 235         break;
 236     case 2:
 237         ret = s->iir;
 238         /* reset THR pending bit */
 239         if ((ret & 0x7) == UART_IIR_THRI)
 240             s->thr_ipending = 0;
 241         serial_update_irq(s);
 242         break;
 243     case 3:
 244         ret = s->lcr;
 245         break;
 246     case 4:
 247         ret = s->mcr;
 248         break;
 249     case 5:
 250         ret = s->lsr;
 251         break;
 252     case 6:
 253         if (s->mcr & UART_MCR_LOOP) {
 254             /* in loopback, the modem output pins are connected to the
 255                inputs */
 256             ret = (s->mcr & 0x0c) << 4;
 257             ret |= (s->mcr & 0x02) << 3;
 258             ret |= (s->mcr & 0x01) << 5;
 259         } else {
 260             ret = s->msr;
 261         }
 262         break;
 263     case 7:
 264         ret = s->scr;
 265         break;
 266     }
 267 #ifdef DEBUG_SERIAL
 268     printf("serial: read addr=0x%02x val=0x%02x\n", addr, ret);
 269 #endif
 270     return ret;
 271 }
 272
 273 static int serial_can_receive(SerialState *s)
 274 {
 275     return !(s->lsr & UART_LSR_DR);
 276 }
 277
 278 static void serial_receive_byte(SerialState *s, int ch)
 279 {
 280     s->rbr = ch;
 281     s->lsr |= UART_LSR_DR;
 282     serial_update_irq(s);
 283 }
 284
 285 static void serial_receive_break(SerialState *s)
 286 {
 287     s->rbr = 0;
 288     s->lsr |= UART_LSR_BI | UART_LSR_DR;
 289     serial_update_irq(s);
 290 }
 291
 292 static int serial_can_receive1(void *opaque)
 293 {
 294     SerialState *s = opaque;
 295     return serial_can_receive(s);
 296 }
 297
 298 static void serial_receive1(void *opaque, const uint8_t *buf, int size)
 299 {
 300     SerialState *s = opaque;
 301     serial_receive_byte(s, buf[0]);
 302 }
 303
 304 static void serial_event(void *opaque, int event)
 305 {
 306     SerialState *s = opaque;
 307     if (event == CHR_EVENT_BREAK)
 308         serial_receive_break(s);
 309 }
 310
 311 static void serial_save(QEMUFile *f, void *opaque)
 312 {
 313     SerialState *s = opaque;
 314
 315     qemu_put_be16s(f,&s->divider);
 316     qemu_put_8s(f,&s->rbr);
 317     qemu_put_8s(f,&s->ier);
 318     qemu_put_8s(f,&s->iir);
 319     qemu_put_8s(f,&s->lcr);
 320     qemu_put_8s(f,&s->mcr);
 321     qemu_put_8s(f,&s->lsr);
 322     qemu_put_8s(f,&s->msr);
 323     qemu_put_8s(f,&s->scr);
 324 }
 325
 326 static int serial_load(QEMUFile *f, void *opaque, int version_id)
 327 {
 328     SerialState *s = opaque;
 329
 330     if(version_id > 2)
 331         return -EINVAL;
 332
 333     if (version_id >= 2)
 334         qemu_get_be16s(f, &s->divider);
 335     else
 336         s->divider = qemu_get_byte(f);
 337     qemu_get_8s(f,&s->rbr);
 338     qemu_get_8s(f,&s->ier);
 339     qemu_get_8s(f,&s->iir);
 340     qemu_get_8s(f,&s->lcr);
 341     qemu_get_8s(f,&s->mcr);
 342     qemu_get_8s(f,&s->lsr);
 343     qemu_get_8s(f,&s->msr);
 344     qemu_get_8s(f,&s->scr);
 345
 346     return 0;
 347 }
 348
 349 /* If fd is zero, it means that the serial device uses the console */
 350 SerialState *serial_init(int base, qemu_irq irq, CharDriverState *chr)
 351 {
 352     SerialState *s;
 353
 354     s = qemu_mallocz(sizeof(SerialState));
 355     if (!s)
 356         return NULL;
 357     s->irq = irq;
 358     s->lsr = UART_LSR_TEMT | UART_LSR_THRE;
 359     s->iir = UART_IIR_NO_INT;
 360     s->msr = UART_MSR_DCD | UART_MSR_DSR | UART_MSR_CTS;
 361
 362     register_savevm("serial", base, 2, serial_save, serial_load, s);
 363
 364     register_ioport_write(base, 8, 1, serial_ioport_write, s);
 365     register_ioport_read(base, 8, 1, serial_ioport_read, s);
 366     s->chr = chr;
 367     qemu_chr_add_handlers(chr, serial_can_receive1, serial_receive1,
 368                           serial_event, s);
 369     return s;
 370 }
 371
 372 /* Memory mapped interface */
 373 uint32_t serial_mm_readb (void *opaque, target_phys_addr_t addr)
 374 {
 375     SerialState *s = opaque;
 376
 377     return serial_ioport_read(s, (addr - s->base) >> s->it_shift) & 0xFF;
 378 }
 379
 380 void serial_mm_writeb (void *opaque,
 381                        target_phys_addr_t addr, uint32_t value)
 382 {
 383     SerialState *s = opaque;
 384
 385     serial_ioport_write(s, (addr - s->base) >> s->it_shift, value & 0xFF);
 386 }
 387
 388 uint32_t serial_mm_readw (void *opaque, target_phys_addr_t addr)
 389 {
 390     SerialState *s = opaque;
 391     uint32_t val;
 392
 393     val = serial_ioport_read(s, (addr - s->base) >> s->it_shift) & 0xFFFF;
 394 #ifdef TARGET_WORDS_BIGENDIAN
 395     val = bswap16(val);
 396 #endif
 397     return val;
 398 }
 399
 400 void serial_mm_writew (void *opaque,
 401                        target_phys_addr_t addr, uint32_t value)
 402 {
 403     SerialState *s = opaque;
 404 #ifdef TARGET_WORDS_BIGENDIAN
 405     value = bswap16(value);
 406 #endif
 407     serial_ioport_write(s, (addr - s->base) >> s->it_shift, value & 0xFFFF);
 408 }
 409
 410 uint32_t serial_mm_readl (void *opaque, target_phys_addr_t addr)
 411 {
 412     SerialState *s = opaque;
 413     uint32_t val;
 414
 415     val = serial_ioport_read(s, (addr - s->base) >> s->it_shift);
 416 #ifdef TARGET_WORDS_BIGENDIAN
 417     val = bswap32(val);
 418 #endif
 419     return val;
 420 }
 421
 422 void serial_mm_writel (void *opaque,
 423                        target_phys_addr_t addr, uint32_t value)
 424 {
 425     SerialState *s = opaque;
 426 #ifdef TARGET_WORDS_BIGENDIAN
 427     value = bswap32(value);
 428 #endif
 429     serial_ioport_write(s, (addr - s->base) >> s->it_shift, value);
 430 }
 431
 432 static CPUReadMemoryFunc *serial_mm_read[] = {
 433     &serial_mm_readb,
 434     &serial_mm_readw,
 435     &serial_mm_readl,
 436 };
 437
 438 static CPUWriteMemoryFunc *serial_mm_write[] = {
 439     &serial_mm_writeb,
 440     &serial_mm_writew,
 441     &serial_mm_writel,
 442 };
 443
 444 SerialState *serial_mm_init (target_phys_addr_t base, int it_shift,
 445                              qemu_irq irq, CharDriverState *chr,
 446                              int ioregister)
 447 {
 448     SerialState *s;
 449     int s_io_memory;
 450
 451     s = qemu_mallocz(sizeof(SerialState));
 452     if (!s)
 453         return NULL;
 454     s->irq = irq;
 455     s->lsr = UART_LSR_TEMT | UART_LSR_THRE;
 456     s->iir = UART_IIR_NO_INT;
 457     s->msr = UART_MSR_DCD | UART_MSR_DSR | UART_MSR_CTS;
 458     s->base = base;
 459     s->it_shift = it_shift;
 460
 461     register_savevm("serial", base, 2, serial_save, serial_load, s);
 462
 463     if (ioregister) {
 464         s_io_memory = cpu_register_io_memory(0, serial_mm_read,
 465                                              serial_mm_write, s);
 466         cpu_register_physical_memory(base, 8 << it_shift, s_io_memory);
 467     }
 468     s->chr = chr;
 469     qemu_chr_add_handlers(chr, serial_can_receive1, serial_receive1,
 470                           serial_event, s);
 471     return s;
 472 }