exec-all.h

   1 /*
   2  * internal execution defines for qemu
   3  *
   4  *  Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  19  */
  20
  21 /* allow to see translation results - the slowdown should be negligible, so we leave it */
  22 #define DEBUG_DISAS
  23
  24 /* is_jmp field values */
  25 #define DISAS_NEXT    0 /* next instruction can be analyzed */
  26 #define DISAS_JUMP    1 /* only pc was modified dynamically */
  27 #define DISAS_UPDATE  2 /* cpu state was modified dynamically */
  28 #define DISAS_TB_JUMP 3 /* only pc was modified statically */
  29
  30 struct TranslationBlock;
  31
  32 /* XXX: make safe guess about sizes */
  33 #define MAX_OP_PER_INSTR 64
  34 /* A Call op needs up to 6 + 2N parameters (N = number of arguments).  */
  35 #define MAX_OPC_PARAM 10
  36 #define OPC_BUF_SIZE 512
  37 #define OPC_MAX_SIZE (OPC_BUF_SIZE - MAX_OP_PER_INSTR)
  38
  39 /* Maximum size a TCG op can expand to.  This is complicated because a
  40    single op may require several host instructions and regirster reloads.
  41    For now take a wild guess at 128 bytes, which should allow at least
  42    a couple of fixup instructions per argument.  */
  43 #define TCG_MAX_OP_SIZE 128
  44
  45 #define OPPARAM_BUF_SIZE (OPC_BUF_SIZE * MAX_OPC_PARAM)
  46
  47 extern target_ulong gen_opc_pc[OPC_BUF_SIZE];
  48 extern target_ulong gen_opc_npc[OPC_BUF_SIZE];
  49 extern uint8_t gen_opc_cc_op[OPC_BUF_SIZE];
  50 extern uint8_t gen_opc_instr_start[OPC_BUF_SIZE];
  51 extern target_ulong gen_opc_jump_pc[2];
  52 extern uint32_t gen_opc_hflags[OPC_BUF_SIZE];
  53
  54 typedef void (GenOpFunc)(void);
  55 typedef void (GenOpFunc1)(long);
  56 typedef void (GenOpFunc2)(long, long);
  57 typedef void (GenOpFunc3)(long, long, long);
  58
  59 #if defined(TARGET_I386)
  60
  61 void optimize_flags_init(void);
  62
  63 #endif
  64
  65 extern FILE *logfile;
  66 extern int loglevel;
  67
  68 int gen_intermediate_code(CPUState *env, struct TranslationBlock *tb);
  69 int gen_intermediate_code_pc(CPUState *env, struct TranslationBlock *tb);
  70 void gen_pc_load(CPUState *env, struct TranslationBlock *tb,
  71                  unsigned long searched_pc, int pc_pos, void *puc);
  72
  73 unsigned long code_gen_max_block_size(void);
  74 void cpu_gen_init(void);
  75 int cpu_gen_code(CPUState *env, struct TranslationBlock *tb,
  76                  int *gen_code_size_ptr);
  77 int cpu_restore_state(struct TranslationBlock *tb,
  78                       CPUState *env, unsigned long searched_pc,
  79                       void *puc);
  80 int cpu_restore_state_copy(struct TranslationBlock *tb,
  81                            CPUState *env, unsigned long searched_pc,
  82                            void *puc);
  83 void cpu_resume_from_signal(CPUState *env1, void *puc);
  84 void cpu_exec_init(CPUState *env);
  85 int page_unprotect(target_ulong address, unsigned long pc, void *puc);
  86 void tb_invalidate_phys_page_range(target_phys_addr_t start, target_phys_addr_t end,
  87                                    int is_cpu_write_access);
  88 void tb_invalidate_page_range(target_ulong start, target_ulong end);
  89 void tlb_flush_page(CPUState *env, target_ulong addr);
  90 void tlb_flush(CPUState *env, int flush_global);
  91 int tlb_set_page_exec(CPUState *env, target_ulong vaddr,
  92                       target_phys_addr_t paddr, int prot,
  93                       int mmu_idx, int is_softmmu);
  94 static inline int tlb_set_page(CPUState *env1, target_ulong vaddr,
  95                                target_phys_addr_t paddr, int prot,
  96                                int mmu_idx, int is_softmmu)
  97 {
  98     if (prot & PAGE_READ)
  99         prot |= PAGE_EXEC;
 100     return tlb_set_page_exec(env1, vaddr, paddr, prot, mmu_idx, is_softmmu);
 101 }
 102
 103 #define CODE_GEN_ALIGN           16 /* must be >= of the size of a icache line */
 104
 105 #define CODE_GEN_PHYS_HASH_BITS     15
 106 #define CODE_GEN_PHYS_HASH_SIZE     (1 << CODE_GEN_PHYS_HASH_BITS)
 107
 108 /* maximum total translate dcode allocated */
 109
 110 /* NOTE: the translated code area cannot be too big because on some
 111    archs the range of "fast" function calls is limited. Here is a
 112    summary of the ranges:
 113
 114    i386  : signed 32 bits
 115    arm   : signed 26 bits
 116    ppc   : signed 24 bits
 117    sparc : signed 32 bits
 118    alpha : signed 23 bits
 119 */
 120
 121 #if defined(__alpha__)
 122 #define CODE_GEN_BUFFER_SIZE     (2 * 1024 * 1024)
 123 #elif defined(__ia64)
 124 #define CODE_GEN_BUFFER_SIZE     (4 * 1024 * 1024)      /* range of addl */
 125 #elif defined(__powerpc__)
 126 #define CODE_GEN_BUFFER_SIZE     (6 * 1024 * 1024)
 127 #else
 128 /* XXX: make it dynamic on x86 */
 129 #define CODE_GEN_BUFFER_SIZE     (16 * 1024 * 1024)
 130 #endif
 131
 132 //#define CODE_GEN_BUFFER_SIZE     (128 * 1024)
 133
 134 /* estimated block size for TB allocation */
 135 /* XXX: use a per code average code fragment size and modulate it
 136    according to the host CPU */
 137 #if defined(CONFIG_SOFTMMU)
 138 #define CODE_GEN_AVG_BLOCK_SIZE 128
 139 #else
 140 #define CODE_GEN_AVG_BLOCK_SIZE 64
 141 #endif
 142
 143 #define CODE_GEN_MAX_BLOCKS    (CODE_GEN_BUFFER_SIZE / CODE_GEN_AVG_BLOCK_SIZE)
 144
 145 #if defined(__powerpc__) || defined(__x86_64__) || defined(__arm__)
 146 #define USE_DIRECT_JUMP
 147 #endif
 148 #if defined(__i386__) && !defined(_WIN32)
 149 #define USE_DIRECT_JUMP
 150 #endif
 151
 152 typedef struct TranslationBlock {
 153     target_ulong pc;   /* simulated PC corresponding to this block (EIP + CS base) */
 154     target_ulong cs_base; /* CS base for this block */
 155     uint64_t flags; /* flags defining in which context the code was generated */
 156     uint16_t size;      /* size of target code for this block (1 <=
 157                            size <= TARGET_PAGE_SIZE) */
 158     uint16_t cflags;    /* compile flags */
 159 #define CF_TB_FP_USED  0x0002 /* fp ops are used in the TB */
 160 #define CF_FP_USED     0x0004 /* fp ops are used in the TB or in a chained TB */
 161 #define CF_SINGLE_INSN 0x0008 /* compile only a single instruction */
 162
 163     uint8_t *tc_ptr;    /* pointer to the translated code */
 164     /* next matching tb for physical address. */
 165     struct TranslationBlock *phys_hash_next;
 166     /* first and second physical page containing code. The lower bit
 167        of the pointer tells the index in page_next[] */
 168     struct TranslationBlock *page_next[2];
 169     target_ulong page_addr[2];
 170
 171     /* the following data are used to directly call another TB from
 172        the code of this one. */
 173     uint16_t tb_next_offset[2]; /* offset of original jump target */
 174 #ifdef USE_DIRECT_JUMP
 175     uint16_t tb_jmp_offset[4]; /* offset of jump instruction */
 176 #else
 177     unsigned long tb_next[2]; /* address of jump generated code */
 178 #endif
 179     /* list of TBs jumping to this one. This is a circular list using
 180        the two least significant bits of the pointers to tell what is
 181        the next pointer: 0 = jmp_next[0], 1 = jmp_next[1], 2 =
 182        jmp_first */
 183     struct TranslationBlock *jmp_next[2];
 184     struct TranslationBlock *jmp_first;
 185 } TranslationBlock;
 186
 187 static inline unsigned int tb_jmp_cache_hash_page(target_ulong pc)
 188 {
 189     target_ulong tmp;
 190     tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS));
 191     return (tmp >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)) & TB_JMP_PAGE_MASK;
 192 }
 193
 194 static inline unsigned int tb_jmp_cache_hash_func(target_ulong pc)
 195 {
 196     target_ulong tmp;
 197     tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS));
 198     return (((tmp >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)) & TB_JMP_PAGE_MASK)
 199             | (tmp & TB_JMP_ADDR_MASK));
 200 }
 201
 202 static inline unsigned int tb_phys_hash_func(unsigned long pc)
 203 {
 204     return pc & (CODE_GEN_PHYS_HASH_SIZE - 1);
 205 }
 206
 207 TranslationBlock *tb_alloc(target_ulong pc);
 208 void tb_flush(CPUState *env);
 209 void tb_link_phys(TranslationBlock *tb,
 210                   target_ulong phys_pc, target_ulong phys_page2);
 211
 212 extern TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE];
 213
 214 extern uint8_t code_gen_buffer[CODE_GEN_BUFFER_SIZE];
 215 extern uint8_t *code_gen_ptr;
 216
 217 #if defined(USE_DIRECT_JUMP)
 218
 219 #if defined(__powerpc__)
 220 static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr)
 221 {
 222     uint32_t val, *ptr;
 223
 224     /* patch the branch destination */
 225     ptr = (uint32_t *)jmp_addr;
 226     val = *ptr;
 227     val = (val & ~0x03fffffc) | ((addr - jmp_addr) & 0x03fffffc);
 228     *ptr = val;
 229     /* flush icache */
 230     asm volatile ("dcbst 0,%0" : : "r"(ptr) : "memory");
 231     asm volatile ("sync" : : : "memory");
 232     asm volatile ("icbi 0,%0" : : "r"(ptr) : "memory");
 233     asm volatile ("sync" : : : "memory");
 234     asm volatile ("isync" : : : "memory");
 235 }
 236 #elif defined(__i386__) || defined(__x86_64__)
 237 static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr)
 238 {
 239     /* patch the branch destination */
 240     *(uint32_t *)jmp_addr = addr - (jmp_addr + 4);
 241     /* no need to flush icache explicitely */
 242 }
 243 #elif defined(__arm__)
 244 static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr)
 245 {
 246     register unsigned long _beg __asm ("a1");
 247     register unsigned long _end __asm ("a2");
 248     register unsigned long _flg __asm ("a3");
 249
 250     /* we could use a ldr pc, [pc, #-4] kind of branch and avoid the flush */
 251     *(uint32_t *)jmp_addr |= ((addr - (jmp_addr + 8)) >> 2) & 0xffffff;
 252
 253     /* flush icache */
 254     _beg = jmp_addr;
 255     _end = jmp_addr + 4;
 256     _flg = 0;
 257     __asm __volatile__ ("swi 0x9f0002" : : "r" (_beg), "r" (_end), "r" (_flg));
 258 }
 259 #endif
 260
 261 static inline void tb_set_jmp_target(TranslationBlock *tb,
 262                                      int n, unsigned long addr)
 263 {
 264     unsigned long offset;
 265
 266     offset = tb->tb_jmp_offset[n];
 267     tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr);
 268     offset = tb->tb_jmp_offset[n + 2];
 269     if (offset != 0xffff)
 270         tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr);
 271 }
 272
 273 #else
 274
 275 /* set the jump target */
 276 static inline void tb_set_jmp_target(TranslationBlock *tb,
 277                                      int n, unsigned long addr)
 278 {
 279     tb->tb_next[n] = addr;
 280 }
 281
 282 #endif
 283
 284 static inline void tb_add_jump(TranslationBlock *tb, int n,
 285                                TranslationBlock *tb_next)
 286 {
 287     /* NOTE: this test is only needed for thread safety */
 288     if (!tb->jmp_next[n]) {
 289         /* patch the native jump address */
 290         tb_set_jmp_target(tb, n, (unsigned long)tb_next->tc_ptr);
 291
 292         /* add in TB jmp circular list */
 293         tb->jmp_next[n] = tb_next->jmp_first;
 294         tb_next->jmp_first = (TranslationBlock *)((long)(tb) | (n));
 295     }
 296 }
 297
 298 TranslationBlock *tb_find_pc(unsigned long pc_ptr);
 299
 300 #ifndef offsetof
 301 #define offsetof(type, field) ((size_t) &((type *)0)->field)
 302 #endif
 303
 304 #if defined(_WIN32)
 305 #define ASM_DATA_SECTION ".section \".data\"\n"
 306 #define ASM_PREVIOUS_SECTION ".section .text\n"
 307 #elif defined(__APPLE__)
 308 #define ASM_DATA_SECTION ".data\n"
 309 #define ASM_PREVIOUS_SECTION ".text\n"
 310 #else
 311 #define ASM_DATA_SECTION ".section \".data\"\n"
 312 #define ASM_PREVIOUS_SECTION ".previous\n"
 313 #endif
 314
 315 #define ASM_OP_LABEL_NAME(n, opname) \
 316     ASM_NAME(__op_label) #n "." ASM_NAME(opname)
 317
 318 extern CPUWriteMemoryFunc *io_mem_write[IO_MEM_NB_ENTRIES][4];
 319 extern CPUReadMemoryFunc *io_mem_read[IO_MEM_NB_ENTRIES][4];
 320 extern void *io_mem_opaque[IO_MEM_NB_ENTRIES];
 321
 322 #if defined(__hppa__)
 323
 324 typedef int spinlock_t[4];
 325
 326 #define SPIN_LOCK_UNLOCKED { 1, 1, 1, 1 }
 327
 328 static inline void resetlock (spinlock_t *p)
 329 {
 330     (*p)[0] = (*p)[1] = (*p)[2] = (*p)[3] = 1;
 331 }
 332
 333 #else
 334
 335 typedef int spinlock_t;
 336
 337 #define SPIN_LOCK_UNLOCKED 0
 338
 339 static inline void resetlock (spinlock_t *p)
 340 {
 341     *p = SPIN_LOCK_UNLOCKED;
 342 }
 343
 344 #endif
 345
 346 #if defined(__powerpc__)
 347 static inline int testandset (int *p)
 348 {
 349     int ret;
 350     __asm__ __volatile__ (
 351                           "0:    lwarx %0,0,%1\n"
 352                           "      xor. %0,%3,%0\n"
 353                           "      bne 1f\n"
 354                           "      stwcx. %2,0,%1\n"
 355                           "      bne- 0b\n"
 356                           "1:    "
 357                           : "=&r" (ret)
 358                           : "r" (p), "r" (1), "r" (0)
 359                           : "cr0", "memory");
 360     return ret;
 361 }
 362 #elif defined(__i386__)
 363 static inline int testandset (int *p)
 364 {
 365     long int readval = 0;
 366
 367     __asm__ __volatile__ ("lock; cmpxchgl %2, %0"
 368                           : "+m" (*p), "+a" (readval)
 369                           : "r" (1)
 370                           : "cc");
 371     return readval;
 372 }
 373 #elif defined(__x86_64__)
 374 static inline int testandset (int *p)
 375 {
 376     long int readval = 0;
 377
 378     __asm__ __volatile__ ("lock; cmpxchgl %2, %0"
 379                           : "+m" (*p), "+a" (readval)
 380                           : "r" (1)
 381                           : "cc");
 382     return readval;
 383 }
 384 #elif defined(__s390__)
 385 static inline int testandset (int *p)
 386 {
 387     int ret;
 388
 389     __asm__ __volatile__ ("0: cs    %0,%1,0(%2)\n"
 390                           "   jl    0b"
 391                           : "=&d" (ret)
 392                           : "r" (1), "a" (p), "0" (*p)
 393                           : "cc", "memory" );
 394     return ret;
 395 }
 396 #elif defined(__alpha__)
 397 static inline int testandset (int *p)
 398 {
 399     int ret;
 400     unsigned long one;
 401
 402     __asm__ __volatile__ ("0:   mov 1,%2\n"
 403                           "     ldl_l %0,%1\n"
 404                           "     stl_c %2,%1\n"
 405                           "     beq %2,1f\n"
 406                           ".subsection 2\n"
 407                           "1:   br 0b\n"
 408                           ".previous"
 409                           : "=r" (ret), "=m" (*p), "=r" (one)
 410                           : "m" (*p));
 411     return ret;
 412 }
 413 #elif defined(__sparc__)
 414 static inline int testandset (int *p)
 415 {
 416         int ret;
 417
 418         __asm__ __volatile__("ldstub    [%1], %0"
 419                              : "=r" (ret)
 420                              : "r" (p)
 421                              : "memory");
 422
 423         return (ret ? 1 : 0);
 424 }
 425 #elif defined(__arm__)
 426 static inline int testandset (int *spinlock)
 427 {
 428     register unsigned int ret;
 429     __asm__ __volatile__("swp %0, %1, [%2]"
 430                          : "=r"(ret)
 431                          : "0"(1), "r"(spinlock));
 432
 433     return ret;
 434 }
 435 #elif defined(__mc68000)
 436 static inline int testandset (int *p)
 437 {
 438     char ret;
 439     __asm__ __volatile__("tas %1; sne %0"
 440                          : "=r" (ret)
 441                          : "m" (p)
 442                          : "cc","memory");
 443     return ret;
 444 }
 445 #elif defined(__hppa__)
 446
 447 /* Because malloc only guarantees 8-byte alignment for malloc'd data,
 448    and GCC only guarantees 8-byte alignment for stack locals, we can't
 449    be assured of 16-byte alignment for atomic lock data even if we
 450    specify "__attribute ((aligned(16)))" in the type declaration.  So,
 451    we use a struct containing an array of four ints for the atomic lock
 452    type and dynamically select the 16-byte aligned int from the array
 453    for the semaphore.  */
 454 #define __PA_LDCW_ALIGNMENT 16
 455 static inline void *ldcw_align (void *p) {
 456     unsigned long a = (unsigned long)p;
 457     a = (a + __PA_LDCW_ALIGNMENT - 1) & ~(__PA_LDCW_ALIGNMENT - 1);
 458     return (void *)a;
 459 }
 460
 461 static inline int testandset (spinlock_t *p)
 462 {
 463     unsigned int ret;
 464     p = ldcw_align(p);
 465     __asm__ __volatile__("ldcw 0(%1),%0"
 466                          : "=r" (ret)
 467                          : "r" (p)
 468                          : "memory" );
 469     return !ret;
 470 }
 471
 472 #elif defined(__ia64)
 473
 474 #include <ia64intrin.h>
 475
 476 static inline int testandset (int *p)
 477 {
 478     return __sync_lock_test_and_set (p, 1);
 479 }
 480 #elif defined(__mips__)
 481 static inline int testandset (int *p)
 482 {
 483     int ret;
 484
 485     __asm__ __volatile__ (
 486         "       .set push               \n"
 487         "       .set noat               \n"
 488         "       .set mips2              \n"
 489         "1:     li      $1, 1           \n"
 490         "       ll      %0, %1          \n"
 491         "       sc      $1, %1          \n"
 492         "       beqz    $1, 1b          \n"
 493         "       .set pop                "
 494         : "=r" (ret), "+R" (*p)
 495         :
 496         : "memory");
 497
 498     return ret;
 499 }
 500 #else
 501 #error unimplemented CPU support
 502 #endif
 503
 504 #if defined(CONFIG_USER_ONLY)
 505 static inline void spin_lock(spinlock_t *lock)
 506 {
 507     while (testandset(lock));
 508 }
 509
 510 static inline void spin_unlock(spinlock_t *lock)
 511 {
 512     resetlock(lock);
 513 }
 514
 515 static inline int spin_trylock(spinlock_t *lock)
 516 {
 517     return !testandset(lock);
 518 }
 519 #else
 520 static inline void spin_lock(spinlock_t *lock)
 521 {
 522 }
 523
 524 static inline void spin_unlock(spinlock_t *lock)
 525 {
 526 }
 527
 528 static inline int spin_trylock(spinlock_t *lock)
 529 {
 530     return 1;
 531 }
 532 #endif
 533
 534 extern spinlock_t tb_lock;
 535
 536 extern int tb_invalidated_flag;
 537
 538 #if !defined(CONFIG_USER_ONLY)
 539
 540 void tlb_fill(target_ulong addr, int is_write, int mmu_idx,
 541               void *retaddr);
 542
 543 #define ACCESS_TYPE (NB_MMU_MODES + 1)
 544 #define MEMSUFFIX _code
 545 #define env cpu_single_env
 546
 547 #define DATA_SIZE 1
 548 #include "softmmu_header.h"
 549
 550 #define DATA_SIZE 2
 551 #include "softmmu_header.h"
 552
 553 #define DATA_SIZE 4
 554 #include "softmmu_header.h"
 555
 556 #define DATA_SIZE 8
 557 #include "softmmu_header.h"
 558
 559 #undef ACCESS_TYPE
 560 #undef MEMSUFFIX
 561 #undef env
 562
 563 #endif
 564
 565 #if defined(CONFIG_USER_ONLY)
 566 static inline target_ulong get_phys_addr_code(CPUState *env1, target_ulong addr)
 567 {
 568     return addr;
 569 }
 570 #else
 571 /* NOTE: this function can trigger an exception */
 572 /* NOTE2: the returned address is not exactly the physical address: it
 573    is the offset relative to phys_ram_base */
 574 static inline target_ulong get_phys_addr_code(CPUState *env1, target_ulong addr)
 575 {
 576     int mmu_idx, page_index, pd;
 577
 578     page_index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
 579     mmu_idx = cpu_mmu_index(env1);
 580     if (__builtin_expect(env1->tlb_table[mmu_idx][page_index].addr_code !=
 581                          (addr & TARGET_PAGE_MASK), 0)) {
 582         ldub_code(addr);
 583     }
 584     pd = env1->tlb_table[mmu_idx][page_index].addr_code & ~TARGET_PAGE_MASK;
 585     if (pd > IO_MEM_ROM && !(pd & IO_MEM_ROMD)) {
 586 #if defined(TARGET_SPARC) || defined(TARGET_MIPS)
 587         do_unassigned_access(addr, 0, 1, 0);
 588 #else
 589         cpu_abort(env1, "Trying to execute code outside RAM or ROM at 0x" TARGET_FMT_lx "\n", addr);
 590 #endif
 591     }
 592     return addr + env1->tlb_table[mmu_idx][page_index].addend - (unsigned long)phys_ram_base;
 593 }
 594 #endif
 595
 596 #ifdef USE_KQEMU
 597 #define KQEMU_MODIFY_PAGE_MASK (0xff & ~(VGA_DIRTY_FLAG | CODE_DIRTY_FLAG))
 598
 599 int kqemu_init(CPUState *env);
 600 int kqemu_cpu_exec(CPUState *env);
 601 void kqemu_flush_page(CPUState *env, target_ulong addr);
 602 void kqemu_flush(CPUState *env, int global);
 603 void kqemu_set_notdirty(CPUState *env, ram_addr_t ram_addr);
 604 void kqemu_modify_page(CPUState *env, ram_addr_t ram_addr);
 605 void kqemu_cpu_interrupt(CPUState *env);
 606 void kqemu_record_dump(void);
 607
 608 static inline int kqemu_is_ok(CPUState *env)
 609 {
 610     return(env->kqemu_enabled &&
 611            (env->cr[0] & CR0_PE_MASK) &&
 612            !(env->hflags & HF_INHIBIT_IRQ_MASK) &&
 613            (env->eflags & IF_MASK) &&
 614            !(env->eflags & VM_MASK) &&
 615            (env->kqemu_enabled == 2 ||
 616             ((env->hflags & HF_CPL_MASK) == 3 &&
 617              (env->eflags & IOPL_MASK) != IOPL_MASK)));
 618 }
 619
 620 #endif