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Fuse EQ and NE handling in tcg_out_brcond2
[qemu-kvm/fedora.git] / tcg / ppc / tcg-target.c
blob0dcf612258a843243fe2b3115526a7573b478f21
1 /*
2 * Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2008 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 static uint8_t *tb_ret_addr;
26
27 #define FAST_PATH
28 #if TARGET_PHYS_ADDR_BITS <= 32
29 #define ADDEND_OFFSET 0
30 #else
31 #define ADDEND_OFFSET 4
32 #endif
33
34 static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
35 "r0",
36 "r1",
37 "rp",
38 "r3",
39 "r4",
40 "r5",
41 "r6",
42 "r7",
43 "r8",
44 "r9",
45 "r10",
46 "r11",
47 "r12",
48 "r13",
49 "r14",
50 "r15",
51 "r16",
52 "r17",
53 "r18",
54 "r19",
55 "r20",
56 "r21",
57 "r22",
58 "r23",
59 "r24",
60 "r25",
61 "r26",
62 "r27",
63 "r28",
64 "r29",
65 "r30",
66 "r31"
67 };
68
69 static const int tcg_target_reg_alloc_order[] = {
70 TCG_REG_R14,
71 TCG_REG_R15,
72 TCG_REG_R16,
73 TCG_REG_R17,
74 TCG_REG_R18,
75 TCG_REG_R19,
76 TCG_REG_R20,
77 TCG_REG_R21,
78 TCG_REG_R22,
79 TCG_REG_R23,
80 TCG_REG_R28,
81 TCG_REG_R29,
82 TCG_REG_R30,
83 TCG_REG_R31,
84 TCG_REG_R3,
85 TCG_REG_R4,
86 TCG_REG_R5,
87 TCG_REG_R6,
88 TCG_REG_R7,
89 TCG_REG_R8,
90 TCG_REG_R9,
91 TCG_REG_R10,
92 TCG_REG_R11,
93 TCG_REG_R12,
94 TCG_REG_R13,
95 TCG_REG_R0,
96 TCG_REG_R1,
97 TCG_REG_R2,
98 TCG_REG_R24,
99 TCG_REG_R25,
100 TCG_REG_R26,
101 TCG_REG_R27
102 };
103
104 static const int tcg_target_call_iarg_regs[] = {
105 TCG_REG_R3,
106 TCG_REG_R4,
107 TCG_REG_R5,
108 TCG_REG_R6,
109 TCG_REG_R7,
110 TCG_REG_R8,
111 TCG_REG_R9,
112 TCG_REG_R10
113 };
114
115 static const int tcg_target_call_oarg_regs[2] = {
116 TCG_REG_R3,
117 TCG_REG_R4
118 };
119
120 static const int tcg_target_callee_save_regs[] = {
121 TCG_REG_R14,
122 TCG_REG_R15,
123 TCG_REG_R16,
124 TCG_REG_R17,
125 TCG_REG_R18,
126 TCG_REG_R19,
127 TCG_REG_R20,
128 TCG_REG_R21,
129 TCG_REG_R22,
130 TCG_REG_R23,
131 TCG_REG_R28,
132 TCG_REG_R29,
133 TCG_REG_R30,
134 TCG_REG_R31
135 };
136
137 static uint32_t reloc_pc24_val (void *pc, tcg_target_long target)
138 {
139 tcg_target_long disp;
140
141 disp = target - (tcg_target_long) pc;
142 if ((disp << 6) >> 6 != disp)
143 tcg_abort ();
144
145 return disp & 0x3fffffc;
146 }
147
148 static void reloc_pc24 (void *pc, tcg_target_long target)
149 {
150 *(uint32_t *) pc = (*(uint32_t *) pc & ~0x3fffffc)
151 | reloc_pc24_val (pc, target);
152 }
153
154 static uint16_t reloc_pc14_val (void *pc, tcg_target_long target)
155 {
156 tcg_target_long disp;
157
158 disp = target - (tcg_target_long) pc;
159 if (disp != (int16_t) disp)
160 tcg_abort ();
161
162 return disp & 0xfffc;
163 }
164
165 static void reloc_pc14 (void *pc, tcg_target_long target)
166 {
167 *(uint32_t *) pc = (*(uint32_t *) pc & ~0xfffc)
168 | reloc_pc14_val (pc, target);
169 }
170
171 static void patch_reloc(uint8_t *code_ptr, int type,
172 tcg_target_long value, tcg_target_long addend)
173 {
174 value += addend;
175 switch (type) {
176 case R_PPC_REL14:
177 reloc_pc14 (code_ptr, value);
178 break;
179 case R_PPC_REL24:
180 reloc_pc24 (code_ptr, value);
181 break;
182 default:
183 tcg_abort();
184 }
185 }
186
187 /* maximum number of register used for input function arguments */
188 static int tcg_target_get_call_iarg_regs_count(int flags)
189 {
190 return sizeof (tcg_target_call_iarg_regs) / sizeof (tcg_target_call_iarg_regs[0]);
191 }
192
193 /* parse target specific constraints */
194 static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
195 {
196 const char *ct_str;
197
198 ct_str = *pct_str;
199 switch (ct_str[0]) {
200 case 'A': case 'B': case 'C': case 'D':
201 ct->ct |= TCG_CT_REG;
202 tcg_regset_set_reg(ct->u.regs, 3 + ct_str[0] - 'A');
203 break;
204 case 'r':
205 ct->ct |= TCG_CT_REG;
206 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
207 break;
208 case 'L': /* qemu_ld constraint */
209 ct->ct |= TCG_CT_REG;
210 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
211 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
212 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4);
213 break;
214 case 'K': /* qemu_st[8..32] constraint */
215 ct->ct |= TCG_CT_REG;
216 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
217 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
218 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4);
219 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5);
220 #if TARGET_LONG_BITS == 64
221 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R6);
222 #endif
223 break;
224 case 'M': /* qemu_st64 constraint */
225 ct->ct |= TCG_CT_REG;
226 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
227 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
228 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4);
229 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5);
230 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R6);
231 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R7);
232 break;
233 default:
234 return -1;
235 }
236 ct_str++;
237 *pct_str = ct_str;
238 return 0;
239 }
240
241 /* test if a constant matches the constraint */
242 static int tcg_target_const_match(tcg_target_long val,
243 const TCGArgConstraint *arg_ct)
244 {
245 int ct;
246
247 ct = arg_ct->ct;
248 if (ct & TCG_CT_CONST)
249 return 1;
250 return 0;
251 }
252
253 #define OPCD(opc) ((opc)<<26)
254 #define XO31(opc) (OPCD(31)|((opc)<<1))
255 #define XO19(opc) (OPCD(19)|((opc)<<1))
256
257 #define B OPCD(18)
258 #define BC OPCD(16)
259 #define LBZ OPCD(34)
260 #define LHZ OPCD(40)
261 #define LHA OPCD(42)
262 #define LWZ OPCD(32)
263 #define STB OPCD(38)
264 #define STH OPCD(44)
265 #define STW OPCD(36)
266
267 #define ADDI OPCD(14)
268 #define ADDIS OPCD(15)
269 #define ORI OPCD(24)
270 #define ORIS OPCD(25)
271 #define XORI OPCD(26)
272 #define XORIS OPCD(27)
273 #define ANDI OPCD(28)
274 #define ANDIS OPCD(29)
275 #define MULLI OPCD( 7)
276 #define CMPLI OPCD(10)
277 #define CMPI OPCD(11)
278
279 #define LWZU OPCD(33)
280 #define STWU OPCD(37)
281
282 #define RLWINM OPCD(21)
283
284 #define BCLR XO19( 16)
285 #define BCCTR XO19(528)
286 #define CRAND XO19(257)
287 #define CRANDC XO19(129)
288 #define CRNAND XO19(225)
289 #define CROR XO19(449)
290
291 #define EXTSB XO31(954)
292 #define EXTSH XO31(922)
293 #define ADD XO31(266)
294 #define ADDE XO31(138)
295 #define ADDC XO31( 10)
296 #define AND XO31( 28)
297 #define SUBF XO31( 40)
298 #define SUBFC XO31( 8)
299 #define SUBFE XO31(136)
300 #define OR XO31(444)
301 #define XOR XO31(316)
302 #define MULLW XO31(235)
303 #define MULHWU XO31( 11)
304 #define DIVW XO31(491)
305 #define DIVWU XO31(459)
306 #define CMP XO31( 0)
307 #define CMPL XO31( 32)
308 #define LHBRX XO31(790)
309 #define LWBRX XO31(534)
310 #define STHBRX XO31(918)
311 #define STWBRX XO31(662)
312 #define MFSPR XO31(339)
313 #define MTSPR XO31(467)
314 #define SRAWI XO31(824)
315 #define NEG XO31(104)
316
317 #define LBZX XO31( 87)
318 #define LHZX XO31(276)
319 #define LHAX XO31(343)
320 #define LWZX XO31( 23)
321 #define STBX XO31(215)
322 #define STHX XO31(407)
323 #define STWX XO31(151)
324
325 #define SPR(a,b) ((((a)<<5)|(b))<<11)
326 #define LR SPR(8, 0)
327 #define CTR SPR(9, 0)
328
329 #define SLW XO31( 24)
330 #define SRW XO31(536)
331 #define SRAW XO31(792)
332
333 #define LMW OPCD(46)
334 #define STMW OPCD(47)
335
336 #define TW XO31(4)
337 #define TRAP (TW | TO (31))
338
339 #define RT(r) ((r)<<21)
340 #define RS(r) ((r)<<21)
341 #define RA(r) ((r)<<16)
342 #define RB(r) ((r)<<11)
343 #define TO(t) ((t)<<21)
344 #define SH(s) ((s)<<11)
345 #define MB(b) ((b)<<6)
346 #define ME(e) ((e)<<1)
347 #define BO(o) ((o)<<21)
348
349 #define LK 1
350
351 #define TAB(t,a,b) (RT(t) | RA(a) | RB(b))
352 #define SAB(s,a,b) (RS(s) | RA(a) | RB(b))
353
354 #define BF(n) ((n)<<23)
355 #define BI(n, c) (((c)+((n)*4))<<16)
356 #define BT(n, c) (((c)+((n)*4))<<21)
357 #define BA(n, c) (((c)+((n)*4))<<16)
358 #define BB(n, c) (((c)+((n)*4))<<11)
359
360 #define BO_COND_TRUE BO (12)
361 #define BO_COND_FALSE BO (4)
362 #define BO_ALWAYS BO (20)
363
364 enum {
365 CR_LT,
366 CR_GT,
367 CR_EQ,
368 CR_SO
369 };
370
371 static const uint32_t tcg_to_bc[10] = {
372 [TCG_COND_EQ] = BC | BI (7, CR_EQ) | BO_COND_TRUE,
373 [TCG_COND_NE] = BC | BI (7, CR_EQ) | BO_COND_FALSE,
374 [TCG_COND_LT] = BC | BI (7, CR_LT) | BO_COND_TRUE,
375 [TCG_COND_GE] = BC | BI (7, CR_LT) | BO_COND_FALSE,
376 [TCG_COND_LE] = BC | BI (7, CR_GT) | BO_COND_FALSE,
377 [TCG_COND_GT] = BC | BI (7, CR_GT) | BO_COND_TRUE,
378 [TCG_COND_LTU] = BC | BI (7, CR_LT) | BO_COND_TRUE,
379 [TCG_COND_GEU] = BC | BI (7, CR_LT) | BO_COND_FALSE,
380 [TCG_COND_LEU] = BC | BI (7, CR_GT) | BO_COND_FALSE,
381 [TCG_COND_GTU] = BC | BI (7, CR_GT) | BO_COND_TRUE,
382 };
383
384 static void tcg_out_mov(TCGContext *s, int ret, int arg)
385 {
386 tcg_out32 (s, OR | SAB (arg, ret, arg));
387 }
388
389 static void tcg_out_movi(TCGContext *s, TCGType type,
390 int ret, tcg_target_long arg)
391 {
392 if (arg == (int16_t) arg)
393 tcg_out32 (s, ADDI | RT (ret) | RA (0) | (arg & 0xffff));
394 else {
395 tcg_out32 (s, ADDIS | RT (ret) | RA (0) | ((arg >> 16) & 0xffff));
396 if (arg & 0xffff)
397 tcg_out32 (s, ORI | RS (ret) | RA (ret) | (arg & 0xffff));
398 }
399 }
400
401 static void tcg_out_ldst (TCGContext *s, int ret, int addr,
402 int offset, int op1, int op2)
403 {
404 if (offset == (int16_t) offset)
405 tcg_out32 (s, op1 | RT (ret) | RA (addr) | (offset & 0xffff));
406 else {
407 tcg_out_movi (s, TCG_TYPE_I32, 0, offset);
408 tcg_out32 (s, op2 | RT (ret) | RA (addr) | RB (0));
409 }
410 }
411
412 static void tcg_out_b (TCGContext *s, int mask, tcg_target_long target)
413 {
414 tcg_target_long disp;
415
416 disp = target - (tcg_target_long) s->code_ptr;
417 if ((disp << 6) >> 6 == disp)
418 tcg_out32 (s, B | (disp & 0x3fffffc) | mask);
419 else {
420 tcg_out_movi (s, TCG_TYPE_I32, 0, (tcg_target_long) target);
421 tcg_out32 (s, MTSPR | RS (0) | CTR);
422 tcg_out32 (s, BCCTR | BO_ALWAYS | mask);
423 }
424 }
425
426 #if defined(CONFIG_SOFTMMU)
427 extern void __ldb_mmu(void);
428 extern void __ldw_mmu(void);
429 extern void __ldl_mmu(void);
430 extern void __ldq_mmu(void);
431
432 extern void __stb_mmu(void);
433 extern void __stw_mmu(void);
434 extern void __stl_mmu(void);
435 extern void __stq_mmu(void);
436
437 static void *qemu_ld_helpers[4] = {
438 __ldb_mmu,
439 __ldw_mmu,
440 __ldl_mmu,
441 __ldq_mmu,
442 };
443
444 static void *qemu_st_helpers[4] = {
445 __stb_mmu,
446 __stw_mmu,
447 __stl_mmu,
448 __stq_mmu,
449 };
450 #endif
451
452 static void tcg_out_qemu_ld (TCGContext *s, const TCGArg *args, int opc)
453 {
454 int addr_reg, data_reg, data_reg2, r0, mem_index, s_bits, bswap;
455 #ifdef CONFIG_SOFTMMU
456 int r1, r2;
457 void *label1_ptr, *label2_ptr;
458 #endif
459 #if TARGET_LONG_BITS == 64
460 int addr_reg2;
461 #endif
462
463 data_reg = *args++;
464 if (opc == 3)
465 data_reg2 = *args++;
466 else
467 data_reg2 = 0;
468 addr_reg = *args++;
469 #if TARGET_LONG_BITS == 64
470 addr_reg2 = *args++;
471 #endif
472 mem_index = *args;
473 s_bits = opc & 3;
474
475 #ifdef CONFIG_SOFTMMU
476 r0 = 3;
477 r1 = 4;
478 r2 = 0;
479
480 tcg_out32 (s, (RLWINM
481 | RA (r0)
482 | RS (addr_reg)
483 | SH (32 - (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS))
484 | MB (32 - (CPU_TLB_BITS + CPU_TLB_ENTRY_BITS))
485 | ME (31 - CPU_TLB_ENTRY_BITS)
486 )
487 );
488 tcg_out32 (s, ADD | RT (r0) | RA (r0) | RB (TCG_AREG0));
489 tcg_out32 (s, (LWZU
490 | RT (r1)
491 | RA (r0)
492 | offsetof (CPUState, tlb_table[mem_index][0].addr_read)
493 )
494 );
495 tcg_out32 (s, (RLWINM
496 | RA (r2)
497 | RS (addr_reg)
498 | SH (0)
499 | MB ((32 - s_bits) & 31)
500 | ME (31 - TARGET_PAGE_BITS)
501 )
502 );
503
504 tcg_out32 (s, CMP | BF (7) | RA (r2) | RB (r1));
505 #if TARGET_LONG_BITS == 64
506 tcg_out32 (s, LWZ | RT (r1) | RA (r0) | 4);
507 tcg_out32 (s, CMP | BF (6) | RA (addr_reg2) | RB (r1));
508 tcg_out32 (s, CRAND | BT (7, CR_EQ) | BA (6, CR_EQ) | BB (7, CR_EQ));
509 #endif
510
511 label1_ptr = s->code_ptr;
512 #ifdef FAST_PATH
513 tcg_out32 (s, BC | BI (7, CR_EQ) | BO_COND_TRUE);
514 #endif
515
516 /* slow path */
517 #if TARGET_LONG_BITS == 32
518 tcg_out_mov (s, 3, addr_reg);
519 tcg_out_movi (s, TCG_TYPE_I32, 4, mem_index);
520 #else
521 tcg_out_mov (s, 3, addr_reg2);
522 tcg_out_mov (s, 4, addr_reg);
523 tcg_out_movi (s, TCG_TYPE_I32, 5, mem_index);
524 #endif
525
526 tcg_out_b (s, LK, (tcg_target_long) qemu_ld_helpers[s_bits]);
527 switch (opc) {
528 case 0|4:
529 tcg_out32 (s, EXTSB | RA (data_reg) | RS (3));
530 break;
531 case 1|4:
532 tcg_out32 (s, EXTSH | RA (data_reg) | RS (3));
533 break;
534 case 0:
535 case 1:
536 case 2:
537 if (data_reg != 3)
538 tcg_out_mov (s, data_reg, 3);
539 break;
540 case 3:
541 if (data_reg == 3) {
542 if (data_reg2 == 4) {
543 tcg_out_mov (s, 0, 4);
544 tcg_out_mov (s, 4, 3);
545 tcg_out_mov (s, 3, 0);
546 }
547 else {
548 tcg_out_mov (s, data_reg2, 3);
549 tcg_out_mov (s, 3, 4);
550 }
551 }
552 else {
553 if (data_reg != 4) tcg_out_mov (s, data_reg, 4);
554 if (data_reg2 != 3) tcg_out_mov (s, data_reg2, 3);
555 }
556 break;
557 }
558 label2_ptr = s->code_ptr;
559 tcg_out32 (s, B);
560
561 /* label1: fast path */
562 #ifdef FAST_PATH
563 reloc_pc14 (label1_ptr, (tcg_target_long) s->code_ptr);
564 #endif
565
566 /* r0 now contains &env->tlb_table[mem_index][index].addr_read */
567 tcg_out32 (s, (LWZ
568 | RT (r0)
569 | RA (r0)
570 | (ADDEND_OFFSET + offsetof (CPUTLBEntry, addend)
571 - offsetof (CPUTLBEntry, addr_read))
572 ));
573 /* r0 = env->tlb_table[mem_index][index].addend */
574 tcg_out32 (s, ADD | RT (r0) | RA (r0) | RB (addr_reg));
575 /* r0 = env->tlb_table[mem_index][index].addend + addr */
576
577 #else /* !CONFIG_SOFTMMU */
578 r0 = addr_reg;
579 #endif
580
581 #ifdef TARGET_WORDS_BIGENDIAN
582 bswap = 0;
583 #else
584 bswap = 1;
585 #endif
586 switch (opc) {
587 default:
588 case 0:
589 tcg_out32 (s, LBZ | RT (data_reg) | RA (r0));
590 break;
591 case 0|4:
592 tcg_out32 (s, LBZ | RT (data_reg) | RA (r0));
593 tcg_out32 (s, EXTSB | RA (data_reg) | RS (data_reg));
594 break;
595 case 1:
596 if (bswap) tcg_out32 (s, LHBRX | RT (data_reg) | RB (r0));
597 else tcg_out32 (s, LHZ | RT (data_reg) | RA (r0));
598 break;
599 case 1|4:
600 if (bswap) {
601 tcg_out32 (s, LHBRX | RT (data_reg) | RB (r0));
602 tcg_out32 (s, EXTSH | RA (data_reg) | RS (data_reg));
603 }
604 else tcg_out32 (s, LHA | RT (data_reg) | RA (r0));
605 break;
606 case 2:
607 if (bswap) tcg_out32 (s, LWBRX | RT (data_reg) | RB (r0));
608 else tcg_out32 (s, LWZ | RT (data_reg)| RA (r0));
609 break;
610 case 3:
611 if (bswap) {
612 if (r0 == data_reg) {
613 tcg_out32 (s, LWBRX | RT (0) | RB (r0));
614 tcg_out32 (s, ADDI | RT (r0) | RA (r0) | 4);
615 tcg_out32 (s, LWBRX | RT (data_reg2) | RB (r0));
616 tcg_out_mov (s, data_reg, 0);
617 }
618 else {
619 tcg_out32 (s, LWBRX | RT (data_reg) | RB (r0));
620 tcg_out32 (s, ADDI | RT (r0) | RA (r0) | 4);
621 tcg_out32 (s, LWBRX | RT (data_reg2) | RB (r0));
622 }
623 }
624 else {
625 if (r0 == data_reg2) {
626 tcg_out32 (s, LWZ | RT (0) | RA (r0));
627 tcg_out32 (s, LWZ | RT (data_reg) | RA (r0) | 4);
628 tcg_out_mov (s, data_reg2, 0);
629 }
630 else {
631 tcg_out32 (s, LWZ | RT (data_reg2) | RA (r0));
632 tcg_out32 (s, LWZ | RT (data_reg) | RA (r0) | 4);
633 }
634 }
635 break;
636 }
637
638 #ifdef CONFIG_SOFTMMU
639 reloc_pc24 (label2_ptr, (tcg_target_long) s->code_ptr);
640 #endif
641 }
642
643 static void tcg_out_qemu_st (TCGContext *s, const TCGArg *args, int opc)
644 {
645 int addr_reg, r0, r1, data_reg, data_reg2, mem_index, bswap;
646 #ifdef CONFIG_SOFTMMU
647 int r2, ir;
648 void *label1_ptr, *label2_ptr;
649 #endif
650 #if TARGET_LONG_BITS == 64
651 int addr_reg2;
652 #endif
653
654 data_reg = *args++;
655 if (opc == 3)
656 data_reg2 = *args++;
657 else
658 data_reg2 = 0;
659 addr_reg = *args++;
660 #if TARGET_LONG_BITS == 64
661 addr_reg2 = *args++;
662 #endif
663 mem_index = *args;
664
665 #ifdef CONFIG_SOFTMMU
666 r0 = 3;
667 r1 = 4;
668 r2 = 0;
669
670 tcg_out32 (s, (RLWINM
671 | RA (r0)
672 | RS (addr_reg)
673 | SH (32 - (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS))
674 | MB (32 - (CPU_TLB_ENTRY_BITS + CPU_TLB_BITS))
675 | ME (31 - CPU_TLB_ENTRY_BITS)
676 )
677 );
678 tcg_out32 (s, ADD | RT (r0) | RA (r0) | RB (TCG_AREG0));
679 tcg_out32 (s, (LWZU
680 | RT (r1)
681 | RA (r0)
682 | offsetof (CPUState, tlb_table[mem_index][0].addr_write)
683 )
684 );
685 tcg_out32 (s, (RLWINM
686 | RA (r2)
687 | RS (addr_reg)
688 | SH (0)
689 | MB ((32 - opc) & 31)
690 | ME (31 - TARGET_PAGE_BITS)
691 )
692 );
693
694 tcg_out32 (s, CMP | (7 << 23) | RA (r2) | RB (r1));
695 #if TARGET_LONG_BITS == 64
696 tcg_out32 (s, LWZ | RT (r1) | RA (r0) | 4);
697 tcg_out32 (s, CMP | BF (6) | RA (addr_reg2) | RB (r1));
698 tcg_out32 (s, CRAND | BT (7, CR_EQ) | BA (6, CR_EQ) | BB (7, CR_EQ));
699 #endif
700
701 label1_ptr = s->code_ptr;
702 #ifdef FAST_PATH
703 tcg_out32 (s, BC | BI (7, CR_EQ) | BO_COND_TRUE);
704 #endif
705
706 /* slow path */
707 #if TARGET_LONG_BITS == 32
708 tcg_out_mov (s, 3, addr_reg);
709 ir = 4;
710 #else
711 tcg_out_mov (s, 3, addr_reg2);
712 tcg_out_mov (s, 4, addr_reg);
713 ir = 5;
714 #endif
715
716 switch (opc) {
717 case 0:
718 tcg_out32 (s, (RLWINM
719 | RA (ir)
720 | RS (data_reg)
721 | SH (0)
722 | MB (24)
723 | ME (31)));
724 break;
725 case 1:
726 tcg_out32 (s, (RLWINM
727 | RA (ir)
728 | RS (data_reg)
729 | SH (0)
730 | MB (16)
731 | ME (31)));
732 break;
733 case 2:
734 tcg_out_mov (s, ir, data_reg);
735 break;
736 case 3:
737 tcg_out_mov (s, 5, data_reg2);
738 tcg_out_mov (s, 6, data_reg);
739 ir = 6;
740 break;
741 }
742 ir++;
743
744 tcg_out_movi (s, TCG_TYPE_I32, ir, mem_index);
745 tcg_out_b (s, LK, (tcg_target_long) qemu_st_helpers[opc]);
746 label2_ptr = s->code_ptr;
747 tcg_out32 (s, B);
748
749 /* label1: fast path */
750 #ifdef FAST_PATH
751 reloc_pc14 (label1_ptr, (tcg_target_long) s->code_ptr);
752 #endif
753
754 tcg_out32 (s, (LWZ
755 | RT (r0)
756 | RA (r0)
757 | (ADDEND_OFFSET + offsetof (CPUTLBEntry, addend)
758 - offsetof (CPUTLBEntry, addr_write))
759 ));
760 /* r0 = env->tlb_table[mem_index][index].addend */
761 tcg_out32 (s, ADD | RT (r0) | RA (r0) | RB (addr_reg));
762 /* r0 = env->tlb_table[mem_index][index].addend + addr */
763
764 #else /* !CONFIG_SOFTMMU */
765 r1 = 4;
766 r0 = addr_reg;
767 #endif
768
769 #ifdef TARGET_WORDS_BIGENDIAN
770 bswap = 0;
771 #else
772 bswap = 1;
773 #endif
774 switch (opc) {
775 case 0:
776 tcg_out32 (s, STB | RS (data_reg) | RA (r0));
777 break;
778 case 1:
779 if (bswap) tcg_out32 (s, STHBRX | RS (data_reg) | RA (0) | RB (r0));
780 else tcg_out32 (s, STH | RS (data_reg) | RA (r0));
781 break;
782 case 2:
783 if (bswap) tcg_out32 (s, STWBRX | RS (data_reg) | RA (0) | RB (r0));
784 else tcg_out32 (s, STW | RS (data_reg) | RA (r0));
785 break;
786 case 3:
787 if (bswap) {
788 tcg_out32 (s, ADDI | RT (r1) | RA (r0) | 4);
789 tcg_out32 (s, STWBRX | RS (data_reg) | RA (0) | RB (r0));
790 tcg_out32 (s, STWBRX | RS (data_reg2) | RA (0) | RB (r1));
791 }
792 else {
793 tcg_out32 (s, STW | RS (data_reg2) | RA (r0));
794 tcg_out32 (s, STW | RS (data_reg) | RA (r0) | 4);
795 }
796 break;
797 }
798
799 #ifdef CONFIG_SOFTMMU
800 reloc_pc24 (label2_ptr, (tcg_target_long) s->code_ptr);
801 #endif
802 }
803
804 void tcg_target_qemu_prologue (TCGContext *s)
805 {
806 int i, frame_size;
807
808 frame_size = 0
809 + 4 /* back chain */
810 + 4 /* LR */
811 + TCG_STATIC_CALL_ARGS_SIZE
812 + ARRAY_SIZE (tcg_target_callee_save_regs) * 4
813 ;
814 frame_size = (frame_size + 15) & ~15;
815
816 tcg_out32 (s, MFSPR | RT (0) | LR);
817 tcg_out32 (s, STWU | RS (1) | RA (1) | (-frame_size & 0xffff));
818 for (i = 0; i < ARRAY_SIZE (tcg_target_callee_save_regs); ++i)
819 tcg_out32 (s, (STW
820 | RS (tcg_target_callee_save_regs[i])
821 | RA (1)
822 | (i * 4 + 8 + TCG_STATIC_CALL_ARGS_SIZE)
823 )
824 );
825 tcg_out32 (s, STW | RS (0) | RA (1) | (frame_size + 4));
826
827 tcg_out32 (s, MTSPR | RS (3) | CTR);
828 tcg_out32 (s, BCCTR | BO_ALWAYS);
829 tb_ret_addr = s->code_ptr;
830
831 for (i = 0; i < ARRAY_SIZE (tcg_target_callee_save_regs); ++i)
832 tcg_out32 (s, (LWZ
833 | RT (tcg_target_callee_save_regs[i])
834 | RA (1)
835 | (i * 4 + 8 + TCG_STATIC_CALL_ARGS_SIZE)
836 )
837 );
838 tcg_out32 (s, LWZ | RT (0) | RA (1) | (frame_size + 4));
839 tcg_out32 (s, MTSPR | RS (0) | LR);
840 tcg_out32 (s, ADDI | RT (1) | RA (1) | frame_size);
841 tcg_out32 (s, BCLR | BO_ALWAYS);
842 }
843
844 static void tcg_out_ld (TCGContext *s, TCGType type, int ret, int arg1,
845 tcg_target_long arg2)
846 {
847 tcg_out_ldst (s, ret, arg1, arg2, LWZ, LWZX);
848 }
849
850 static void tcg_out_st (TCGContext *s, TCGType type, int arg, int arg1,
851 tcg_target_long arg2)
852 {
853 tcg_out_ldst (s, arg, arg1, arg2, STW, STWX);
854 }
855
856 static void ppc_addi (TCGContext *s, int rt, int ra, tcg_target_long si)
857 {
858 if (!si && rt == ra)
859 return;
860
861 if (si == (int16_t) si)
862 tcg_out32 (s, ADDI | RT (rt) | RA (ra) | (si & 0xffff));
863 else {
864 uint16_t h = ((si >> 16) & 0xffff) + ((uint16_t) si >> 15);
865 tcg_out32 (s, ADDIS | RT (rt) | RA (ra) | h);
866 tcg_out32 (s, ADDI | RT (rt) | RA (rt) | (si & 0xffff));
867 }
868 }
869
870 static void tcg_out_addi(TCGContext *s, int reg, tcg_target_long val)
871 {
872 ppc_addi (s, reg, reg, val);
873 }
874
875 static void tcg_out_cmp (TCGContext *s, int cond, TCGArg arg1, TCGArg arg2,
876 int const_arg2, int cr)
877 {
878 int imm;
879 uint32_t op;
880
881 switch (cond) {
882 case TCG_COND_EQ:
883 case TCG_COND_NE:
884 if (const_arg2) {
885 if ((int16_t) arg2 == arg2) {
886 op = CMPI;
887 imm = 1;
888 break;
889 }
890 else if ((uint16_t) arg2 == arg2) {
891 op = CMPLI;
892 imm = 1;
893 break;
894 }
895 }
896 op = CMPL;
897 imm = 0;
898 break;
899
900 case TCG_COND_LT:
901 case TCG_COND_GE:
902 case TCG_COND_LE:
903 case TCG_COND_GT:
904 if (const_arg2) {
905 if ((int16_t) arg2 == arg2) {
906 op = CMPI;
907 imm = 1;
908 break;
909 }
910 }
911 op = CMP;
912 imm = 0;
913 break;
914
915 case TCG_COND_LTU:
916 case TCG_COND_GEU:
917 case TCG_COND_LEU:
918 case TCG_COND_GTU:
919 if (const_arg2) {
920 if ((uint16_t) arg2 == arg2) {
921 op = CMPLI;
922 imm = 1;
923 break;
924 }
925 }
926 op = CMPL;
927 imm = 0;
928 break;
929
930 default:
931 tcg_abort ();
932 }
933 op |= BF (cr);
934
935 if (imm)
936 tcg_out32 (s, op | RA (arg1) | (arg2 & 0xffff));
937 else {
938 if (const_arg2) {
939 tcg_out_movi (s, TCG_TYPE_I32, 0, arg2);
940 tcg_out32 (s, op | RA (arg1) | RB (0));
941 }
942 else
943 tcg_out32 (s, op | RA (arg1) | RB (arg2));
944 }
945
946 }
947
948 static void tcg_out_bc (TCGContext *s, int bc, int label_index)
949 {
950 TCGLabel *l = &s->labels[label_index];
951
952 if (l->has_value)
953 tcg_out32 (s, bc | reloc_pc14_val (s->code_ptr, l->u.value));
954 else {
955 uint16_t val = *(uint16_t *) &s->code_ptr[2];
956
957 /* Thanks to Andrzej Zaborowski */
958 tcg_out32 (s, bc | (val & 0xfffc));
959 tcg_out_reloc (s, s->code_ptr - 4, R_PPC_REL14, label_index, 0);
960 }
961 }
962
963 static void tcg_out_brcond (TCGContext *s, int cond,
964 TCGArg arg1, TCGArg arg2, int const_arg2,
965 int label_index)
966 {
967 tcg_out_cmp (s, cond, arg1, arg2, const_arg2, 7);
968 tcg_out_bc (s, tcg_to_bc[cond], label_index);
969 }
970
971 /* XXX: we implement it at the target level to avoid having to
972 handle cross basic blocks temporaries */
973 static void tcg_out_brcond2 (TCGContext *s, const TCGArg *args,
974 const int *const_args)
975 {
976 int cond = args[4], label_index = args[5], op;
977 struct { int bit1; int bit2; int cond2; } bits[] = {
978 [TCG_COND_LT ] = { CR_LT, CR_LT, TCG_COND_LT },
979 [TCG_COND_LE ] = { CR_LT, CR_GT, TCG_COND_LT },
980 [TCG_COND_GT ] = { CR_GT, CR_GT, TCG_COND_GT },
981 [TCG_COND_GE ] = { CR_GT, CR_LT, TCG_COND_GT },
982 [TCG_COND_LTU] = { CR_LT, CR_LT, TCG_COND_LTU },
983 [TCG_COND_LEU] = { CR_LT, CR_GT, TCG_COND_LTU },
984 [TCG_COND_GTU] = { CR_GT, CR_GT, TCG_COND_GTU },
985 [TCG_COND_GEU] = { CR_GT, CR_LT, TCG_COND_GTU },
986 }, *b = &bits[cond];
987
988 switch (cond) {
989 case TCG_COND_EQ:
990 case TCG_COND_NE:
991 op = (cond == TCG_COND_EQ) ? CRAND : CRNAND;
992 tcg_out_cmp (s, cond, args[0], args[2], const_args[2], 6);
993 tcg_out_cmp (s, cond, args[1], args[3], const_args[3], 7);
994 tcg_out32 (s, op | BT (7, CR_EQ) | BA (6, CR_EQ) | BB (7, CR_EQ));
995 break;
996 case TCG_COND_LT:
997 case TCG_COND_LE:
998 case TCG_COND_GT:
999 case TCG_COND_GE:
1000 case TCG_COND_LTU:
1001 case TCG_COND_LEU:
1002 case TCG_COND_GTU:
1003 case TCG_COND_GEU:
1004 op = (b->bit1 != b->bit2) ? CRANDC : CRAND;
1005 tcg_out_cmp (s, b->cond2, args[1], args[3], const_args[3], 5);
1006 tcg_out_cmp (s, TCG_COND_EQ, args[1], args[3], const_args[3], 6);
1007 tcg_out_cmp (s, cond, args[0], args[2], const_args[2], 7);
1008 tcg_out32 (s, op | BT (7, CR_EQ) | BA (6, CR_EQ) | BB (7, b->bit2));
1009 tcg_out32 (s, CROR | BT (7, CR_EQ) | BA (5, b->bit1) | BB (7, CR_EQ));
1010 break;
1011 default:
1012 tcg_abort();
1013 }
1014
1015 tcg_out_bc (s, (BC | BI (7, CR_EQ) | BO_COND_TRUE), label_index);
1016 }
1017
1018 static void tcg_out_op(TCGContext *s, int opc, const TCGArg *args,
1019 const int *const_args)
1020 {
1021 switch (opc) {
1022 case INDEX_op_exit_tb:
1023 tcg_out_movi (s, TCG_TYPE_I32, TCG_REG_R3, args[0]);
1024 tcg_out_b (s, 0, (tcg_target_long) tb_ret_addr);
1025 break;
1026 case INDEX_op_goto_tb:
1027 if (s->tb_jmp_offset) {
1028 /* direct jump method */
1029
1030 s->tb_jmp_offset[args[0]] = s->code_ptr - s->code_buf;
1031 s->code_ptr += 16;
1032 }
1033 else {
1034 tcg_abort ();
1035 }
1036 s->tb_next_offset[args[0]] = s->code_ptr - s->code_buf;
1037 break;
1038 case INDEX_op_br:
1039 {
1040 TCGLabel *l = &s->labels[args[0]];
1041
1042 if (l->has_value) {
1043 tcg_out_b (s, 0, l->u.value);
1044 }
1045 else {
1046 uint32_t val = *(uint32_t *) s->code_ptr;
1047
1048 /* Thanks to Andrzej Zaborowski */
1049 tcg_out32 (s, B | (val & 0x3fffffc));
1050 tcg_out_reloc (s, s->code_ptr - 4, R_PPC_REL24, args[0], 0);
1051 }
1052 }
1053 break;
1054 case INDEX_op_call:
1055 if (const_args[0]) {
1056 tcg_out_b (s, LK, args[0]);
1057 }
1058 else {
1059 tcg_out32 (s, MTSPR | RS (args[0]) | LR);
1060 tcg_out32 (s, BCLR | BO_ALWAYS | LK);
1061 }
1062 break;
1063 case INDEX_op_jmp:
1064 if (const_args[0]) {
1065 tcg_out_b (s, 0, args[0]);
1066 }
1067 else {
1068 tcg_out32 (s, MTSPR | RS (args[0]) | CTR);
1069 tcg_out32 (s, BCCTR | BO_ALWAYS);
1070 }
1071 break;
1072 case INDEX_op_movi_i32:
1073 tcg_out_movi(s, TCG_TYPE_I32, args[0], args[1]);
1074 break;
1075 case INDEX_op_ld8u_i32:
1076 tcg_out_ldst (s, args[0], args[1], args[2], LBZ, LBZX);
1077 break;
1078 case INDEX_op_ld8s_i32:
1079 tcg_out_ldst (s, args[0], args[1], args[2], LBZ, LBZX);
1080 tcg_out32 (s, EXTSB | RS (args[0]) | RA (args[0]));
1081 break;
1082 case INDEX_op_ld16u_i32:
1083 tcg_out_ldst (s, args[0], args[1], args[2], LHZ, LHZX);
1084 break;
1085 case INDEX_op_ld16s_i32:
1086 tcg_out_ldst (s, args[0], args[1], args[2], LHA, LHAX);
1087 break;
1088 case INDEX_op_ld_i32:
1089 tcg_out_ldst (s, args[0], args[1], args[2], LWZ, LWZX);
1090 break;
1091 case INDEX_op_st8_i32:
1092 tcg_out_ldst (s, args[0], args[1], args[2], STB, STBX);
1093 break;
1094 case INDEX_op_st16_i32:
1095 tcg_out_ldst (s, args[0], args[1], args[2], STH, STHX);
1096 break;
1097 case INDEX_op_st_i32:
1098 tcg_out_ldst (s, args[0], args[1], args[2], STW, STWX);
1099 break;
1100
1101 case INDEX_op_add_i32:
1102 if (const_args[2])
1103 ppc_addi (s, args[0], args[1], args[2]);
1104 else
1105 tcg_out32 (s, ADD | TAB (args[0], args[1], args[2]));
1106 break;
1107 case INDEX_op_sub_i32:
1108 if (const_args[2])
1109 ppc_addi (s, args[0], args[1], -args[2]);
1110 else
1111 tcg_out32 (s, SUBF | TAB (args[0], args[2], args[1]));
1112 break;
1113
1114 case INDEX_op_and_i32:
1115 if (const_args[2]) {
1116 if (!args[2])
1117 tcg_out_movi (s, TCG_TYPE_I32, args[0], 0);
1118 else {
1119 if ((args[2] & 0xffff) == args[2])
1120 tcg_out32 (s, ANDI | RS (args[1]) | RA (args[0]) | args[2]);
1121 else if ((args[2] & 0xffff0000) == args[2])
1122 tcg_out32 (s, ANDIS | RS (args[1]) | RA (args[0])
1123 | ((args[2] >> 16) & 0xffff));
1124 else if (args[2] == 0xffffffff) {
1125 if (args[0] != args[1])
1126 tcg_out_mov (s, args[0], args[1]);
1127 }
1128 else {
1129 tcg_out_movi (s, TCG_TYPE_I32, 0, args[2]);
1130 tcg_out32 (s, AND | SAB (args[1], args[0], 0));
1131 }
1132 }
1133 }
1134 else
1135 tcg_out32 (s, AND | SAB (args[1], args[0], args[2]));
1136 break;
1137 case INDEX_op_or_i32:
1138 if (const_args[2]) {
1139 if (args[2]) {
1140 if (args[2] & 0xffff) {
1141 tcg_out32 (s, ORI | RS (args[1]) | RA (args[0])
1142 | (args[2] & 0xffff));
1143 if (args[2] >> 16)
1144 tcg_out32 (s, ORIS | RS (args[0]) | RA (args[0])
1145 | ((args[2] >> 16) & 0xffff));
1146 }
1147 else {
1148 tcg_out32 (s, ORIS | RS (args[1]) | RA (args[0])
1149 | ((args[2] >> 16) & 0xffff));
1150 }
1151 }
1152 else {
1153 if (args[0] != args[1])
1154 tcg_out_mov (s, args[0], args[1]);
1155 }
1156 }
1157 else
1158 tcg_out32 (s, OR | SAB (args[1], args[0], args[2]));
1159 break;
1160 case INDEX_op_xor_i32:
1161 if (const_args[2]) {
1162 if (args[2]) {
1163 if ((args[2] & 0xffff) == args[2])
1164 tcg_out32 (s, XORI | RS (args[1]) | RA (args[0])
1165 | (args[2] & 0xffff));
1166 else if ((args[2] & 0xffff0000) == args[2])
1167 tcg_out32 (s, XORIS | RS (args[1]) | RA (args[0])
1168 | ((args[2] >> 16) & 0xffff));
1169 else {
1170 tcg_out_movi (s, TCG_TYPE_I32, 0, args[2]);
1171 tcg_out32 (s, XOR | SAB (args[1], args[0], 0));
1172 }
1173 }
1174 else {
1175 if (args[0] != args[1])
1176 tcg_out_mov (s, args[0], args[1]);
1177 }
1178 }
1179 else
1180 tcg_out32 (s, XOR | SAB (args[1], args[0], args[2]));
1181 break;
1182
1183 case INDEX_op_mul_i32:
1184 if (const_args[2]) {
1185 if (args[2] == (int16_t) args[2])
1186 tcg_out32 (s, MULLI | RT (args[0]) | RA (args[1])
1187 | (args[2] & 0xffff));
1188 else {
1189 tcg_out_movi (s, TCG_TYPE_I32, 0, args[2]);
1190 tcg_out32 (s, MULLW | TAB (args[0], args[1], 0));
1191 }
1192 }
1193 else
1194 tcg_out32 (s, MULLW | TAB (args[0], args[1], args[2]));
1195 break;
1196
1197 case INDEX_op_div_i32:
1198 tcg_out32 (s, DIVW | TAB (args[0], args[1], args[2]));
1199 break;
1200
1201 case INDEX_op_divu_i32:
1202 tcg_out32 (s, DIVWU | TAB (args[0], args[1], args[2]));
1203 break;
1204
1205 case INDEX_op_rem_i32:
1206 tcg_out32 (s, DIVW | TAB (0, args[1], args[2]));
1207 tcg_out32 (s, MULLW | TAB (0, 0, args[2]));
1208 tcg_out32 (s, SUBF | TAB (args[0], 0, args[1]));
1209 break;
1210
1211 case INDEX_op_remu_i32:
1212 tcg_out32 (s, DIVWU | TAB (0, args[1], args[2]));
1213 tcg_out32 (s, MULLW | TAB (0, 0, args[2]));
1214 tcg_out32 (s, SUBF | TAB (args[0], 0, args[1]));
1215 break;
1216
1217 case INDEX_op_mulu2_i32:
1218 if (args[0] == args[2] || args[0] == args[3]) {
1219 tcg_out32 (s, MULLW | TAB (0, args[2], args[3]));
1220 tcg_out32 (s, MULHWU | TAB (args[1], args[2], args[3]));
1221 tcg_out_mov (s, args[0], 0);
1222 }
1223 else {
1224 tcg_out32 (s, MULLW | TAB (args[0], args[2], args[3]));
1225 tcg_out32 (s, MULHWU | TAB (args[1], args[2], args[3]));
1226 }
1227 break;
1228
1229 case INDEX_op_shl_i32:
1230 if (const_args[2]) {
1231 if (args[2])
1232 tcg_out32 (s, (RLWINM
1233 | RA (args[0])
1234 | RS (args[1])
1235 | SH (args[2])
1236 | MB (0)
1237 | ME (31 - args[2])
1238 )
1239 );
1240 else
1241 tcg_out_mov (s, args[0], args[1]);
1242 }
1243 else
1244 tcg_out32 (s, SLW | SAB (args[1], args[0], args[2]));
1245 break;
1246 case INDEX_op_shr_i32:
1247 if (const_args[2]) {
1248 if (args[2])
1249 tcg_out32 (s, (RLWINM
1250 | RA (args[0])
1251 | RS (args[1])
1252 | SH (32 - args[2])
1253 | MB (args[2])
1254 | ME (31)
1255 )
1256 );
1257 else
1258 tcg_out_mov (s, args[0], args[1]);
1259 }
1260 else
1261 tcg_out32 (s, SRW | SAB (args[1], args[0], args[2]));
1262 break;
1263 case INDEX_op_sar_i32:
1264 if (const_args[2])
1265 tcg_out32 (s, SRAWI | RS (args[1]) | RA (args[0]) | SH (args[2]));
1266 else
1267 tcg_out32 (s, SRAW | SAB (args[1], args[0], args[2]));
1268 break;
1269
1270 case INDEX_op_add2_i32:
1271 if (args[0] == args[3] || args[0] == args[5]) {
1272 tcg_out32 (s, ADDC | TAB (0, args[2], args[4]));
1273 tcg_out32 (s, ADDE | TAB (args[1], args[3], args[5]));
1274 tcg_out_mov (s, args[0], 0);
1275 }
1276 else {
1277 tcg_out32 (s, ADDC | TAB (args[0], args[2], args[4]));
1278 tcg_out32 (s, ADDE | TAB (args[1], args[3], args[5]));
1279 }
1280 break;
1281 case INDEX_op_sub2_i32:
1282 if (args[0] == args[3] || args[0] == args[5]) {
1283 tcg_out32 (s, SUBFC | TAB (0, args[4], args[2]));
1284 tcg_out32 (s, SUBFE | TAB (args[1], args[5], args[3]));
1285 tcg_out_mov (s, args[0], 0);
1286 }
1287 else {
1288 tcg_out32 (s, SUBFC | TAB (args[0], args[4], args[2]));
1289 tcg_out32 (s, SUBFE | TAB (args[1], args[5], args[3]));
1290 }
1291 break;
1292
1293 case INDEX_op_brcond_i32:
1294 /*
1295 args[0] = r0
1296 args[1] = r1
1297 args[2] = cond
1298 args[3] = r1 is const
1299 args[4] = label_index
1300 */
1301 tcg_out_brcond (s, args[2], args[0], args[1], const_args[1], args[3]);
1302 break;
1303 case INDEX_op_brcond2_i32:
1304 tcg_out_brcond2(s, args, const_args);
1305 break;
1306
1307 case INDEX_op_neg_i32:
1308 tcg_out32 (s, NEG | RT (args[0]) | RA (args[1]));
1309 break;
1310
1311 case INDEX_op_qemu_ld8u:
1312 tcg_out_qemu_ld(s, args, 0);
1313 break;
1314 case INDEX_op_qemu_ld8s:
1315 tcg_out_qemu_ld(s, args, 0 | 4);
1316 break;
1317 case INDEX_op_qemu_ld16u:
1318 tcg_out_qemu_ld(s, args, 1);
1319 break;
1320 case INDEX_op_qemu_ld16s:
1321 tcg_out_qemu_ld(s, args, 1 | 4);
1322 break;
1323 case INDEX_op_qemu_ld32u:
1324 tcg_out_qemu_ld(s, args, 2);
1325 break;
1326 case INDEX_op_qemu_ld64:
1327 tcg_out_qemu_ld(s, args, 3);
1328 break;
1329 case INDEX_op_qemu_st8:
1330 tcg_out_qemu_st(s, args, 0);
1331 break;
1332 case INDEX_op_qemu_st16:
1333 tcg_out_qemu_st(s, args, 1);
1334 break;
1335 case INDEX_op_qemu_st32:
1336 tcg_out_qemu_st(s, args, 2);
1337 break;
1338 case INDEX_op_qemu_st64:
1339 tcg_out_qemu_st(s, args, 3);
1340 break;
1341
1342 default:
1343 tcg_dump_ops (s, stderr);
1344 tcg_abort ();
1345 }
1346 }
1347
1348 static const TCGTargetOpDef ppc_op_defs[] = {
1349 { INDEX_op_exit_tb, { } },
1350 { INDEX_op_goto_tb, { } },
1351 { INDEX_op_call, { "ri" } },
1352 { INDEX_op_jmp, { "ri" } },
1353 { INDEX_op_br, { } },
1354
1355 { INDEX_op_mov_i32, { "r", "r" } },
1356 { INDEX_op_movi_i32, { "r" } },
1357 { INDEX_op_ld8u_i32, { "r", "r" } },
1358 { INDEX_op_ld8s_i32, { "r", "r" } },
1359 { INDEX_op_ld16u_i32, { "r", "r" } },
1360 { INDEX_op_ld16s_i32, { "r", "r" } },
1361 { INDEX_op_ld_i32, { "r", "r" } },
1362 { INDEX_op_st8_i32, { "r", "r" } },
1363 { INDEX_op_st16_i32, { "r", "r" } },
1364 { INDEX_op_st_i32, { "r", "r" } },
1365
1366 { INDEX_op_add_i32, { "r", "r", "ri" } },
1367 { INDEX_op_mul_i32, { "r", "r", "ri" } },
1368 { INDEX_op_div_i32, { "r", "r", "r" } },
1369 { INDEX_op_divu_i32, { "r", "r", "r" } },
1370 { INDEX_op_rem_i32, { "r", "r", "r" } },
1371 { INDEX_op_remu_i32, { "r", "r", "r" } },
1372 { INDEX_op_mulu2_i32, { "r", "r", "r", "r" } },
1373 { INDEX_op_sub_i32, { "r", "r", "ri" } },
1374 { INDEX_op_and_i32, { "r", "r", "ri" } },
1375 { INDEX_op_or_i32, { "r", "r", "ri" } },
1376 { INDEX_op_xor_i32, { "r", "r", "ri" } },
1377
1378 { INDEX_op_shl_i32, { "r", "r", "ri" } },
1379 { INDEX_op_shr_i32, { "r", "r", "ri" } },
1380 { INDEX_op_sar_i32, { "r", "r", "ri" } },
1381
1382 { INDEX_op_brcond_i32, { "r", "ri" } },
1383
1384 { INDEX_op_add2_i32, { "r", "r", "r", "r", "r", "r" } },
1385 { INDEX_op_sub2_i32, { "r", "r", "r", "r", "r", "r" } },
1386 { INDEX_op_brcond2_i32, { "r", "r", "r", "r" } },
1387
1388 { INDEX_op_neg_i32, { "r", "r" } },
1389
1390 #if TARGET_LONG_BITS == 32
1391 { INDEX_op_qemu_ld8u, { "r", "L" } },
1392 { INDEX_op_qemu_ld8s, { "r", "L" } },
1393 { INDEX_op_qemu_ld16u, { "r", "L" } },
1394 { INDEX_op_qemu_ld16s, { "r", "L" } },
1395 { INDEX_op_qemu_ld32u, { "r", "L" } },
1396 { INDEX_op_qemu_ld32s, { "r", "L" } },
1397 { INDEX_op_qemu_ld64, { "r", "r", "L" } },
1398
1399 { INDEX_op_qemu_st8, { "K", "K" } },
1400 { INDEX_op_qemu_st16, { "K", "K" } },
1401 { INDEX_op_qemu_st32, { "K", "K" } },
1402 { INDEX_op_qemu_st64, { "M", "M", "M" } },
1403 #else
1404 { INDEX_op_qemu_ld8u, { "r", "L", "L" } },
1405 { INDEX_op_qemu_ld8s, { "r", "L", "L" } },
1406 { INDEX_op_qemu_ld16u, { "r", "L", "L" } },
1407 { INDEX_op_qemu_ld16s, { "r", "L", "L" } },
1408 { INDEX_op_qemu_ld32u, { "r", "L", "L" } },
1409 { INDEX_op_qemu_ld32s, { "r", "L", "L" } },
1410 { INDEX_op_qemu_ld64, { "r", "L", "L", "L" } },
1411
1412 { INDEX_op_qemu_st8, { "K", "K", "K" } },
1413 { INDEX_op_qemu_st16, { "K", "K", "K" } },
1414 { INDEX_op_qemu_st32, { "K", "K", "K" } },
1415 { INDEX_op_qemu_st64, { "M", "M", "M", "M" } },
1416 #endif
1417
1418 { -1 },
1419 };
1420
1421 void tcg_target_init(TCGContext *s)
1422 {
1423 tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffffffff);
1424 tcg_regset_set32(tcg_target_call_clobber_regs, 0,
1425 (1 << TCG_REG_R0) |
1426 (1 << TCG_REG_R3) |
1427 (1 << TCG_REG_R4) |
1428 (1 << TCG_REG_R5) |
1429 (1 << TCG_REG_R6) |
1430 (1 << TCG_REG_R7) |
1431 (1 << TCG_REG_R8) |
1432 (1 << TCG_REG_R9) |
1433 (1 << TCG_REG_R10) |
1434 (1 << TCG_REG_R11) |
1435 (1 << TCG_REG_R12)
1436 );
1437
1438 tcg_regset_clear(s->reserved_regs);
1439 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R0);
1440 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R1);
1441 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R2);
1442
1443 tcg_add_target_add_op_defs(ppc_op_defs);
1444 }
Patches shipped by Fedora