pc-bios/bios.diff

   1 ? _rombios_.c
   2 ? _rombiosl_.c
   3 ? biossums
   4 ? rombios.s
   5 ? rombios.sym
   6 ? rombios.txt
   7 ? rombios16.bin
   8 ? rombios32.bin
   9 ? rombios32.out
  10 ? rombiosl.s
  11 ? rombiosl.sym
  12 ? rombiosl.txt
  13 Index: BIOS-bochs-latest
  14 ===================================================================
  15 RCS file: /cvsroot/bochs/bochs/bios/BIOS-bochs-latest,v
  16 retrieving revision 1.173
  17 diff -u -d -p -r1.173 BIOS-bochs-latest
  18 Binary files /tmp/cvsItPJ31 and BIOS-bochs-latest differ
  19 Index: BIOS-bochs-legacy
  20 ===================================================================
  21 RCS file: /cvsroot/bochs/bochs/bios/BIOS-bochs-legacy,v
  22 retrieving revision 1.33
  23 diff -u -d -p -r1.33 BIOS-bochs-legacy
  24 Binary files /tmp/cvsMYE2Kz and BIOS-bochs-legacy differ
  25 Index: rombios.c
  26 ===================================================================
  27 RCS file: /cvsroot/bochs/bochs/bios/rombios.c,v
  28 retrieving revision 1.207
  29 diff -u -d -p -r1.207 rombios.c
  30 --- rombios.c   21 Apr 2008 14:22:01 -0000      1.207
  31 +++ rombios.c   28 Apr 2008 07:53:57 -0000
  32 @@ -4404,22 +4404,25 @@ BX_DEBUG_INT15("case default:\n");
  33  #endif // BX_USE_PS2_MOUSE
  34
  35
  36 -void set_e820_range(ES, DI, start, end, type)
  37 +void set_e820_range(ES, DI, start, end, extra_start, extra_end, type)
  38       Bit16u ES;
  39       Bit16u DI;
  40       Bit32u start;
  41       Bit32u end;
  42 +     Bit8u extra_start;
  43 +     Bit8u extra_end;
  44       Bit16u type;
  45  {
  46      write_word(ES, DI, start);
  47      write_word(ES, DI+2, start >> 16);
  48 -    write_word(ES, DI+4, 0x00);
  49 +    write_word(ES, DI+4, extra_start);
  50      write_word(ES, DI+6, 0x00);
  51
  52      end -= start;
  53 +    extra_end -= extra_start;
  54      write_word(ES, DI+8, end);
  55      write_word(ES, DI+10, end >> 16);
  56 -    write_word(ES, DI+12, 0x0000);
  57 +    write_word(ES, DI+12, extra_end);
  58      write_word(ES, DI+14, 0x0000);
  59
  60      write_word(ES, DI+16, type);
  61 @@ -4432,7 +4435,9 @@ int15_function32(regs, ES, DS, FLAGS)
  62    Bit16u ES, DS, FLAGS;
  63  {
  64    Bit32u  extended_memory_size=0; // 64bits long
  65 +  Bit32u  extra_lowbits_memory_size=0;
  66    Bit16u  CX,DX;
  67 +  Bit8u   extra_highbits_memory_size=0;
  68
  69  BX_DEBUG_INT15("int15 AX=%04x\n",regs.u.r16.ax);
  70
  71 @@ -4506,11 +4511,18 @@ ASM_END
  72                      extended_memory_size += (1L * 1024 * 1024);
  73                  }
  74
  75 +                extra_lowbits_memory_size = inb_cmos(0x5c);
  76 +                extra_lowbits_memory_size <<= 8;
  77 +                extra_lowbits_memory_size |= inb_cmos(0x5b);
  78 +                extra_lowbits_memory_size *= 64;
  79 +                extra_lowbits_memory_size *= 1024;
  80 +                extra_highbits_memory_size = inb_cmos(0x5d);
  81 +
  82                  switch(regs.u.r16.bx)
  83                  {
  84                      case 0:
  85                          set_e820_range(ES, regs.u.r16.di,
  86 -                                       0x0000000L, 0x0009fc00L, 1);
  87 +                                       0x0000000L, 0x0009fc00L, 0, 0, 1);
  88                          regs.u.r32.ebx = 1;
  89                          regs.u.r32.eax = 0x534D4150;
  90                          regs.u.r32.ecx = 0x14;
  91 @@ -4519,7 +4531,7 @@ ASM_END
  92                          break;
  93                      case 1:
  94                          set_e820_range(ES, regs.u.r16.di,
  95 -                                       0x0009fc00L, 0x000a0000L, 2);
  96 +                                       0x0009fc00L, 0x000a0000L, 0, 0, 2);
  97                          regs.u.r32.ebx = 2;
  98                          regs.u.r32.eax = 0x534D4150;
  99                          regs.u.r32.ecx = 0x14;
 100 @@ -4528,7 +4540,7 @@ ASM_END
 101                          break;
 102                      case 2:
 103                          set_e820_range(ES, regs.u.r16.di,
 104 -                                       0x000e8000L, 0x00100000L, 2);
 105 +                                       0x000e8000L, 0x00100000L, 0, 0, 2);
 106                          regs.u.r32.ebx = 3;
 107                          regs.u.r32.eax = 0x534D4150;
 108                          regs.u.r32.ecx = 0x14;
 109 @@ -4539,7 +4551,7 @@ ASM_END
 110  #if BX_ROMBIOS32
 111                          set_e820_range(ES, regs.u.r16.di,
 112                                         0x00100000L,
 113 -                                       extended_memory_size - ACPI_DATA_SIZE, 1);
 114 +                                       extended_memory_size - ACPI_DATA_SIZE ,0, 0, 1);
 115                          regs.u.r32.ebx = 4;
 116  #else
 117                          set_e820_range(ES, regs.u.r16.di,
 118 @@ -4555,7 +4567,7 @@ ASM_END
 119                      case 4:
 120                          set_e820_range(ES, regs.u.r16.di,
 121                                         extended_memory_size - ACPI_DATA_SIZE,
 122 -                                       extended_memory_size, 3); // ACPI RAM
 123 +                                       extended_memory_size ,0, 0, 3); // ACPI RAM
 124                          regs.u.r32.ebx = 5;
 125                          regs.u.r32.eax = 0x534D4150;
 126                          regs.u.r32.ecx = 0x14;
 127 @@ -4565,7 +4577,20 @@ ASM_END
 128                      case 5:
 129                          /* 256KB BIOS area at the end of 4 GB */
 130                          set_e820_range(ES, regs.u.r16.di,
 131 -                                       0xfffc0000L, 0x00000000L, 2);
 132 +                                       0xfffc0000L, 0x00000000L ,0, 0, 2);
 133 +                        if (extra_highbits_memory_size || extra_lowbits_memory_size)
 134 +                            regs.u.r32.ebx = 6;
 135 +                        else
 136 +                            regs.u.r32.ebx = 0;
 137 +                        regs.u.r32.eax = 0x534D4150;
 138 +                        regs.u.r32.ecx = 0x14;
 139 +                        CLEAR_CF();
 140 +                        return;
 141 +                    case 6:
 142 +                        /* Maping of memory above 4 GB */
 143 +                        set_e820_range(ES, regs.u.r16.di, 0x00000000L,
 144 +                        extra_lowbits_memory_size, 1, extra_highbits_memory_size
 145 +                                       + 1, 1);
 146                          regs.u.r32.ebx = 0;
 147                          regs.u.r32.eax = 0x534D4150;
 148                          regs.u.r32.ecx = 0x14;
 149 Index: rombios.h
 150 ===================================================================
 151 RCS file: /cvsroot/bochs/bochs/bios/rombios.h,v
 152 retrieving revision 1.6
 153 diff -u -d -p -r1.6 rombios.h
 154 --- rombios.h   26 Jan 2008 09:15:27 -0000      1.6
 155 +++ rombios.h   28 Apr 2008 07:53:57 -0000
 156 @@ -19,7 +19,7 @@
 157  //  Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301 USA
 158
 159  /* define it to include QEMU specific code */
 160 -//#define BX_QEMU
 161 +#define BX_QEMU
 162
 163  #ifndef LEGACY
 164  #  define BX_ROMBIOS32     1
 165 Index: rombios32.c
 166 ===================================================================
 167 RCS file: /cvsroot/bochs/bochs/bios/rombios32.c,v
 168 retrieving revision 1.26
 169 diff -u -d -p -r1.26 rombios32.c
 170 --- rombios32.c 8 Apr 2008 16:41:18 -0000       1.26
 171 +++ rombios32.c 28 Apr 2008 07:53:58 -0000
 172 @@ -478,7 +478,12 @@ void smp_probe(void)
 173          sipi_vector = AP_BOOT_ADDR >> 12;
 174          writel(APIC_BASE + APIC_ICR_LOW, 0x000C4600 | sipi_vector);
 175
 176 +#ifndef BX_QEMU
 177          delay_ms(10);
 178 +#else
 179 +       while (cmos_readb(0x5f) + 1 != readw((void *)CPU_COUNT_ADDR))
 180 +               ;
 181 +#endif
 182
 183          smp_cpus = readw((void *)CPU_COUNT_ADDR);
 184      }
 185 @@ -1423,9 +1428,8 @@ void acpi_bios_init(void)
 186      fadt->pm1_evt_len = 4;
 187      fadt->pm1_cnt_len = 2;
 188      fadt->pm_tmr_len = 4;
 189 -    fadt->plvl2_lat = cpu_to_le16(50);
 190 -    fadt->plvl3_lat = cpu_to_le16(50);
 191 -    fadt->plvl3_lat = cpu_to_le16(50);
 192 +    fadt->plvl2_lat = cpu_to_le16(0x0fff); // C2 state not supported
 193 +    fadt->plvl3_lat = cpu_to_le16(0x0fff); // C3 state not supported
 194      /* WBINVD + PROC_C1 + PWR_BUTTON + SLP_BUTTON + FIX_RTC */
 195      fadt->flags = cpu_to_le32((1 << 0) | (1 << 2) | (1 << 4) | (1 << 5) | (1 << 6));
 196      acpi_build_table_header((struct acpi_table_header *)fadt, "FACP",