hw/sun4u.c

   1 /*
   2  * QEMU Sun4u/Sun4v System Emulator
   3  *
   4  * Copyright (c) 2005 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "pci.h"
  26 #include "pc.h"
  27 #include "nvram.h"
  28 #include "fdc.h"
  29 #include "net.h"
  30 #include "qemu-timer.h"
  31 #include "sysemu.h"
  32 #include "boards.h"
  33 #include "firmware_abi.h"
  34
  35 #define KERNEL_LOAD_ADDR     0x00404000
  36 #define CMDLINE_ADDR         0x003ff000
  37 #define INITRD_LOAD_ADDR     0x00300000
  38 #define PROM_SIZE_MAX        (4 * 1024 * 1024)
  39 #define PROM_ADDR            0x1fff0000000ULL
  40 #define PROM_VADDR           0x000ffd00000ULL
  41 #define APB_SPECIAL_BASE     0x1fe00000000ULL
  42 #define APB_MEM_BASE         0x1ff00000000ULL
  43 #define VGA_BASE             (APB_MEM_BASE + 0x400000ULL)
  44 #define PROM_FILENAME        "openbios-sparc64"
  45 #define NVRAM_SIZE           0x2000
  46 #define MAX_IDE_BUS          2
  47
  48 struct hwdef {
  49     const char * const default_cpu_model;
  50 };
  51
  52 int DMA_get_channel_mode (int nchan)
  53 {
  54     return 0;
  55 }
  56 int DMA_read_memory (int nchan, void *buf, int pos, int size)
  57 {
  58     return 0;
  59 }
  60 int DMA_write_memory (int nchan, void *buf, int pos, int size)
  61 {
  62     return 0;
  63 }
  64 void DMA_hold_DREQ (int nchan) {}
  65 void DMA_release_DREQ (int nchan) {}
  66 void DMA_schedule(int nchan) {}
  67 void DMA_run (void) {}
  68 void DMA_init (int high_page_enable) {}
  69 void DMA_register_channel (int nchan,
  70                            DMA_transfer_handler transfer_handler,
  71                            void *opaque)
  72 {
  73 }
  74
  75 static int nvram_boot_set(void *opaque, const char *boot_device)
  76 {
  77     unsigned int i;
  78     uint8_t image[sizeof(ohwcfg_v3_t)];
  79     ohwcfg_v3_t *header = (ohwcfg_v3_t *)&image;
  80     m48t59_t *nvram = (m48t59_t *)opaque;
  81
  82     for (i = 0; i < sizeof(image); i++)
  83         image[i] = m48t59_read(nvram, i) & 0xff;
  84
  85     pstrcpy((char *)header->boot_devices, sizeof(header->boot_devices),
  86             boot_device);
  87     header->nboot_devices = strlen(boot_device) & 0xff;
  88     header->crc = cpu_to_be16(OHW_compute_crc(header, 0x00, 0xF8));
  89
  90     for (i = 0; i < sizeof(image); i++)
  91         m48t59_write(nvram, i, image[i]);
  92
  93     return 0;
  94 }
  95
  96 extern int nographic;
  97
  98 static int sun4u_NVRAM_set_params (m48t59_t *nvram, uint16_t NVRAM_size,
  99                                    const char *arch,
 100                                    ram_addr_t RAM_size,
 101                                    const char *boot_devices,
 102                                    uint32_t kernel_image, uint32_t kernel_size,
 103                                    const char *cmdline,
 104                                    uint32_t initrd_image, uint32_t initrd_size,
 105                                    uint32_t NVRAM_image,
 106                                    int width, int height, int depth,
 107                                    const uint8_t *macaddr)
 108 {
 109     unsigned int i;
 110     uint32_t start, end;
 111     uint8_t image[0x1ff0];
 112     ohwcfg_v3_t *header = (ohwcfg_v3_t *)&image;
 113     struct sparc_arch_cfg *sparc_header;
 114     struct OpenBIOS_nvpart_v1 *part_header;
 115
 116     memset(image, '\0', sizeof(image));
 117
 118     // Try to match PPC NVRAM
 119     pstrcpy((char *)header->struct_ident, sizeof(header->struct_ident),
 120             "QEMU_BIOS");
 121     header->struct_version = cpu_to_be32(3); /* structure v3 */
 122
 123     header->nvram_size = cpu_to_be16(NVRAM_size);
 124     header->nvram_arch_ptr = cpu_to_be16(sizeof(ohwcfg_v3_t));
 125     header->nvram_arch_size = cpu_to_be16(sizeof(struct sparc_arch_cfg));
 126     pstrcpy((char *)header->arch, sizeof(header->arch), arch);
 127     header->nb_cpus = smp_cpus & 0xff;
 128     header->RAM0_base = 0;
 129     header->RAM0_size = cpu_to_be64((uint64_t)RAM_size);
 130     pstrcpy((char *)header->boot_devices, sizeof(header->boot_devices),
 131             boot_devices);
 132     header->nboot_devices = strlen(boot_devices) & 0xff;
 133     header->kernel_image = cpu_to_be64((uint64_t)kernel_image);
 134     header->kernel_size = cpu_to_be64((uint64_t)kernel_size);
 135     if (cmdline) {
 136         pstrcpy_targphys(CMDLINE_ADDR, TARGET_PAGE_SIZE, cmdline);
 137         header->cmdline = cpu_to_be64((uint64_t)CMDLINE_ADDR);
 138         header->cmdline_size = cpu_to_be64((uint64_t)strlen(cmdline));
 139     }
 140     header->initrd_image = cpu_to_be64((uint64_t)initrd_image);
 141     header->initrd_size = cpu_to_be64((uint64_t)initrd_size);
 142     header->NVRAM_image = cpu_to_be64((uint64_t)NVRAM_image);
 143
 144     header->width = cpu_to_be16(width);
 145     header->height = cpu_to_be16(height);
 146     header->depth = cpu_to_be16(depth);
 147     if (nographic)
 148         header->graphic_flags = cpu_to_be16(OHW_GF_NOGRAPHICS);
 149
 150     header->crc = cpu_to_be16(OHW_compute_crc(header, 0x00, 0xF8));
 151
 152     // Architecture specific header
 153     start = sizeof(ohwcfg_v3_t);
 154     sparc_header = (struct sparc_arch_cfg *)&image[start];
 155     sparc_header->valid = 0;
 156     start += sizeof(struct sparc_arch_cfg);
 157
 158     // OpenBIOS nvram variables
 159     // Variable partition
 160     part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
 161     part_header->signature = OPENBIOS_PART_SYSTEM;
 162     pstrcpy(part_header->name, sizeof(part_header->name), "system");
 163
 164     end = start + sizeof(struct OpenBIOS_nvpart_v1);
 165     for (i = 0; i < nb_prom_envs; i++)
 166         end = OpenBIOS_set_var(image, end, prom_envs[i]);
 167
 168     // End marker
 169     image[end++] = '\0';
 170
 171     end = start + ((end - start + 15) & ~15);
 172     OpenBIOS_finish_partition(part_header, end - start);
 173
 174     // free partition
 175     start = end;
 176     part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
 177     part_header->signature = OPENBIOS_PART_FREE;
 178     pstrcpy(part_header->name, sizeof(part_header->name), "free");
 179
 180     end = 0x1fd0;
 181     OpenBIOS_finish_partition(part_header, end - start);
 182
 183     Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, 0x80);
 184
 185     for (i = 0; i < sizeof(image); i++)
 186         m48t59_write(nvram, i, image[i]);
 187
 188     qemu_register_boot_set(nvram_boot_set, nvram);
 189
 190     return 0;
 191 }
 192
 193 void pic_info(void)
 194 {
 195 }
 196
 197 void irq_info(void)
 198 {
 199 }
 200
 201 void qemu_system_powerdown(void)
 202 {
 203 }
 204
 205 static void main_cpu_reset(void *opaque)
 206 {
 207     CPUState *env = opaque;
 208
 209     cpu_reset(env);
 210     ptimer_set_limit(env->tick, 0x7fffffffffffffffULL, 1);
 211     ptimer_run(env->tick, 0);
 212     ptimer_set_limit(env->stick, 0x7fffffffffffffffULL, 1);
 213     ptimer_run(env->stick, 0);
 214     ptimer_set_limit(env->hstick, 0x7fffffffffffffffULL, 1);
 215     ptimer_run(env->hstick, 0);
 216 }
 217
 218 static void tick_irq(void *opaque)
 219 {
 220     CPUState *env = opaque;
 221
 222     cpu_interrupt(env, CPU_INTERRUPT_TIMER);
 223 }
 224
 225 static void stick_irq(void *opaque)
 226 {
 227     CPUState *env = opaque;
 228
 229     cpu_interrupt(env, CPU_INTERRUPT_TIMER);
 230 }
 231
 232 static void hstick_irq(void *opaque)
 233 {
 234     CPUState *env = opaque;
 235
 236     cpu_interrupt(env, CPU_INTERRUPT_TIMER);
 237 }
 238
 239 static void dummy_cpu_set_irq(void *opaque, int irq, int level)
 240 {
 241 }
 242
 243 static const int ide_iobase[2] = { 0x1f0, 0x170 };
 244 static const int ide_iobase2[2] = { 0x3f6, 0x376 };
 245 static const int ide_irq[2] = { 14, 15 };
 246
 247 static const int serial_io[MAX_SERIAL_PORTS] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 };
 248 static const int serial_irq[MAX_SERIAL_PORTS] = { 4, 3, 4, 3 };
 249
 250 static const int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc };
 251 static const int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 };
 252
 253 static fdctrl_t *floppy_controller;
 254
 255 static void sun4uv_init(ram_addr_t RAM_size, int vga_ram_size,
 256                         const char *boot_devices, DisplayState *ds,
 257                         const char *kernel_filename, const char *kernel_cmdline,
 258                         const char *initrd_filename, const char *cpu_model,
 259                         const struct hwdef *hwdef)
 260 {
 261     CPUState *env;
 262     char buf[1024];
 263     m48t59_t *nvram;
 264     int ret, linux_boot;
 265     unsigned int i;
 266     long prom_offset, initrd_size, kernel_size;
 267     PCIBus *pci_bus;
 268     QEMUBH *bh;
 269     qemu_irq *irq;
 270     int drive_index;
 271     BlockDriverState *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
 272     BlockDriverState *fd[MAX_FD];
 273
 274     linux_boot = (kernel_filename != NULL);
 275
 276     /* init CPUs */
 277     if (!cpu_model)
 278         cpu_model = hwdef->default_cpu_model;
 279
 280     env = cpu_init(cpu_model);
 281     if (!env) {
 282         fprintf(stderr, "Unable to find Sparc CPU definition\n");
 283         exit(1);
 284     }
 285     bh = qemu_bh_new(tick_irq, env);
 286     env->tick = ptimer_init(bh);
 287     ptimer_set_period(env->tick, 1ULL);
 288
 289     bh = qemu_bh_new(stick_irq, env);
 290     env->stick = ptimer_init(bh);
 291     ptimer_set_period(env->stick, 1ULL);
 292
 293     bh = qemu_bh_new(hstick_irq, env);
 294     env->hstick = ptimer_init(bh);
 295     ptimer_set_period(env->hstick, 1ULL);
 296     qemu_register_reset(main_cpu_reset, env);
 297     main_cpu_reset(env);
 298
 299     /* allocate RAM */
 300     cpu_register_physical_memory(0, RAM_size, 0);
 301
 302     prom_offset = RAM_size + vga_ram_size;
 303     cpu_register_physical_memory(PROM_ADDR,
 304                                  (PROM_SIZE_MAX + TARGET_PAGE_SIZE) &
 305                                  TARGET_PAGE_MASK,
 306                                  prom_offset | IO_MEM_ROM);
 307
 308     if (bios_name == NULL)
 309         bios_name = PROM_FILENAME;
 310     snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
 311     ret = load_elf(buf, PROM_ADDR - PROM_VADDR, NULL, NULL, NULL);
 312     if (ret < 0) {
 313         fprintf(stderr, "qemu: could not load prom '%s'\n",
 314                 buf);
 315         exit(1);
 316     }
 317
 318     kernel_size = 0;
 319     initrd_size = 0;
 320     if (linux_boot) {
 321         /* XXX: put correct offset */
 322         kernel_size = load_elf(kernel_filename, 0, NULL, NULL, NULL);
 323         if (kernel_size < 0)
 324             kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR,
 325                                     ram_size - KERNEL_LOAD_ADDR);
 326         if (kernel_size < 0)
 327             kernel_size = load_image_targphys(kernel_filename,
 328                                               KERNEL_LOAD_ADDR,
 329                                               ram_size - KERNEL_LOAD_ADDR);
 330         if (kernel_size < 0) {
 331             fprintf(stderr, "qemu: could not load kernel '%s'\n",
 332                     kernel_filename);
 333             exit(1);
 334         }
 335
 336         /* load initrd */
 337         if (initrd_filename) {
 338             initrd_size = load_image_targphys(initrd_filename,
 339                                               INITRD_LOAD_ADDR,
 340                                               ram_size - INITRD_LOAD_ADDR);
 341             if (initrd_size < 0) {
 342                 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
 343                         initrd_filename);
 344                 exit(1);
 345             }
 346         }
 347         if (initrd_size > 0) {
 348             for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
 349                 if (ldl_phys(KERNEL_LOAD_ADDR + i) == 0x48647253) { // HdrS
 350                     stl_phys(KERNEL_LOAD_ADDR + i + 16, INITRD_LOAD_ADDR);
 351                     stl_phys(KERNEL_LOAD_ADDR + i + 20, initrd_size);
 352                     break;
 353                 }
 354             }
 355         }
 356     }
 357     pci_bus = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE, NULL);
 358     isa_mem_base = VGA_BASE;
 359     pci_cirrus_vga_init(pci_bus, ds, phys_ram_base + RAM_size, RAM_size,
 360                         vga_ram_size);
 361
 362     for(i = 0; i < MAX_SERIAL_PORTS; i++) {
 363         if (serial_hds[i]) {
 364             serial_init(serial_io[i], NULL/*serial_irq[i]*/, 115200,
 365                         serial_hds[i]);
 366         }
 367     }
 368
 369     for(i = 0; i < MAX_PARALLEL_PORTS; i++) {
 370         if (parallel_hds[i]) {
 371             parallel_init(parallel_io[i], NULL/*parallel_irq[i]*/,
 372                           parallel_hds[i]);
 373         }
 374     }
 375
 376     for(i = 0; i < nb_nics; i++) {
 377         if (!nd_table[i].model)
 378             nd_table[i].model = "ne2k_pci";
 379         if (!pci_nic_init(pci_bus, &nd_table[i], -1))
 380             exit(1);
 381     }
 382
 383     irq = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, 32);
 384     if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) {
 385         fprintf(stderr, "qemu: too many IDE bus\n");
 386         exit(1);
 387     }
 388     for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) {
 389         drive_index = drive_get_index(IF_IDE, i / MAX_IDE_DEVS,
 390                                       i % MAX_IDE_DEVS);
 391        if (drive_index != -1)
 392            hd[i] = drives_table[drive_index].bdrv;
 393        else
 394            hd[i] = NULL;
 395     }
 396
 397     // XXX pci_cmd646_ide_init(pci_bus, hd, 1);
 398     pci_piix3_ide_init(pci_bus, hd, -1, irq);
 399     /* FIXME: wire up interrupts.  */
 400     i8042_init(NULL/*1*/, NULL/*12*/, 0x60);
 401     for(i = 0; i < MAX_FD; i++) {
 402         drive_index = drive_get_index(IF_FLOPPY, 0, i);
 403        if (drive_index != -1)
 404            fd[i] = drives_table[drive_index].bdrv;
 405        else
 406            fd[i] = NULL;
 407     }
 408     floppy_controller = fdctrl_init(NULL/*6*/, 2, 0, 0x3f0, fd);
 409     nvram = m48t59_init(NULL/*8*/, 0, 0x0074, NVRAM_SIZE, 59);
 410     sun4u_NVRAM_set_params(nvram, NVRAM_SIZE, "Sun4u", RAM_size, boot_devices,
 411                            KERNEL_LOAD_ADDR, kernel_size,
 412                            kernel_cmdline,
 413                            INITRD_LOAD_ADDR, initrd_size,
 414                            /* XXX: need an option to load a NVRAM image */
 415                            0,
 416                            graphic_width, graphic_height, graphic_depth,
 417                            (uint8_t *)&nd_table[0].macaddr);
 418
 419 }
 420
 421 static const struct hwdef hwdefs[] = {
 422     /* Sun4u generic PC-like machine */
 423     {
 424         .default_cpu_model = "TI UltraSparc II",
 425     },
 426     /* Sun4v generic PC-like machine */
 427     {
 428         .default_cpu_model = "Sun UltraSparc T1",
 429     },
 430 };
 431
 432 /* Sun4u hardware initialisation */
 433 static void sun4u_init(ram_addr_t RAM_size, int vga_ram_size,
 434                        const char *boot_devices, DisplayState *ds,
 435                        const char *kernel_filename, const char *kernel_cmdline,
 436                        const char *initrd_filename, const char *cpu_model)
 437 {
 438     sun4uv_init(RAM_size, vga_ram_size, boot_devices, ds, kernel_filename,
 439                 kernel_cmdline, initrd_filename, cpu_model, &hwdefs[0]);
 440 }
 441
 442 /* Sun4v hardware initialisation */
 443 static void sun4v_init(ram_addr_t RAM_size, int vga_ram_size,
 444                        const char *boot_devices, DisplayState *ds,
 445                        const char *kernel_filename, const char *kernel_cmdline,
 446                        const char *initrd_filename, const char *cpu_model)
 447 {
 448     sun4uv_init(RAM_size, vga_ram_size, boot_devices, ds, kernel_filename,
 449                 kernel_cmdline, initrd_filename, cpu_model, &hwdefs[1]);
 450 }
 451
 452 QEMUMachine sun4u_machine = {
 453     .name = "sun4u",
 454     .desc = "Sun4u platform",
 455     .init = sun4u_init,
 456     .ram_require = PROM_SIZE_MAX + VGA_RAM_SIZE,
 457     .nodisk_ok = 1,
 458 };
 459
 460 QEMUMachine sun4v_machine = {
 461     .name = "sun4v",
 462     .desc = "Sun4v platform",
 463     .init = sun4v_init,
 464     .ram_require = PROM_SIZE_MAX + VGA_RAM_SIZE,
 465     .nodisk_ok = 1,
 466 };