hw/pci.c

   1 /*
   2  * QEMU PCI bus manager
   3  *
   4  * Copyright (c) 2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "pci.h"
  26 #include "console.h"
  27 #include "net.h"
  28 #include "pc.h"
  29 #include "qemu-kvm.h"
  30
  31 //#define DEBUG_PCI
  32
  33 struct PCIBus {
  34     int bus_num;
  35     int devfn_min;
  36     pci_set_irq_fn set_irq;
  37     pci_map_irq_fn map_irq;
  38     uint32_t config_reg; /* XXX: suppress */
  39     /* low level pic */
  40     SetIRQFunc *low_set_irq;
  41     qemu_irq *irq_opaque;
  42     PCIDevice *devices[256];
  43     PCIDevice *parent_dev;
  44     PCIBus *next;
  45     /* The bus IRQ state is the logical OR of the connected devices.
  46        Keep a count of the number of devices with raised IRQs.  */
  47     int nirq;
  48     int irq_count[];
  49 };
  50
  51 static void pci_update_mappings(PCIDevice *d);
  52 static void pci_set_irq(void *opaque, int irq_num, int level);
  53
  54 target_phys_addr_t pci_mem_base;
  55 static int pci_irq_index;
  56 static PCIBus *first_bus;
  57
  58 static void pcibus_save(QEMUFile *f, void *opaque)
  59 {
  60     PCIBus *bus = (PCIBus *)opaque;
  61     int i;
  62
  63     qemu_put_be32(f, bus->nirq);
  64     for (i = 0; i < bus->nirq; i++)
  65         qemu_put_be32(f, bus->irq_count[i]);
  66 }
  67
  68 static int  pcibus_load(QEMUFile *f, void *opaque, int version_id)
  69 {
  70     PCIBus *bus = (PCIBus *)opaque;
  71     int i, nirq;
  72
  73     if (version_id != 1)
  74         return -EINVAL;
  75
  76     nirq = qemu_get_be32(f);
  77     if (bus->nirq != nirq) {
  78         fprintf(stderr, "pcibus_load: nirq mismatch: src=%d dst=%d\n",
  79                 nirq, bus->nirq);
  80         return -EINVAL;
  81     }
  82
  83     for (i = 0; i < nirq; i++)
  84         bus->irq_count[i] = qemu_get_be32(f);
  85
  86     return 0;
  87 }
  88
  89 PCIBus *pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
  90                          qemu_irq *pic, int devfn_min, int nirq)
  91 {
  92     PCIBus *bus;
  93     static int nbus = 0;
  94
  95     bus = qemu_mallocz(sizeof(PCIBus) + (nirq * sizeof(int)));
  96     bus->set_irq = set_irq;
  97     bus->map_irq = map_irq;
  98     bus->irq_opaque = pic;
  99     bus->devfn_min = devfn_min;
 100     bus->nirq = nirq;
 101     first_bus = bus;
 102     register_savevm("PCIBUS", nbus++, 1, pcibus_save, pcibus_load, bus);
 103     return bus;
 104 }
 105
 106 static PCIBus *pci_register_secondary_bus(PCIDevice *dev, pci_map_irq_fn map_irq)
 107 {
 108     PCIBus *bus;
 109     bus = qemu_mallocz(sizeof(PCIBus));
 110     bus->map_irq = map_irq;
 111     bus->parent_dev = dev;
 112     bus->next = dev->bus->next;
 113     dev->bus->next = bus;
 114     return bus;
 115 }
 116
 117 int pci_bus_num(PCIBus *s)
 118 {
 119     return s->bus_num;
 120 }
 121
 122 void pci_device_save(PCIDevice *s, QEMUFile *f)
 123 {
 124     int i;
 125
 126     qemu_put_be32(f, 2); /* PCI device version */
 127     qemu_put_buffer(f, s->config, 256);
 128     for (i = 0; i < 4; i++)
 129         qemu_put_be32(f, s->irq_state[i]);
 130 }
 131
 132 int pci_device_load(PCIDevice *s, QEMUFile *f)
 133 {
 134     uint32_t version_id;
 135     int i;
 136
 137     version_id = qemu_get_be32(f);
 138     if (version_id > 2)
 139         return -EINVAL;
 140     qemu_get_buffer(f, s->config, 256);
 141     pci_update_mappings(s);
 142
 143     if (version_id >= 2)
 144         for (i = 0; i < 4; i ++)
 145             s->irq_state[i] = qemu_get_be32(f);
 146
 147     return 0;
 148 }
 149
 150 /* -1 for devfn means auto assign */
 151 PCIDevice *pci_register_device(PCIBus *bus, const char *name,
 152                                int instance_size, int devfn,
 153                                PCIConfigReadFunc *config_read,
 154                                PCIConfigWriteFunc *config_write)
 155 {
 156     PCIDevice *pci_dev;
 157
 158     if (pci_irq_index >= PCI_DEVICES_MAX)
 159         return NULL;
 160
 161     if (devfn < 0) {
 162         for(devfn = bus->devfn_min ; devfn < 256; devfn += 8) {
 163             if (!bus->devices[devfn])
 164                 goto found;
 165         }
 166         return NULL;
 167     found: ;
 168     }
 169     pci_dev = qemu_mallocz(instance_size);
 170     if (!pci_dev)
 171         return NULL;
 172     pci_dev->bus = bus;
 173     pci_dev->devfn = devfn;
 174     pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);
 175     memset(pci_dev->irq_state, 0, sizeof(pci_dev->irq_state));
 176
 177     if (!config_read)
 178         config_read = pci_default_read_config;
 179     if (!config_write)
 180         config_write = pci_default_write_config;
 181     pci_dev->config_read = config_read;
 182     pci_dev->config_write = config_write;
 183     pci_dev->irq_index = pci_irq_index++;
 184     bus->devices[devfn] = pci_dev;
 185     pci_dev->irq = qemu_allocate_irqs(pci_set_irq, pci_dev, 4);
 186     return pci_dev;
 187 }
 188
 189 static target_phys_addr_t pci_to_cpu_addr(target_phys_addr_t addr)
 190 {
 191     return addr + pci_mem_base;
 192 }
 193
 194 static void pci_unregister_io_regions(PCIDevice *pci_dev)
 195 {
 196     PCIIORegion *r;
 197     int i;
 198
 199     for(i = 0; i < PCI_NUM_REGIONS; i++) {
 200         r = &pci_dev->io_regions[i];
 201         if (!r->size)
 202             continue;
 203         if (r->type == PCI_ADDRESS_SPACE_IO) {
 204             isa_unassign_ioport(r->addr, r->size);
 205         } else {
 206             cpu_register_physical_memory(pci_to_cpu_addr(r->addr),
 207                                                      r->size,
 208                                                      IO_MEM_UNASSIGNED);
 209         }
 210     }
 211 }
 212
 213 int pci_unregister_device(PCIDevice *pci_dev)
 214 {
 215     int ret = 0;
 216
 217     if (pci_dev->unregister)
 218         ret = pci_dev->unregister(pci_dev);
 219     if (ret)
 220         return ret;
 221
 222     pci_unregister_io_regions(pci_dev);
 223
 224     qemu_free_irqs(pci_dev->irq);
 225     pci_irq_index--;
 226     pci_dev->bus->devices[pci_dev->devfn] = NULL;
 227     qemu_free(pci_dev);
 228     return 0;
 229 }
 230
 231 void pci_register_io_region(PCIDevice *pci_dev, int region_num,
 232                             uint32_t size, int type,
 233                             PCIMapIORegionFunc *map_func)
 234 {
 235     PCIIORegion *r;
 236     uint32_t addr;
 237
 238     if ((unsigned int)region_num >= PCI_NUM_REGIONS)
 239         return;
 240
 241     if (size & (size-1))
 242         term_printf("WARNING: PCI region size must be pow2 "
 243                     "type=0x%x, size=0x%x\n", type, size);
 244
 245     r = &pci_dev->io_regions[region_num];
 246     r->addr = -1;
 247     r->size = size;
 248     r->type = type;
 249     r->map_func = map_func;
 250     if (region_num == PCI_ROM_SLOT) {
 251         addr = 0x30;
 252     } else {
 253         addr = 0x10 + region_num * 4;
 254     }
 255     *(uint32_t *)(pci_dev->config + addr) = cpu_to_le32(type);
 256 }
 257
 258
 259 static void pci_update_mappings(PCIDevice *d)
 260 {
 261     PCIIORegion *r;
 262     int cmd, i;
 263     uint32_t last_addr, new_addr, config_ofs;
 264
 265     cmd = le16_to_cpu(*(uint16_t *)(d->config + PCI_COMMAND));
 266     for(i = 0; i < PCI_NUM_REGIONS; i++) {
 267         r = &d->io_regions[i];
 268         if (i == PCI_ROM_SLOT) {
 269             config_ofs = 0x30;
 270         } else {
 271             config_ofs = 0x10 + i * 4;
 272         }
 273         if (r->size != 0) {
 274             if (r->type & PCI_ADDRESS_SPACE_IO) {
 275                 if (cmd & PCI_COMMAND_IO) {
 276                     new_addr = le32_to_cpu(*(uint32_t *)(d->config +
 277                                                          config_ofs));
 278                     new_addr = new_addr & ~(r->size - 1);
 279                     last_addr = new_addr + r->size - 1;
 280                     /* NOTE: we have only 64K ioports on PC */
 281                     if (last_addr <= new_addr || new_addr == 0 ||
 282                         last_addr >= 0x10000) {
 283                         new_addr = -1;
 284                     }
 285                 } else {
 286                     new_addr = -1;
 287                 }
 288             } else {
 289                 if (cmd & PCI_COMMAND_MEMORY) {
 290                     new_addr = le32_to_cpu(*(uint32_t *)(d->config +
 291                                                          config_ofs));
 292                     /* the ROM slot has a specific enable bit */
 293                     if (i == PCI_ROM_SLOT && !(new_addr & 1))
 294                         goto no_mem_map;
 295                     new_addr = new_addr & ~(r->size - 1);
 296                     last_addr = new_addr + r->size - 1;
 297                     /* NOTE: we do not support wrapping */
 298                     /* XXX: as we cannot support really dynamic
 299                        mappings, we handle specific values as invalid
 300                        mappings. */
 301                     if (last_addr <= new_addr || new_addr == 0 ||
 302                         last_addr == -1) {
 303                         new_addr = -1;
 304                     }
 305                 } else {
 306                 no_mem_map:
 307                     new_addr = -1;
 308                 }
 309             }
 310             /* now do the real mapping */
 311             if (new_addr != r->addr) {
 312                 if (r->addr != -1) {
 313                     if (r->type & PCI_ADDRESS_SPACE_IO) {
 314                         int class;
 315                         /* NOTE: specific hack for IDE in PC case:
 316                            only one byte must be mapped. */
 317                         class = d->config[0x0a] | (d->config[0x0b] << 8);
 318                         if (class == 0x0101 && r->size == 4) {
 319                             isa_unassign_ioport(r->addr + 2, 1);
 320                         } else {
 321                             isa_unassign_ioport(r->addr, r->size);
 322                         }
 323                     } else {
 324                         cpu_register_physical_memory(pci_to_cpu_addr(r->addr),
 325                                                      r->size,
 326                                                      IO_MEM_UNASSIGNED);
 327                         if (kvm_enabled())
 328                                 qemu_kvm_unregister_coalesced_mmio(r->addr,
 329                                                                  r->size);
 330                     }
 331                 }
 332                 r->addr = new_addr;
 333                 if (r->addr != -1) {
 334                     r->map_func(d, i, r->addr, r->size, r->type);
 335                 }
 336             }
 337         }
 338     }
 339 }
 340
 341 uint32_t pci_default_read_config(PCIDevice *d,
 342                                  uint32_t address, int len)
 343 {
 344     uint32_t val;
 345
 346     switch(len) {
 347     default:
 348     case 4:
 349         if (address <= 0xfc) {
 350             val = le32_to_cpu(*(uint32_t *)(d->config + address));
 351             break;
 352         }
 353         /* fall through */
 354     case 2:
 355         if (address <= 0xfe) {
 356             val = le16_to_cpu(*(uint16_t *)(d->config + address));
 357             break;
 358         }
 359         /* fall through */
 360     case 1:
 361         val = d->config[address];
 362         break;
 363     }
 364     return val;
 365 }
 366
 367 void pci_default_write_config(PCIDevice *d,
 368                               uint32_t address, uint32_t val, int len)
 369 {
 370     int can_write, i;
 371     uint32_t end, addr;
 372
 373     if (len == 4 && ((address >= 0x10 && address < 0x10 + 4 * 6) ||
 374                      (address >= 0x30 && address < 0x34))) {
 375         PCIIORegion *r;
 376         int reg;
 377
 378         if ( address >= 0x30 ) {
 379             reg = PCI_ROM_SLOT;
 380         }else{
 381             reg = (address - 0x10) >> 2;
 382         }
 383         r = &d->io_regions[reg];
 384         if (r->size == 0)
 385             goto default_config;
 386         /* compute the stored value */
 387         if (reg == PCI_ROM_SLOT) {
 388             /* keep ROM enable bit */
 389             val &= (~(r->size - 1)) | 1;
 390         } else {
 391             val &= ~(r->size - 1);
 392             val |= r->type;
 393         }
 394         *(uint32_t *)(d->config + address) = cpu_to_le32(val);
 395         pci_update_mappings(d);
 396         return;
 397     }
 398  default_config:
 399     /* not efficient, but simple */
 400     addr = address;
 401     for(i = 0; i < len; i++) {
 402         /* default read/write accesses */
 403         switch(d->config[0x0e]) {
 404         case 0x00:
 405         case 0x80:
 406             switch(addr) {
 407             case 0x00:
 408             case 0x01:
 409             case 0x02:
 410             case 0x03:
 411             case 0x08:
 412             case 0x09:
 413             case 0x0a:
 414             case 0x0b:
 415             case 0x0e:
 416             case 0x10 ... 0x27: /* base */
 417             case 0x30 ... 0x33: /* rom */
 418             case 0x3d:
 419                 can_write = 0;
 420                 break;
 421             default:
 422                 can_write = 1;
 423                 break;
 424             }
 425             break;
 426         default:
 427         case 0x01:
 428             switch(addr) {
 429             case 0x00:
 430             case 0x01:
 431             case 0x02:
 432             case 0x03:
 433             case 0x08:
 434             case 0x09:
 435             case 0x0a:
 436             case 0x0b:
 437             case 0x0e:
 438             case 0x38 ... 0x3b: /* rom */
 439             case 0x3d:
 440                 can_write = 0;
 441                 break;
 442             default:
 443                 can_write = 1;
 444                 break;
 445             }
 446             break;
 447         }
 448         if (can_write) {
 449             d->config[addr] = val;
 450         }
 451         if (++addr > 0xff)
 452                 break;
 453         val >>= 8;
 454     }
 455
 456     end = address + len;
 457     if (end > PCI_COMMAND && address < (PCI_COMMAND + 2)) {
 458         /* if the command register is modified, we must modify the mappings */
 459         pci_update_mappings(d);
 460     }
 461 }
 462
 463 void pci_data_write(void *opaque, uint32_t addr, uint32_t val, int len)
 464 {
 465     PCIBus *s = opaque;
 466     PCIDevice *pci_dev;
 467     int config_addr, bus_num;
 468
 469 #if defined(DEBUG_PCI) && 0
 470     printf("pci_data_write: addr=%08x val=%08x len=%d\n",
 471            addr, val, len);
 472 #endif
 473     bus_num = (addr >> 16) & 0xff;
 474     while (s && s->bus_num != bus_num)
 475         s = s->next;
 476     if (!s)
 477         return;
 478     pci_dev = s->devices[(addr >> 8) & 0xff];
 479     if (!pci_dev)
 480         return;
 481     config_addr = addr & 0xff;
 482 #if defined(DEBUG_PCI)
 483     printf("pci_config_write: %s: addr=%02x val=%08x len=%d\n",
 484            pci_dev->name, config_addr, val, len);
 485 #endif
 486     pci_dev->config_write(pci_dev, config_addr, val, len);
 487 }
 488
 489 uint32_t pci_data_read(void *opaque, uint32_t addr, int len)
 490 {
 491     PCIBus *s = opaque;
 492     PCIDevice *pci_dev;
 493     int config_addr, bus_num;
 494     uint32_t val;
 495
 496     bus_num = (addr >> 16) & 0xff;
 497     while (s && s->bus_num != bus_num)
 498         s= s->next;
 499     if (!s)
 500         goto fail;
 501     pci_dev = s->devices[(addr >> 8) & 0xff];
 502     if (!pci_dev) {
 503     fail:
 504         switch(len) {
 505         case 1:
 506             val = 0xff;
 507             break;
 508         case 2:
 509             val = 0xffff;
 510             break;
 511         default:
 512         case 4:
 513             val = 0xffffffff;
 514             break;
 515         }
 516         goto the_end;
 517     }
 518     config_addr = addr & 0xff;
 519     val = pci_dev->config_read(pci_dev, config_addr, len);
 520 #if defined(DEBUG_PCI)
 521     printf("pci_config_read: %s: addr=%02x val=%08x len=%d\n",
 522            pci_dev->name, config_addr, val, len);
 523 #endif
 524  the_end:
 525 #if defined(DEBUG_PCI) && 0
 526     printf("pci_data_read: addr=%08x val=%08x len=%d\n",
 527            addr, val, len);
 528 #endif
 529     return val;
 530 }
 531
 532 /***********************************************************/
 533 /* generic PCI irq support */
 534
 535 /* 0 <= irq_num <= 3. level must be 0 or 1 */
 536 static void pci_set_irq(void *opaque, int irq_num, int level)
 537 {
 538     PCIDevice *pci_dev = (PCIDevice *)opaque;
 539     PCIBus *bus;
 540     int change;
 541
 542     change = level - pci_dev->irq_state[irq_num];
 543     if (!change)
 544         return;
 545
 546     pci_dev->irq_state[irq_num] = level;
 547
 548 #if defined(TARGET_IA64)
 549     ioapic_set_irq(pci_dev, irq_num, level);
 550 #endif
 551
 552     for (;;) {
 553         bus = pci_dev->bus;
 554         irq_num = bus->map_irq(pci_dev, irq_num);
 555         if (bus->set_irq)
 556             break;
 557         pci_dev = bus->parent_dev;
 558     }
 559     bus->irq_count[irq_num] += change;
 560     bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0);
 561 }
 562
 563 /***********************************************************/
 564 /* monitor info on PCI */
 565
 566 typedef struct {
 567     uint16_t class;
 568     const char *desc;
 569 } pci_class_desc;
 570
 571 static pci_class_desc pci_class_descriptions[] =
 572 {
 573     { 0x0100, "SCSI controller"},
 574     { 0x0101, "IDE controller"},
 575     { 0x0102, "Floppy controller"},
 576     { 0x0103, "IPI controller"},
 577     { 0x0104, "RAID controller"},
 578     { 0x0106, "SATA controller"},
 579     { 0x0107, "SAS controller"},
 580     { 0x0180, "Storage controller"},
 581     { 0x0200, "Ethernet controller"},
 582     { 0x0201, "Token Ring controller"},
 583     { 0x0202, "FDDI controller"},
 584     { 0x0203, "ATM controller"},
 585     { 0x0280, "Network controller"},
 586     { 0x0300, "VGA controller"},
 587     { 0x0301, "XGA controller"},
 588     { 0x0302, "3D controller"},
 589     { 0x0380, "Display controller"},
 590     { 0x0400, "Video controller"},
 591     { 0x0401, "Audio controller"},
 592     { 0x0402, "Phone"},
 593     { 0x0480, "Multimedia controller"},
 594     { 0x0500, "RAM controller"},
 595     { 0x0501, "Flash controller"},
 596     { 0x0580, "Memory controller"},
 597     { 0x0600, "Host bridge"},
 598     { 0x0601, "ISA bridge"},
 599     { 0x0602, "EISA bridge"},
 600     { 0x0603, "MC bridge"},
 601     { 0x0604, "PCI bridge"},
 602     { 0x0605, "PCMCIA bridge"},
 603     { 0x0606, "NUBUS bridge"},
 604     { 0x0607, "CARDBUS bridge"},
 605     { 0x0608, "RACEWAY bridge"},
 606     { 0x0680, "Bridge"},
 607     { 0x0c03, "USB controller"},
 608     { 0, NULL}
 609 };
 610
 611 static void pci_info_device(PCIDevice *d)
 612 {
 613     int i, class;
 614     PCIIORegion *r;
 615     pci_class_desc *desc;
 616
 617     term_printf("  Bus %2d, device %3d, function %d:\n",
 618            d->bus->bus_num, d->devfn >> 3, d->devfn & 7);
 619     class = le16_to_cpu(*((uint16_t *)(d->config + PCI_CLASS_DEVICE)));
 620     term_printf("    ");
 621     desc = pci_class_descriptions;
 622     while (desc->desc && class != desc->class)
 623         desc++;
 624     if (desc->desc) {
 625         term_printf("%s", desc->desc);
 626     } else {
 627         term_printf("Class %04x", class);
 628     }
 629     term_printf(": PCI device %04x:%04x\n",
 630            le16_to_cpu(*((uint16_t *)(d->config + PCI_VENDOR_ID))),
 631            le16_to_cpu(*((uint16_t *)(d->config + PCI_DEVICE_ID))));
 632
 633     if (d->config[PCI_INTERRUPT_PIN] != 0) {
 634         term_printf("      IRQ %d.\n", d->config[PCI_INTERRUPT_LINE]);
 635     }
 636     if (class == 0x0604) {
 637         term_printf("      BUS %d.\n", d->config[0x19]);
 638     }
 639     for(i = 0;i < PCI_NUM_REGIONS; i++) {
 640         r = &d->io_regions[i];
 641         if (r->size != 0) {
 642             term_printf("      BAR%d: ", i);
 643             if (r->type & PCI_ADDRESS_SPACE_IO) {
 644                 term_printf("I/O at 0x%04x [0x%04x].\n",
 645                        r->addr, r->addr + r->size - 1);
 646             } else {
 647                 term_printf("32 bit memory at 0x%08x [0x%08x].\n",
 648                        r->addr, r->addr + r->size - 1);
 649             }
 650         }
 651     }
 652     if (class == 0x0604 && d->config[0x19] != 0) {
 653         pci_for_each_device(d->config[0x19], pci_info_device);
 654     }
 655 }
 656
 657 void pci_for_each_device(int bus_num, void (*fn)(PCIDevice *d))
 658 {
 659     PCIBus *bus = first_bus;
 660     PCIDevice *d;
 661     int devfn;
 662
 663     while (bus && bus->bus_num != bus_num)
 664         bus = bus->next;
 665     if (bus) {
 666         for(devfn = 0; devfn < 256; devfn++) {
 667             d = bus->devices[devfn];
 668             if (d)
 669                 fn(d);
 670         }
 671     }
 672 }
 673
 674 void pci_info(void)
 675 {
 676     pci_for_each_device(0, pci_info_device);
 677 }
 678
 679 /* Initialize a PCI NIC.  */
 680 PCIDevice *pci_nic_init(PCIBus *bus, NICInfo *nd, int devfn)
 681 {
 682     PCIDevice *pci_dev;
 683
 684     if (strcmp(nd->model, "ne2k_pci") == 0) {
 685         pci_dev = pci_ne2000_init(bus, nd, devfn);
 686     } else if (strcmp(nd->model, "i82551") == 0) {
 687         pci_dev = pci_i82551_init(bus, nd, devfn);
 688     } else if (strcmp(nd->model, "i82557b") == 0) {
 689         pci_dev = pci_i82557b_init(bus, nd, devfn);
 690     } else if (strcmp(nd->model, "i82559er") == 0) {
 691         pci_dev = pci_i82559er_init(bus, nd, devfn);
 692     } else if (strcmp(nd->model, "rtl8139") == 0) {
 693         pci_dev = pci_rtl8139_init(bus, nd, devfn);
 694     } else if (strcmp(nd->model, "e1000") == 0) {
 695         pci_dev = pci_e1000_init(bus, nd, devfn);
 696     } else if (strcmp(nd->model, "pcnet") == 0) {
 697         pci_dev = pci_pcnet_init(bus, nd, devfn);
 698     } else if (strcmp(nd->model, "virtio") == 0) {
 699         pci_dev = virtio_net_init(bus, nd, devfn);
 700     } else if (strcmp(nd->model, "?") == 0) {
 701         fprintf(stderr, "qemu: Supported PCI NICs: i82551 i82557b i82559er"
 702                         " ne2k_pci pcnet rtl8139 e1000 virtio\n");
 703         return NULL;
 704     } else {
 705         fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd->model);
 706         return NULL;
 707     }
 708
 709     if (!pci_dev) {
 710         fprintf(stderr, "qemu: Unable to initialze NIC: %s\n", nd->model);
 711         return NULL;
 712     }
 713
 714     nd->devfn = pci_dev->devfn;
 715     return pci_dev;
 716 }
 717
 718 typedef struct {
 719     PCIDevice dev;
 720     PCIBus *bus;
 721 } PCIBridge;
 722
 723 static void pci_bridge_write_config(PCIDevice *d,
 724                              uint32_t address, uint32_t val, int len)
 725 {
 726     PCIBridge *s = (PCIBridge *)d;
 727
 728     if (address == 0x19 || (address == 0x18 && len > 1)) {
 729         if (address == 0x19)
 730             s->bus->bus_num = val & 0xff;
 731         else
 732             s->bus->bus_num = (val >> 8) & 0xff;
 733 #if defined(DEBUG_PCI)
 734         printf ("pci-bridge: %s: Assigned bus %d\n", d->name, s->bus->bus_num);
 735 #endif
 736     }
 737     pci_default_write_config(d, address, val, len);
 738 }
 739
 740 PCIBus *pci_find_bus(int bus_num)
 741 {
 742     PCIBus *bus = first_bus;
 743
 744     while (bus && bus->bus_num != bus_num)
 745         bus = bus->next;
 746
 747     return bus;
 748 }
 749
 750 PCIDevice *pci_find_device(int bus_num, int slot)
 751 {
 752     int devfn;
 753     PCIDevice *d;
 754     PCIBus *bus = pci_find_bus(bus_num);
 755
 756     if (!bus)
 757         return NULL;
 758
 759     for(devfn = 0; devfn < 256; devfn++) {
 760         d = bus->devices[devfn];
 761             if (d && PCI_SLOT(devfn) == slot)
 762                 return d;
 763     }
 764     return NULL;
 765 }
 766
 767 PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint32_t id,
 768                         pci_map_irq_fn map_irq, const char *name)
 769 {
 770     PCIBridge *s;
 771     s = (PCIBridge *)pci_register_device(bus, name, sizeof(PCIBridge),
 772                                          devfn, NULL, pci_bridge_write_config);
 773     s->dev.config[0x00] = id >> 16;
 774     s->dev.config[0x01] = id >> 24;
 775     s->dev.config[0x02] = id; // device_id
 776     s->dev.config[0x03] = id >> 8;
 777     s->dev.config[0x04] = 0x06; // command = bus master, pci mem
 778     s->dev.config[0x05] = 0x00;
 779     s->dev.config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error
 780     s->dev.config[0x07] = 0x00; // status = fast devsel
 781     s->dev.config[0x08] = 0x00; // revision
 782     s->dev.config[0x09] = 0x00; // programming i/f
 783     s->dev.config[0x0A] = 0x04; // class_sub = PCI to PCI bridge
 784     s->dev.config[0x0B] = 0x06; // class_base = PCI_bridge
 785     s->dev.config[0x0D] = 0x10; // latency_timer
 786     s->dev.config[0x0E] = 0x81; // header_type
 787     s->dev.config[0x1E] = 0xa0; // secondary status
 788
 789     s->bus = pci_register_secondary_bus(&s->dev, map_irq);
 790     return s->bus;
 791 }