kvm/include/x86/asm/kvm.h

   1 #ifndef KVM_UNIFDEF_H
   2 #define KVM_UNIFDEF_H
   3
   4 #ifdef __i386__
   5 #ifndef CONFIG_X86_32
   6 #define CONFIG_X86_32 1
   7 #endif
   8 #endif
   9
  10 #ifdef __x86_64__
  11 #ifndef CONFIG_X86_64
  12 #define CONFIG_X86_64 1
  13 #endif
  14 #endif
  15
  16 #if defined(__i386__) || defined (__x86_64__)
  17 #ifndef CONFIG_X86
  18 #define CONFIG_X86 1
  19 #endif
  20 #endif
  21
  22 #ifdef __ia64__
  23 #ifndef CONFIG_IA64
  24 #define CONFIG_IA64 1
  25 #endif
  26 #endif
  27
  28 #ifdef __PPC__
  29 #ifndef CONFIG_PPC
  30 #define CONFIG_PPC 1
  31 #endif
  32 #endif
  33
  34 #ifdef __s390__
  35 #ifndef CONFIG_S390
  36 #define CONFIG_S390 1
  37 #endif
  38 #endif
  39
  40 #endif
  41 #ifndef _ASM_X86_KVM_H
  42 #define _ASM_X86_KVM_H
  43
  44 /*
  45  * KVM x86 specific structures and definitions
  46  *
  47  */
  48
  49 #include <asm/types.h>
  50 #include <linux/ioctl.h>
  51
  52 /* Select x86 specific features in <linux/kvm.h> */
  53 #define __KVM_HAVE_PIT
  54 #define __KVM_HAVE_IOAPIC
  55 #define __KVM_HAVE_DEVICE_ASSIGNMENT
  56 #define __KVM_HAVE_MSI
  57 #define __KVM_HAVE_USER_NMI
  58 #define __KVM_HAVE_GUEST_DEBUG
  59 #define __KVM_HAVE_MSIX
  60
  61 /* Architectural interrupt line count. */
  62 #define KVM_NR_INTERRUPTS 256
  63
  64 struct kvm_memory_alias {
  65         __u32 slot;  /* this has a different namespace than memory slots */
  66         __u32 flags;
  67         __u64 guest_phys_addr;
  68         __u64 memory_size;
  69         __u64 target_phys_addr;
  70 };
  71
  72 /* for KVM_GET_IRQCHIP and KVM_SET_IRQCHIP */
  73 struct kvm_pic_state {
  74         __u8 last_irr;  /* edge detection */
  75         __u8 irr;               /* interrupt request register */
  76         __u8 imr;               /* interrupt mask register */
  77         __u8 isr;               /* interrupt service register */
  78         __u8 priority_add;      /* highest irq priority */
  79         __u8 irq_base;
  80         __u8 read_reg_select;
  81         __u8 poll;
  82         __u8 special_mask;
  83         __u8 init_state;
  84         __u8 auto_eoi;
  85         __u8 rotate_on_auto_eoi;
  86         __u8 special_fully_nested_mode;
  87         __u8 init4;             /* true if 4 byte init */
  88         __u8 elcr;              /* PIIX edge/trigger selection */
  89         __u8 elcr_mask;
  90 };
  91
  92 #define KVM_IOAPIC_NUM_PINS  24
  93 struct kvm_ioapic_state {
  94         __u64 base_address;
  95         __u32 ioregsel;
  96         __u32 id;
  97         __u32 irr;
  98         __u32 pad;
  99         union {
 100                 __u64 bits;
 101                 struct {
 102                         __u8 vector;
 103                         __u8 delivery_mode:3;
 104                         __u8 dest_mode:1;
 105                         __u8 delivery_status:1;
 106                         __u8 polarity:1;
 107                         __u8 remote_irr:1;
 108                         __u8 trig_mode:1;
 109                         __u8 mask:1;
 110                         __u8 reserve:7;
 111                         __u8 reserved[4];
 112                         __u8 dest_id;
 113                 } fields;
 114         } redirtbl[KVM_IOAPIC_NUM_PINS];
 115 };
 116
 117 #define KVM_IRQCHIP_PIC_MASTER   0
 118 #define KVM_IRQCHIP_PIC_SLAVE    1
 119 #define KVM_IRQCHIP_IOAPIC       2
 120
 121 /* for KVM_GET_REGS and KVM_SET_REGS */
 122 struct kvm_regs {
 123         /* out (KVM_GET_REGS) / in (KVM_SET_REGS) */
 124         __u64 rax, rbx, rcx, rdx;
 125         __u64 rsi, rdi, rsp, rbp;
 126         __u64 r8,  r9,  r10, r11;
 127         __u64 r12, r13, r14, r15;
 128         __u64 rip, rflags;
 129 };
 130
 131 /* for KVM_GET_LAPIC and KVM_SET_LAPIC */
 132 #define KVM_APIC_REG_SIZE 0x400
 133 struct kvm_lapic_state {
 134         char regs[KVM_APIC_REG_SIZE];
 135 };
 136
 137 struct kvm_segment {
 138         __u64 base;
 139         __u32 limit;
 140         __u16 selector;
 141         __u8  type;
 142         __u8  present, dpl, db, s, l, g, avl;
 143         __u8  unusable;
 144         __u8  padding;
 145 };
 146
 147 struct kvm_dtable {
 148         __u64 base;
 149         __u16 limit;
 150         __u16 padding[3];
 151 };
 152
 153
 154 /* for KVM_GET_SREGS and KVM_SET_SREGS */
 155 struct kvm_sregs {
 156         /* out (KVM_GET_SREGS) / in (KVM_SET_SREGS) */
 157         struct kvm_segment cs, ds, es, fs, gs, ss;
 158         struct kvm_segment tr, ldt;
 159         struct kvm_dtable gdt, idt;
 160         __u64 cr0, cr2, cr3, cr4, cr8;
 161         __u64 efer;
 162         __u64 apic_base;
 163         __u64 interrupt_bitmap[(KVM_NR_INTERRUPTS + 63) / 64];
 164 };
 165
 166 /* for KVM_GET_FPU and KVM_SET_FPU */
 167 struct kvm_fpu {
 168         __u8  fpr[8][16];
 169         __u16 fcw;
 170         __u16 fsw;
 171         __u8  ftwx;  /* in fxsave format */
 172         __u8  pad1;
 173         __u16 last_opcode;
 174         __u64 last_ip;
 175         __u64 last_dp;
 176         __u8  xmm[16][16];
 177         __u32 mxcsr;
 178         __u32 pad2;
 179 };
 180
 181 struct kvm_msr_entry {
 182         __u32 index;
 183         __u32 reserved;
 184         __u64 data;
 185 };
 186
 187 /* for KVM_GET_MSRS and KVM_SET_MSRS */
 188 struct kvm_msrs {
 189         __u32 nmsrs; /* number of msrs in entries */
 190         __u32 pad;
 191
 192         struct kvm_msr_entry entries[0];
 193 };
 194
 195 /* for KVM_GET_MSR_INDEX_LIST */
 196 struct kvm_msr_list {
 197         __u32 nmsrs; /* number of msrs in entries */
 198         __u32 indices[0];
 199 };
 200
 201
 202 struct kvm_cpuid_entry {
 203         __u32 function;
 204         __u32 eax;
 205         __u32 ebx;
 206         __u32 ecx;
 207         __u32 edx;
 208         __u32 padding;
 209 };
 210
 211 /* for KVM_SET_CPUID */
 212 struct kvm_cpuid {
 213         __u32 nent;
 214         __u32 padding;
 215         struct kvm_cpuid_entry entries[0];
 216 };
 217
 218 struct kvm_cpuid_entry2 {
 219         __u32 function;
 220         __u32 index;
 221         __u32 flags;
 222         __u32 eax;
 223         __u32 ebx;
 224         __u32 ecx;
 225         __u32 edx;
 226         __u32 padding[3];
 227 };
 228
 229 #define KVM_CPUID_FLAG_SIGNIFCANT_INDEX 1
 230 #define KVM_CPUID_FLAG_STATEFUL_FUNC    2
 231 #define KVM_CPUID_FLAG_STATE_READ_NEXT  4
 232
 233 /* for KVM_SET_CPUID2 */
 234 struct kvm_cpuid2 {
 235         __u32 nent;
 236         __u32 padding;
 237         struct kvm_cpuid_entry2 entries[0];
 238 };
 239
 240 /* for KVM_GET_PIT and KVM_SET_PIT */
 241 struct kvm_pit_channel_state {
 242         __u32 count; /* can be 65536 */
 243         __u16 latched_count;
 244         __u8 count_latched;
 245         __u8 status_latched;
 246         __u8 status;
 247         __u8 read_state;
 248         __u8 write_state;
 249         __u8 write_latch;
 250         __u8 rw_mode;
 251         __u8 mode;
 252         __u8 bcd;
 253         __u8 gate;
 254         __s64 count_load_time;
 255 };
 256
 257 struct kvm_debug_exit_arch {
 258         __u32 exception;
 259         __u32 pad;
 260         __u64 pc;
 261         __u64 dr6;
 262         __u64 dr7;
 263 };
 264
 265 #define KVM_GUESTDBG_USE_SW_BP          0x00010000
 266 #define KVM_GUESTDBG_USE_HW_BP          0x00020000
 267 #define KVM_GUESTDBG_INJECT_DB          0x00040000
 268 #define KVM_GUESTDBG_INJECT_BP          0x00080000
 269
 270 /* for KVM_SET_GUEST_DEBUG */
 271 struct kvm_guest_debug_arch {
 272         __u64 debugreg[8];
 273 };
 274
 275 struct kvm_pit_state {
 276         struct kvm_pit_channel_state channels[3];
 277 };
 278
 279 struct kvm_reinject_control {
 280         __u8 pit_reinject;
 281         __u8 reserved[31];
 282 };
 283 #endif /* _ASM_X86_KVM_H */