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Remove reserved registers from tcg_target_reg_alloc_order
[qemu-kvm/fedora.git] / target-ppc / translate.c
blob9ba493749867978ec9af415547a0f413d32796ed
1 /*
2 * PowerPC emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA 02110-1301 USA
19 */
20 #include <stdarg.h>
21 #include <stdlib.h>
22 #include <stdio.h>
23 #include <string.h>
24 #include <inttypes.h>
25
26 #include "cpu.h"
27 #include "exec-all.h"
28 #include "disas.h"
29 #include "tcg-op.h"
30 #include "qemu-common.h"
31 #include "host-utils.h"
32
33 #include "helper.h"
34 #define GEN_HELPER 1
35 #include "helper.h"
36
37 #define CPU_SINGLE_STEP 0x1
38 #define CPU_BRANCH_STEP 0x2
39 #define GDBSTUB_SINGLE_STEP 0x4
40
41 /* Include definitions for instructions classes and implementations flags */
42 //#define PPC_DEBUG_DISAS
43 //#define DO_PPC_STATISTICS
44
45 #ifdef PPC_DEBUG_DISAS
46 # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
47 #else
48 # define LOG_DISAS(...) do { } while (0)
49 #endif
50 /*****************************************************************************/
51 /* Code translation helpers */
52
53 /* global register indexes */
54 static TCGv_ptr cpu_env;
55 static char cpu_reg_names[10*3 + 22*4 /* GPR */
56 #if !defined(TARGET_PPC64)
57 + 10*4 + 22*5 /* SPE GPRh */
58 #endif
59 + 10*4 + 22*5 /* FPR */
60 + 2*(10*6 + 22*7) /* AVRh, AVRl */
61 + 8*5 /* CRF */];
62 static TCGv cpu_gpr[32];
63 #if !defined(TARGET_PPC64)
64 static TCGv cpu_gprh[32];
65 #endif
66 static TCGv_i64 cpu_fpr[32];
67 static TCGv_i64 cpu_avrh[32], cpu_avrl[32];
68 static TCGv_i32 cpu_crf[8];
69 static TCGv cpu_nip;
70 static TCGv cpu_msr;
71 static TCGv cpu_ctr;
72 static TCGv cpu_lr;
73 static TCGv cpu_xer;
74 static TCGv cpu_reserve;
75 static TCGv_i32 cpu_fpscr;
76 static TCGv_i32 cpu_access_type;
77
78 #include "gen-icount.h"
79
80 void ppc_translate_init(void)
81 {
82 int i;
83 char* p;
84 static int done_init = 0;
85
86 if (done_init)
87 return;
88
89 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
90
91 p = cpu_reg_names;
92
93 for (i = 0; i < 8; i++) {
94 sprintf(p, "crf%d", i);
95 cpu_crf[i] = tcg_global_mem_new_i32(TCG_AREG0,
96 offsetof(CPUState, crf[i]), p);
97 p += 5;
98 }
99
100 for (i = 0; i < 32; i++) {
101 sprintf(p, "r%d", i);
102 cpu_gpr[i] = tcg_global_mem_new(TCG_AREG0,
103 offsetof(CPUState, gpr[i]), p);
104 p += (i < 10) ? 3 : 4;
105 #if !defined(TARGET_PPC64)
106 sprintf(p, "r%dH", i);
107 cpu_gprh[i] = tcg_global_mem_new_i32(TCG_AREG0,
108 offsetof(CPUState, gprh[i]), p);
109 p += (i < 10) ? 4 : 5;
110 #endif
111
112 sprintf(p, "fp%d", i);
113 cpu_fpr[i] = tcg_global_mem_new_i64(TCG_AREG0,
114 offsetof(CPUState, fpr[i]), p);
115 p += (i < 10) ? 4 : 5;
116
117 sprintf(p, "avr%dH", i);
118 #ifdef WORDS_BIGENDIAN
119 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
120 offsetof(CPUState, avr[i].u64[0]), p);
121 #else
122 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
123 offsetof(CPUState, avr[i].u64[1]), p);
124 #endif
125 p += (i < 10) ? 6 : 7;
126
127 sprintf(p, "avr%dL", i);
128 #ifdef WORDS_BIGENDIAN
129 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
130 offsetof(CPUState, avr[i].u64[1]), p);
131 #else
132 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
133 offsetof(CPUState, avr[i].u64[0]), p);
134 #endif
135 p += (i < 10) ? 6 : 7;
136 }
137
138 cpu_nip = tcg_global_mem_new(TCG_AREG0,
139 offsetof(CPUState, nip), "nip");
140
141 cpu_msr = tcg_global_mem_new(TCG_AREG0,
142 offsetof(CPUState, msr), "msr");
143
144 cpu_ctr = tcg_global_mem_new(TCG_AREG0,
145 offsetof(CPUState, ctr), "ctr");
146
147 cpu_lr = tcg_global_mem_new(TCG_AREG0,
148 offsetof(CPUState, lr), "lr");
149
150 cpu_xer = tcg_global_mem_new(TCG_AREG0,
151 offsetof(CPUState, xer), "xer");
152
153 cpu_reserve = tcg_global_mem_new(TCG_AREG0,
154 offsetof(CPUState, reserve), "reserve");
155
156 cpu_fpscr = tcg_global_mem_new_i32(TCG_AREG0,
157 offsetof(CPUState, fpscr), "fpscr");
158
159 cpu_access_type = tcg_global_mem_new_i32(TCG_AREG0,
160 offsetof(CPUState, access_type), "access_type");
161
162 /* register helpers */
163 #define GEN_HELPER 2
164 #include "helper.h"
165
166 done_init = 1;
167 }
168
169 /* internal defines */
170 typedef struct DisasContext {
171 struct TranslationBlock *tb;
172 target_ulong nip;
173 uint32_t opcode;
174 uint32_t exception;
175 /* Routine used to access memory */
176 int mem_idx;
177 int access_type;
178 /* Translation flags */
179 int le_mode;
180 #if defined(TARGET_PPC64)
181 int sf_mode;
182 #endif
183 int fpu_enabled;
184 int altivec_enabled;
185 int spe_enabled;
186 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
187 int singlestep_enabled;
188 } DisasContext;
189
190 struct opc_handler_t {
191 /* invalid bits */
192 uint32_t inval;
193 /* instruction type */
194 uint64_t type;
195 /* handler */
196 void (*handler)(DisasContext *ctx);
197 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
198 const char *oname;
199 #endif
200 #if defined(DO_PPC_STATISTICS)
201 uint64_t count;
202 #endif
203 };
204
205 static always_inline void gen_reset_fpstatus (void)
206 {
207 #ifdef CONFIG_SOFTFLOAT
208 gen_helper_reset_fpstatus();
209 #endif
210 }
211
212 static always_inline void gen_compute_fprf (TCGv_i64 arg, int set_fprf, int set_rc)
213 {
214 TCGv_i32 t0 = tcg_temp_new_i32();
215
216 if (set_fprf != 0) {
217 /* This case might be optimized later */
218 tcg_gen_movi_i32(t0, 1);
219 gen_helper_compute_fprf(t0, arg, t0);
220 if (unlikely(set_rc)) {
221 tcg_gen_mov_i32(cpu_crf[1], t0);
222 }
223 gen_helper_float_check_status();
224 } else if (unlikely(set_rc)) {
225 /* We always need to compute fpcc */
226 tcg_gen_movi_i32(t0, 0);
227 gen_helper_compute_fprf(t0, arg, t0);
228 tcg_gen_mov_i32(cpu_crf[1], t0);
229 }
230
231 tcg_temp_free_i32(t0);
232 }
233
234 static always_inline void gen_set_access_type (DisasContext *ctx, int access_type)
235 {
236 if (ctx->access_type != access_type) {
237 tcg_gen_movi_i32(cpu_access_type, access_type);
238 ctx->access_type = access_type;
239 }
240 }
241
242 static always_inline void gen_update_nip (DisasContext *ctx, target_ulong nip)
243 {
244 #if defined(TARGET_PPC64)
245 if (ctx->sf_mode)
246 tcg_gen_movi_tl(cpu_nip, nip);
247 else
248 #endif
249 tcg_gen_movi_tl(cpu_nip, (uint32_t)nip);
250 }
251
252 static always_inline void gen_exception_err (DisasContext *ctx, uint32_t excp, uint32_t error)
253 {
254 TCGv_i32 t0, t1;
255 if (ctx->exception == POWERPC_EXCP_NONE) {
256 gen_update_nip(ctx, ctx->nip);
257 }
258 t0 = tcg_const_i32(excp);
259 t1 = tcg_const_i32(error);
260 gen_helper_raise_exception_err(t0, t1);
261 tcg_temp_free_i32(t0);
262 tcg_temp_free_i32(t1);
263 ctx->exception = (excp);
264 }
265
266 static always_inline void gen_exception (DisasContext *ctx, uint32_t excp)
267 {
268 TCGv_i32 t0;
269 if (ctx->exception == POWERPC_EXCP_NONE) {
270 gen_update_nip(ctx, ctx->nip);
271 }
272 t0 = tcg_const_i32(excp);
273 gen_helper_raise_exception(t0);
274 tcg_temp_free_i32(t0);
275 ctx->exception = (excp);
276 }
277
278 static always_inline void gen_debug_exception (DisasContext *ctx)
279 {
280 TCGv_i32 t0;
281
282 if (ctx->exception != POWERPC_EXCP_BRANCH)
283 gen_update_nip(ctx, ctx->nip);
284 t0 = tcg_const_i32(EXCP_DEBUG);
285 gen_helper_raise_exception(t0);
286 tcg_temp_free_i32(t0);
287 }
288
289 static always_inline void gen_inval_exception (DisasContext *ctx, uint32_t error)
290 {
291 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_INVAL | error);
292 }
293
294 /* Stop translation */
295 static always_inline void gen_stop_exception (DisasContext *ctx)
296 {
297 gen_update_nip(ctx, ctx->nip);
298 ctx->exception = POWERPC_EXCP_STOP;
299 }
300
301 /* No need to update nip here, as execution flow will change */
302 static always_inline void gen_sync_exception (DisasContext *ctx)
303 {
304 ctx->exception = POWERPC_EXCP_SYNC;
305 }
306
307 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
308 static void gen_##name (DisasContext *ctx); \
309 GEN_OPCODE(name, opc1, opc2, opc3, inval, type); \
310 static void gen_##name (DisasContext *ctx)
311
312 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
313 static void gen_##name (DisasContext *ctx); \
314 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type); \
315 static void gen_##name (DisasContext *ctx)
316
317 typedef struct opcode_t {
318 unsigned char opc1, opc2, opc3;
319 #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
320 unsigned char pad[5];
321 #else
322 unsigned char pad[1];
323 #endif
324 opc_handler_t handler;
325 const char *oname;
326 } opcode_t;
327
328 /*****************************************************************************/
329 /*** Instruction decoding ***/
330 #define EXTRACT_HELPER(name, shift, nb) \
331 static always_inline uint32_t name (uint32_t opcode) \
332 { \
333 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
334 }
335
336 #define EXTRACT_SHELPER(name, shift, nb) \
337 static always_inline int32_t name (uint32_t opcode) \
338 { \
339 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
340 }
341
342 /* Opcode part 1 */
343 EXTRACT_HELPER(opc1, 26, 6);
344 /* Opcode part 2 */
345 EXTRACT_HELPER(opc2, 1, 5);
346 /* Opcode part 3 */
347 EXTRACT_HELPER(opc3, 6, 5);
348 /* Update Cr0 flags */
349 EXTRACT_HELPER(Rc, 0, 1);
350 /* Destination */
351 EXTRACT_HELPER(rD, 21, 5);
352 /* Source */
353 EXTRACT_HELPER(rS, 21, 5);
354 /* First operand */
355 EXTRACT_HELPER(rA, 16, 5);
356 /* Second operand */
357 EXTRACT_HELPER(rB, 11, 5);
358 /* Third operand */
359 EXTRACT_HELPER(rC, 6, 5);
360 /*** Get CRn ***/
361 EXTRACT_HELPER(crfD, 23, 3);
362 EXTRACT_HELPER(crfS, 18, 3);
363 EXTRACT_HELPER(crbD, 21, 5);
364 EXTRACT_HELPER(crbA, 16, 5);
365 EXTRACT_HELPER(crbB, 11, 5);
366 /* SPR / TBL */
367 EXTRACT_HELPER(_SPR, 11, 10);
368 static always_inline uint32_t SPR (uint32_t opcode)
369 {
370 uint32_t sprn = _SPR(opcode);
371
372 return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
373 }
374 /*** Get constants ***/
375 EXTRACT_HELPER(IMM, 12, 8);
376 /* 16 bits signed immediate value */
377 EXTRACT_SHELPER(SIMM, 0, 16);
378 /* 16 bits unsigned immediate value */
379 EXTRACT_HELPER(UIMM, 0, 16);
380 /* 5 bits signed immediate value */
381 EXTRACT_HELPER(SIMM5, 16, 5);
382 /* 5 bits signed immediate value */
383 EXTRACT_HELPER(UIMM5, 16, 5);
384 /* Bit count */
385 EXTRACT_HELPER(NB, 11, 5);
386 /* Shift count */
387 EXTRACT_HELPER(SH, 11, 5);
388 /* Vector shift count */
389 EXTRACT_HELPER(VSH, 6, 4);
390 /* Mask start */
391 EXTRACT_HELPER(MB, 6, 5);
392 /* Mask end */
393 EXTRACT_HELPER(ME, 1, 5);
394 /* Trap operand */
395 EXTRACT_HELPER(TO, 21, 5);
396
397 EXTRACT_HELPER(CRM, 12, 8);
398 EXTRACT_HELPER(FM, 17, 8);
399 EXTRACT_HELPER(SR, 16, 4);
400 EXTRACT_HELPER(FPIMM, 12, 4);
401
402 /*** Jump target decoding ***/
403 /* Displacement */
404 EXTRACT_SHELPER(d, 0, 16);
405 /* Immediate address */
406 static always_inline target_ulong LI (uint32_t opcode)
407 {
408 return (opcode >> 0) & 0x03FFFFFC;
409 }
410
411 static always_inline uint32_t BD (uint32_t opcode)
412 {
413 return (opcode >> 0) & 0xFFFC;
414 }
415
416 EXTRACT_HELPER(BO, 21, 5);
417 EXTRACT_HELPER(BI, 16, 5);
418 /* Absolute/relative address */
419 EXTRACT_HELPER(AA, 1, 1);
420 /* Link */
421 EXTRACT_HELPER(LK, 0, 1);
422
423 /* Create a mask between <start> and <end> bits */
424 static always_inline target_ulong MASK (uint32_t start, uint32_t end)
425 {
426 target_ulong ret;
427
428 #if defined(TARGET_PPC64)
429 if (likely(start == 0)) {
430 ret = UINT64_MAX << (63 - end);
431 } else if (likely(end == 63)) {
432 ret = UINT64_MAX >> start;
433 }
434 #else
435 if (likely(start == 0)) {
436 ret = UINT32_MAX << (31 - end);
437 } else if (likely(end == 31)) {
438 ret = UINT32_MAX >> start;
439 }
440 #endif
441 else {
442 ret = (((target_ulong)(-1ULL)) >> (start)) ^
443 (((target_ulong)(-1ULL) >> (end)) >> 1);
444 if (unlikely(start > end))
445 return ~ret;
446 }
447
448 return ret;
449 }
450
451 /*****************************************************************************/
452 /* PowerPC Instructions types definitions */
453 enum {
454 PPC_NONE = 0x0000000000000000ULL,
455 /* PowerPC base instructions set */
456 PPC_INSNS_BASE = 0x0000000000000001ULL,
457 /* integer operations instructions */
458 #define PPC_INTEGER PPC_INSNS_BASE
459 /* flow control instructions */
460 #define PPC_FLOW PPC_INSNS_BASE
461 /* virtual memory instructions */
462 #define PPC_MEM PPC_INSNS_BASE
463 /* ld/st with reservation instructions */
464 #define PPC_RES PPC_INSNS_BASE
465 /* spr/msr access instructions */
466 #define PPC_MISC PPC_INSNS_BASE
467 /* Deprecated instruction sets */
468 /* Original POWER instruction set */
469 PPC_POWER = 0x0000000000000002ULL,
470 /* POWER2 instruction set extension */
471 PPC_POWER2 = 0x0000000000000004ULL,
472 /* Power RTC support */
473 PPC_POWER_RTC = 0x0000000000000008ULL,
474 /* Power-to-PowerPC bridge (601) */
475 PPC_POWER_BR = 0x0000000000000010ULL,
476 /* 64 bits PowerPC instruction set */
477 PPC_64B = 0x0000000000000020ULL,
478 /* New 64 bits extensions (PowerPC 2.0x) */
479 PPC_64BX = 0x0000000000000040ULL,
480 /* 64 bits hypervisor extensions */
481 PPC_64H = 0x0000000000000080ULL,
482 /* New wait instruction (PowerPC 2.0x) */
483 PPC_WAIT = 0x0000000000000100ULL,
484 /* Time base mftb instruction */
485 PPC_MFTB = 0x0000000000000200ULL,
486
487 /* Fixed-point unit extensions */
488 /* PowerPC 602 specific */
489 PPC_602_SPEC = 0x0000000000000400ULL,
490 /* isel instruction */
491 PPC_ISEL = 0x0000000000000800ULL,
492 /* popcntb instruction */
493 PPC_POPCNTB = 0x0000000000001000ULL,
494 /* string load / store */
495 PPC_STRING = 0x0000000000002000ULL,
496
497 /* Floating-point unit extensions */
498 /* Optional floating point instructions */
499 PPC_FLOAT = 0x0000000000010000ULL,
500 /* New floating-point extensions (PowerPC 2.0x) */
501 PPC_FLOAT_EXT = 0x0000000000020000ULL,
502 PPC_FLOAT_FSQRT = 0x0000000000040000ULL,
503 PPC_FLOAT_FRES = 0x0000000000080000ULL,
504 PPC_FLOAT_FRSQRTE = 0x0000000000100000ULL,
505 PPC_FLOAT_FRSQRTES = 0x0000000000200000ULL,
506 PPC_FLOAT_FSEL = 0x0000000000400000ULL,
507 PPC_FLOAT_STFIWX = 0x0000000000800000ULL,
508
509 /* Vector/SIMD extensions */
510 /* Altivec support */
511 PPC_ALTIVEC = 0x0000000001000000ULL,
512 /* PowerPC 2.03 SPE extension */
513 PPC_SPE = 0x0000000002000000ULL,
514 /* PowerPC 2.03 SPE single-precision floating-point extension */
515 PPC_SPE_SINGLE = 0x0000000004000000ULL,
516 /* PowerPC 2.03 SPE double-precision floating-point extension */
517 PPC_SPE_DOUBLE = 0x0000000008000000ULL,
518
519 /* Optional memory control instructions */
520 PPC_MEM_TLBIA = 0x0000000010000000ULL,
521 PPC_MEM_TLBIE = 0x0000000020000000ULL,
522 PPC_MEM_TLBSYNC = 0x0000000040000000ULL,
523 /* sync instruction */
524 PPC_MEM_SYNC = 0x0000000080000000ULL,
525 /* eieio instruction */
526 PPC_MEM_EIEIO = 0x0000000100000000ULL,
527
528 /* Cache control instructions */
529 PPC_CACHE = 0x0000000200000000ULL,
530 /* icbi instruction */
531 PPC_CACHE_ICBI = 0x0000000400000000ULL,
532 /* dcbz instruction with fixed cache line size */
533 PPC_CACHE_DCBZ = 0x0000000800000000ULL,
534 /* dcbz instruction with tunable cache line size */
535 PPC_CACHE_DCBZT = 0x0000001000000000ULL,
536 /* dcba instruction */
537 PPC_CACHE_DCBA = 0x0000002000000000ULL,
538 /* Freescale cache locking instructions */
539 PPC_CACHE_LOCK = 0x0000004000000000ULL,
540
541 /* MMU related extensions */
542 /* external control instructions */
543 PPC_EXTERN = 0x0000010000000000ULL,
544 /* segment register access instructions */
545 PPC_SEGMENT = 0x0000020000000000ULL,
546 /* PowerPC 6xx TLB management instructions */
547 PPC_6xx_TLB = 0x0000040000000000ULL,
548 /* PowerPC 74xx TLB management instructions */
549 PPC_74xx_TLB = 0x0000080000000000ULL,
550 /* PowerPC 40x TLB management instructions */
551 PPC_40x_TLB = 0x0000100000000000ULL,
552 /* segment register access instructions for PowerPC 64 "bridge" */
553 PPC_SEGMENT_64B = 0x0000200000000000ULL,
554 /* SLB management */
555 PPC_SLBI = 0x0000400000000000ULL,
556
557 /* Embedded PowerPC dedicated instructions */
558 PPC_WRTEE = 0x0001000000000000ULL,
559 /* PowerPC 40x exception model */
560 PPC_40x_EXCP = 0x0002000000000000ULL,
561 /* PowerPC 405 Mac instructions */
562 PPC_405_MAC = 0x0004000000000000ULL,
563 /* PowerPC 440 specific instructions */
564 PPC_440_SPEC = 0x0008000000000000ULL,
565 /* BookE (embedded) PowerPC specification */
566 PPC_BOOKE = 0x0010000000000000ULL,
567 /* mfapidi instruction */
568 PPC_MFAPIDI = 0x0020000000000000ULL,
569 /* tlbiva instruction */
570 PPC_TLBIVA = 0x0040000000000000ULL,
571 /* tlbivax instruction */
572 PPC_TLBIVAX = 0x0080000000000000ULL,
573 /* PowerPC 4xx dedicated instructions */
574 PPC_4xx_COMMON = 0x0100000000000000ULL,
575 /* PowerPC 40x ibct instructions */
576 PPC_40x_ICBT = 0x0200000000000000ULL,
577 /* rfmci is not implemented in all BookE PowerPC */
578 PPC_RFMCI = 0x0400000000000000ULL,
579 /* rfdi instruction */
580 PPC_RFDI = 0x0800000000000000ULL,
581 /* DCR accesses */
582 PPC_DCR = 0x1000000000000000ULL,
583 /* DCR extended accesse */
584 PPC_DCRX = 0x2000000000000000ULL,
585 /* user-mode DCR access, implemented in PowerPC 460 */
586 PPC_DCRUX = 0x4000000000000000ULL,
587 };
588
589 /*****************************************************************************/
590 /* PowerPC instructions table */
591 #if HOST_LONG_BITS == 64
592 #define OPC_ALIGN 8
593 #else
594 #define OPC_ALIGN 4
595 #endif
596 #if defined(__APPLE__)
597 #define OPCODES_SECTION \
598 __attribute__ ((section("__TEXT,__opcodes"), unused, aligned (OPC_ALIGN) ))
599 #else
600 #define OPCODES_SECTION \
601 __attribute__ ((section(".opcodes"), unused, aligned (OPC_ALIGN) ))
602 #endif
603
604 #if defined(DO_PPC_STATISTICS)
605 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \
606 extern opcode_t opc_##name; \
607 OPCODES_SECTION opcode_t opc_##name = { \
608 .opc1 = op1, \
609 .opc2 = op2, \
610 .opc3 = op3, \
611 .pad = { 0, }, \
612 .handler = { \
613 .inval = invl, \
614 .type = _typ, \
615 .handler = &gen_##name, \
616 .oname = stringify(name), \
617 }, \
618 .oname = stringify(name), \
619 }
620 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ) \
621 OPCODES_SECTION opcode_t opc_##name = { \
622 .opc1 = op1, \
623 .opc2 = op2, \
624 .opc3 = op3, \
625 .pad = { 0, }, \
626 .handler = { \
627 .inval = invl, \
628 .type = _typ, \
629 .handler = &gen_##name, \
630 .oname = onam, \
631 }, \
632 .oname = onam, \
633 }
634 #else
635 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \
636 extern opcode_t opc_##name; \
637 OPCODES_SECTION opcode_t opc_##name = { \
638 .opc1 = op1, \
639 .opc2 = op2, \
640 .opc3 = op3, \
641 .pad = { 0, }, \
642 .handler = { \
643 .inval = invl, \
644 .type = _typ, \
645 .handler = &gen_##name, \
646 }, \
647 .oname = stringify(name), \
648 }
649 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ) \
650 extern opcode_t opc_##name; \
651 OPCODES_SECTION opcode_t opc_##name = { \
652 .opc1 = op1, \
653 .opc2 = op2, \
654 .opc3 = op3, \
655 .pad = { 0, }, \
656 .handler = { \
657 .inval = invl, \
658 .type = _typ, \
659 .handler = &gen_##name, \
660 }, \
661 .oname = onam, \
662 }
663 #endif
664
665 #define GEN_OPCODE_MARK(name) \
666 extern opcode_t opc_##name; \
667 OPCODES_SECTION opcode_t opc_##name = { \
668 .opc1 = 0xFF, \
669 .opc2 = 0xFF, \
670 .opc3 = 0xFF, \
671 .pad = { 0, }, \
672 .handler = { \
673 .inval = 0x00000000, \
674 .type = 0x00, \
675 .handler = NULL, \
676 }, \
677 .oname = stringify(name), \
678 }
679
680 /* SPR load/store helpers */
681 static always_inline void gen_load_spr(TCGv t, int reg)
682 {
683 tcg_gen_ld_tl(t, cpu_env, offsetof(CPUState, spr[reg]));
684 }
685
686 static always_inline void gen_store_spr(int reg, TCGv t)
687 {
688 tcg_gen_st_tl(t, cpu_env, offsetof(CPUState, spr[reg]));
689 }
690
691 /* Start opcode list */
692 GEN_OPCODE_MARK(start);
693
694 /* Invalid instruction */
695 GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE)
696 {
697 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
698 }
699
700 static opc_handler_t invalid_handler = {
701 .inval = 0xFFFFFFFF,
702 .type = PPC_NONE,
703 .handler = gen_invalid,
704 };
705
706 /*** Integer comparison ***/
707
708 static always_inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
709 {
710 int l1, l2, l3;
711
712 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_xer);
713 tcg_gen_shri_i32(cpu_crf[crf], cpu_crf[crf], XER_SO);
714 tcg_gen_andi_i32(cpu_crf[crf], cpu_crf[crf], 1);
715
716 l1 = gen_new_label();
717 l2 = gen_new_label();
718 l3 = gen_new_label();
719 if (s) {
720 tcg_gen_brcond_tl(TCG_COND_LT, arg0, arg1, l1);
721 tcg_gen_brcond_tl(TCG_COND_GT, arg0, arg1, l2);
722 } else {
723 tcg_gen_brcond_tl(TCG_COND_LTU, arg0, arg1, l1);
724 tcg_gen_brcond_tl(TCG_COND_GTU, arg0, arg1, l2);
725 }
726 tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_EQ);
727 tcg_gen_br(l3);
728 gen_set_label(l1);
729 tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_LT);
730 tcg_gen_br(l3);
731 gen_set_label(l2);
732 tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_GT);
733 gen_set_label(l3);
734 }
735
736 static always_inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
737 {
738 TCGv t0 = tcg_const_local_tl(arg1);
739 gen_op_cmp(arg0, t0, s, crf);
740 tcg_temp_free(t0);
741 }
742
743 #if defined(TARGET_PPC64)
744 static always_inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
745 {
746 TCGv t0, t1;
747 t0 = tcg_temp_local_new();
748 t1 = tcg_temp_local_new();
749 if (s) {
750 tcg_gen_ext32s_tl(t0, arg0);
751 tcg_gen_ext32s_tl(t1, arg1);
752 } else {
753 tcg_gen_ext32u_tl(t0, arg0);
754 tcg_gen_ext32u_tl(t1, arg1);
755 }
756 gen_op_cmp(t0, t1, s, crf);
757 tcg_temp_free(t1);
758 tcg_temp_free(t0);
759 }
760
761 static always_inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
762 {
763 TCGv t0 = tcg_const_local_tl(arg1);
764 gen_op_cmp32(arg0, t0, s, crf);
765 tcg_temp_free(t0);
766 }
767 #endif
768
769 static always_inline void gen_set_Rc0 (DisasContext *ctx, TCGv reg)
770 {
771 #if defined(TARGET_PPC64)
772 if (!(ctx->sf_mode))
773 gen_op_cmpi32(reg, 0, 1, 0);
774 else
775 #endif
776 gen_op_cmpi(reg, 0, 1, 0);
777 }
778
779 /* cmp */
780 GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER)
781 {
782 #if defined(TARGET_PPC64)
783 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
784 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
785 1, crfD(ctx->opcode));
786 else
787 #endif
788 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
789 1, crfD(ctx->opcode));
790 }
791
792 /* cmpi */
793 GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
794 {
795 #if defined(TARGET_PPC64)
796 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
797 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
798 1, crfD(ctx->opcode));
799 else
800 #endif
801 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
802 1, crfD(ctx->opcode));
803 }
804
805 /* cmpl */
806 GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER)
807 {
808 #if defined(TARGET_PPC64)
809 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
810 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
811 0, crfD(ctx->opcode));
812 else
813 #endif
814 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
815 0, crfD(ctx->opcode));
816 }
817
818 /* cmpli */
819 GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
820 {
821 #if defined(TARGET_PPC64)
822 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
823 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
824 0, crfD(ctx->opcode));
825 else
826 #endif
827 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
828 0, crfD(ctx->opcode));
829 }
830
831 /* isel (PowerPC 2.03 specification) */
832 GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL)
833 {
834 int l1, l2;
835 uint32_t bi = rC(ctx->opcode);
836 uint32_t mask;
837 TCGv_i32 t0;
838
839 l1 = gen_new_label();
840 l2 = gen_new_label();
841
842 mask = 1 << (3 - (bi & 0x03));
843 t0 = tcg_temp_new_i32();
844 tcg_gen_andi_i32(t0, cpu_crf[bi >> 2], mask);
845 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
846 if (rA(ctx->opcode) == 0)
847 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
848 else
849 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
850 tcg_gen_br(l2);
851 gen_set_label(l1);
852 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
853 gen_set_label(l2);
854 tcg_temp_free_i32(t0);
855 }
856
857 /*** Integer arithmetic ***/
858
859 static always_inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0, TCGv arg1, TCGv arg2, int sub)
860 {
861 int l1;
862 TCGv t0;
863
864 l1 = gen_new_label();
865 /* Start with XER OV disabled, the most likely case */
866 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
867 t0 = tcg_temp_local_new();
868 tcg_gen_xor_tl(t0, arg0, arg1);
869 #if defined(TARGET_PPC64)
870 if (!ctx->sf_mode)
871 tcg_gen_ext32s_tl(t0, t0);
872 #endif
873 if (sub)
874 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0, l1);
875 else
876 tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
877 tcg_gen_xor_tl(t0, arg1, arg2);
878 #if defined(TARGET_PPC64)
879 if (!ctx->sf_mode)
880 tcg_gen_ext32s_tl(t0, t0);
881 #endif
882 if (sub)
883 tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
884 else
885 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0, l1);
886 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
887 gen_set_label(l1);
888 tcg_temp_free(t0);
889 }
890
891 static always_inline void gen_op_arith_compute_ca(DisasContext *ctx, TCGv arg1, TCGv arg2, int sub)
892 {
893 int l1 = gen_new_label();
894
895 #if defined(TARGET_PPC64)
896 if (!(ctx->sf_mode)) {
897 TCGv t0, t1;
898 t0 = tcg_temp_new();
899 t1 = tcg_temp_new();
900
901 tcg_gen_ext32u_tl(t0, arg1);
902 tcg_gen_ext32u_tl(t1, arg2);
903 if (sub) {
904 tcg_gen_brcond_tl(TCG_COND_GTU, t0, t1, l1);
905 } else {
906 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
907 }
908 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
909 gen_set_label(l1);
910 tcg_temp_free(t0);
911 tcg_temp_free(t1);
912 } else
913 #endif
914 {
915 if (sub) {
916 tcg_gen_brcond_tl(TCG_COND_GTU, arg1, arg2, l1);
917 } else {
918 tcg_gen_brcond_tl(TCG_COND_GEU, arg1, arg2, l1);
919 }
920 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
921 gen_set_label(l1);
922 }
923 }
924
925 /* Common add function */
926 static always_inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
927 int add_ca, int compute_ca, int compute_ov)
928 {
929 TCGv t0, t1;
930
931 if ((!compute_ca && !compute_ov) ||
932 (!TCGV_EQUAL(ret,arg1) && !TCGV_EQUAL(ret, arg2))) {
933 t0 = ret;
934 } else {
935 t0 = tcg_temp_local_new();
936 }
937
938 if (add_ca) {
939 t1 = tcg_temp_local_new();
940 tcg_gen_andi_tl(t1, cpu_xer, (1 << XER_CA));
941 tcg_gen_shri_tl(t1, t1, XER_CA);
942 }
943
944 if (compute_ca && compute_ov) {
945 /* Start with XER CA and OV disabled, the most likely case */
946 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~((1 << XER_CA) | (1 << XER_OV)));
947 } else if (compute_ca) {
948 /* Start with XER CA disabled, the most likely case */
949 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
950 } else if (compute_ov) {
951 /* Start with XER OV disabled, the most likely case */
952 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
953 }
954
955 tcg_gen_add_tl(t0, arg1, arg2);
956
957 if (compute_ca) {
958 gen_op_arith_compute_ca(ctx, t0, arg1, 0);
959 }
960 if (add_ca) {
961 tcg_gen_add_tl(t0, t0, t1);
962 gen_op_arith_compute_ca(ctx, t0, t1, 0);
963 tcg_temp_free(t1);
964 }
965 if (compute_ov) {
966 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0);
967 }
968
969 if (unlikely(Rc(ctx->opcode) != 0))
970 gen_set_Rc0(ctx, t0);
971
972 if (!TCGV_EQUAL(t0, ret)) {
973 tcg_gen_mov_tl(ret, t0);
974 tcg_temp_free(t0);
975 }
976 }
977 /* Add functions with two operands */
978 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
979 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER) \
980 { \
981 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
982 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
983 add_ca, compute_ca, compute_ov); \
984 }
985 /* Add functions with one operand and one immediate */
986 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
987 add_ca, compute_ca, compute_ov) \
988 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER) \
989 { \
990 TCGv t0 = tcg_const_local_tl(const_val); \
991 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
992 cpu_gpr[rA(ctx->opcode)], t0, \
993 add_ca, compute_ca, compute_ov); \
994 tcg_temp_free(t0); \
995 }
996
997 /* add add. addo addo. */
998 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
999 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
1000 /* addc addc. addco addco. */
1001 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
1002 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
1003 /* adde adde. addeo addeo. */
1004 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
1005 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
1006 /* addme addme. addmeo addmeo. */
1007 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
1008 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
1009 /* addze addze. addzeo addzeo.*/
1010 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
1011 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
1012 /* addi */
1013 GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1014 {
1015 target_long simm = SIMM(ctx->opcode);
1016
1017 if (rA(ctx->opcode) == 0) {
1018 /* li case */
1019 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm);
1020 } else {
1021 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], simm);
1022 }
1023 }
1024 /* addic addic.*/
1025 static always_inline void gen_op_addic (DisasContext *ctx, TCGv ret, TCGv arg1,
1026 int compute_Rc0)
1027 {
1028 target_long simm = SIMM(ctx->opcode);
1029
1030 /* Start with XER CA and OV disabled, the most likely case */
1031 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1032
1033 if (likely(simm != 0)) {
1034 TCGv t0 = tcg_temp_local_new();
1035 tcg_gen_addi_tl(t0, arg1, simm);
1036 gen_op_arith_compute_ca(ctx, t0, arg1, 0);
1037 tcg_gen_mov_tl(ret, t0);
1038 tcg_temp_free(t0);
1039 } else {
1040 tcg_gen_mov_tl(ret, arg1);
1041 }
1042 if (compute_Rc0) {
1043 gen_set_Rc0(ctx, ret);
1044 }
1045 }
1046 GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1047 {
1048 gen_op_addic(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0);
1049 }
1050 GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1051 {
1052 gen_op_addic(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1);
1053 }
1054 /* addis */
1055 GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1056 {
1057 target_long simm = SIMM(ctx->opcode);
1058
1059 if (rA(ctx->opcode) == 0) {
1060 /* lis case */
1061 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16);
1062 } else {
1063 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], simm << 16);
1064 }
1065 }
1066
1067 static always_inline void gen_op_arith_divw (DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
1068 int sign, int compute_ov)
1069 {
1070 int l1 = gen_new_label();
1071 int l2 = gen_new_label();
1072 TCGv_i32 t0 = tcg_temp_local_new_i32();
1073 TCGv_i32 t1 = tcg_temp_local_new_i32();
1074
1075 tcg_gen_trunc_tl_i32(t0, arg1);
1076 tcg_gen_trunc_tl_i32(t1, arg2);
1077 tcg_gen_brcondi_i32(TCG_COND_EQ, t1, 0, l1);
1078 if (sign) {
1079 int l3 = gen_new_label();
1080 tcg_gen_brcondi_i32(TCG_COND_NE, t1, -1, l3);
1081 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, INT32_MIN, l1);
1082 gen_set_label(l3);
1083 tcg_gen_div_i32(t0, t0, t1);
1084 } else {
1085 tcg_gen_divu_i32(t0, t0, t1);
1086 }
1087 if (compute_ov) {
1088 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1089 }
1090 tcg_gen_br(l2);
1091 gen_set_label(l1);
1092 if (sign) {
1093 tcg_gen_sari_i32(t0, t0, 31);
1094 } else {
1095 tcg_gen_movi_i32(t0, 0);
1096 }
1097 if (compute_ov) {
1098 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1099 }
1100 gen_set_label(l2);
1101 tcg_gen_extu_i32_tl(ret, t0);
1102 tcg_temp_free_i32(t0);
1103 tcg_temp_free_i32(t1);
1104 if (unlikely(Rc(ctx->opcode) != 0))
1105 gen_set_Rc0(ctx, ret);
1106 }
1107 /* Div functions */
1108 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
1109 GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER) \
1110 { \
1111 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
1112 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1113 sign, compute_ov); \
1114 }
1115 /* divwu divwu. divwuo divwuo. */
1116 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0);
1117 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1);
1118 /* divw divw. divwo divwo. */
1119 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0);
1120 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
1121 #if defined(TARGET_PPC64)
1122 static always_inline void gen_op_arith_divd (DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
1123 int sign, int compute_ov)
1124 {
1125 int l1 = gen_new_label();
1126 int l2 = gen_new_label();
1127
1128 tcg_gen_brcondi_i64(TCG_COND_EQ, arg2, 0, l1);
1129 if (sign) {
1130 int l3 = gen_new_label();
1131 tcg_gen_brcondi_i64(TCG_COND_NE, arg2, -1, l3);
1132 tcg_gen_brcondi_i64(TCG_COND_EQ, arg1, INT64_MIN, l1);
1133 gen_set_label(l3);
1134 tcg_gen_div_i64(ret, arg1, arg2);
1135 } else {
1136 tcg_gen_divu_i64(ret, arg1, arg2);
1137 }
1138 if (compute_ov) {
1139 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1140 }
1141 tcg_gen_br(l2);
1142 gen_set_label(l1);
1143 if (sign) {
1144 tcg_gen_sari_i64(ret, arg1, 63);
1145 } else {
1146 tcg_gen_movi_i64(ret, 0);
1147 }
1148 if (compute_ov) {
1149 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1150 }
1151 gen_set_label(l2);
1152 if (unlikely(Rc(ctx->opcode) != 0))
1153 gen_set_Rc0(ctx, ret);
1154 }
1155 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
1156 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) \
1157 { \
1158 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \
1159 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1160 sign, compute_ov); \
1161 }
1162 /* divwu divwu. divwuo divwuo. */
1163 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0);
1164 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1);
1165 /* divw divw. divwo divwo. */
1166 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0);
1167 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1);
1168 #endif
1169
1170 /* mulhw mulhw. */
1171 GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER)
1172 {
1173 TCGv_i64 t0, t1;
1174
1175 t0 = tcg_temp_new_i64();
1176 t1 = tcg_temp_new_i64();
1177 #if defined(TARGET_PPC64)
1178 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
1179 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
1180 tcg_gen_mul_i64(t0, t0, t1);
1181 tcg_gen_shri_i64(cpu_gpr[rD(ctx->opcode)], t0, 32);
1182 #else
1183 tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1184 tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1185 tcg_gen_mul_i64(t0, t0, t1);
1186 tcg_gen_shri_i64(t0, t0, 32);
1187 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
1188 #endif
1189 tcg_temp_free_i64(t0);
1190 tcg_temp_free_i64(t1);
1191 if (unlikely(Rc(ctx->opcode) != 0))
1192 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1193 }
1194 /* mulhwu mulhwu. */
1195 GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER)
1196 {
1197 TCGv_i64 t0, t1;
1198
1199 t0 = tcg_temp_new_i64();
1200 t1 = tcg_temp_new_i64();
1201 #if defined(TARGET_PPC64)
1202 tcg_gen_ext32u_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1203 tcg_gen_ext32u_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1204 tcg_gen_mul_i64(t0, t0, t1);
1205 tcg_gen_shri_i64(cpu_gpr[rD(ctx->opcode)], t0, 32);
1206 #else
1207 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1208 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1209 tcg_gen_mul_i64(t0, t0, t1);
1210 tcg_gen_shri_i64(t0, t0, 32);
1211 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
1212 #endif
1213 tcg_temp_free_i64(t0);
1214 tcg_temp_free_i64(t1);
1215 if (unlikely(Rc(ctx->opcode) != 0))
1216 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1217 }
1218 /* mullw mullw. */
1219 GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER)
1220 {
1221 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1222 cpu_gpr[rB(ctx->opcode)]);
1223 tcg_gen_ext32s_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)]);
1224 if (unlikely(Rc(ctx->opcode) != 0))
1225 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1226 }
1227 /* mullwo mullwo. */
1228 GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER)
1229 {
1230 int l1;
1231 TCGv_i64 t0, t1;
1232
1233 t0 = tcg_temp_new_i64();
1234 t1 = tcg_temp_new_i64();
1235 l1 = gen_new_label();
1236 /* Start with XER OV disabled, the most likely case */
1237 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1238 #if defined(TARGET_PPC64)
1239 tcg_gen_ext32s_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1240 tcg_gen_ext32s_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1241 #else
1242 tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1243 tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1244 #endif
1245 tcg_gen_mul_i64(t0, t0, t1);
1246 #if defined(TARGET_PPC64)
1247 tcg_gen_ext32s_i64(cpu_gpr[rD(ctx->opcode)], t0);
1248 tcg_gen_brcond_i64(TCG_COND_EQ, t0, cpu_gpr[rD(ctx->opcode)], l1);
1249 #else
1250 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
1251 tcg_gen_ext32s_i64(t1, t0);
1252 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
1253 #endif
1254 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1255 gen_set_label(l1);
1256 tcg_temp_free_i64(t0);
1257 tcg_temp_free_i64(t1);
1258 if (unlikely(Rc(ctx->opcode) != 0))
1259 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1260 }
1261 /* mulli */
1262 GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1263 {
1264 tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1265 SIMM(ctx->opcode));
1266 }
1267 #if defined(TARGET_PPC64)
1268 #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
1269 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) \
1270 { \
1271 gen_helper_##name (cpu_gpr[rD(ctx->opcode)], \
1272 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
1273 if (unlikely(Rc(ctx->opcode) != 0)) \
1274 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \
1275 }
1276 /* mulhd mulhd. */
1277 GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00);
1278 /* mulhdu mulhdu. */
1279 GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02);
1280 /* mulld mulld. */
1281 GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B)
1282 {
1283 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1284 cpu_gpr[rB(ctx->opcode)]);
1285 if (unlikely(Rc(ctx->opcode) != 0))
1286 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1287 }
1288 /* mulldo mulldo. */
1289 GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17);
1290 #endif
1291
1292 /* neg neg. nego nego. */
1293 static always_inline void gen_op_arith_neg (DisasContext *ctx, TCGv ret, TCGv arg1, int ov_check)
1294 {
1295 int l1 = gen_new_label();
1296 int l2 = gen_new_label();
1297 TCGv t0 = tcg_temp_local_new();
1298 #if defined(TARGET_PPC64)
1299 if (ctx->sf_mode) {
1300 tcg_gen_mov_tl(t0, arg1);
1301 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, INT64_MIN, l1);
1302 } else
1303 #endif
1304 {
1305 tcg_gen_ext32s_tl(t0, arg1);
1306 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, INT32_MIN, l1);
1307 }
1308 tcg_gen_neg_tl(ret, arg1);
1309 if (ov_check) {
1310 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1311 }
1312 tcg_gen_br(l2);
1313 gen_set_label(l1);
1314 tcg_gen_mov_tl(ret, t0);
1315 if (ov_check) {
1316 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1317 }
1318 gen_set_label(l2);
1319 tcg_temp_free(t0);
1320 if (unlikely(Rc(ctx->opcode) != 0))
1321 gen_set_Rc0(ctx, ret);
1322 }
1323 GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER)
1324 {
1325 gen_op_arith_neg(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0);
1326 }
1327 GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER)
1328 {
1329 gen_op_arith_neg(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1);
1330 }
1331
1332 /* Common subf function */
1333 static always_inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
1334 int add_ca, int compute_ca, int compute_ov)
1335 {
1336 TCGv t0, t1;
1337
1338 if ((!compute_ca && !compute_ov) ||
1339 (!TCGV_EQUAL(ret, arg1) && !TCGV_EQUAL(ret, arg2))) {
1340 t0 = ret;
1341 } else {
1342 t0 = tcg_temp_local_new();
1343 }
1344
1345 if (add_ca) {
1346 t1 = tcg_temp_local_new();
1347 tcg_gen_andi_tl(t1, cpu_xer, (1 << XER_CA));
1348 tcg_gen_shri_tl(t1, t1, XER_CA);
1349 }
1350
1351 if (compute_ca && compute_ov) {
1352 /* Start with XER CA and OV disabled, the most likely case */
1353 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~((1 << XER_CA) | (1 << XER_OV)));
1354 } else if (compute_ca) {
1355 /* Start with XER CA disabled, the most likely case */
1356 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1357 } else if (compute_ov) {
1358 /* Start with XER OV disabled, the most likely case */
1359 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1360 }
1361
1362 if (add_ca) {
1363 tcg_gen_not_tl(t0, arg1);
1364 tcg_gen_add_tl(t0, t0, arg2);
1365 gen_op_arith_compute_ca(ctx, t0, arg2, 0);
1366 tcg_gen_add_tl(t0, t0, t1);
1367 gen_op_arith_compute_ca(ctx, t0, t1, 0);
1368 tcg_temp_free(t1);
1369 } else {
1370 tcg_gen_sub_tl(t0, arg2, arg1);
1371 if (compute_ca) {
1372 gen_op_arith_compute_ca(ctx, t0, arg2, 1);
1373 }
1374 }
1375 if (compute_ov) {
1376 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1);
1377 }
1378
1379 if (unlikely(Rc(ctx->opcode) != 0))
1380 gen_set_Rc0(ctx, t0);
1381
1382 if (!TCGV_EQUAL(t0, ret)) {
1383 tcg_gen_mov_tl(ret, t0);
1384 tcg_temp_free(t0);
1385 }
1386 }
1387 /* Sub functions with Two operands functions */
1388 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
1389 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER) \
1390 { \
1391 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1392 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1393 add_ca, compute_ca, compute_ov); \
1394 }
1395 /* Sub functions with one operand and one immediate */
1396 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
1397 add_ca, compute_ca, compute_ov) \
1398 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER) \
1399 { \
1400 TCGv t0 = tcg_const_local_tl(const_val); \
1401 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1402 cpu_gpr[rA(ctx->opcode)], t0, \
1403 add_ca, compute_ca, compute_ov); \
1404 tcg_temp_free(t0); \
1405 }
1406 /* subf subf. subfo subfo. */
1407 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
1408 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
1409 /* subfc subfc. subfco subfco. */
1410 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
1411 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
1412 /* subfe subfe. subfeo subfo. */
1413 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
1414 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
1415 /* subfme subfme. subfmeo subfmeo. */
1416 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
1417 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
1418 /* subfze subfze. subfzeo subfzeo.*/
1419 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
1420 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
1421 /* subfic */
1422 GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1423 {
1424 /* Start with XER CA and OV disabled, the most likely case */
1425 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1426 TCGv t0 = tcg_temp_local_new();
1427 TCGv t1 = tcg_const_local_tl(SIMM(ctx->opcode));
1428 tcg_gen_sub_tl(t0, t1, cpu_gpr[rA(ctx->opcode)]);
1429 gen_op_arith_compute_ca(ctx, t0, t1, 1);
1430 tcg_temp_free(t1);
1431 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
1432 tcg_temp_free(t0);
1433 }
1434
1435 /*** Integer logical ***/
1436 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
1437 GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type) \
1438 { \
1439 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
1440 cpu_gpr[rB(ctx->opcode)]); \
1441 if (unlikely(Rc(ctx->opcode) != 0)) \
1442 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1443 }
1444
1445 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
1446 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type) \
1447 { \
1448 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
1449 if (unlikely(Rc(ctx->opcode) != 0)) \
1450 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1451 }
1452
1453 /* and & and. */
1454 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER);
1455 /* andc & andc. */
1456 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER);
1457 /* andi. */
1458 GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1459 {
1460 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode));
1461 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1462 }
1463 /* andis. */
1464 GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1465 {
1466 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16);
1467 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1468 }
1469 /* cntlzw */
1470 GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER)
1471 {
1472 gen_helper_cntlzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1473 if (unlikely(Rc(ctx->opcode) != 0))
1474 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1475 }
1476 /* eqv & eqv. */
1477 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
1478 /* extsb & extsb. */
1479 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER);
1480 /* extsh & extsh. */
1481 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER);
1482 /* nand & nand. */
1483 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER);
1484 /* nor & nor. */
1485 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
1486 /* or & or. */
1487 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER)
1488 {
1489 int rs, ra, rb;
1490
1491 rs = rS(ctx->opcode);
1492 ra = rA(ctx->opcode);
1493 rb = rB(ctx->opcode);
1494 /* Optimisation for mr. ri case */
1495 if (rs != ra || rs != rb) {
1496 if (rs != rb)
1497 tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]);
1498 else
1499 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]);
1500 if (unlikely(Rc(ctx->opcode) != 0))
1501 gen_set_Rc0(ctx, cpu_gpr[ra]);
1502 } else if (unlikely(Rc(ctx->opcode) != 0)) {
1503 gen_set_Rc0(ctx, cpu_gpr[rs]);
1504 #if defined(TARGET_PPC64)
1505 } else {
1506 int prio = 0;
1507
1508 switch (rs) {
1509 case 1:
1510 /* Set process priority to low */
1511 prio = 2;
1512 break;
1513 case 6:
1514 /* Set process priority to medium-low */
1515 prio = 3;
1516 break;
1517 case 2:
1518 /* Set process priority to normal */
1519 prio = 4;
1520 break;
1521 #if !defined(CONFIG_USER_ONLY)
1522 case 31:
1523 if (ctx->mem_idx > 0) {
1524 /* Set process priority to very low */
1525 prio = 1;
1526 }
1527 break;
1528 case 5:
1529 if (ctx->mem_idx > 0) {
1530 /* Set process priority to medium-hight */
1531 prio = 5;
1532 }
1533 break;
1534 case 3:
1535 if (ctx->mem_idx > 0) {
1536 /* Set process priority to high */
1537 prio = 6;
1538 }
1539 break;
1540 case 7:
1541 if (ctx->mem_idx > 1) {
1542 /* Set process priority to very high */
1543 prio = 7;
1544 }
1545 break;
1546 #endif
1547 default:
1548 /* nop */
1549 break;
1550 }
1551 if (prio) {
1552 TCGv t0 = tcg_temp_new();
1553 gen_load_spr(t0, SPR_PPR);
1554 tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL);
1555 tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
1556 gen_store_spr(SPR_PPR, t0);
1557 tcg_temp_free(t0);
1558 }
1559 #endif
1560 }
1561 }
1562 /* orc & orc. */
1563 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER);
1564 /* xor & xor. */
1565 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER)
1566 {
1567 /* Optimisation for "set to zero" case */
1568 if (rS(ctx->opcode) != rB(ctx->opcode))
1569 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1570 else
1571 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1572 if (unlikely(Rc(ctx->opcode) != 0))
1573 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1574 }
1575 /* ori */
1576 GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1577 {
1578 target_ulong uimm = UIMM(ctx->opcode);
1579
1580 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1581 /* NOP */
1582 /* XXX: should handle special NOPs for POWER series */
1583 return;
1584 }
1585 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1586 }
1587 /* oris */
1588 GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1589 {
1590 target_ulong uimm = UIMM(ctx->opcode);
1591
1592 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1593 /* NOP */
1594 return;
1595 }
1596 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1597 }
1598 /* xori */
1599 GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1600 {
1601 target_ulong uimm = UIMM(ctx->opcode);
1602
1603 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1604 /* NOP */
1605 return;
1606 }
1607 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1608 }
1609 /* xoris */
1610 GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1611 {
1612 target_ulong uimm = UIMM(ctx->opcode);
1613
1614 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1615 /* NOP */
1616 return;
1617 }
1618 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1619 }
1620 /* popcntb : PowerPC 2.03 specification */
1621 GEN_HANDLER(popcntb, 0x1F, 0x03, 0x03, 0x0000F801, PPC_POPCNTB)
1622 {
1623 #if defined(TARGET_PPC64)
1624 if (ctx->sf_mode)
1625 gen_helper_popcntb_64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1626 else
1627 #endif
1628 gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1629 }
1630
1631 #if defined(TARGET_PPC64)
1632 /* extsw & extsw. */
1633 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
1634 /* cntlzd */
1635 GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B)
1636 {
1637 gen_helper_cntlzd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1638 if (unlikely(Rc(ctx->opcode) != 0))
1639 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1640 }
1641 #endif
1642
1643 /*** Integer rotate ***/
1644 /* rlwimi & rlwimi. */
1645 GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1646 {
1647 uint32_t mb, me, sh;
1648
1649 mb = MB(ctx->opcode);
1650 me = ME(ctx->opcode);
1651 sh = SH(ctx->opcode);
1652 if (likely(sh == 0 && mb == 0 && me == 31)) {
1653 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1654 } else {
1655 target_ulong mask;
1656 TCGv t1;
1657 TCGv t0 = tcg_temp_new();
1658 #if defined(TARGET_PPC64)
1659 TCGv_i32 t2 = tcg_temp_new_i32();
1660 tcg_gen_trunc_i64_i32(t2, cpu_gpr[rS(ctx->opcode)]);
1661 tcg_gen_rotli_i32(t2, t2, sh);
1662 tcg_gen_extu_i32_i64(t0, t2);
1663 tcg_temp_free_i32(t2);
1664 #else
1665 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1666 #endif
1667 #if defined(TARGET_PPC64)
1668 mb += 32;
1669 me += 32;
1670 #endif
1671 mask = MASK(mb, me);
1672 t1 = tcg_temp_new();
1673 tcg_gen_andi_tl(t0, t0, mask);
1674 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1675 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1676 tcg_temp_free(t0);
1677 tcg_temp_free(t1);
1678 }
1679 if (unlikely(Rc(ctx->opcode) != 0))
1680 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1681 }
1682 /* rlwinm & rlwinm. */
1683 GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1684 {
1685 uint32_t mb, me, sh;
1686
1687 sh = SH(ctx->opcode);
1688 mb = MB(ctx->opcode);
1689 me = ME(ctx->opcode);
1690
1691 if (likely(mb == 0 && me == (31 - sh))) {
1692 if (likely(sh == 0)) {
1693 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1694 } else {
1695 TCGv t0 = tcg_temp_new();
1696 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1697 tcg_gen_shli_tl(t0, t0, sh);
1698 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1699 tcg_temp_free(t0);
1700 }
1701 } else if (likely(sh != 0 && me == 31 && sh == (32 - mb))) {
1702 TCGv t0 = tcg_temp_new();
1703 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1704 tcg_gen_shri_tl(t0, t0, mb);
1705 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1706 tcg_temp_free(t0);
1707 } else {
1708 TCGv t0 = tcg_temp_new();
1709 #if defined(TARGET_PPC64)
1710 TCGv_i32 t1 = tcg_temp_new_i32();
1711 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1712 tcg_gen_rotli_i32(t1, t1, sh);
1713 tcg_gen_extu_i32_i64(t0, t1);
1714 tcg_temp_free_i32(t1);
1715 #else
1716 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1717 #endif
1718 #if defined(TARGET_PPC64)
1719 mb += 32;
1720 me += 32;
1721 #endif
1722 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1723 tcg_temp_free(t0);
1724 }
1725 if (unlikely(Rc(ctx->opcode) != 0))
1726 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1727 }
1728 /* rlwnm & rlwnm. */
1729 GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1730 {
1731 uint32_t mb, me;
1732 TCGv t0;
1733 #if defined(TARGET_PPC64)
1734 TCGv_i32 t1, t2;
1735 #endif
1736
1737 mb = MB(ctx->opcode);
1738 me = ME(ctx->opcode);
1739 t0 = tcg_temp_new();
1740 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1f);
1741 #if defined(TARGET_PPC64)
1742 t1 = tcg_temp_new_i32();
1743 t2 = tcg_temp_new_i32();
1744 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1745 tcg_gen_trunc_i64_i32(t2, t0);
1746 tcg_gen_rotl_i32(t1, t1, t2);
1747 tcg_gen_extu_i32_i64(t0, t1);
1748 tcg_temp_free_i32(t1);
1749 tcg_temp_free_i32(t2);
1750 #else
1751 tcg_gen_rotl_i32(t0, cpu_gpr[rS(ctx->opcode)], t0);
1752 #endif
1753 if (unlikely(mb != 0 || me != 31)) {
1754 #if defined(TARGET_PPC64)
1755 mb += 32;
1756 me += 32;
1757 #endif
1758 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1759 } else {
1760 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1761 }
1762 tcg_temp_free(t0);
1763 if (unlikely(Rc(ctx->opcode) != 0))
1764 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1765 }
1766
1767 #if defined(TARGET_PPC64)
1768 #define GEN_PPC64_R2(name, opc1, opc2) \
1769 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B) \
1770 { \
1771 gen_##name(ctx, 0); \
1772 } \
1773 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
1774 PPC_64B) \
1775 { \
1776 gen_##name(ctx, 1); \
1777 }
1778 #define GEN_PPC64_R4(name, opc1, opc2) \
1779 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B) \
1780 { \
1781 gen_##name(ctx, 0, 0); \
1782 } \
1783 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
1784 PPC_64B) \
1785 { \
1786 gen_##name(ctx, 0, 1); \
1787 } \
1788 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
1789 PPC_64B) \
1790 { \
1791 gen_##name(ctx, 1, 0); \
1792 } \
1793 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
1794 PPC_64B) \
1795 { \
1796 gen_##name(ctx, 1, 1); \
1797 }
1798
1799 static always_inline void gen_rldinm (DisasContext *ctx, uint32_t mb,
1800 uint32_t me, uint32_t sh)
1801 {
1802 if (likely(sh != 0 && mb == 0 && me == (63 - sh))) {
1803 tcg_gen_shli_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
1804 } else if (likely(sh != 0 && me == 63 && sh == (64 - mb))) {
1805 tcg_gen_shri_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], mb);
1806 } else {
1807 TCGv t0 = tcg_temp_new();
1808 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
1809 if (likely(mb == 0 && me == 63)) {
1810 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1811 } else {
1812 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1813 }
1814 tcg_temp_free(t0);
1815 }
1816 if (unlikely(Rc(ctx->opcode) != 0))
1817 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1818 }
1819 /* rldicl - rldicl. */
1820 static always_inline void gen_rldicl (DisasContext *ctx, int mbn, int shn)
1821 {
1822 uint32_t sh, mb;
1823
1824 sh = SH(ctx->opcode) | (shn << 5);
1825 mb = MB(ctx->opcode) | (mbn << 5);
1826 gen_rldinm(ctx, mb, 63, sh);
1827 }
1828 GEN_PPC64_R4(rldicl, 0x1E, 0x00);
1829 /* rldicr - rldicr. */
1830 static always_inline void gen_rldicr (DisasContext *ctx, int men, int shn)
1831 {
1832 uint32_t sh, me;
1833
1834 sh = SH(ctx->opcode) | (shn << 5);
1835 me = MB(ctx->opcode) | (men << 5);
1836 gen_rldinm(ctx, 0, me, sh);
1837 }
1838 GEN_PPC64_R4(rldicr, 0x1E, 0x02);
1839 /* rldic - rldic. */
1840 static always_inline void gen_rldic (DisasContext *ctx, int mbn, int shn)
1841 {
1842 uint32_t sh, mb;
1843
1844 sh = SH(ctx->opcode) | (shn << 5);
1845 mb = MB(ctx->opcode) | (mbn << 5);
1846 gen_rldinm(ctx, mb, 63 - sh, sh);
1847 }
1848 GEN_PPC64_R4(rldic, 0x1E, 0x04);
1849
1850 static always_inline void gen_rldnm (DisasContext *ctx, uint32_t mb,
1851 uint32_t me)
1852 {
1853 TCGv t0;
1854
1855 mb = MB(ctx->opcode);
1856 me = ME(ctx->opcode);
1857 t0 = tcg_temp_new();
1858 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
1859 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1860 if (unlikely(mb != 0 || me != 63)) {
1861 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1862 } else {
1863 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1864 }
1865 tcg_temp_free(t0);
1866 if (unlikely(Rc(ctx->opcode) != 0))
1867 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1868 }
1869
1870 /* rldcl - rldcl. */
1871 static always_inline void gen_rldcl (DisasContext *ctx, int mbn)
1872 {
1873 uint32_t mb;
1874
1875 mb = MB(ctx->opcode) | (mbn << 5);
1876 gen_rldnm(ctx, mb, 63);
1877 }
1878 GEN_PPC64_R2(rldcl, 0x1E, 0x08);
1879 /* rldcr - rldcr. */
1880 static always_inline void gen_rldcr (DisasContext *ctx, int men)
1881 {
1882 uint32_t me;
1883
1884 me = MB(ctx->opcode) | (men << 5);
1885 gen_rldnm(ctx, 0, me);
1886 }
1887 GEN_PPC64_R2(rldcr, 0x1E, 0x09);
1888 /* rldimi - rldimi. */
1889 static always_inline void gen_rldimi (DisasContext *ctx, int mbn, int shn)
1890 {
1891 uint32_t sh, mb, me;
1892
1893 sh = SH(ctx->opcode) | (shn << 5);
1894 mb = MB(ctx->opcode) | (mbn << 5);
1895 me = 63 - sh;
1896 if (unlikely(sh == 0 && mb == 0)) {
1897 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1898 } else {
1899 TCGv t0, t1;
1900 target_ulong mask;
1901
1902 t0 = tcg_temp_new();
1903 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
1904 t1 = tcg_temp_new();
1905 mask = MASK(mb, me);
1906 tcg_gen_andi_tl(t0, t0, mask);
1907 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1908 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1909 tcg_temp_free(t0);
1910 tcg_temp_free(t1);
1911 }
1912 if (unlikely(Rc(ctx->opcode) != 0))
1913 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1914 }
1915 GEN_PPC64_R4(rldimi, 0x1E, 0x06);
1916 #endif
1917
1918 /*** Integer shift ***/
1919 /* slw & slw. */
1920 GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER)
1921 {
1922 TCGv t0;
1923 int l1, l2;
1924 l1 = gen_new_label();
1925 l2 = gen_new_label();
1926
1927 t0 = tcg_temp_local_new();
1928 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
1929 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x20, l1);
1930 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1931 tcg_gen_br(l2);
1932 gen_set_label(l1);
1933 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t0);
1934 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
1935 gen_set_label(l2);
1936 tcg_temp_free(t0);
1937 if (unlikely(Rc(ctx->opcode) != 0))
1938 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1939 }
1940 /* sraw & sraw. */
1941 GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER)
1942 {
1943 gen_helper_sraw(cpu_gpr[rA(ctx->opcode)],
1944 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1945 if (unlikely(Rc(ctx->opcode) != 0))
1946 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1947 }
1948 /* srawi & srawi. */
1949 GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER)
1950 {
1951 int sh = SH(ctx->opcode);
1952 if (sh != 0) {
1953 int l1, l2;
1954 TCGv t0;
1955 l1 = gen_new_label();
1956 l2 = gen_new_label();
1957 t0 = tcg_temp_local_new();
1958 tcg_gen_ext32s_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1959 tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
1960 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1ULL << sh) - 1);
1961 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
1962 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
1963 tcg_gen_br(l2);
1964 gen_set_label(l1);
1965 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1966 gen_set_label(l2);
1967 tcg_gen_ext32s_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1968 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], t0, sh);
1969 tcg_temp_free(t0);
1970 } else {
1971 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1972 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1973 }
1974 if (unlikely(Rc(ctx->opcode) != 0))
1975 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1976 }
1977 /* srw & srw. */
1978 GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER)
1979 {
1980 TCGv t0, t1;
1981 int l1, l2;
1982 l1 = gen_new_label();
1983 l2 = gen_new_label();
1984
1985 t0 = tcg_temp_local_new();
1986 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
1987 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x20, l1);
1988 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1989 tcg_gen_br(l2);
1990 gen_set_label(l1);
1991 t1 = tcg_temp_new();
1992 tcg_gen_ext32u_tl(t1, cpu_gpr[rS(ctx->opcode)]);
1993 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t1, t0);
1994 tcg_temp_free(t1);
1995 gen_set_label(l2);
1996 tcg_temp_free(t0);
1997 if (unlikely(Rc(ctx->opcode) != 0))
1998 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1999 }
2000 #if defined(TARGET_PPC64)
2001 /* sld & sld. */
2002 GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B)
2003 {
2004 TCGv t0;
2005 int l1, l2;
2006 l1 = gen_new_label();
2007 l2 = gen_new_label();
2008
2009 t0 = tcg_temp_local_new();
2010 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x7f);
2011 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x40, l1);
2012 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
2013 tcg_gen_br(l2);
2014 gen_set_label(l1);
2015 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t0);
2016 gen_set_label(l2);
2017 tcg_temp_free(t0);
2018 if (unlikely(Rc(ctx->opcode) != 0))
2019 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2020 }
2021 /* srad & srad. */
2022 GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B)
2023 {
2024 gen_helper_srad(cpu_gpr[rA(ctx->opcode)],
2025 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2026 if (unlikely(Rc(ctx->opcode) != 0))
2027 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2028 }
2029 /* sradi & sradi. */
2030 static always_inline void gen_sradi (DisasContext *ctx, int n)
2031 {
2032 int sh = SH(ctx->opcode) + (n << 5);
2033 if (sh != 0) {
2034 int l1, l2;
2035 TCGv t0;
2036 l1 = gen_new_label();
2037 l2 = gen_new_label();
2038 t0 = tcg_temp_local_new();
2039 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
2040 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1ULL << sh) - 1);
2041 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
2042 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
2043 tcg_gen_br(l2);
2044 gen_set_label(l1);
2045 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
2046 gen_set_label(l2);
2047 tcg_temp_free(t0);
2048 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
2049 } else {
2050 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
2051 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
2052 }
2053 if (unlikely(Rc(ctx->opcode) != 0))
2054 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2055 }
2056 GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B)
2057 {
2058 gen_sradi(ctx, 0);
2059 }
2060 GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B)
2061 {
2062 gen_sradi(ctx, 1);
2063 }
2064 /* srd & srd. */
2065 GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B)
2066 {
2067 TCGv t0;
2068 int l1, l2;
2069 l1 = gen_new_label();
2070 l2 = gen_new_label();
2071
2072 t0 = tcg_temp_local_new();
2073 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x7f);
2074 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x40, l1);
2075 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
2076 tcg_gen_br(l2);
2077 gen_set_label(l1);
2078 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t0);
2079 gen_set_label(l2);
2080 tcg_temp_free(t0);
2081 if (unlikely(Rc(ctx->opcode) != 0))
2082 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2083 }
2084 #endif
2085
2086 /*** Floating-Point arithmetic ***/
2087 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
2088 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type) \
2089 { \
2090 if (unlikely(!ctx->fpu_enabled)) { \
2091 gen_exception(ctx, POWERPC_EXCP_FPU); \
2092 return; \
2093 } \
2094 /* NIP cannot be restored if the memory exception comes from an helper */ \
2095 gen_update_nip(ctx, ctx->nip - 4); \
2096 gen_reset_fpstatus(); \
2097 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], \
2098 cpu_fpr[rC(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
2099 if (isfloat) { \
2100 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); \
2101 } \
2102 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], set_fprf, \
2103 Rc(ctx->opcode) != 0); \
2104 }
2105
2106 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
2107 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \
2108 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type);
2109
2110 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2111 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) \
2112 { \
2113 if (unlikely(!ctx->fpu_enabled)) { \
2114 gen_exception(ctx, POWERPC_EXCP_FPU); \
2115 return; \
2116 } \
2117 /* NIP cannot be restored if the memory exception comes from an helper */ \
2118 gen_update_nip(ctx, ctx->nip - 4); \
2119 gen_reset_fpstatus(); \
2120 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], \
2121 cpu_fpr[rB(ctx->opcode)]); \
2122 if (isfloat) { \
2123 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); \
2124 } \
2125 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2126 set_fprf, Rc(ctx->opcode) != 0); \
2127 }
2128 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
2129 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2130 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2131
2132 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2133 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) \
2134 { \
2135 if (unlikely(!ctx->fpu_enabled)) { \
2136 gen_exception(ctx, POWERPC_EXCP_FPU); \
2137 return; \
2138 } \
2139 /* NIP cannot be restored if the memory exception comes from an helper */ \
2140 gen_update_nip(ctx, ctx->nip - 4); \
2141 gen_reset_fpstatus(); \
2142 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], \
2143 cpu_fpr[rC(ctx->opcode)]); \
2144 if (isfloat) { \
2145 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); \
2146 } \
2147 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2148 set_fprf, Rc(ctx->opcode) != 0); \
2149 }
2150 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
2151 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2152 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2153
2154 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
2155 GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type) \
2156 { \
2157 if (unlikely(!ctx->fpu_enabled)) { \
2158 gen_exception(ctx, POWERPC_EXCP_FPU); \
2159 return; \
2160 } \
2161 /* NIP cannot be restored if the memory exception comes from an helper */ \
2162 gen_update_nip(ctx, ctx->nip - 4); \
2163 gen_reset_fpstatus(); \
2164 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
2165 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2166 set_fprf, Rc(ctx->opcode) != 0); \
2167 }
2168
2169 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
2170 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type) \
2171 { \
2172 if (unlikely(!ctx->fpu_enabled)) { \
2173 gen_exception(ctx, POWERPC_EXCP_FPU); \
2174 return; \
2175 } \
2176 /* NIP cannot be restored if the memory exception comes from an helper */ \
2177 gen_update_nip(ctx, ctx->nip - 4); \
2178 gen_reset_fpstatus(); \
2179 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
2180 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2181 set_fprf, Rc(ctx->opcode) != 0); \
2182 }
2183
2184 /* fadd - fadds */
2185 GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT);
2186 /* fdiv - fdivs */
2187 GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT);
2188 /* fmul - fmuls */
2189 GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT);
2190
2191 /* fre */
2192 GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT);
2193
2194 /* fres */
2195 GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES);
2196
2197 /* frsqrte */
2198 GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE);
2199
2200 /* frsqrtes */
2201 GEN_HANDLER(frsqrtes, 0x3B, 0x1A, 0xFF, 0x001F07C0, PPC_FLOAT_FRSQRTES)
2202 {
2203 if (unlikely(!ctx->fpu_enabled)) {
2204 gen_exception(ctx, POWERPC_EXCP_FPU);
2205 return;
2206 }
2207 /* NIP cannot be restored if the memory exception comes from an helper */
2208 gen_update_nip(ctx, ctx->nip - 4);
2209 gen_reset_fpstatus();
2210 gen_helper_frsqrte(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2211 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]);
2212 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2213 }
2214
2215 /* fsel */
2216 _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL);
2217 /* fsub - fsubs */
2218 GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT);
2219 /* Optional: */
2220 /* fsqrt */
2221 GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT)
2222 {
2223 if (unlikely(!ctx->fpu_enabled)) {
2224 gen_exception(ctx, POWERPC_EXCP_FPU);
2225 return;
2226 }
2227 /* NIP cannot be restored if the memory exception comes from an helper */
2228 gen_update_nip(ctx, ctx->nip - 4);
2229 gen_reset_fpstatus();
2230 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2231 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2232 }
2233
2234 GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT)
2235 {
2236 if (unlikely(!ctx->fpu_enabled)) {
2237 gen_exception(ctx, POWERPC_EXCP_FPU);
2238 return;
2239 }
2240 /* NIP cannot be restored if the memory exception comes from an helper */
2241 gen_update_nip(ctx, ctx->nip - 4);
2242 gen_reset_fpstatus();
2243 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2244 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]);
2245 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2246 }
2247
2248 /*** Floating-Point multiply-and-add ***/
2249 /* fmadd - fmadds */
2250 GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT);
2251 /* fmsub - fmsubs */
2252 GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT);
2253 /* fnmadd - fnmadds */
2254 GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT);
2255 /* fnmsub - fnmsubs */
2256 GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT);
2257
2258 /*** Floating-Point round & convert ***/
2259 /* fctiw */
2260 GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT);
2261 /* fctiwz */
2262 GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT);
2263 /* frsp */
2264 GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT);
2265 #if defined(TARGET_PPC64)
2266 /* fcfid */
2267 GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B);
2268 /* fctid */
2269 GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B);
2270 /* fctidz */
2271 GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B);
2272 #endif
2273
2274 /* frin */
2275 GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT);
2276 /* friz */
2277 GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT);
2278 /* frip */
2279 GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT);
2280 /* frim */
2281 GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT);
2282
2283 /*** Floating-Point compare ***/
2284 /* fcmpo */
2285 GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT)
2286 {
2287 TCGv_i32 crf;
2288 if (unlikely(!ctx->fpu_enabled)) {
2289 gen_exception(ctx, POWERPC_EXCP_FPU);
2290 return;
2291 }
2292 /* NIP cannot be restored if the memory exception comes from an helper */
2293 gen_update_nip(ctx, ctx->nip - 4);
2294 gen_reset_fpstatus();
2295 crf = tcg_const_i32(crfD(ctx->opcode));
2296 gen_helper_fcmpo(cpu_fpr[rA(ctx->opcode)], cpu_fpr[rB(ctx->opcode)], crf);
2297 tcg_temp_free_i32(crf);
2298 gen_helper_float_check_status();
2299 }
2300
2301 /* fcmpu */
2302 GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT)
2303 {
2304 TCGv_i32 crf;
2305 if (unlikely(!ctx->fpu_enabled)) {
2306 gen_exception(ctx, POWERPC_EXCP_FPU);
2307 return;
2308 }
2309 /* NIP cannot be restored if the memory exception comes from an helper */
2310 gen_update_nip(ctx, ctx->nip - 4);
2311 gen_reset_fpstatus();
2312 crf = tcg_const_i32(crfD(ctx->opcode));
2313 gen_helper_fcmpu(cpu_fpr[rA(ctx->opcode)], cpu_fpr[rB(ctx->opcode)], crf);
2314 tcg_temp_free_i32(crf);
2315 gen_helper_float_check_status();
2316 }
2317
2318 /*** Floating-point move ***/
2319 /* fabs */
2320 /* XXX: beware that fabs never checks for NaNs nor update FPSCR */
2321 GEN_FLOAT_B(abs, 0x08, 0x08, 0, PPC_FLOAT);
2322
2323 /* fmr - fmr. */
2324 /* XXX: beware that fmr never checks for NaNs nor update FPSCR */
2325 GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT)
2326 {
2327 if (unlikely(!ctx->fpu_enabled)) {
2328 gen_exception(ctx, POWERPC_EXCP_FPU);
2329 return;
2330 }
2331 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2332 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2333 }
2334
2335 /* fnabs */
2336 /* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
2337 GEN_FLOAT_B(nabs, 0x08, 0x04, 0, PPC_FLOAT);
2338 /* fneg */
2339 /* XXX: beware that fneg never checks for NaNs nor update FPSCR */
2340 GEN_FLOAT_B(neg, 0x08, 0x01, 0, PPC_FLOAT);
2341
2342 /*** Floating-Point status & ctrl register ***/
2343 /* mcrfs */
2344 GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT)
2345 {
2346 int bfa;
2347
2348 if (unlikely(!ctx->fpu_enabled)) {
2349 gen_exception(ctx, POWERPC_EXCP_FPU);
2350 return;
2351 }
2352 bfa = 4 * (7 - crfS(ctx->opcode));
2353 tcg_gen_shri_i32(cpu_crf[crfD(ctx->opcode)], cpu_fpscr, bfa);
2354 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], 0xf);
2355 tcg_gen_andi_i32(cpu_fpscr, cpu_fpscr, ~(0xF << bfa));
2356 }
2357
2358 /* mffs */
2359 GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT)
2360 {
2361 if (unlikely(!ctx->fpu_enabled)) {
2362 gen_exception(ctx, POWERPC_EXCP_FPU);
2363 return;
2364 }
2365 gen_reset_fpstatus();
2366 tcg_gen_extu_i32_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpscr);
2367 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2368 }
2369
2370 /* mtfsb0 */
2371 GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT)
2372 {
2373 uint8_t crb;
2374
2375 if (unlikely(!ctx->fpu_enabled)) {
2376 gen_exception(ctx, POWERPC_EXCP_FPU);
2377 return;
2378 }
2379 crb = 31 - crbD(ctx->opcode);
2380 gen_reset_fpstatus();
2381 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX)) {
2382 TCGv_i32 t0;
2383 /* NIP cannot be restored if the memory exception comes from an helper */
2384 gen_update_nip(ctx, ctx->nip - 4);
2385 t0 = tcg_const_i32(crb);
2386 gen_helper_fpscr_clrbit(t0);
2387 tcg_temp_free_i32(t0);
2388 }
2389 if (unlikely(Rc(ctx->opcode) != 0)) {
2390 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
2391 }
2392 }
2393
2394 /* mtfsb1 */
2395 GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT)
2396 {
2397 uint8_t crb;
2398
2399 if (unlikely(!ctx->fpu_enabled)) {
2400 gen_exception(ctx, POWERPC_EXCP_FPU);
2401 return;
2402 }
2403 crb = 31 - crbD(ctx->opcode);
2404 gen_reset_fpstatus();
2405 /* XXX: we pretend we can only do IEEE floating-point computations */
2406 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI)) {
2407 TCGv_i32 t0;
2408 /* NIP cannot be restored if the memory exception comes from an helper */
2409 gen_update_nip(ctx, ctx->nip - 4);
2410 t0 = tcg_const_i32(crb);
2411 gen_helper_fpscr_setbit(t0);
2412 tcg_temp_free_i32(t0);
2413 }
2414 if (unlikely(Rc(ctx->opcode) != 0)) {
2415 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
2416 }
2417 /* We can raise a differed exception */
2418 gen_helper_float_check_status();
2419 }
2420
2421 /* mtfsf */
2422 GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x00010000, PPC_FLOAT)
2423 {
2424 TCGv_i32 t0;
2425 int L = ctx->opcode & 0x02000000;
2426
2427 if (unlikely(!ctx->fpu_enabled)) {
2428 gen_exception(ctx, POWERPC_EXCP_FPU);
2429 return;
2430 }
2431 /* NIP cannot be restored if the memory exception comes from an helper */
2432 gen_update_nip(ctx, ctx->nip - 4);
2433 gen_reset_fpstatus();
2434 if (L)
2435 t0 = tcg_const_i32(0xff);
2436 else
2437 t0 = tcg_const_i32(FM(ctx->opcode));
2438 gen_helper_store_fpscr(cpu_fpr[rB(ctx->opcode)], t0);
2439 tcg_temp_free_i32(t0);
2440 if (unlikely(Rc(ctx->opcode) != 0)) {
2441 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
2442 }
2443 /* We can raise a differed exception */
2444 gen_helper_float_check_status();
2445 }
2446
2447 /* mtfsfi */
2448 GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT)
2449 {
2450 int bf, sh;
2451 TCGv_i64 t0;
2452 TCGv_i32 t1;
2453
2454 if (unlikely(!ctx->fpu_enabled)) {
2455 gen_exception(ctx, POWERPC_EXCP_FPU);
2456 return;
2457 }
2458 bf = crbD(ctx->opcode) >> 2;
2459 sh = 7 - bf;
2460 /* NIP cannot be restored if the memory exception comes from an helper */
2461 gen_update_nip(ctx, ctx->nip - 4);
2462 gen_reset_fpstatus();
2463 t0 = tcg_const_i64(FPIMM(ctx->opcode) << (4 * sh));
2464 t1 = tcg_const_i32(1 << sh);
2465 gen_helper_store_fpscr(t0, t1);
2466 tcg_temp_free_i64(t0);
2467 tcg_temp_free_i32(t1);
2468 if (unlikely(Rc(ctx->opcode) != 0)) {
2469 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
2470 }
2471 /* We can raise a differed exception */
2472 gen_helper_float_check_status();
2473 }
2474
2475 /*** Addressing modes ***/
2476 /* Register indirect with immediate index : EA = (rA|0) + SIMM */
2477 static always_inline void gen_addr_imm_index (DisasContext *ctx, TCGv EA, target_long maskl)
2478 {
2479 target_long simm = SIMM(ctx->opcode);
2480
2481 simm &= ~maskl;
2482 if (rA(ctx->opcode) == 0) {
2483 #if defined(TARGET_PPC64)
2484 if (!ctx->sf_mode) {
2485 tcg_gen_movi_tl(EA, (uint32_t)simm);
2486 } else
2487 #endif
2488 tcg_gen_movi_tl(EA, simm);
2489 } else if (likely(simm != 0)) {
2490 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm);
2491 #if defined(TARGET_PPC64)
2492 if (!ctx->sf_mode) {
2493 tcg_gen_ext32u_tl(EA, EA);
2494 }
2495 #endif
2496 } else {
2497 #if defined(TARGET_PPC64)
2498 if (!ctx->sf_mode) {
2499 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2500 } else
2501 #endif
2502 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2503 }
2504 }
2505
2506 static always_inline void gen_addr_reg_index (DisasContext *ctx, TCGv EA)
2507 {
2508 if (rA(ctx->opcode) == 0) {
2509 #if defined(TARGET_PPC64)
2510 if (!ctx->sf_mode) {
2511 tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2512 } else
2513 #endif
2514 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2515 } else {
2516 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2517 #if defined(TARGET_PPC64)
2518 if (!ctx->sf_mode) {
2519 tcg_gen_ext32u_tl(EA, EA);
2520 }
2521 #endif
2522 }
2523 }
2524
2525 static always_inline void gen_addr_register (DisasContext *ctx, TCGv EA)
2526 {
2527 if (rA(ctx->opcode) == 0) {
2528 tcg_gen_movi_tl(EA, 0);
2529 } else {
2530 #if defined(TARGET_PPC64)
2531 if (!ctx->sf_mode) {
2532 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2533 } else
2534 #endif
2535 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2536 }
2537 }
2538
2539 static always_inline void gen_addr_add (DisasContext *ctx, TCGv ret, TCGv arg1, target_long val)
2540 {
2541 tcg_gen_addi_tl(ret, arg1, val);
2542 #if defined(TARGET_PPC64)
2543 if (!ctx->sf_mode) {
2544 tcg_gen_ext32u_tl(ret, ret);
2545 }
2546 #endif
2547 }
2548
2549 static always_inline void gen_check_align (DisasContext *ctx, TCGv EA, int mask)
2550 {
2551 int l1 = gen_new_label();
2552 TCGv t0 = tcg_temp_new();
2553 TCGv_i32 t1, t2;
2554 /* NIP cannot be restored if the memory exception comes from an helper */
2555 gen_update_nip(ctx, ctx->nip - 4);
2556 tcg_gen_andi_tl(t0, EA, mask);
2557 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
2558 t1 = tcg_const_i32(POWERPC_EXCP_ALIGN);
2559 t2 = tcg_const_i32(0);
2560 gen_helper_raise_exception_err(t1, t2);
2561 tcg_temp_free_i32(t1);
2562 tcg_temp_free_i32(t2);
2563 gen_set_label(l1);
2564 tcg_temp_free(t0);
2565 }
2566
2567 /*** Integer load ***/
2568 static always_inline void gen_qemu_ld8u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2569 {
2570 tcg_gen_qemu_ld8u(arg1, arg2, ctx->mem_idx);
2571 }
2572
2573 static always_inline void gen_qemu_ld8s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2574 {
2575 tcg_gen_qemu_ld8s(arg1, arg2, ctx->mem_idx);
2576 }
2577
2578 static always_inline void gen_qemu_ld16u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2579 {
2580 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2581 if (unlikely(ctx->le_mode)) {
2582 tcg_gen_bswap16_tl(arg1, arg1);
2583 }
2584 }
2585
2586 static always_inline void gen_qemu_ld16s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2587 {
2588 if (unlikely(ctx->le_mode)) {
2589 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2590 tcg_gen_bswap16_tl(arg1, arg1);
2591 tcg_gen_ext16s_tl(arg1, arg1);
2592 } else {
2593 tcg_gen_qemu_ld16s(arg1, arg2, ctx->mem_idx);
2594 }
2595 }
2596
2597 static always_inline void gen_qemu_ld32u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2598 {
2599 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2600 if (unlikely(ctx->le_mode)) {
2601 tcg_gen_bswap32_tl(arg1, arg1);
2602 }
2603 }
2604
2605 #if defined(TARGET_PPC64)
2606 static always_inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2607 {
2608 if (unlikely(ctx->le_mode)) {
2609 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2610 tcg_gen_bswap32_tl(arg1, arg1);
2611 tcg_gen_ext32s_tl(arg1, arg1);
2612 } else
2613 tcg_gen_qemu_ld32s(arg1, arg2, ctx->mem_idx);
2614 }
2615 #endif
2616
2617 static always_inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2618 {
2619 tcg_gen_qemu_ld64(arg1, arg2, ctx->mem_idx);
2620 if (unlikely(ctx->le_mode)) {
2621 tcg_gen_bswap64_i64(arg1, arg1);
2622 }
2623 }
2624
2625 static always_inline void gen_qemu_st8(DisasContext *ctx, TCGv arg1, TCGv arg2)
2626 {
2627 tcg_gen_qemu_st8(arg1, arg2, ctx->mem_idx);
2628 }
2629
2630 static always_inline void gen_qemu_st16(DisasContext *ctx, TCGv arg1, TCGv arg2)
2631 {
2632 if (unlikely(ctx->le_mode)) {
2633 TCGv t0 = tcg_temp_new();
2634 tcg_gen_ext16u_tl(t0, arg1);
2635 tcg_gen_bswap16_tl(t0, t0);
2636 tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx);
2637 tcg_temp_free(t0);
2638 } else {
2639 tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx);
2640 }
2641 }
2642
2643 static always_inline void gen_qemu_st32(DisasContext *ctx, TCGv arg1, TCGv arg2)
2644 {
2645 if (unlikely(ctx->le_mode)) {
2646 TCGv t0 = tcg_temp_new();
2647 tcg_gen_ext32u_tl(t0, arg1);
2648 tcg_gen_bswap32_tl(t0, t0);
2649 tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx);
2650 tcg_temp_free(t0);
2651 } else {
2652 tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx);
2653 }
2654 }
2655
2656 static always_inline void gen_qemu_st64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2657 {
2658 if (unlikely(ctx->le_mode)) {
2659 TCGv_i64 t0 = tcg_temp_new_i64();
2660 tcg_gen_bswap64_i64(t0, arg1);
2661 tcg_gen_qemu_st64(t0, arg2, ctx->mem_idx);
2662 tcg_temp_free_i64(t0);
2663 } else
2664 tcg_gen_qemu_st64(arg1, arg2, ctx->mem_idx);
2665 }
2666
2667 #define GEN_LD(name, ldop, opc, type) \
2668 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type) \
2669 { \
2670 TCGv EA; \
2671 gen_set_access_type(ctx, ACCESS_INT); \
2672 EA = tcg_temp_new(); \
2673 gen_addr_imm_index(ctx, EA, 0); \
2674 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2675 tcg_temp_free(EA); \
2676 }
2677
2678 #define GEN_LDU(name, ldop, opc, type) \
2679 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type) \
2680 { \
2681 TCGv EA; \
2682 if (unlikely(rA(ctx->opcode) == 0 || \
2683 rA(ctx->opcode) == rD(ctx->opcode))) { \
2684 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2685 return; \
2686 } \
2687 gen_set_access_type(ctx, ACCESS_INT); \
2688 EA = tcg_temp_new(); \
2689 if (type == PPC_64B) \
2690 gen_addr_imm_index(ctx, EA, 0x03); \
2691 else \
2692 gen_addr_imm_index(ctx, EA, 0); \
2693 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2694 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2695 tcg_temp_free(EA); \
2696 }
2697
2698 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
2699 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type) \
2700 { \
2701 TCGv EA; \
2702 if (unlikely(rA(ctx->opcode) == 0 || \
2703 rA(ctx->opcode) == rD(ctx->opcode))) { \
2704 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2705 return; \
2706 } \
2707 gen_set_access_type(ctx, ACCESS_INT); \
2708 EA = tcg_temp_new(); \
2709 gen_addr_reg_index(ctx, EA); \
2710 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2711 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2712 tcg_temp_free(EA); \
2713 }
2714
2715 #define GEN_LDX(name, ldop, opc2, opc3, type) \
2716 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type) \
2717 { \
2718 TCGv EA; \
2719 gen_set_access_type(ctx, ACCESS_INT); \
2720 EA = tcg_temp_new(); \
2721 gen_addr_reg_index(ctx, EA); \
2722 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2723 tcg_temp_free(EA); \
2724 }
2725
2726 #define GEN_LDS(name, ldop, op, type) \
2727 GEN_LD(name, ldop, op | 0x20, type); \
2728 GEN_LDU(name, ldop, op | 0x21, type); \
2729 GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \
2730 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
2731
2732 /* lbz lbzu lbzux lbzx */
2733 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER);
2734 /* lha lhau lhaux lhax */
2735 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER);
2736 /* lhz lhzu lhzux lhzx */
2737 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER);
2738 /* lwz lwzu lwzux lwzx */
2739 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER);
2740 #if defined(TARGET_PPC64)
2741 /* lwaux */
2742 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B);
2743 /* lwax */
2744 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B);
2745 /* ldux */
2746 GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B);
2747 /* ldx */
2748 GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B);
2749 GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B)
2750 {
2751 TCGv EA;
2752 if (Rc(ctx->opcode)) {
2753 if (unlikely(rA(ctx->opcode) == 0 ||
2754 rA(ctx->opcode) == rD(ctx->opcode))) {
2755 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2756 return;
2757 }
2758 }
2759 gen_set_access_type(ctx, ACCESS_INT);
2760 EA = tcg_temp_new();
2761 gen_addr_imm_index(ctx, EA, 0x03);
2762 if (ctx->opcode & 0x02) {
2763 /* lwa (lwau is undefined) */
2764 gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2765 } else {
2766 /* ld - ldu */
2767 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2768 }
2769 if (Rc(ctx->opcode))
2770 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2771 tcg_temp_free(EA);
2772 }
2773 /* lq */
2774 GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX)
2775 {
2776 #if defined(CONFIG_USER_ONLY)
2777 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2778 #else
2779 int ra, rd;
2780 TCGv EA;
2781
2782 /* Restore CPU state */
2783 if (unlikely(ctx->mem_idx == 0)) {
2784 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2785 return;
2786 }
2787 ra = rA(ctx->opcode);
2788 rd = rD(ctx->opcode);
2789 if (unlikely((rd & 1) || rd == ra)) {
2790 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2791 return;
2792 }
2793 if (unlikely(ctx->le_mode)) {
2794 /* Little-endian mode is not handled */
2795 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2796 return;
2797 }
2798 gen_set_access_type(ctx, ACCESS_INT);
2799 EA = tcg_temp_new();
2800 gen_addr_imm_index(ctx, EA, 0x0F);
2801 gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
2802 gen_addr_add(ctx, EA, EA, 8);
2803 gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
2804 tcg_temp_free(EA);
2805 #endif
2806 }
2807 #endif
2808
2809 /*** Integer store ***/
2810 #define GEN_ST(name, stop, opc, type) \
2811 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type) \
2812 { \
2813 TCGv EA; \
2814 gen_set_access_type(ctx, ACCESS_INT); \
2815 EA = tcg_temp_new(); \
2816 gen_addr_imm_index(ctx, EA, 0); \
2817 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2818 tcg_temp_free(EA); \
2819 }
2820
2821 #define GEN_STU(name, stop, opc, type) \
2822 GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type) \
2823 { \
2824 TCGv EA; \
2825 if (unlikely(rA(ctx->opcode) == 0)) { \
2826 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2827 return; \
2828 } \
2829 gen_set_access_type(ctx, ACCESS_INT); \
2830 EA = tcg_temp_new(); \
2831 if (type == PPC_64B) \
2832 gen_addr_imm_index(ctx, EA, 0x03); \
2833 else \
2834 gen_addr_imm_index(ctx, EA, 0); \
2835 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2836 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2837 tcg_temp_free(EA); \
2838 }
2839
2840 #define GEN_STUX(name, stop, opc2, opc3, type) \
2841 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type) \
2842 { \
2843 TCGv EA; \
2844 if (unlikely(rA(ctx->opcode) == 0)) { \
2845 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2846 return; \
2847 } \
2848 gen_set_access_type(ctx, ACCESS_INT); \
2849 EA = tcg_temp_new(); \
2850 gen_addr_reg_index(ctx, EA); \
2851 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2852 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2853 tcg_temp_free(EA); \
2854 }
2855
2856 #define GEN_STX(name, stop, opc2, opc3, type) \
2857 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type) \
2858 { \
2859 TCGv EA; \
2860 gen_set_access_type(ctx, ACCESS_INT); \
2861 EA = tcg_temp_new(); \
2862 gen_addr_reg_index(ctx, EA); \
2863 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2864 tcg_temp_free(EA); \
2865 }
2866
2867 #define GEN_STS(name, stop, op, type) \
2868 GEN_ST(name, stop, op | 0x20, type); \
2869 GEN_STU(name, stop, op | 0x21, type); \
2870 GEN_STUX(name, stop, 0x17, op | 0x01, type); \
2871 GEN_STX(name, stop, 0x17, op | 0x00, type)
2872
2873 /* stb stbu stbux stbx */
2874 GEN_STS(stb, st8, 0x06, PPC_INTEGER);
2875 /* sth sthu sthux sthx */
2876 GEN_STS(sth, st16, 0x0C, PPC_INTEGER);
2877 /* stw stwu stwux stwx */
2878 GEN_STS(stw, st32, 0x04, PPC_INTEGER);
2879 #if defined(TARGET_PPC64)
2880 GEN_STUX(std, st64, 0x15, 0x05, PPC_64B);
2881 GEN_STX(std, st64, 0x15, 0x04, PPC_64B);
2882 GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B)
2883 {
2884 int rs;
2885 TCGv EA;
2886
2887 rs = rS(ctx->opcode);
2888 if ((ctx->opcode & 0x3) == 0x2) {
2889 #if defined(CONFIG_USER_ONLY)
2890 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2891 #else
2892 /* stq */
2893 if (unlikely(ctx->mem_idx == 0)) {
2894 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2895 return;
2896 }
2897 if (unlikely(rs & 1)) {
2898 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2899 return;
2900 }
2901 if (unlikely(ctx->le_mode)) {
2902 /* Little-endian mode is not handled */
2903 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2904 return;
2905 }
2906 gen_set_access_type(ctx, ACCESS_INT);
2907 EA = tcg_temp_new();
2908 gen_addr_imm_index(ctx, EA, 0x03);
2909 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
2910 gen_addr_add(ctx, EA, EA, 8);
2911 gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
2912 tcg_temp_free(EA);
2913 #endif
2914 } else {
2915 /* std / stdu */
2916 if (Rc(ctx->opcode)) {
2917 if (unlikely(rA(ctx->opcode) == 0)) {
2918 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2919 return;
2920 }
2921 }
2922 gen_set_access_type(ctx, ACCESS_INT);
2923 EA = tcg_temp_new();
2924 gen_addr_imm_index(ctx, EA, 0x03);
2925 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
2926 if (Rc(ctx->opcode))
2927 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2928 tcg_temp_free(EA);
2929 }
2930 }
2931 #endif
2932 /*** Integer load and store with byte reverse ***/
2933 /* lhbrx */
2934 static void always_inline gen_qemu_ld16ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
2935 {
2936 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2937 if (likely(!ctx->le_mode)) {
2938 tcg_gen_bswap16_tl(arg1, arg1);
2939 }
2940 }
2941 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER);
2942
2943 /* lwbrx */
2944 static void always_inline gen_qemu_ld32ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
2945 {
2946 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2947 if (likely(!ctx->le_mode)) {
2948 tcg_gen_bswap32_tl(arg1, arg1);
2949 }
2950 }
2951 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
2952
2953 /* sthbrx */
2954 static void always_inline gen_qemu_st16r(DisasContext *ctx, TCGv arg1, TCGv arg2)
2955 {
2956 if (likely(!ctx->le_mode)) {
2957 TCGv t0 = tcg_temp_new();
2958 tcg_gen_ext16u_tl(t0, arg1);
2959 tcg_gen_bswap16_tl(t0, t0);
2960 tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx);
2961 tcg_temp_free(t0);
2962 } else {
2963 tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx);
2964 }
2965 }
2966 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER);
2967
2968 /* stwbrx */
2969 static void always_inline gen_qemu_st32r(DisasContext *ctx, TCGv arg1, TCGv arg2)
2970 {
2971 if (likely(!ctx->le_mode)) {
2972 TCGv t0 = tcg_temp_new();
2973 tcg_gen_ext32u_tl(t0, arg1);
2974 tcg_gen_bswap32_tl(t0, t0);
2975 tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx);
2976 tcg_temp_free(t0);
2977 } else {
2978 tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx);
2979 }
2980 }
2981 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER);
2982
2983 /*** Integer load and store multiple ***/
2984 /* lmw */
2985 GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
2986 {
2987 TCGv t0;
2988 TCGv_i32 t1;
2989 gen_set_access_type(ctx, ACCESS_INT);
2990 /* NIP cannot be restored if the memory exception comes from an helper */
2991 gen_update_nip(ctx, ctx->nip - 4);
2992 t0 = tcg_temp_new();
2993 t1 = tcg_const_i32(rD(ctx->opcode));
2994 gen_addr_imm_index(ctx, t0, 0);
2995 gen_helper_lmw(t0, t1);
2996 tcg_temp_free(t0);
2997 tcg_temp_free_i32(t1);
2998 }
2999
3000 /* stmw */
3001 GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
3002 {
3003 TCGv t0;
3004 TCGv_i32 t1;
3005 gen_set_access_type(ctx, ACCESS_INT);
3006 /* NIP cannot be restored if the memory exception comes from an helper */
3007 gen_update_nip(ctx, ctx->nip - 4);
3008 t0 = tcg_temp_new();
3009 t1 = tcg_const_i32(rS(ctx->opcode));
3010 gen_addr_imm_index(ctx, t0, 0);
3011 gen_helper_stmw(t0, t1);
3012 tcg_temp_free(t0);
3013 tcg_temp_free_i32(t1);
3014 }
3015
3016 /*** Integer load and store strings ***/
3017 /* lswi */
3018 /* PowerPC32 specification says we must generate an exception if
3019 * rA is in the range of registers to be loaded.
3020 * In an other hand, IBM says this is valid, but rA won't be loaded.
3021 * For now, I'll follow the spec...
3022 */
3023 GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING)
3024 {
3025 TCGv t0;
3026 TCGv_i32 t1, t2;
3027 int nb = NB(ctx->opcode);
3028 int start = rD(ctx->opcode);
3029 int ra = rA(ctx->opcode);
3030 int nr;
3031
3032 if (nb == 0)
3033 nb = 32;
3034 nr = nb / 4;
3035 if (unlikely(((start + nr) > 32 &&
3036 start <= ra && (start + nr - 32) > ra) ||
3037 ((start + nr) <= 32 && start <= ra && (start + nr) > ra))) {
3038 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
3039 return;
3040 }
3041 gen_set_access_type(ctx, ACCESS_INT);
3042 /* NIP cannot be restored if the memory exception comes from an helper */
3043 gen_update_nip(ctx, ctx->nip - 4);
3044 t0 = tcg_temp_new();
3045 gen_addr_register(ctx, t0);
3046 t1 = tcg_const_i32(nb);
3047 t2 = tcg_const_i32(start);
3048 gen_helper_lsw(t0, t1, t2);
3049 tcg_temp_free(t0);
3050 tcg_temp_free_i32(t1);
3051 tcg_temp_free_i32(t2);
3052 }
3053
3054 /* lswx */
3055 GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING)
3056 {
3057 TCGv t0;
3058 TCGv_i32 t1, t2, t3;
3059 gen_set_access_type(ctx, ACCESS_INT);
3060 /* NIP cannot be restored if the memory exception comes from an helper */
3061 gen_update_nip(ctx, ctx->nip - 4);
3062 t0 = tcg_temp_new();
3063 gen_addr_reg_index(ctx, t0);
3064 t1 = tcg_const_i32(rD(ctx->opcode));
3065 t2 = tcg_const_i32(rA(ctx->opcode));
3066 t3 = tcg_const_i32(rB(ctx->opcode));
3067 gen_helper_lswx(t0, t1, t2, t3);
3068 tcg_temp_free(t0);
3069 tcg_temp_free_i32(t1);
3070 tcg_temp_free_i32(t2);
3071 tcg_temp_free_i32(t3);
3072 }
3073
3074 /* stswi */
3075 GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING)
3076 {
3077 TCGv t0;
3078 TCGv_i32 t1, t2;
3079 int nb = NB(ctx->opcode);
3080 gen_set_access_type(ctx, ACCESS_INT);
3081 /* NIP cannot be restored if the memory exception comes from an helper */
3082 gen_update_nip(ctx, ctx->nip - 4);
3083 t0 = tcg_temp_new();
3084 gen_addr_register(ctx, t0);
3085 if (nb == 0)
3086 nb = 32;
3087 t1 = tcg_const_i32(nb);
3088 t2 = tcg_const_i32(rS(ctx->opcode));
3089 gen_helper_stsw(t0, t1, t2);
3090 tcg_temp_free(t0);
3091 tcg_temp_free_i32(t1);
3092 tcg_temp_free_i32(t2);
3093 }
3094
3095 /* stswx */
3096 GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING)
3097 {
3098 TCGv t0;
3099 TCGv_i32 t1, t2;
3100 gen_set_access_type(ctx, ACCESS_INT);
3101 /* NIP cannot be restored if the memory exception comes from an helper */
3102 gen_update_nip(ctx, ctx->nip - 4);
3103 t0 = tcg_temp_new();
3104 gen_addr_reg_index(ctx, t0);
3105 t1 = tcg_temp_new_i32();
3106 tcg_gen_trunc_tl_i32(t1, cpu_xer);
3107 tcg_gen_andi_i32(t1, t1, 0x7F);
3108 t2 = tcg_const_i32(rS(ctx->opcode));
3109 gen_helper_stsw(t0, t1, t2);
3110 tcg_temp_free(t0);
3111 tcg_temp_free_i32(t1);
3112 tcg_temp_free_i32(t2);
3113 }
3114
3115 /*** Memory synchronisation ***/
3116 /* eieio */
3117 GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO)
3118 {
3119 }
3120
3121 /* isync */
3122 GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM)
3123 {
3124 gen_stop_exception(ctx);
3125 }
3126
3127 /* lwarx */
3128 GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000001, PPC_RES)
3129 {
3130 TCGv t0;
3131 gen_set_access_type(ctx, ACCESS_RES);
3132 t0 = tcg_temp_local_new();
3133 gen_addr_reg_index(ctx, t0);
3134 gen_check_align(ctx, t0, 0x03);
3135 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0);
3136 tcg_gen_mov_tl(cpu_reserve, t0);
3137 tcg_temp_free(t0);
3138 }
3139
3140 /* stwcx. */
3141 GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES)
3142 {
3143 int l1;
3144 TCGv t0;
3145 gen_set_access_type(ctx, ACCESS_RES);
3146 t0 = tcg_temp_local_new();
3147 gen_addr_reg_index(ctx, t0);
3148 gen_check_align(ctx, t0, 0x03);
3149 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
3150 tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO);
3151 tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1);
3152 l1 = gen_new_label();
3153 tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1);
3154 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
3155 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], t0);
3156 gen_set_label(l1);
3157 tcg_gen_movi_tl(cpu_reserve, -1);
3158 tcg_temp_free(t0);
3159 }
3160
3161 #if defined(TARGET_PPC64)
3162 /* ldarx */
3163 GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000001, PPC_64B)
3164 {
3165 TCGv t0;
3166 gen_set_access_type(ctx, ACCESS_RES);
3167 t0 = tcg_temp_local_new();
3168 gen_addr_reg_index(ctx, t0);
3169 gen_check_align(ctx, t0, 0x07);
3170 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], t0);
3171 tcg_gen_mov_tl(cpu_reserve, t0);
3172 tcg_temp_free(t0);
3173 }
3174
3175 /* stdcx. */
3176 GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B)
3177 {
3178 int l1;
3179 TCGv t0;
3180 gen_set_access_type(ctx, ACCESS_RES);
3181 t0 = tcg_temp_local_new();
3182 gen_addr_reg_index(ctx, t0);
3183 gen_check_align(ctx, t0, 0x07);
3184 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
3185 tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO);
3186 tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1);
3187 l1 = gen_new_label();
3188 tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1);
3189 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
3190 gen_qemu_st64(ctx, cpu_gpr[rS(ctx->opcode)], t0);
3191 gen_set_label(l1);
3192 tcg_gen_movi_tl(cpu_reserve, -1);
3193 tcg_temp_free(t0);
3194 }
3195 #endif /* defined(TARGET_PPC64) */
3196
3197 /* sync */
3198 GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC)
3199 {
3200 }
3201
3202 /* wait */
3203 GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT)
3204 {
3205 TCGv_i32 t0 = tcg_temp_new_i32();
3206 tcg_gen_st_i32(t0, cpu_env, offsetof(CPUState, halted));
3207 tcg_temp_free_i32(t0);
3208 /* Stop translation, as the CPU is supposed to sleep from now */
3209 gen_exception_err(ctx, EXCP_HLT, 1);
3210 }
3211
3212 /*** Floating-point load ***/
3213 #define GEN_LDF(name, ldop, opc, type) \
3214 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type) \
3215 { \
3216 TCGv EA; \
3217 if (unlikely(!ctx->fpu_enabled)) { \
3218 gen_exception(ctx, POWERPC_EXCP_FPU); \
3219 return; \
3220 } \
3221 gen_set_access_type(ctx, ACCESS_FLOAT); \
3222 EA = tcg_temp_new(); \
3223 gen_addr_imm_index(ctx, EA, 0); \
3224 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3225 tcg_temp_free(EA); \
3226 }
3227
3228 #define GEN_LDUF(name, ldop, opc, type) \
3229 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type) \
3230 { \
3231 TCGv EA; \
3232 if (unlikely(!ctx->fpu_enabled)) { \
3233 gen_exception(ctx, POWERPC_EXCP_FPU); \
3234 return; \
3235 } \
3236 if (unlikely(rA(ctx->opcode) == 0)) { \
3237 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3238 return; \
3239 } \
3240 gen_set_access_type(ctx, ACCESS_FLOAT); \
3241 EA = tcg_temp_new(); \
3242 gen_addr_imm_index(ctx, EA, 0); \
3243 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3244 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3245 tcg_temp_free(EA); \
3246 }
3247
3248 #define GEN_LDUXF(name, ldop, opc, type) \
3249 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type) \
3250 { \
3251 TCGv EA; \
3252 if (unlikely(!ctx->fpu_enabled)) { \
3253 gen_exception(ctx, POWERPC_EXCP_FPU); \
3254 return; \
3255 } \
3256 if (unlikely(rA(ctx->opcode) == 0)) { \
3257 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3258 return; \
3259 } \
3260 gen_set_access_type(ctx, ACCESS_FLOAT); \
3261 EA = tcg_temp_new(); \
3262 gen_addr_reg_index(ctx, EA); \
3263 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3264 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3265 tcg_temp_free(EA); \
3266 }
3267
3268 #define GEN_LDXF(name, ldop, opc2, opc3, type) \
3269 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type) \
3270 { \
3271 TCGv EA; \
3272 if (unlikely(!ctx->fpu_enabled)) { \
3273 gen_exception(ctx, POWERPC_EXCP_FPU); \
3274 return; \
3275 } \
3276 gen_set_access_type(ctx, ACCESS_FLOAT); \
3277 EA = tcg_temp_new(); \
3278 gen_addr_reg_index(ctx, EA); \
3279 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3280 tcg_temp_free(EA); \
3281 }
3282
3283 #define GEN_LDFS(name, ldop, op, type) \
3284 GEN_LDF(name, ldop, op | 0x20, type); \
3285 GEN_LDUF(name, ldop, op | 0x21, type); \
3286 GEN_LDUXF(name, ldop, op | 0x01, type); \
3287 GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
3288
3289 static always_inline void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3290 {
3291 TCGv t0 = tcg_temp_new();
3292 TCGv_i32 t1 = tcg_temp_new_i32();
3293 gen_qemu_ld32u(ctx, t0, arg2);
3294 tcg_gen_trunc_tl_i32(t1, t0);
3295 tcg_temp_free(t0);
3296 gen_helper_float32_to_float64(arg1, t1);
3297 tcg_temp_free_i32(t1);
3298 }
3299
3300 /* lfd lfdu lfdux lfdx */
3301 GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT);
3302 /* lfs lfsu lfsux lfsx */
3303 GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT);
3304
3305 /*** Floating-point store ***/
3306 #define GEN_STF(name, stop, opc, type) \
3307 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type) \
3308 { \
3309 TCGv EA; \
3310 if (unlikely(!ctx->fpu_enabled)) { \
3311 gen_exception(ctx, POWERPC_EXCP_FPU); \
3312 return; \
3313 } \
3314 gen_set_access_type(ctx, ACCESS_FLOAT); \
3315 EA = tcg_temp_new(); \
3316 gen_addr_imm_index(ctx, EA, 0); \
3317 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3318 tcg_temp_free(EA); \
3319 }
3320
3321 #define GEN_STUF(name, stop, opc, type) \
3322 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type) \
3323 { \
3324 TCGv EA; \
3325 if (unlikely(!ctx->fpu_enabled)) { \
3326 gen_exception(ctx, POWERPC_EXCP_FPU); \
3327 return; \
3328 } \
3329 if (unlikely(rA(ctx->opcode) == 0)) { \
3330 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3331 return; \
3332 } \
3333 gen_set_access_type(ctx, ACCESS_FLOAT); \
3334 EA = tcg_temp_new(); \
3335 gen_addr_imm_index(ctx, EA, 0); \
3336 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3337 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3338 tcg_temp_free(EA); \
3339 }
3340
3341 #define GEN_STUXF(name, stop, opc, type) \
3342 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type) \
3343 { \
3344 TCGv EA; \
3345 if (unlikely(!ctx->fpu_enabled)) { \
3346 gen_exception(ctx, POWERPC_EXCP_FPU); \
3347 return; \
3348 } \
3349 if (unlikely(rA(ctx->opcode) == 0)) { \
3350 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3351 return; \
3352 } \
3353 gen_set_access_type(ctx, ACCESS_FLOAT); \
3354 EA = tcg_temp_new(); \
3355 gen_addr_reg_index(ctx, EA); \
3356 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3357 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3358 tcg_temp_free(EA); \
3359 }
3360
3361 #define GEN_STXF(name, stop, opc2, opc3, type) \
3362 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type) \
3363 { \
3364 TCGv EA; \
3365 if (unlikely(!ctx->fpu_enabled)) { \
3366 gen_exception(ctx, POWERPC_EXCP_FPU); \
3367 return; \
3368 } \
3369 gen_set_access_type(ctx, ACCESS_FLOAT); \
3370 EA = tcg_temp_new(); \
3371 gen_addr_reg_index(ctx, EA); \
3372 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3373 tcg_temp_free(EA); \
3374 }
3375
3376 #define GEN_STFS(name, stop, op, type) \
3377 GEN_STF(name, stop, op | 0x20, type); \
3378 GEN_STUF(name, stop, op | 0x21, type); \
3379 GEN_STUXF(name, stop, op | 0x01, type); \
3380 GEN_STXF(name, stop, 0x17, op | 0x00, type)
3381
3382 static always_inline void gen_qemu_st32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3383 {
3384 TCGv_i32 t0 = tcg_temp_new_i32();
3385 TCGv t1 = tcg_temp_new();
3386 gen_helper_float64_to_float32(t0, arg1);
3387 tcg_gen_extu_i32_tl(t1, t0);
3388 tcg_temp_free_i32(t0);
3389 gen_qemu_st32(ctx, t1, arg2);
3390 tcg_temp_free(t1);
3391 }
3392
3393 /* stfd stfdu stfdux stfdx */
3394 GEN_STFS(stfd, st64, 0x16, PPC_FLOAT);
3395 /* stfs stfsu stfsux stfsx */
3396 GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT);
3397
3398 /* Optional: */
3399 static always_inline void gen_qemu_st32fiw(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3400 {
3401 TCGv t0 = tcg_temp_new();
3402 tcg_gen_trunc_i64_tl(t0, arg1),
3403 gen_qemu_st32(ctx, t0, arg2);
3404 tcg_temp_free(t0);
3405 }
3406 /* stfiwx */
3407 GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX);
3408
3409 /*** Branch ***/
3410 static always_inline void gen_goto_tb (DisasContext *ctx, int n,
3411 target_ulong dest)
3412 {
3413 TranslationBlock *tb;
3414 tb = ctx->tb;
3415 #if defined(TARGET_PPC64)
3416 if (!ctx->sf_mode)
3417 dest = (uint32_t) dest;
3418 #endif
3419 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
3420 likely(!ctx->singlestep_enabled)) {
3421 tcg_gen_goto_tb(n);
3422 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3423 tcg_gen_exit_tb((long)tb + n);
3424 } else {
3425 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3426 if (unlikely(ctx->singlestep_enabled)) {
3427 if ((ctx->singlestep_enabled &
3428 (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) &&
3429 ctx->exception == POWERPC_EXCP_BRANCH) {
3430 target_ulong tmp = ctx->nip;
3431 ctx->nip = dest;
3432 gen_exception(ctx, POWERPC_EXCP_TRACE);
3433 ctx->nip = tmp;
3434 }
3435 if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
3436 gen_debug_exception(ctx);
3437 }
3438 }
3439 tcg_gen_exit_tb(0);
3440 }
3441 }
3442
3443 static always_inline void gen_setlr (DisasContext *ctx, target_ulong nip)
3444 {
3445 #if defined(TARGET_PPC64)
3446 if (ctx->sf_mode == 0)
3447 tcg_gen_movi_tl(cpu_lr, (uint32_t)nip);
3448 else
3449 #endif
3450 tcg_gen_movi_tl(cpu_lr, nip);
3451 }
3452
3453 /* b ba bl bla */
3454 GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3455 {
3456 target_ulong li, target;
3457
3458 ctx->exception = POWERPC_EXCP_BRANCH;
3459 /* sign extend LI */
3460 #if defined(TARGET_PPC64)
3461 if (ctx->sf_mode)
3462 li = ((int64_t)LI(ctx->opcode) << 38) >> 38;
3463 else
3464 #endif
3465 li = ((int32_t)LI(ctx->opcode) << 6) >> 6;
3466 if (likely(AA(ctx->opcode) == 0))
3467 target = ctx->nip + li - 4;
3468 else
3469 target = li;
3470 if (LK(ctx->opcode))
3471 gen_setlr(ctx, ctx->nip);
3472 gen_goto_tb(ctx, 0, target);
3473 }
3474
3475 #define BCOND_IM 0
3476 #define BCOND_LR 1
3477 #define BCOND_CTR 2
3478
3479 static always_inline void gen_bcond (DisasContext *ctx, int type)
3480 {
3481 uint32_t bo = BO(ctx->opcode);
3482 int l1 = gen_new_label();
3483 TCGv target;
3484
3485 ctx->exception = POWERPC_EXCP_BRANCH;
3486 if (type == BCOND_LR || type == BCOND_CTR) {
3487 target = tcg_temp_local_new();
3488 if (type == BCOND_CTR)
3489 tcg_gen_mov_tl(target, cpu_ctr);
3490 else
3491 tcg_gen_mov_tl(target, cpu_lr);
3492 }
3493 if (LK(ctx->opcode))
3494 gen_setlr(ctx, ctx->nip);
3495 l1 = gen_new_label();
3496 if ((bo & 0x4) == 0) {
3497 /* Decrement and test CTR */
3498 TCGv temp = tcg_temp_new();
3499 if (unlikely(type == BCOND_CTR)) {
3500 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3501 return;
3502 }
3503 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
3504 #if defined(TARGET_PPC64)
3505 if (!ctx->sf_mode)
3506 tcg_gen_ext32u_tl(temp, cpu_ctr);
3507 else
3508 #endif
3509 tcg_gen_mov_tl(temp, cpu_ctr);
3510 if (bo & 0x2) {
3511 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
3512 } else {
3513 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
3514 }
3515 tcg_temp_free(temp);
3516 }
3517 if ((bo & 0x10) == 0) {
3518 /* Test CR */
3519 uint32_t bi = BI(ctx->opcode);
3520 uint32_t mask = 1 << (3 - (bi & 0x03));
3521 TCGv_i32 temp = tcg_temp_new_i32();
3522
3523 if (bo & 0x8) {
3524 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3525 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
3526 } else {
3527 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3528 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1);
3529 }
3530 tcg_temp_free_i32(temp);
3531 }
3532 if (type == BCOND_IM) {
3533 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode)));
3534 if (likely(AA(ctx->opcode) == 0)) {
3535 gen_goto_tb(ctx, 0, ctx->nip + li - 4);
3536 } else {
3537 gen_goto_tb(ctx, 0, li);
3538 }
3539 gen_set_label(l1);
3540 gen_goto_tb(ctx, 1, ctx->nip);
3541 } else {
3542 #if defined(TARGET_PPC64)
3543 if (!(ctx->sf_mode))
3544 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3);
3545 else
3546 #endif
3547 tcg_gen_andi_tl(cpu_nip, target, ~3);
3548 tcg_gen_exit_tb(0);
3549 gen_set_label(l1);
3550 #if defined(TARGET_PPC64)
3551 if (!(ctx->sf_mode))
3552 tcg_gen_movi_tl(cpu_nip, (uint32_t)ctx->nip);
3553 else
3554 #endif
3555 tcg_gen_movi_tl(cpu_nip, ctx->nip);
3556 tcg_gen_exit_tb(0);
3557 }
3558 }
3559
3560 GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3561 {
3562 gen_bcond(ctx, BCOND_IM);
3563 }
3564
3565 GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW)
3566 {
3567 gen_bcond(ctx, BCOND_CTR);
3568 }
3569
3570 GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW)
3571 {
3572 gen_bcond(ctx, BCOND_LR);
3573 }
3574
3575 /*** Condition register logical ***/
3576 #define GEN_CRLOGIC(name, tcg_op, opc) \
3577 GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) \
3578 { \
3579 uint8_t bitmask; \
3580 int sh; \
3581 TCGv_i32 t0, t1; \
3582 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
3583 t0 = tcg_temp_new_i32(); \
3584 if (sh > 0) \
3585 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
3586 else if (sh < 0) \
3587 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
3588 else \
3589 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
3590 t1 = tcg_temp_new_i32(); \
3591 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
3592 if (sh > 0) \
3593 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
3594 else if (sh < 0) \
3595 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
3596 else \
3597 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
3598 tcg_op(t0, t0, t1); \
3599 bitmask = 1 << (3 - (crbD(ctx->opcode) & 0x03)); \
3600 tcg_gen_andi_i32(t0, t0, bitmask); \
3601 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
3602 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
3603 tcg_temp_free_i32(t0); \
3604 tcg_temp_free_i32(t1); \
3605 }
3606
3607 /* crand */
3608 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08);
3609 /* crandc */
3610 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04);
3611 /* creqv */
3612 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09);
3613 /* crnand */
3614 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07);
3615 /* crnor */
3616 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01);
3617 /* cror */
3618 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E);
3619 /* crorc */
3620 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D);
3621 /* crxor */
3622 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06);
3623 /* mcrf */
3624 GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER)
3625 {
3626 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]);
3627 }
3628
3629 /*** System linkage ***/
3630 /* rfi (mem_idx only) */
3631 GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW)
3632 {
3633 #if defined(CONFIG_USER_ONLY)
3634 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3635 #else
3636 /* Restore CPU state */
3637 if (unlikely(!ctx->mem_idx)) {
3638 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3639 return;
3640 }
3641 gen_helper_rfi();
3642 gen_sync_exception(ctx);
3643 #endif
3644 }
3645
3646 #if defined(TARGET_PPC64)
3647 GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B)
3648 {
3649 #if defined(CONFIG_USER_ONLY)
3650 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3651 #else
3652 /* Restore CPU state */
3653 if (unlikely(!ctx->mem_idx)) {
3654 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3655 return;
3656 }
3657 gen_helper_rfid();
3658 gen_sync_exception(ctx);
3659 #endif
3660 }
3661
3662 GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H)
3663 {
3664 #if defined(CONFIG_USER_ONLY)
3665 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3666 #else
3667 /* Restore CPU state */
3668 if (unlikely(ctx->mem_idx <= 1)) {
3669 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3670 return;
3671 }
3672 gen_helper_hrfid();
3673 gen_sync_exception(ctx);
3674 #endif
3675 }
3676 #endif
3677
3678 /* sc */
3679 #if defined(CONFIG_USER_ONLY)
3680 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
3681 #else
3682 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
3683 #endif
3684 GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW)
3685 {
3686 uint32_t lev;
3687
3688 lev = (ctx->opcode >> 5) & 0x7F;
3689 gen_exception_err(ctx, POWERPC_SYSCALL, lev);
3690 }
3691
3692 /*** Trap ***/
3693 /* tw */
3694 GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW)
3695 {
3696 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
3697 /* Update the nip since this might generate a trap exception */
3698 gen_update_nip(ctx, ctx->nip);
3699 gen_helper_tw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
3700 tcg_temp_free_i32(t0);
3701 }
3702
3703 /* twi */
3704 GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3705 {
3706 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
3707 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
3708 /* Update the nip since this might generate a trap exception */
3709 gen_update_nip(ctx, ctx->nip);
3710 gen_helper_tw(cpu_gpr[rA(ctx->opcode)], t0, t1);
3711 tcg_temp_free(t0);
3712 tcg_temp_free_i32(t1);
3713 }
3714
3715 #if defined(TARGET_PPC64)
3716 /* td */
3717 GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B)
3718 {
3719 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
3720 /* Update the nip since this might generate a trap exception */
3721 gen_update_nip(ctx, ctx->nip);
3722 gen_helper_td(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
3723 tcg_temp_free_i32(t0);
3724 }
3725
3726 /* tdi */
3727 GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B)
3728 {
3729 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
3730 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
3731 /* Update the nip since this might generate a trap exception */
3732 gen_update_nip(ctx, ctx->nip);
3733 gen_helper_td(cpu_gpr[rA(ctx->opcode)], t0, t1);
3734 tcg_temp_free(t0);
3735 tcg_temp_free_i32(t1);
3736 }
3737 #endif
3738
3739 /*** Processor control ***/
3740 /* mcrxr */
3741 GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC)
3742 {
3743 tcg_gen_trunc_tl_i32(cpu_crf[crfD(ctx->opcode)], cpu_xer);
3744 tcg_gen_shri_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], XER_CA);
3745 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_SO | 1 << XER_OV | 1 << XER_CA));
3746 }
3747
3748 /* mfcr mfocrf */
3749 GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC)
3750 {
3751 uint32_t crm, crn;
3752
3753 if (likely(ctx->opcode & 0x00100000)) {
3754 crm = CRM(ctx->opcode);
3755 if (likely(crm && ((crm & (crm - 1)) == 0))) {
3756 crn = ctz32 (crm);
3757 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
3758 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)],
3759 cpu_gpr[rD(ctx->opcode)], crn * 4);
3760 }
3761 } else {
3762 TCGv_i32 t0 = tcg_temp_new_i32();
3763 tcg_gen_mov_i32(t0, cpu_crf[0]);
3764 tcg_gen_shli_i32(t0, t0, 4);
3765 tcg_gen_or_i32(t0, t0, cpu_crf[1]);
3766 tcg_gen_shli_i32(t0, t0, 4);
3767 tcg_gen_or_i32(t0, t0, cpu_crf[2]);
3768 tcg_gen_shli_i32(t0, t0, 4);
3769 tcg_gen_or_i32(t0, t0, cpu_crf[3]);
3770 tcg_gen_shli_i32(t0, t0, 4);
3771 tcg_gen_or_i32(t0, t0, cpu_crf[4]);
3772 tcg_gen_shli_i32(t0, t0, 4);
3773 tcg_gen_or_i32(t0, t0, cpu_crf[5]);
3774 tcg_gen_shli_i32(t0, t0, 4);
3775 tcg_gen_or_i32(t0, t0, cpu_crf[6]);
3776 tcg_gen_shli_i32(t0, t0, 4);
3777 tcg_gen_or_i32(t0, t0, cpu_crf[7]);
3778 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
3779 tcg_temp_free_i32(t0);
3780 }
3781 }
3782
3783 /* mfmsr */
3784 GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC)
3785 {
3786 #if defined(CONFIG_USER_ONLY)
3787 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3788 #else
3789 if (unlikely(!ctx->mem_idx)) {
3790 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3791 return;
3792 }
3793 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr);
3794 #endif
3795 }
3796
3797 #if 1
3798 #define SPR_NOACCESS ((void *)(-1UL))
3799 #else
3800 static void spr_noaccess (void *opaque, int sprn)
3801 {
3802 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
3803 printf("ERROR: try to access SPR %d !\n", sprn);
3804 }
3805 #define SPR_NOACCESS (&spr_noaccess)
3806 #endif
3807
3808 /* mfspr */
3809 static always_inline void gen_op_mfspr (DisasContext *ctx)
3810 {
3811 void (*read_cb)(void *opaque, int gprn, int sprn);
3812 uint32_t sprn = SPR(ctx->opcode);
3813
3814 #if !defined(CONFIG_USER_ONLY)
3815 if (ctx->mem_idx == 2)
3816 read_cb = ctx->spr_cb[sprn].hea_read;
3817 else if (ctx->mem_idx)
3818 read_cb = ctx->spr_cb[sprn].oea_read;
3819 else
3820 #endif
3821 read_cb = ctx->spr_cb[sprn].uea_read;
3822 if (likely(read_cb != NULL)) {
3823 if (likely(read_cb != SPR_NOACCESS)) {
3824 (*read_cb)(ctx, rD(ctx->opcode), sprn);
3825 } else {
3826 /* Privilege exception */
3827 /* This is a hack to avoid warnings when running Linux:
3828 * this OS breaks the PowerPC virtualisation model,
3829 * allowing userland application to read the PVR
3830 */
3831 if (sprn != SPR_PVR) {
3832 qemu_log("Trying to read privileged spr %d %03x at "
3833 ADDRX "\n", sprn, sprn, ctx->nip);
3834 printf("Trying to read privileged spr %d %03x at " ADDRX "\n",
3835 sprn, sprn, ctx->nip);
3836 }
3837 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3838 }
3839 } else {
3840 /* Not defined */
3841 qemu_log("Trying to read invalid spr %d %03x at "
3842 ADDRX "\n", sprn, sprn, ctx->nip);
3843 printf("Trying to read invalid spr %d %03x at " ADDRX "\n",
3844 sprn, sprn, ctx->nip);
3845 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
3846 }
3847 }
3848
3849 GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC)
3850 {
3851 gen_op_mfspr(ctx);
3852 }
3853
3854 /* mftb */
3855 GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB)
3856 {
3857 gen_op_mfspr(ctx);
3858 }
3859
3860 /* mtcrf mtocrf*/
3861 GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC)
3862 {
3863 uint32_t crm, crn;
3864
3865 crm = CRM(ctx->opcode);
3866 if (likely((ctx->opcode & 0x00100000))) {
3867 if (crm && ((crm & (crm - 1)) == 0)) {
3868 TCGv_i32 temp = tcg_temp_new_i32();
3869 crn = ctz32 (crm);
3870 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
3871 tcg_gen_shri_i32(temp, temp, crn * 4);
3872 tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf);
3873 tcg_temp_free_i32(temp);
3874 }
3875 } else {
3876 TCGv_i32 temp = tcg_temp_new_i32();
3877 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
3878 for (crn = 0 ; crn < 8 ; crn++) {
3879 if (crm & (1 << crn)) {
3880 tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4);
3881 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
3882 }
3883 }
3884 tcg_temp_free_i32(temp);
3885 }
3886 }
3887
3888 /* mtmsr */
3889 #if defined(TARGET_PPC64)
3890 GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B)
3891 {
3892 #if defined(CONFIG_USER_ONLY)
3893 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3894 #else
3895 if (unlikely(!ctx->mem_idx)) {
3896 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3897 return;
3898 }
3899 if (ctx->opcode & 0x00010000) {
3900 /* Special form that does not need any synchronisation */
3901 TCGv t0 = tcg_temp_new();
3902 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
3903 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
3904 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
3905 tcg_temp_free(t0);
3906 } else {
3907 /* XXX: we need to update nip before the store
3908 * if we enter power saving mode, we will exit the loop
3909 * directly from ppc_store_msr
3910 */
3911 gen_update_nip(ctx, ctx->nip);
3912 gen_helper_store_msr(cpu_gpr[rS(ctx->opcode)]);
3913 /* Must stop the translation as machine state (may have) changed */
3914 /* Note that mtmsr is not always defined as context-synchronizing */
3915 gen_stop_exception(ctx);
3916 }
3917 #endif
3918 }
3919 #endif
3920
3921 GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC)
3922 {
3923 #if defined(CONFIG_USER_ONLY)
3924 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3925 #else
3926 if (unlikely(!ctx->mem_idx)) {
3927 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3928 return;
3929 }
3930 if (ctx->opcode & 0x00010000) {
3931 /* Special form that does not need any synchronisation */
3932 TCGv t0 = tcg_temp_new();
3933 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
3934 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
3935 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
3936 tcg_temp_free(t0);
3937 } else {
3938 /* XXX: we need to update nip before the store
3939 * if we enter power saving mode, we will exit the loop
3940 * directly from ppc_store_msr
3941 */
3942 gen_update_nip(ctx, ctx->nip);
3943 #if defined(TARGET_PPC64)
3944 if (!ctx->sf_mode) {
3945 TCGv t0 = tcg_temp_new();
3946 TCGv t1 = tcg_temp_new();
3947 tcg_gen_andi_tl(t0, cpu_msr, 0xFFFFFFFF00000000ULL);
3948 tcg_gen_ext32u_tl(t1, cpu_gpr[rS(ctx->opcode)]);
3949 tcg_gen_or_tl(t0, t0, t1);
3950 tcg_temp_free(t1);
3951 gen_helper_store_msr(t0);
3952 tcg_temp_free(t0);
3953 } else
3954 #endif
3955 gen_helper_store_msr(cpu_gpr[rS(ctx->opcode)]);
3956 /* Must stop the translation as machine state (may have) changed */
3957 /* Note that mtmsr is not always defined as context-synchronizing */
3958 gen_stop_exception(ctx);
3959 }
3960 #endif
3961 }
3962
3963 /* mtspr */
3964 GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC)
3965 {
3966 void (*write_cb)(void *opaque, int sprn, int gprn);
3967 uint32_t sprn = SPR(ctx->opcode);
3968
3969 #if !defined(CONFIG_USER_ONLY)
3970 if (ctx->mem_idx == 2)
3971 write_cb = ctx->spr_cb[sprn].hea_write;
3972 else if (ctx->mem_idx)
3973 write_cb = ctx->spr_cb[sprn].oea_write;
3974 else
3975 #endif
3976 write_cb = ctx->spr_cb[sprn].uea_write;
3977 if (likely(write_cb != NULL)) {
3978 if (likely(write_cb != SPR_NOACCESS)) {
3979 (*write_cb)(ctx, sprn, rS(ctx->opcode));
3980 } else {
3981 /* Privilege exception */
3982 qemu_log("Trying to write privileged spr %d %03x at "
3983 ADDRX "\n", sprn, sprn, ctx->nip);
3984 printf("Trying to write privileged spr %d %03x at " ADDRX "\n",
3985 sprn, sprn, ctx->nip);
3986 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3987 }
3988 } else {
3989 /* Not defined */
3990 qemu_log("Trying to write invalid spr %d %03x at "
3991 ADDRX "\n", sprn, sprn, ctx->nip);
3992 printf("Trying to write invalid spr %d %03x at " ADDRX "\n",
3993 sprn, sprn, ctx->nip);
3994 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
3995 }
3996 }
3997
3998 /*** Cache management ***/
3999 /* dcbf */
4000 GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE)
4001 {
4002 /* XXX: specification says this is treated as a load by the MMU */
4003 TCGv t0;
4004 gen_set_access_type(ctx, ACCESS_CACHE);
4005 t0 = tcg_temp_new();
4006 gen_addr_reg_index(ctx, t0);
4007 gen_qemu_ld8u(ctx, t0, t0);
4008 tcg_temp_free(t0);
4009 }
4010
4011 /* dcbi (Supervisor only) */
4012 GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE)
4013 {
4014 #if defined(CONFIG_USER_ONLY)
4015 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4016 #else
4017 TCGv EA, val;
4018 if (unlikely(!ctx->mem_idx)) {
4019 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4020 return;
4021 }
4022 EA = tcg_temp_new();
4023 gen_set_access_type(ctx, ACCESS_CACHE);
4024 gen_addr_reg_index(ctx, EA);
4025 val = tcg_temp_new();
4026 /* XXX: specification says this should be treated as a store by the MMU */
4027 gen_qemu_ld8u(ctx, val, EA);
4028 gen_qemu_st8(ctx, val, EA);
4029 tcg_temp_free(val);
4030 tcg_temp_free(EA);
4031 #endif
4032 }
4033
4034 /* dcdst */
4035 GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE)
4036 {
4037 /* XXX: specification say this is treated as a load by the MMU */
4038 TCGv t0;
4039 gen_set_access_type(ctx, ACCESS_CACHE);
4040 t0 = tcg_temp_new();
4041 gen_addr_reg_index(ctx, t0);
4042 gen_qemu_ld8u(ctx, t0, t0);
4043 tcg_temp_free(t0);
4044 }
4045
4046 /* dcbt */
4047 GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x02000001, PPC_CACHE)
4048 {
4049 /* interpreted as no-op */
4050 /* XXX: specification say this is treated as a load by the MMU
4051 * but does not generate any exception
4052 */
4053 }
4054
4055 /* dcbtst */
4056 GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x02000001, PPC_CACHE)
4057 {
4058 /* interpreted as no-op */
4059 /* XXX: specification say this is treated as a load by the MMU
4060 * but does not generate any exception
4061 */
4062 }
4063
4064 /* dcbz */
4065 GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03E00001, PPC_CACHE_DCBZ)
4066 {
4067 TCGv t0;
4068 gen_set_access_type(ctx, ACCESS_CACHE);
4069 /* NIP cannot be restored if the memory exception comes from an helper */
4070 gen_update_nip(ctx, ctx->nip - 4);
4071 t0 = tcg_temp_new();
4072 gen_addr_reg_index(ctx, t0);
4073 gen_helper_dcbz(t0);
4074 tcg_temp_free(t0);
4075 }
4076
4077 GEN_HANDLER2(dcbz_970, "dcbz", 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZT)
4078 {
4079 TCGv t0;
4080 gen_set_access_type(ctx, ACCESS_CACHE);
4081 /* NIP cannot be restored if the memory exception comes from an helper */
4082 gen_update_nip(ctx, ctx->nip - 4);
4083 t0 = tcg_temp_new();
4084 gen_addr_reg_index(ctx, t0);
4085 if (ctx->opcode & 0x00200000)
4086 gen_helper_dcbz(t0);
4087 else
4088 gen_helper_dcbz_970(t0);
4089 tcg_temp_free(t0);
4090 }
4091
4092 /* dst / dstt */
4093 GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC)
4094 {
4095 if (rA(ctx->opcode) == 0) {
4096 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4097 } else {
4098 /* interpreted as no-op */
4099 }
4100 }
4101
4102 /* dstst /dststt */
4103 GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC)
4104 {
4105 if (rA(ctx->opcode) == 0) {
4106 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4107 } else {
4108 /* interpreted as no-op */
4109 }
4110
4111 }
4112
4113 /* dss / dssall */
4114 GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC)
4115 {
4116 /* interpreted as no-op */
4117 }
4118
4119 /* icbi */
4120 GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI)
4121 {
4122 TCGv t0;
4123 gen_set_access_type(ctx, ACCESS_CACHE);
4124 /* NIP cannot be restored if the memory exception comes from an helper */
4125 gen_update_nip(ctx, ctx->nip - 4);
4126 t0 = tcg_temp_new();
4127 gen_addr_reg_index(ctx, t0);
4128 gen_helper_icbi(t0);
4129 tcg_temp_free(t0);
4130 }
4131
4132 /* Optional: */
4133 /* dcba */
4134 GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA)
4135 {
4136 /* interpreted as no-op */
4137 /* XXX: specification say this is treated as a store by the MMU
4138 * but does not generate any exception
4139 */
4140 }
4141
4142 /*** Segment register manipulation ***/
4143 /* Supervisor only: */
4144 /* mfsr */
4145 GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT)
4146 {
4147 #if defined(CONFIG_USER_ONLY)
4148 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4149 #else
4150 TCGv t0;
4151 if (unlikely(!ctx->mem_idx)) {
4152 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4153 return;
4154 }
4155 t0 = tcg_const_tl(SR(ctx->opcode));
4156 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], t0);
4157 tcg_temp_free(t0);
4158 #endif
4159 }
4160
4161 /* mfsrin */
4162 GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT)
4163 {
4164 #if defined(CONFIG_USER_ONLY)
4165 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4166 #else
4167 TCGv t0;
4168 if (unlikely(!ctx->mem_idx)) {
4169 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4170 return;
4171 }
4172 t0 = tcg_temp_new();
4173 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4174 tcg_gen_andi_tl(t0, t0, 0xF);
4175 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], t0);
4176 tcg_temp_free(t0);
4177 #endif
4178 }
4179
4180 /* mtsr */
4181 GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT)
4182 {
4183 #if defined(CONFIG_USER_ONLY)
4184 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4185 #else
4186 TCGv t0;
4187 if (unlikely(!ctx->mem_idx)) {
4188 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4189 return;
4190 }
4191 t0 = tcg_const_tl(SR(ctx->opcode));
4192 gen_helper_store_sr(t0, cpu_gpr[rS(ctx->opcode)]);
4193 tcg_temp_free(t0);
4194 #endif
4195 }
4196
4197 /* mtsrin */
4198 GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT)
4199 {
4200 #if defined(CONFIG_USER_ONLY)
4201 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4202 #else
4203 TCGv t0;
4204 if (unlikely(!ctx->mem_idx)) {
4205 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4206 return;
4207 }
4208 t0 = tcg_temp_new();
4209 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4210 tcg_gen_andi_tl(t0, t0, 0xF);
4211 gen_helper_store_sr(t0, cpu_gpr[rD(ctx->opcode)]);
4212 tcg_temp_free(t0);
4213 #endif
4214 }
4215
4216 #if defined(TARGET_PPC64)
4217 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4218 /* mfsr */
4219 GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B)
4220 {
4221 #if defined(CONFIG_USER_ONLY)
4222 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4223 #else
4224 TCGv t0;
4225 if (unlikely(!ctx->mem_idx)) {
4226 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4227 return;
4228 }
4229 t0 = tcg_const_tl(SR(ctx->opcode));
4230 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], t0);
4231 tcg_temp_free(t0);
4232 #endif
4233 }
4234
4235 /* mfsrin */
4236 GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
4237 PPC_SEGMENT_64B)
4238 {
4239 #if defined(CONFIG_USER_ONLY)
4240 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4241 #else
4242 TCGv t0;
4243 if (unlikely(!ctx->mem_idx)) {
4244 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4245 return;
4246 }
4247 t0 = tcg_temp_new();
4248 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4249 tcg_gen_andi_tl(t0, t0, 0xF);
4250 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], t0);
4251 tcg_temp_free(t0);
4252 #endif
4253 }
4254
4255 /* mtsr */
4256 GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B)
4257 {
4258 #if defined(CONFIG_USER_ONLY)
4259 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4260 #else
4261 TCGv t0;
4262 if (unlikely(!ctx->mem_idx)) {
4263 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4264 return;
4265 }
4266 t0 = tcg_const_tl(SR(ctx->opcode));
4267 gen_helper_store_sr(t0, cpu_gpr[rS(ctx->opcode)]);
4268 tcg_temp_free(t0);
4269 #endif
4270 }
4271
4272 /* mtsrin */
4273 GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
4274 PPC_SEGMENT_64B)
4275 {
4276 #if defined(CONFIG_USER_ONLY)
4277 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4278 #else
4279 TCGv t0;
4280 if (unlikely(!ctx->mem_idx)) {
4281 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4282 return;
4283 }
4284 t0 = tcg_temp_new();
4285 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4286 tcg_gen_andi_tl(t0, t0, 0xF);
4287 gen_helper_store_sr(t0, cpu_gpr[rS(ctx->opcode)]);
4288 tcg_temp_free(t0);
4289 #endif
4290 }
4291
4292 /* slbmte */
4293 GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x00000000, PPC_SEGMENT_64B)
4294 {
4295 #if defined(CONFIG_USER_ONLY)
4296 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4297 #else
4298 if (unlikely(!ctx->mem_idx)) {
4299 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4300 return;
4301 }
4302 gen_helper_store_slb(cpu_gpr[rB(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
4303 #endif
4304 }
4305
4306 #endif /* defined(TARGET_PPC64) */
4307
4308 /*** Lookaside buffer management ***/
4309 /* Optional & mem_idx only: */
4310 /* tlbia */
4311 GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA)
4312 {
4313 #if defined(CONFIG_USER_ONLY)
4314 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4315 #else
4316 if (unlikely(!ctx->mem_idx)) {
4317 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4318 return;
4319 }
4320 gen_helper_tlbia();
4321 #endif
4322 }
4323
4324 /* tlbiel */
4325 GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x03FF0001, PPC_MEM_TLBIE)
4326 {
4327 #if defined(CONFIG_USER_ONLY)
4328 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4329 #else
4330 if (unlikely(!ctx->mem_idx)) {
4331 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4332 return;
4333 }
4334 gen_helper_tlbie(cpu_gpr[rB(ctx->opcode)]);
4335 #endif
4336 }
4337
4338 /* tlbie */
4339 GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE)
4340 {
4341 #if defined(CONFIG_USER_ONLY)
4342 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4343 #else
4344 if (unlikely(!ctx->mem_idx)) {
4345 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4346 return;
4347 }
4348 #if defined(TARGET_PPC64)
4349 if (!ctx->sf_mode) {
4350 TCGv t0 = tcg_temp_new();
4351 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
4352 gen_helper_tlbie(t0);
4353 tcg_temp_free(t0);
4354 } else
4355 #endif
4356 gen_helper_tlbie(cpu_gpr[rB(ctx->opcode)]);
4357 #endif
4358 }
4359
4360 /* tlbsync */
4361 GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC)
4362 {
4363 #if defined(CONFIG_USER_ONLY)
4364 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4365 #else
4366 if (unlikely(!ctx->mem_idx)) {
4367 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4368 return;
4369 }
4370 /* This has no effect: it should ensure that all previous
4371 * tlbie have completed
4372 */
4373 gen_stop_exception(ctx);
4374 #endif
4375 }
4376
4377 #if defined(TARGET_PPC64)
4378 /* slbia */
4379 GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI)
4380 {
4381 #if defined(CONFIG_USER_ONLY)
4382 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4383 #else
4384 if (unlikely(!ctx->mem_idx)) {
4385 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4386 return;
4387 }
4388 gen_helper_slbia();
4389 #endif
4390 }
4391
4392 /* slbie */
4393 GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI)
4394 {
4395 #if defined(CONFIG_USER_ONLY)
4396 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4397 #else
4398 if (unlikely(!ctx->mem_idx)) {
4399 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4400 return;
4401 }
4402 gen_helper_slbie(cpu_gpr[rB(ctx->opcode)]);
4403 #endif
4404 }
4405 #endif
4406
4407 /*** External control ***/
4408 /* Optional: */
4409 /* eciwx */
4410 GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN)
4411 {
4412 TCGv t0;
4413 /* Should check EAR[E] ! */
4414 gen_set_access_type(ctx, ACCESS_EXT);
4415 t0 = tcg_temp_new();
4416 gen_addr_reg_index(ctx, t0);
4417 gen_check_align(ctx, t0, 0x03);
4418 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4419 tcg_temp_free(t0);
4420 }
4421
4422 /* ecowx */
4423 GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN)
4424 {
4425 TCGv t0;
4426 /* Should check EAR[E] ! */
4427 gen_set_access_type(ctx, ACCESS_EXT);
4428 t0 = tcg_temp_new();
4429 gen_addr_reg_index(ctx, t0);
4430 gen_check_align(ctx, t0, 0x03);
4431 gen_qemu_st32(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4432 tcg_temp_free(t0);
4433 }
4434
4435 /* PowerPC 601 specific instructions */
4436 /* abs - abs. */
4437 GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR)
4438 {
4439 int l1 = gen_new_label();
4440 int l2 = gen_new_label();
4441 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1);
4442 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4443 tcg_gen_br(l2);
4444 gen_set_label(l1);
4445 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4446 gen_set_label(l2);
4447 if (unlikely(Rc(ctx->opcode) != 0))
4448 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4449 }
4450
4451 /* abso - abso. */
4452 GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR)
4453 {
4454 int l1 = gen_new_label();
4455 int l2 = gen_new_label();
4456 int l3 = gen_new_label();
4457 /* Start with XER OV disabled, the most likely case */
4458 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
4459 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2);
4460 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1);
4461 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
4462 tcg_gen_br(l2);
4463 gen_set_label(l1);
4464 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4465 tcg_gen_br(l3);
4466 gen_set_label(l2);
4467 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4468 gen_set_label(l3);
4469 if (unlikely(Rc(ctx->opcode) != 0))
4470 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4471 }
4472
4473 /* clcs */
4474 GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR)
4475 {
4476 TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode));
4477 gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], t0);
4478 tcg_temp_free_i32(t0);
4479 /* Rc=1 sets CR0 to an undefined state */
4480 }
4481
4482 /* div - div. */
4483 GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR)
4484 {
4485 gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4486 if (unlikely(Rc(ctx->opcode) != 0))
4487 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4488 }
4489
4490 /* divo - divo. */
4491 GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR)
4492 {
4493 gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4494 if (unlikely(Rc(ctx->opcode) != 0))
4495 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4496 }
4497
4498 /* divs - divs. */
4499 GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR)
4500 {
4501 gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4502 if (unlikely(Rc(ctx->opcode) != 0))
4503 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4504 }
4505
4506 /* divso - divso. */
4507 GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR)
4508 {
4509 gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4510 if (unlikely(Rc(ctx->opcode) != 0))
4511 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4512 }
4513
4514 /* doz - doz. */
4515 GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR)
4516 {
4517 int l1 = gen_new_label();
4518 int l2 = gen_new_label();
4519 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4520 tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4521 tcg_gen_br(l2);
4522 gen_set_label(l1);
4523 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4524 gen_set_label(l2);
4525 if (unlikely(Rc(ctx->opcode) != 0))
4526 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4527 }
4528
4529 /* dozo - dozo. */
4530 GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR)
4531 {
4532 int l1 = gen_new_label();
4533 int l2 = gen_new_label();
4534 TCGv t0 = tcg_temp_new();
4535 TCGv t1 = tcg_temp_new();
4536 TCGv t2 = tcg_temp_new();
4537 /* Start with XER OV disabled, the most likely case */
4538 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
4539 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4540 tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4541 tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4542 tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0);
4543 tcg_gen_andc_tl(t1, t1, t2);
4544 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
4545 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
4546 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
4547 tcg_gen_br(l2);
4548 gen_set_label(l1);
4549 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4550 gen_set_label(l2);
4551 tcg_temp_free(t0);
4552 tcg_temp_free(t1);
4553 tcg_temp_free(t2);
4554 if (unlikely(Rc(ctx->opcode) != 0))
4555 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4556 }
4557
4558 /* dozi */
4559 GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR)
4560 {
4561 target_long simm = SIMM(ctx->opcode);
4562 int l1 = gen_new_label();
4563 int l2 = gen_new_label();
4564 tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1);
4565 tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]);
4566 tcg_gen_br(l2);
4567 gen_set_label(l1);
4568 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4569 gen_set_label(l2);
4570 if (unlikely(Rc(ctx->opcode) != 0))
4571 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4572 }
4573
4574 /* lscbx - lscbx. */
4575 GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR)
4576 {
4577 TCGv t0 = tcg_temp_new();
4578 TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode));
4579 TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode));
4580 TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode));
4581
4582 gen_addr_reg_index(ctx, t0);
4583 /* NIP cannot be restored if the memory exception comes from an helper */
4584 gen_update_nip(ctx, ctx->nip - 4);
4585 gen_helper_lscbx(t0, t0, t1, t2, t3);
4586 tcg_temp_free_i32(t1);
4587 tcg_temp_free_i32(t2);
4588 tcg_temp_free_i32(t3);
4589 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
4590 tcg_gen_or_tl(cpu_xer, cpu_xer, t0);
4591 if (unlikely(Rc(ctx->opcode) != 0))
4592 gen_set_Rc0(ctx, t0);
4593 tcg_temp_free(t0);
4594 }
4595
4596 /* maskg - maskg. */
4597 GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR)
4598 {
4599 int l1 = gen_new_label();
4600 TCGv t0 = tcg_temp_new();
4601 TCGv t1 = tcg_temp_new();
4602 TCGv t2 = tcg_temp_new();
4603 TCGv t3 = tcg_temp_new();
4604 tcg_gen_movi_tl(t3, 0xFFFFFFFF);
4605 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4606 tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F);
4607 tcg_gen_addi_tl(t2, t0, 1);
4608 tcg_gen_shr_tl(t2, t3, t2);
4609 tcg_gen_shr_tl(t3, t3, t1);
4610 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3);
4611 tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1);
4612 tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4613 gen_set_label(l1);
4614 tcg_temp_free(t0);
4615 tcg_temp_free(t1);
4616 tcg_temp_free(t2);
4617 tcg_temp_free(t3);
4618 if (unlikely(Rc(ctx->opcode) != 0))
4619 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4620 }
4621
4622 /* maskir - maskir. */
4623 GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR)
4624 {
4625 TCGv t0 = tcg_temp_new();
4626 TCGv t1 = tcg_temp_new();
4627 tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4628 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4629 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4630 tcg_temp_free(t0);
4631 tcg_temp_free(t1);
4632 if (unlikely(Rc(ctx->opcode) != 0))
4633 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4634 }
4635
4636 /* mul - mul. */
4637 GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR)
4638 {
4639 TCGv_i64 t0 = tcg_temp_new_i64();
4640 TCGv_i64 t1 = tcg_temp_new_i64();
4641 TCGv t2 = tcg_temp_new();
4642 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4643 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4644 tcg_gen_mul_i64(t0, t0, t1);
4645 tcg_gen_trunc_i64_tl(t2, t0);
4646 gen_store_spr(SPR_MQ, t2);
4647 tcg_gen_shri_i64(t1, t0, 32);
4648 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4649 tcg_temp_free_i64(t0);
4650 tcg_temp_free_i64(t1);
4651 tcg_temp_free(t2);
4652 if (unlikely(Rc(ctx->opcode) != 0))
4653 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4654 }
4655
4656 /* mulo - mulo. */
4657 GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR)
4658 {
4659 int l1 = gen_new_label();
4660 TCGv_i64 t0 = tcg_temp_new_i64();
4661 TCGv_i64 t1 = tcg_temp_new_i64();
4662 TCGv t2 = tcg_temp_new();
4663 /* Start with XER OV disabled, the most likely case */
4664 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
4665 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4666 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4667 tcg_gen_mul_i64(t0, t0, t1);
4668 tcg_gen_trunc_i64_tl(t2, t0);
4669 gen_store_spr(SPR_MQ, t2);
4670 tcg_gen_shri_i64(t1, t0, 32);
4671 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4672 tcg_gen_ext32s_i64(t1, t0);
4673 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
4674 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
4675 gen_set_label(l1);
4676 tcg_temp_free_i64(t0);
4677 tcg_temp_free_i64(t1);
4678 tcg_temp_free(t2);
4679 if (unlikely(Rc(ctx->opcode) != 0))
4680 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4681 }
4682
4683 /* nabs - nabs. */
4684 GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR)
4685 {
4686 int l1 = gen_new_label();
4687 int l2 = gen_new_label();
4688 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4689 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4690 tcg_gen_br(l2);
4691 gen_set_label(l1);
4692 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4693 gen_set_label(l2);
4694 if (unlikely(Rc(ctx->opcode) != 0))
4695 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4696 }
4697
4698 /* nabso - nabso. */
4699 GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR)
4700 {
4701 int l1 = gen_new_label();
4702 int l2 = gen_new_label();
4703 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4704 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4705 tcg_gen_br(l2);
4706 gen_set_label(l1);
4707 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4708 gen_set_label(l2);
4709 /* nabs never overflows */
4710 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
4711 if (unlikely(Rc(ctx->opcode) != 0))
4712 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4713 }
4714
4715 /* rlmi - rlmi. */
4716 GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR)
4717 {
4718 uint32_t mb = MB(ctx->opcode);
4719 uint32_t me = ME(ctx->opcode);
4720 TCGv t0 = tcg_temp_new();
4721 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4722 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4723 tcg_gen_andi_tl(t0, t0, MASK(mb, me));
4724 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~MASK(mb, me));
4725 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0);
4726 tcg_temp_free(t0);
4727 if (unlikely(Rc(ctx->opcode) != 0))
4728 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4729 }
4730
4731 /* rrib - rrib. */
4732 GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR)
4733 {
4734 TCGv t0 = tcg_temp_new();
4735 TCGv t1 = tcg_temp_new();
4736 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4737 tcg_gen_movi_tl(t1, 0x80000000);
4738 tcg_gen_shr_tl(t1, t1, t0);
4739 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4740 tcg_gen_and_tl(t0, t0, t1);
4741 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1);
4742 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4743 tcg_temp_free(t0);
4744 tcg_temp_free(t1);
4745 if (unlikely(Rc(ctx->opcode) != 0))
4746 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4747 }
4748
4749 /* sle - sle. */
4750 GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR)
4751 {
4752 TCGv t0 = tcg_temp_new();
4753 TCGv t1 = tcg_temp_new();
4754 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4755 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4756 tcg_gen_subfi_tl(t1, 32, t1);
4757 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4758 tcg_gen_or_tl(t1, t0, t1);
4759 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4760 gen_store_spr(SPR_MQ, t1);
4761 tcg_temp_free(t0);
4762 tcg_temp_free(t1);
4763 if (unlikely(Rc(ctx->opcode) != 0))
4764 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4765 }
4766
4767 /* sleq - sleq. */
4768 GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR)
4769 {
4770 TCGv t0 = tcg_temp_new();
4771 TCGv t1 = tcg_temp_new();
4772 TCGv t2 = tcg_temp_new();
4773 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4774 tcg_gen_movi_tl(t2, 0xFFFFFFFF);
4775 tcg_gen_shl_tl(t2, t2, t0);
4776 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4777 gen_load_spr(t1, SPR_MQ);
4778 gen_store_spr(SPR_MQ, t0);
4779 tcg_gen_and_tl(t0, t0, t2);
4780 tcg_gen_andc_tl(t1, t1, t2);
4781 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4782 tcg_temp_free(t0);
4783 tcg_temp_free(t1);
4784 tcg_temp_free(t2);
4785 if (unlikely(Rc(ctx->opcode) != 0))
4786 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4787 }
4788
4789 /* sliq - sliq. */
4790 GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR)
4791 {
4792 int sh = SH(ctx->opcode);
4793 TCGv t0 = tcg_temp_new();
4794 TCGv t1 = tcg_temp_new();
4795 tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4796 tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
4797 tcg_gen_or_tl(t1, t0, t1);
4798 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4799 gen_store_spr(SPR_MQ, t1);
4800 tcg_temp_free(t0);
4801 tcg_temp_free(t1);
4802 if (unlikely(Rc(ctx->opcode) != 0))
4803 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4804 }
4805
4806 /* slliq - slliq. */
4807 GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR)
4808 {
4809 int sh = SH(ctx->opcode);
4810 TCGv t0 = tcg_temp_new();
4811 TCGv t1 = tcg_temp_new();
4812 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4813 gen_load_spr(t1, SPR_MQ);
4814 gen_store_spr(SPR_MQ, t0);
4815 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh));
4816 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh));
4817 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4818 tcg_temp_free(t0);
4819 tcg_temp_free(t1);
4820 if (unlikely(Rc(ctx->opcode) != 0))
4821 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4822 }
4823
4824 /* sllq - sllq. */
4825 GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR)
4826 {
4827 int l1 = gen_new_label();
4828 int l2 = gen_new_label();
4829 TCGv t0 = tcg_temp_local_new();
4830 TCGv t1 = tcg_temp_local_new();
4831 TCGv t2 = tcg_temp_local_new();
4832 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
4833 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
4834 tcg_gen_shl_tl(t1, t1, t2);
4835 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
4836 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
4837 gen_load_spr(t0, SPR_MQ);
4838 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4839 tcg_gen_br(l2);
4840 gen_set_label(l1);
4841 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
4842 gen_load_spr(t2, SPR_MQ);
4843 tcg_gen_andc_tl(t1, t2, t1);
4844 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4845 gen_set_label(l2);
4846 tcg_temp_free(t0);
4847 tcg_temp_free(t1);
4848 tcg_temp_free(t2);
4849 if (unlikely(Rc(ctx->opcode) != 0))
4850 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4851 }
4852
4853 /* slq - slq. */
4854 GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR)
4855 {
4856 int l1 = gen_new_label();
4857 TCGv t0 = tcg_temp_new();
4858 TCGv t1 = tcg_temp_new();
4859 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4860 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4861 tcg_gen_subfi_tl(t1, 32, t1);
4862 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4863 tcg_gen_or_tl(t1, t0, t1);
4864 gen_store_spr(SPR_MQ, t1);
4865 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
4866 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4867 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
4868 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
4869 gen_set_label(l1);
4870 tcg_temp_free(t0);
4871 tcg_temp_free(t1);
4872 if (unlikely(Rc(ctx->opcode) != 0))
4873 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4874 }
4875
4876 /* sraiq - sraiq. */
4877 GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR)
4878 {
4879 int sh = SH(ctx->opcode);
4880 int l1 = gen_new_label();
4881 TCGv t0 = tcg_temp_new();
4882 TCGv t1 = tcg_temp_new();
4883 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4884 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
4885 tcg_gen_or_tl(t0, t0, t1);
4886 gen_store_spr(SPR_MQ, t0);
4887 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
4888 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
4889 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
4890 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_CA));
4891 gen_set_label(l1);
4892 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
4893 tcg_temp_free(t0);
4894 tcg_temp_free(t1);
4895 if (unlikely(Rc(ctx->opcode) != 0))
4896 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4897 }
4898
4899 /* sraq - sraq. */
4900 GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR)
4901 {
4902 int l1 = gen_new_label();
4903 int l2 = gen_new_label();
4904 TCGv t0 = tcg_temp_new();
4905 TCGv t1 = tcg_temp_local_new();
4906 TCGv t2 = tcg_temp_local_new();
4907 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
4908 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
4909 tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2);
4910 tcg_gen_subfi_tl(t2, 32, t2);
4911 tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2);
4912 tcg_gen_or_tl(t0, t0, t2);
4913 gen_store_spr(SPR_MQ, t0);
4914 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
4915 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1);
4916 tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]);
4917 tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31);
4918 gen_set_label(l1);
4919 tcg_temp_free(t0);
4920 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1);
4921 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
4922 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
4923 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2);
4924 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_CA));
4925 gen_set_label(l2);
4926 tcg_temp_free(t1);
4927 tcg_temp_free(t2);
4928 if (unlikely(Rc(ctx->opcode) != 0))
4929 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4930 }
4931
4932 /* sre - sre. */
4933 GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR)
4934 {
4935 TCGv t0 = tcg_temp_new();
4936 TCGv t1 = tcg_temp_new();
4937 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4938 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4939 tcg_gen_subfi_tl(t1, 32, t1);
4940 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4941 tcg_gen_or_tl(t1, t0, t1);
4942 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4943 gen_store_spr(SPR_MQ, t1);
4944 tcg_temp_free(t0);
4945 tcg_temp_free(t1);
4946 if (unlikely(Rc(ctx->opcode) != 0))
4947 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4948 }
4949
4950 /* srea - srea. */
4951 GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR)
4952 {
4953 TCGv t0 = tcg_temp_new();
4954 TCGv t1 = tcg_temp_new();
4955 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4956 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4957 gen_store_spr(SPR_MQ, t0);
4958 tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1);
4959 tcg_temp_free(t0);
4960 tcg_temp_free(t1);
4961 if (unlikely(Rc(ctx->opcode) != 0))
4962 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4963 }
4964
4965 /* sreq */
4966 GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR)
4967 {
4968 TCGv t0 = tcg_temp_new();
4969 TCGv t1 = tcg_temp_new();
4970 TCGv t2 = tcg_temp_new();
4971 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4972 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
4973 tcg_gen_shr_tl(t1, t1, t0);
4974 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4975 gen_load_spr(t2, SPR_MQ);
4976 gen_store_spr(SPR_MQ, t0);
4977 tcg_gen_and_tl(t0, t0, t1);
4978 tcg_gen_andc_tl(t2, t2, t1);
4979 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
4980 tcg_temp_free(t0);
4981 tcg_temp_free(t1);
4982 tcg_temp_free(t2);
4983 if (unlikely(Rc(ctx->opcode) != 0))
4984 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4985 }
4986
4987 /* sriq */
4988 GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR)
4989 {
4990 int sh = SH(ctx->opcode);
4991 TCGv t0 = tcg_temp_new();
4992 TCGv t1 = tcg_temp_new();
4993 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4994 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
4995 tcg_gen_or_tl(t1, t0, t1);
4996 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4997 gen_store_spr(SPR_MQ, t1);
4998 tcg_temp_free(t0);
4999 tcg_temp_free(t1);
5000 if (unlikely(Rc(ctx->opcode) != 0))
5001 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5002 }
5003
5004 /* srliq */
5005 GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR)
5006 {
5007 int sh = SH(ctx->opcode);
5008 TCGv t0 = tcg_temp_new();
5009 TCGv t1 = tcg_temp_new();
5010 tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5011 gen_load_spr(t1, SPR_MQ);
5012 gen_store_spr(SPR_MQ, t0);
5013 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh));
5014 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh));
5015 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5016 tcg_temp_free(t0);
5017 tcg_temp_free(t1);
5018 if (unlikely(Rc(ctx->opcode) != 0))
5019 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5020 }
5021
5022 /* srlq */
5023 GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR)
5024 {
5025 int l1 = gen_new_label();
5026 int l2 = gen_new_label();
5027 TCGv t0 = tcg_temp_local_new();
5028 TCGv t1 = tcg_temp_local_new();
5029 TCGv t2 = tcg_temp_local_new();
5030 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5031 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5032 tcg_gen_shr_tl(t2, t1, t2);
5033 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5034 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5035 gen_load_spr(t0, SPR_MQ);
5036 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5037 tcg_gen_br(l2);
5038 gen_set_label(l1);
5039 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5040 tcg_gen_and_tl(t0, t0, t2);
5041 gen_load_spr(t1, SPR_MQ);
5042 tcg_gen_andc_tl(t1, t1, t2);
5043 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5044 gen_set_label(l2);
5045 tcg_temp_free(t0);
5046 tcg_temp_free(t1);
5047 tcg_temp_free(t2);
5048 if (unlikely(Rc(ctx->opcode) != 0))
5049 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5050 }
5051
5052 /* srq */
5053 GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR)
5054 {
5055 int l1 = gen_new_label();
5056 TCGv t0 = tcg_temp_new();
5057 TCGv t1 = tcg_temp_new();
5058 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5059 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5060 tcg_gen_subfi_tl(t1, 32, t1);
5061 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5062 tcg_gen_or_tl(t1, t0, t1);
5063 gen_store_spr(SPR_MQ, t1);
5064 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5065 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5066 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5067 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5068 gen_set_label(l1);
5069 tcg_temp_free(t0);
5070 tcg_temp_free(t1);
5071 if (unlikely(Rc(ctx->opcode) != 0))
5072 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5073 }
5074
5075 /* PowerPC 602 specific instructions */
5076 /* dsa */
5077 GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC)
5078 {
5079 /* XXX: TODO */
5080 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5081 }
5082
5083 /* esa */
5084 GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC)
5085 {
5086 /* XXX: TODO */
5087 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5088 }
5089
5090 /* mfrom */
5091 GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC)
5092 {
5093 #if defined(CONFIG_USER_ONLY)
5094 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5095 #else
5096 if (unlikely(!ctx->mem_idx)) {
5097 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5098 return;
5099 }
5100 gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5101 #endif
5102 }
5103
5104 /* 602 - 603 - G2 TLB management */
5105 /* tlbld */
5106 GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB)
5107 {
5108 #if defined(CONFIG_USER_ONLY)
5109 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5110 #else
5111 if (unlikely(!ctx->mem_idx)) {
5112 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5113 return;
5114 }
5115 gen_helper_6xx_tlbd(cpu_gpr[rB(ctx->opcode)]);
5116 #endif
5117 }
5118
5119 /* tlbli */
5120 GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB)
5121 {
5122 #if defined(CONFIG_USER_ONLY)
5123 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5124 #else
5125 if (unlikely(!ctx->mem_idx)) {
5126 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5127 return;
5128 }
5129 gen_helper_6xx_tlbi(cpu_gpr[rB(ctx->opcode)]);
5130 #endif
5131 }
5132
5133 /* 74xx TLB management */
5134 /* tlbld */
5135 GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB)
5136 {
5137 #if defined(CONFIG_USER_ONLY)
5138 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5139 #else
5140 if (unlikely(!ctx->mem_idx)) {
5141 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5142 return;
5143 }
5144 gen_helper_74xx_tlbd(cpu_gpr[rB(ctx->opcode)]);
5145 #endif
5146 }
5147
5148 /* tlbli */
5149 GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB)
5150 {
5151 #if defined(CONFIG_USER_ONLY)
5152 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5153 #else
5154 if (unlikely(!ctx->mem_idx)) {
5155 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5156 return;
5157 }
5158 gen_helper_74xx_tlbi(cpu_gpr[rB(ctx->opcode)]);
5159 #endif
5160 }
5161
5162 /* POWER instructions not in PowerPC 601 */
5163 /* clf */
5164 GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER)
5165 {
5166 /* Cache line flush: implemented as no-op */
5167 }
5168
5169 /* cli */
5170 GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER)
5171 {
5172 /* Cache line invalidate: privileged and treated as no-op */
5173 #if defined(CONFIG_USER_ONLY)
5174 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5175 #else
5176 if (unlikely(!ctx->mem_idx)) {
5177 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5178 return;
5179 }
5180 #endif
5181 }
5182
5183 /* dclst */
5184 GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER)
5185 {
5186 /* Data cache line store: treated as no-op */
5187 }
5188
5189 GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER)
5190 {
5191 #if defined(CONFIG_USER_ONLY)
5192 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5193 #else
5194 int ra = rA(ctx->opcode);
5195 int rd = rD(ctx->opcode);
5196 TCGv t0;
5197 if (unlikely(!ctx->mem_idx)) {
5198 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5199 return;
5200 }
5201 t0 = tcg_temp_new();
5202 gen_addr_reg_index(ctx, t0);
5203 tcg_gen_shri_tl(t0, t0, 28);
5204 tcg_gen_andi_tl(t0, t0, 0xF);
5205 gen_helper_load_sr(cpu_gpr[rd], t0);
5206 tcg_temp_free(t0);
5207 if (ra != 0 && ra != rd)
5208 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]);
5209 #endif
5210 }
5211
5212 GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER)
5213 {
5214 #if defined(CONFIG_USER_ONLY)
5215 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5216 #else
5217 TCGv t0;
5218 if (unlikely(!ctx->mem_idx)) {
5219 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5220 return;
5221 }
5222 t0 = tcg_temp_new();
5223 gen_addr_reg_index(ctx, t0);
5224 gen_helper_rac(cpu_gpr[rD(ctx->opcode)], t0);
5225 tcg_temp_free(t0);
5226 #endif
5227 }
5228
5229 GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER)
5230 {
5231 #if defined(CONFIG_USER_ONLY)
5232 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5233 #else
5234 if (unlikely(!ctx->mem_idx)) {
5235 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5236 return;
5237 }
5238 gen_helper_rfsvc();
5239 gen_sync_exception(ctx);
5240 #endif
5241 }
5242
5243 /* svc is not implemented for now */
5244
5245 /* POWER2 specific instructions */
5246 /* Quad manipulation (load/store two floats at a time) */
5247
5248 /* lfq */
5249 GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
5250 {
5251 int rd = rD(ctx->opcode);
5252 TCGv t0;
5253 gen_set_access_type(ctx, ACCESS_FLOAT);
5254 t0 = tcg_temp_new();
5255 gen_addr_imm_index(ctx, t0, 0);
5256 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5257 gen_addr_add(ctx, t0, t0, 8);
5258 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5259 tcg_temp_free(t0);
5260 }
5261
5262 /* lfqu */
5263 GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
5264 {
5265 int ra = rA(ctx->opcode);
5266 int rd = rD(ctx->opcode);
5267 TCGv t0, t1;
5268 gen_set_access_type(ctx, ACCESS_FLOAT);
5269 t0 = tcg_temp_new();
5270 t1 = tcg_temp_new();
5271 gen_addr_imm_index(ctx, t0, 0);
5272 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5273 gen_addr_add(ctx, t1, t0, 8);
5274 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5275 if (ra != 0)
5276 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5277 tcg_temp_free(t0);
5278 tcg_temp_free(t1);
5279 }
5280
5281 /* lfqux */
5282 GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2)
5283 {
5284 int ra = rA(ctx->opcode);
5285 int rd = rD(ctx->opcode);
5286 gen_set_access_type(ctx, ACCESS_FLOAT);
5287 TCGv t0, t1;
5288 t0 = tcg_temp_new();
5289 gen_addr_reg_index(ctx, t0);
5290 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5291 t1 = tcg_temp_new();
5292 gen_addr_add(ctx, t1, t0, 8);
5293 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5294 tcg_temp_free(t1);
5295 if (ra != 0)
5296 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5297 tcg_temp_free(t0);
5298 }
5299
5300 /* lfqx */
5301 GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2)
5302 {
5303 int rd = rD(ctx->opcode);
5304 TCGv t0;
5305 gen_set_access_type(ctx, ACCESS_FLOAT);
5306 t0 = tcg_temp_new();
5307 gen_addr_reg_index(ctx, t0);
5308 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5309 gen_addr_add(ctx, t0, t0, 8);
5310 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5311 tcg_temp_free(t0);
5312 }
5313
5314 /* stfq */
5315 GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
5316 {
5317 int rd = rD(ctx->opcode);
5318 TCGv t0;
5319 gen_set_access_type(ctx, ACCESS_FLOAT);
5320 t0 = tcg_temp_new();
5321 gen_addr_imm_index(ctx, t0, 0);
5322 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5323 gen_addr_add(ctx, t0, t0, 8);
5324 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5325 tcg_temp_free(t0);
5326 }
5327
5328 /* stfqu */
5329 GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
5330 {
5331 int ra = rA(ctx->opcode);
5332 int rd = rD(ctx->opcode);
5333 TCGv t0, t1;
5334 gen_set_access_type(ctx, ACCESS_FLOAT);
5335 t0 = tcg_temp_new();
5336 gen_addr_imm_index(ctx, t0, 0);
5337 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5338 t1 = tcg_temp_new();
5339 gen_addr_add(ctx, t1, t0, 8);
5340 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5341 tcg_temp_free(t1);
5342 if (ra != 0)
5343 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5344 tcg_temp_free(t0);
5345 }
5346
5347 /* stfqux */
5348 GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2)
5349 {
5350 int ra = rA(ctx->opcode);
5351 int rd = rD(ctx->opcode);
5352 TCGv t0, t1;
5353 gen_set_access_type(ctx, ACCESS_FLOAT);
5354 t0 = tcg_temp_new();
5355 gen_addr_reg_index(ctx, t0);
5356 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5357 t1 = tcg_temp_new();
5358 gen_addr_add(ctx, t1, t0, 8);
5359 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5360 tcg_temp_free(t1);
5361 if (ra != 0)
5362 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5363 tcg_temp_free(t0);
5364 }
5365
5366 /* stfqx */
5367 GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2)
5368 {
5369 int rd = rD(ctx->opcode);
5370 TCGv t0;
5371 gen_set_access_type(ctx, ACCESS_FLOAT);
5372 t0 = tcg_temp_new();
5373 gen_addr_reg_index(ctx, t0);
5374 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5375 gen_addr_add(ctx, t0, t0, 8);
5376 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5377 tcg_temp_free(t0);
5378 }
5379
5380 /* BookE specific instructions */
5381 /* XXX: not implemented on 440 ? */
5382 GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI)
5383 {
5384 /* XXX: TODO */
5385 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5386 }
5387
5388 /* XXX: not implemented on 440 ? */
5389 GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA)
5390 {
5391 #if defined(CONFIG_USER_ONLY)
5392 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5393 #else
5394 TCGv t0;
5395 if (unlikely(!ctx->mem_idx)) {
5396 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5397 return;
5398 }
5399 t0 = tcg_temp_new();
5400 gen_addr_reg_index(ctx, t0);
5401 gen_helper_tlbie(cpu_gpr[rB(ctx->opcode)]);
5402 tcg_temp_free(t0);
5403 #endif
5404 }
5405
5406 /* All 405 MAC instructions are translated here */
5407 static always_inline void gen_405_mulladd_insn (DisasContext *ctx,
5408 int opc2, int opc3,
5409 int ra, int rb, int rt, int Rc)
5410 {
5411 TCGv t0, t1;
5412
5413 t0 = tcg_temp_local_new();
5414 t1 = tcg_temp_local_new();
5415
5416 switch (opc3 & 0x0D) {
5417 case 0x05:
5418 /* macchw - macchw. - macchwo - macchwo. */
5419 /* macchws - macchws. - macchwso - macchwso. */
5420 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
5421 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
5422 /* mulchw - mulchw. */
5423 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5424 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5425 tcg_gen_ext16s_tl(t1, t1);
5426 break;
5427 case 0x04:
5428 /* macchwu - macchwu. - macchwuo - macchwuo. */
5429 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
5430 /* mulchwu - mulchwu. */
5431 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5432 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5433 tcg_gen_ext16u_tl(t1, t1);
5434 break;
5435 case 0x01:
5436 /* machhw - machhw. - machhwo - machhwo. */
5437 /* machhws - machhws. - machhwso - machhwso. */
5438 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
5439 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
5440 /* mulhhw - mulhhw. */
5441 tcg_gen_sari_tl(t0, cpu_gpr[ra], 16);
5442 tcg_gen_ext16s_tl(t0, t0);
5443 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5444 tcg_gen_ext16s_tl(t1, t1);
5445 break;
5446 case 0x00:
5447 /* machhwu - machhwu. - machhwuo - machhwuo. */
5448 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
5449 /* mulhhwu - mulhhwu. */
5450 tcg_gen_shri_tl(t0, cpu_gpr[ra], 16);
5451 tcg_gen_ext16u_tl(t0, t0);
5452 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5453 tcg_gen_ext16u_tl(t1, t1);
5454 break;
5455 case 0x0D:
5456 /* maclhw - maclhw. - maclhwo - maclhwo. */
5457 /* maclhws - maclhws. - maclhwso - maclhwso. */
5458 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
5459 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
5460 /* mullhw - mullhw. */
5461 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5462 tcg_gen_ext16s_tl(t1, cpu_gpr[rb]);
5463 break;
5464 case 0x0C:
5465 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
5466 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
5467 /* mullhwu - mullhwu. */
5468 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5469 tcg_gen_ext16u_tl(t1, cpu_gpr[rb]);
5470 break;
5471 }
5472 if (opc2 & 0x04) {
5473 /* (n)multiply-and-accumulate (0x0C / 0x0E) */
5474 tcg_gen_mul_tl(t1, t0, t1);
5475 if (opc2 & 0x02) {
5476 /* nmultiply-and-accumulate (0x0E) */
5477 tcg_gen_sub_tl(t0, cpu_gpr[rt], t1);
5478 } else {
5479 /* multiply-and-accumulate (0x0C) */
5480 tcg_gen_add_tl(t0, cpu_gpr[rt], t1);
5481 }
5482
5483 if (opc3 & 0x12) {
5484 /* Check overflow and/or saturate */
5485 int l1 = gen_new_label();
5486
5487 if (opc3 & 0x10) {
5488 /* Start with XER OV disabled, the most likely case */
5489 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
5490 }
5491 if (opc3 & 0x01) {
5492 /* Signed */
5493 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1);
5494 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
5495 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0);
5496 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1);
5497 if (opc3 & 0x02) {
5498 /* Saturate */
5499 tcg_gen_sari_tl(t0, cpu_gpr[rt], 31);
5500 tcg_gen_xori_tl(t0, t0, 0x7fffffff);
5501 }
5502 } else {
5503 /* Unsigned */
5504 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
5505 if (opc3 & 0x02) {
5506 /* Saturate */
5507 tcg_gen_movi_tl(t0, UINT32_MAX);
5508 }
5509 }
5510 if (opc3 & 0x10) {
5511 /* Check overflow */
5512 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
5513 }
5514 gen_set_label(l1);
5515 tcg_gen_mov_tl(cpu_gpr[rt], t0);
5516 }
5517 } else {
5518 tcg_gen_mul_tl(cpu_gpr[rt], t0, t1);
5519 }
5520 tcg_temp_free(t0);
5521 tcg_temp_free(t1);
5522 if (unlikely(Rc) != 0) {
5523 /* Update Rc0 */
5524 gen_set_Rc0(ctx, cpu_gpr[rt]);
5525 }
5526 }
5527
5528 #define GEN_MAC_HANDLER(name, opc2, opc3) \
5529 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) \
5530 { \
5531 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
5532 rD(ctx->opcode), Rc(ctx->opcode)); \
5533 }
5534
5535 /* macchw - macchw. */
5536 GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
5537 /* macchwo - macchwo. */
5538 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
5539 /* macchws - macchws. */
5540 GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
5541 /* macchwso - macchwso. */
5542 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
5543 /* macchwsu - macchwsu. */
5544 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
5545 /* macchwsuo - macchwsuo. */
5546 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
5547 /* macchwu - macchwu. */
5548 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
5549 /* macchwuo - macchwuo. */
5550 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
5551 /* machhw - machhw. */
5552 GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
5553 /* machhwo - machhwo. */
5554 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
5555 /* machhws - machhws. */
5556 GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
5557 /* machhwso - machhwso. */
5558 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
5559 /* machhwsu - machhwsu. */
5560 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
5561 /* machhwsuo - machhwsuo. */
5562 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
5563 /* machhwu - machhwu. */
5564 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
5565 /* machhwuo - machhwuo. */
5566 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
5567 /* maclhw - maclhw. */
5568 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
5569 /* maclhwo - maclhwo. */
5570 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
5571 /* maclhws - maclhws. */
5572 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
5573 /* maclhwso - maclhwso. */
5574 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
5575 /* maclhwu - maclhwu. */
5576 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
5577 /* maclhwuo - maclhwuo. */
5578 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
5579 /* maclhwsu - maclhwsu. */
5580 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
5581 /* maclhwsuo - maclhwsuo. */
5582 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
5583 /* nmacchw - nmacchw. */
5584 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
5585 /* nmacchwo - nmacchwo. */
5586 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
5587 /* nmacchws - nmacchws. */
5588 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
5589 /* nmacchwso - nmacchwso. */
5590 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
5591 /* nmachhw - nmachhw. */
5592 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
5593 /* nmachhwo - nmachhwo. */
5594 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
5595 /* nmachhws - nmachhws. */
5596 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
5597 /* nmachhwso - nmachhwso. */
5598 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
5599 /* nmaclhw - nmaclhw. */
5600 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
5601 /* nmaclhwo - nmaclhwo. */
5602 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
5603 /* nmaclhws - nmaclhws. */
5604 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
5605 /* nmaclhwso - nmaclhwso. */
5606 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
5607
5608 /* mulchw - mulchw. */
5609 GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
5610 /* mulchwu - mulchwu. */
5611 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
5612 /* mulhhw - mulhhw. */
5613 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
5614 /* mulhhwu - mulhhwu. */
5615 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
5616 /* mullhw - mullhw. */
5617 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
5618 /* mullhwu - mullhwu. */
5619 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
5620
5621 /* mfdcr */
5622 GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR)
5623 {
5624 #if defined(CONFIG_USER_ONLY)
5625 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5626 #else
5627 TCGv dcrn;
5628 if (unlikely(!ctx->mem_idx)) {
5629 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5630 return;
5631 }
5632 /* NIP cannot be restored if the memory exception comes from an helper */
5633 gen_update_nip(ctx, ctx->nip - 4);
5634 dcrn = tcg_const_tl(SPR(ctx->opcode));
5635 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], dcrn);
5636 tcg_temp_free(dcrn);
5637 #endif
5638 }
5639
5640 /* mtdcr */
5641 GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR)
5642 {
5643 #if defined(CONFIG_USER_ONLY)
5644 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5645 #else
5646 TCGv dcrn;
5647 if (unlikely(!ctx->mem_idx)) {
5648 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5649 return;
5650 }
5651 /* NIP cannot be restored if the memory exception comes from an helper */
5652 gen_update_nip(ctx, ctx->nip - 4);
5653 dcrn = tcg_const_tl(SPR(ctx->opcode));
5654 gen_helper_store_dcr(dcrn, cpu_gpr[rS(ctx->opcode)]);
5655 tcg_temp_free(dcrn);
5656 #endif
5657 }
5658
5659 /* mfdcrx */
5660 /* XXX: not implemented on 440 ? */
5661 GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX)
5662 {
5663 #if defined(CONFIG_USER_ONLY)
5664 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5665 #else
5666 if (unlikely(!ctx->mem_idx)) {
5667 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5668 return;
5669 }
5670 /* NIP cannot be restored if the memory exception comes from an helper */
5671 gen_update_nip(ctx, ctx->nip - 4);
5672 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5673 /* Note: Rc update flag set leads to undefined state of Rc0 */
5674 #endif
5675 }
5676
5677 /* mtdcrx */
5678 /* XXX: not implemented on 440 ? */
5679 GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX)
5680 {
5681 #if defined(CONFIG_USER_ONLY)
5682 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5683 #else
5684 if (unlikely(!ctx->mem_idx)) {
5685 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5686 return;
5687 }
5688 /* NIP cannot be restored if the memory exception comes from an helper */
5689 gen_update_nip(ctx, ctx->nip - 4);
5690 gen_helper_store_dcr(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
5691 /* Note: Rc update flag set leads to undefined state of Rc0 */
5692 #endif
5693 }
5694
5695 /* mfdcrux (PPC 460) : user-mode access to DCR */
5696 GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX)
5697 {
5698 /* NIP cannot be restored if the memory exception comes from an helper */
5699 gen_update_nip(ctx, ctx->nip - 4);
5700 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5701 /* Note: Rc update flag set leads to undefined state of Rc0 */
5702 }
5703
5704 /* mtdcrux (PPC 460) : user-mode access to DCR */
5705 GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX)
5706 {
5707 /* NIP cannot be restored if the memory exception comes from an helper */
5708 gen_update_nip(ctx, ctx->nip - 4);
5709 gen_helper_store_dcr(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
5710 /* Note: Rc update flag set leads to undefined state of Rc0 */
5711 }
5712
5713 /* dccci */
5714 GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON)
5715 {
5716 #if defined(CONFIG_USER_ONLY)
5717 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5718 #else
5719 if (unlikely(!ctx->mem_idx)) {
5720 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5721 return;
5722 }
5723 /* interpreted as no-op */
5724 #endif
5725 }
5726
5727 /* dcread */
5728 GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON)
5729 {
5730 #if defined(CONFIG_USER_ONLY)
5731 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5732 #else
5733 TCGv EA, val;
5734 if (unlikely(!ctx->mem_idx)) {
5735 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5736 return;
5737 }
5738 gen_set_access_type(ctx, ACCESS_CACHE);
5739 EA = tcg_temp_new();
5740 gen_addr_reg_index(ctx, EA);
5741 val = tcg_temp_new();
5742 gen_qemu_ld32u(ctx, val, EA);
5743 tcg_temp_free(val);
5744 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA);
5745 tcg_temp_free(EA);
5746 #endif
5747 }
5748
5749 /* icbt */
5750 GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT)
5751 {
5752 /* interpreted as no-op */
5753 /* XXX: specification say this is treated as a load by the MMU
5754 * but does not generate any exception
5755 */
5756 }
5757
5758 /* iccci */
5759 GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON)
5760 {
5761 #if defined(CONFIG_USER_ONLY)
5762 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5763 #else
5764 if (unlikely(!ctx->mem_idx)) {
5765 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5766 return;
5767 }
5768 /* interpreted as no-op */
5769 #endif
5770 }
5771
5772 /* icread */
5773 GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON)
5774 {
5775 #if defined(CONFIG_USER_ONLY)
5776 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5777 #else
5778 if (unlikely(!ctx->mem_idx)) {
5779 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5780 return;
5781 }
5782 /* interpreted as no-op */
5783 #endif
5784 }
5785
5786 /* rfci (mem_idx only) */
5787 GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP)
5788 {
5789 #if defined(CONFIG_USER_ONLY)
5790 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5791 #else
5792 if (unlikely(!ctx->mem_idx)) {
5793 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5794 return;
5795 }
5796 /* Restore CPU state */
5797 gen_helper_40x_rfci();
5798 gen_sync_exception(ctx);
5799 #endif
5800 }
5801
5802 GEN_HANDLER(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE)
5803 {
5804 #if defined(CONFIG_USER_ONLY)
5805 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5806 #else
5807 if (unlikely(!ctx->mem_idx)) {
5808 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5809 return;
5810 }
5811 /* Restore CPU state */
5812 gen_helper_rfci();
5813 gen_sync_exception(ctx);
5814 #endif
5815 }
5816
5817 /* BookE specific */
5818 /* XXX: not implemented on 440 ? */
5819 GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI)
5820 {
5821 #if defined(CONFIG_USER_ONLY)
5822 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5823 #else
5824 if (unlikely(!ctx->mem_idx)) {
5825 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5826 return;
5827 }
5828 /* Restore CPU state */
5829 gen_helper_rfdi();
5830 gen_sync_exception(ctx);
5831 #endif
5832 }
5833
5834 /* XXX: not implemented on 440 ? */
5835 GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI)
5836 {
5837 #if defined(CONFIG_USER_ONLY)
5838 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5839 #else
5840 if (unlikely(!ctx->mem_idx)) {
5841 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5842 return;
5843 }
5844 /* Restore CPU state */
5845 gen_helper_rfmci();
5846 gen_sync_exception(ctx);
5847 #endif
5848 }
5849
5850 /* TLB management - PowerPC 405 implementation */
5851 /* tlbre */
5852 GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB)
5853 {
5854 #if defined(CONFIG_USER_ONLY)
5855 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5856 #else
5857 if (unlikely(!ctx->mem_idx)) {
5858 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5859 return;
5860 }
5861 switch (rB(ctx->opcode)) {
5862 case 0:
5863 gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5864 break;
5865 case 1:
5866 gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5867 break;
5868 default:
5869 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5870 break;
5871 }
5872 #endif
5873 }
5874
5875 /* tlbsx - tlbsx. */
5876 GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB)
5877 {
5878 #if defined(CONFIG_USER_ONLY)
5879 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5880 #else
5881 TCGv t0;
5882 if (unlikely(!ctx->mem_idx)) {
5883 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5884 return;
5885 }
5886 t0 = tcg_temp_new();
5887 gen_addr_reg_index(ctx, t0);
5888 gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], t0);
5889 tcg_temp_free(t0);
5890 if (Rc(ctx->opcode)) {
5891 int l1 = gen_new_label();
5892 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
5893 tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO);
5894 tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1);
5895 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
5896 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
5897 gen_set_label(l1);
5898 }
5899 #endif
5900 }
5901
5902 /* tlbwe */
5903 GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB)
5904 {
5905 #if defined(CONFIG_USER_ONLY)
5906 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5907 #else
5908 if (unlikely(!ctx->mem_idx)) {
5909 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5910 return;
5911 }
5912 switch (rB(ctx->opcode)) {
5913 case 0:
5914 gen_helper_4xx_tlbwe_hi(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
5915 break;
5916 case 1:
5917 gen_helper_4xx_tlbwe_lo(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
5918 break;
5919 default:
5920 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5921 break;
5922 }
5923 #endif
5924 }
5925
5926 /* TLB management - PowerPC 440 implementation */
5927 /* tlbre */
5928 GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE)
5929 {
5930 #if defined(CONFIG_USER_ONLY)
5931 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5932 #else
5933 if (unlikely(!ctx->mem_idx)) {
5934 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5935 return;
5936 }
5937 switch (rB(ctx->opcode)) {
5938 case 0:
5939 case 1:
5940 case 2:
5941 {
5942 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
5943 gen_helper_440_tlbwe(t0, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5944 tcg_temp_free_i32(t0);
5945 }
5946 break;
5947 default:
5948 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5949 break;
5950 }
5951 #endif
5952 }
5953
5954 /* tlbsx - tlbsx. */
5955 GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE)
5956 {
5957 #if defined(CONFIG_USER_ONLY)
5958 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5959 #else
5960 TCGv t0;
5961 if (unlikely(!ctx->mem_idx)) {
5962 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5963 return;
5964 }
5965 t0 = tcg_temp_new();
5966 gen_addr_reg_index(ctx, t0);
5967 gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], t0);
5968 tcg_temp_free(t0);
5969 if (Rc(ctx->opcode)) {
5970 int l1 = gen_new_label();
5971 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
5972 tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO);
5973 tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1);
5974 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
5975 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
5976 gen_set_label(l1);
5977 }
5978 #endif
5979 }
5980
5981 /* tlbwe */
5982 GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE)
5983 {
5984 #if defined(CONFIG_USER_ONLY)
5985 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5986 #else
5987 if (unlikely(!ctx->mem_idx)) {
5988 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5989 return;
5990 }
5991 switch (rB(ctx->opcode)) {
5992 case 0:
5993 case 1:
5994 case 2:
5995 {
5996 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
5997 gen_helper_440_tlbwe(t0, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
5998 tcg_temp_free_i32(t0);
5999 }
6000 break;
6001 default:
6002 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6003 break;
6004 }
6005 #endif
6006 }
6007
6008 /* wrtee */
6009 GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE)
6010 {
6011 #if defined(CONFIG_USER_ONLY)
6012 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6013 #else
6014 TCGv t0;
6015 if (unlikely(!ctx->mem_idx)) {
6016 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6017 return;
6018 }
6019 t0 = tcg_temp_new();
6020 tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE));
6021 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6022 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
6023 tcg_temp_free(t0);
6024 /* Stop translation to have a chance to raise an exception
6025 * if we just set msr_ee to 1
6026 */
6027 gen_stop_exception(ctx);
6028 #endif
6029 }
6030
6031 /* wrteei */
6032 GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000EFC01, PPC_WRTEE)
6033 {
6034 #if defined(CONFIG_USER_ONLY)
6035 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6036 #else
6037 if (unlikely(!ctx->mem_idx)) {
6038 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6039 return;
6040 }
6041 if (ctx->opcode & 0x00010000) {
6042 tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE));
6043 /* Stop translation to have a chance to raise an exception */
6044 gen_stop_exception(ctx);
6045 } else {
6046 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6047 }
6048 #endif
6049 }
6050
6051 /* PowerPC 440 specific instructions */
6052 /* dlmzb */
6053 GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC)
6054 {
6055 TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode));
6056 gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
6057 cpu_gpr[rB(ctx->opcode)], t0);
6058 tcg_temp_free_i32(t0);
6059 }
6060
6061 /* mbar replaces eieio on 440 */
6062 GEN_HANDLER(mbar, 0x1F, 0x16, 0x1a, 0x001FF801, PPC_BOOKE)
6063 {
6064 /* interpreted as no-op */
6065 }
6066
6067 /* msync replaces sync on 440 */
6068 GEN_HANDLER(msync, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE)
6069 {
6070 /* interpreted as no-op */
6071 }
6072
6073 /* icbt */
6074 GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, PPC_BOOKE)
6075 {
6076 /* interpreted as no-op */
6077 /* XXX: specification say this is treated as a load by the MMU
6078 * but does not generate any exception
6079 */
6080 }
6081
6082 /*** Altivec vector extension ***/
6083 /* Altivec registers moves */
6084
6085 static always_inline TCGv_ptr gen_avr_ptr(int reg)
6086 {
6087 TCGv_ptr r = tcg_temp_new_ptr();
6088 tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, avr[reg]));
6089 return r;
6090 }
6091
6092 #define GEN_VR_LDX(name, opc2, opc3) \
6093 GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
6094 { \
6095 TCGv EA; \
6096 if (unlikely(!ctx->altivec_enabled)) { \
6097 gen_exception(ctx, POWERPC_EXCP_VPU); \
6098 return; \
6099 } \
6100 gen_set_access_type(ctx, ACCESS_INT); \
6101 EA = tcg_temp_new(); \
6102 gen_addr_reg_index(ctx, EA); \
6103 tcg_gen_andi_tl(EA, EA, ~0xf); \
6104 if (ctx->le_mode) { \
6105 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6106 tcg_gen_addi_tl(EA, EA, 8); \
6107 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6108 } else { \
6109 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6110 tcg_gen_addi_tl(EA, EA, 8); \
6111 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6112 } \
6113 tcg_temp_free(EA); \
6114 }
6115
6116 #define GEN_VR_STX(name, opc2, opc3) \
6117 GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
6118 { \
6119 TCGv EA; \
6120 if (unlikely(!ctx->altivec_enabled)) { \
6121 gen_exception(ctx, POWERPC_EXCP_VPU); \
6122 return; \
6123 } \
6124 gen_set_access_type(ctx, ACCESS_INT); \
6125 EA = tcg_temp_new(); \
6126 gen_addr_reg_index(ctx, EA); \
6127 tcg_gen_andi_tl(EA, EA, ~0xf); \
6128 if (ctx->le_mode) { \
6129 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6130 tcg_gen_addi_tl(EA, EA, 8); \
6131 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6132 } else { \
6133 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6134 tcg_gen_addi_tl(EA, EA, 8); \
6135 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6136 } \
6137 tcg_temp_free(EA); \
6138 }
6139
6140 #define GEN_VR_LVE(name, opc2, opc3) \
6141 GEN_HANDLER(lve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
6142 { \
6143 TCGv EA; \
6144 TCGv_ptr rs; \
6145 if (unlikely(!ctx->altivec_enabled)) { \
6146 gen_exception(ctx, POWERPC_EXCP_VPU); \
6147 return; \
6148 } \
6149 gen_set_access_type(ctx, ACCESS_INT); \
6150 EA = tcg_temp_new(); \
6151 gen_addr_reg_index(ctx, EA); \
6152 rs = gen_avr_ptr(rS(ctx->opcode)); \
6153 gen_helper_lve##name (rs, EA); \
6154 tcg_temp_free(EA); \
6155 tcg_temp_free_ptr(rs); \
6156 }
6157
6158 #define GEN_VR_STVE(name, opc2, opc3) \
6159 GEN_HANDLER(stve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
6160 { \
6161 TCGv EA; \
6162 TCGv_ptr rs; \
6163 if (unlikely(!ctx->altivec_enabled)) { \
6164 gen_exception(ctx, POWERPC_EXCP_VPU); \
6165 return; \
6166 } \
6167 gen_set_access_type(ctx, ACCESS_INT); \
6168 EA = tcg_temp_new(); \
6169 gen_addr_reg_index(ctx, EA); \
6170 rs = gen_avr_ptr(rS(ctx->opcode)); \
6171 gen_helper_stve##name (rs, EA); \
6172 tcg_temp_free(EA); \
6173 tcg_temp_free_ptr(rs); \
6174 }
6175
6176 GEN_VR_LDX(lvx, 0x07, 0x03);
6177 /* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
6178 GEN_VR_LDX(lvxl, 0x07, 0x0B);
6179
6180 GEN_VR_LVE(bx, 0x07, 0x00);
6181 GEN_VR_LVE(hx, 0x07, 0x01);
6182 GEN_VR_LVE(wx, 0x07, 0x02);
6183
6184 GEN_VR_STX(svx, 0x07, 0x07);
6185 /* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
6186 GEN_VR_STX(svxl, 0x07, 0x0F);
6187
6188 GEN_VR_STVE(bx, 0x07, 0x04);
6189 GEN_VR_STVE(hx, 0x07, 0x05);
6190 GEN_VR_STVE(wx, 0x07, 0x06);
6191
6192 GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC)
6193 {
6194 TCGv_ptr rd;
6195 TCGv EA;
6196 if (unlikely(!ctx->altivec_enabled)) {
6197 gen_exception(ctx, POWERPC_EXCP_VPU);
6198 return;
6199 }
6200 EA = tcg_temp_new();
6201 gen_addr_reg_index(ctx, EA);
6202 rd = gen_avr_ptr(rD(ctx->opcode));
6203 gen_helper_lvsl(rd, EA);
6204 tcg_temp_free(EA);
6205 tcg_temp_free_ptr(rd);
6206 }
6207
6208 GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC)
6209 {
6210 TCGv_ptr rd;
6211 TCGv EA;
6212 if (unlikely(!ctx->altivec_enabled)) {
6213 gen_exception(ctx, POWERPC_EXCP_VPU);
6214 return;
6215 }
6216 EA = tcg_temp_new();
6217 gen_addr_reg_index(ctx, EA);
6218 rd = gen_avr_ptr(rD(ctx->opcode));
6219 gen_helper_lvsr(rd, EA);
6220 tcg_temp_free(EA);
6221 tcg_temp_free_ptr(rd);
6222 }
6223
6224 GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC)
6225 {
6226 TCGv_i32 t;
6227 if (unlikely(!ctx->altivec_enabled)) {
6228 gen_exception(ctx, POWERPC_EXCP_VPU);
6229 return;
6230 }
6231 tcg_gen_movi_i64(cpu_avrh[rD(ctx->opcode)], 0);
6232 t = tcg_temp_new_i32();
6233 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUState, vscr));
6234 tcg_gen_extu_i32_i64(cpu_avrl[rD(ctx->opcode)], t);
6235 tcg_temp_free_i32(t);
6236 }
6237
6238 GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC)
6239 {
6240 TCGv_ptr p;
6241 if (unlikely(!ctx->altivec_enabled)) {
6242 gen_exception(ctx, POWERPC_EXCP_VPU);
6243 return;
6244 }
6245 p = gen_avr_ptr(rD(ctx->opcode));
6246 gen_helper_mtvscr(p);
6247 tcg_temp_free_ptr(p);
6248 }
6249
6250 /* Logical operations */
6251 #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
6252 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) \
6253 { \
6254 if (unlikely(!ctx->altivec_enabled)) { \
6255 gen_exception(ctx, POWERPC_EXCP_VPU); \
6256 return; \
6257 } \
6258 tcg_op(cpu_avrh[rD(ctx->opcode)], cpu_avrh[rA(ctx->opcode)], cpu_avrh[rB(ctx->opcode)]); \
6259 tcg_op(cpu_avrl[rD(ctx->opcode)], cpu_avrl[rA(ctx->opcode)], cpu_avrl[rB(ctx->opcode)]); \
6260 }
6261
6262 GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16);
6263 GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17);
6264 GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18);
6265 GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19);
6266 GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20);
6267
6268 #define GEN_VXFORM(name, opc2, opc3) \
6269 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) \
6270 { \
6271 TCGv_ptr ra, rb, rd; \
6272 if (unlikely(!ctx->altivec_enabled)) { \
6273 gen_exception(ctx, POWERPC_EXCP_VPU); \
6274 return; \
6275 } \
6276 ra = gen_avr_ptr(rA(ctx->opcode)); \
6277 rb = gen_avr_ptr(rB(ctx->opcode)); \
6278 rd = gen_avr_ptr(rD(ctx->opcode)); \
6279 gen_helper_##name (rd, ra, rb); \
6280 tcg_temp_free_ptr(ra); \
6281 tcg_temp_free_ptr(rb); \
6282 tcg_temp_free_ptr(rd); \
6283 }
6284
6285 GEN_VXFORM(vaddubm, 0, 0);
6286 GEN_VXFORM(vadduhm, 0, 1);
6287 GEN_VXFORM(vadduwm, 0, 2);
6288 GEN_VXFORM(vsububm, 0, 16);
6289 GEN_VXFORM(vsubuhm, 0, 17);
6290 GEN_VXFORM(vsubuwm, 0, 18);
6291 GEN_VXFORM(vmaxub, 1, 0);
6292 GEN_VXFORM(vmaxuh, 1, 1);
6293 GEN_VXFORM(vmaxuw, 1, 2);
6294 GEN_VXFORM(vmaxsb, 1, 4);
6295 GEN_VXFORM(vmaxsh, 1, 5);
6296 GEN_VXFORM(vmaxsw, 1, 6);
6297 GEN_VXFORM(vminub, 1, 8);
6298 GEN_VXFORM(vminuh, 1, 9);
6299 GEN_VXFORM(vminuw, 1, 10);
6300 GEN_VXFORM(vminsb, 1, 12);
6301 GEN_VXFORM(vminsh, 1, 13);
6302 GEN_VXFORM(vminsw, 1, 14);
6303 GEN_VXFORM(vavgub, 1, 16);
6304 GEN_VXFORM(vavguh, 1, 17);
6305 GEN_VXFORM(vavguw, 1, 18);
6306 GEN_VXFORM(vavgsb, 1, 20);
6307 GEN_VXFORM(vavgsh, 1, 21);
6308 GEN_VXFORM(vavgsw, 1, 22);
6309 GEN_VXFORM(vmrghb, 6, 0);
6310 GEN_VXFORM(vmrghh, 6, 1);
6311 GEN_VXFORM(vmrghw, 6, 2);
6312 GEN_VXFORM(vmrglb, 6, 4);
6313 GEN_VXFORM(vmrglh, 6, 5);
6314 GEN_VXFORM(vmrglw, 6, 6);
6315 GEN_VXFORM(vmuloub, 4, 0);
6316 GEN_VXFORM(vmulouh, 4, 1);
6317 GEN_VXFORM(vmulosb, 4, 4);
6318 GEN_VXFORM(vmulosh, 4, 5);
6319 GEN_VXFORM(vmuleub, 4, 8);
6320 GEN_VXFORM(vmuleuh, 4, 9);
6321 GEN_VXFORM(vmulesb, 4, 12);
6322 GEN_VXFORM(vmulesh, 4, 13);
6323 GEN_VXFORM(vslb, 2, 4);
6324 GEN_VXFORM(vslh, 2, 5);
6325 GEN_VXFORM(vslw, 2, 6);
6326 GEN_VXFORM(vsrb, 2, 8);
6327 GEN_VXFORM(vsrh, 2, 9);
6328 GEN_VXFORM(vsrw, 2, 10);
6329 GEN_VXFORM(vsrab, 2, 12);
6330 GEN_VXFORM(vsrah, 2, 13);
6331 GEN_VXFORM(vsraw, 2, 14);
6332 GEN_VXFORM(vslo, 6, 16);
6333 GEN_VXFORM(vsro, 6, 17);
6334 GEN_VXFORM(vaddcuw, 0, 6);
6335 GEN_VXFORM(vsubcuw, 0, 22);
6336 GEN_VXFORM(vaddubs, 0, 8);
6337 GEN_VXFORM(vadduhs, 0, 9);
6338 GEN_VXFORM(vadduws, 0, 10);
6339 GEN_VXFORM(vaddsbs, 0, 12);
6340 GEN_VXFORM(vaddshs, 0, 13);
6341 GEN_VXFORM(vaddsws, 0, 14);
6342 GEN_VXFORM(vsububs, 0, 24);
6343 GEN_VXFORM(vsubuhs, 0, 25);
6344 GEN_VXFORM(vsubuws, 0, 26);
6345 GEN_VXFORM(vsubsbs, 0, 28);
6346 GEN_VXFORM(vsubshs, 0, 29);
6347 GEN_VXFORM(vsubsws, 0, 30);
6348 GEN_VXFORM(vrlb, 2, 0);
6349 GEN_VXFORM(vrlh, 2, 1);
6350 GEN_VXFORM(vrlw, 2, 2);
6351 GEN_VXFORM(vsl, 2, 7);
6352 GEN_VXFORM(vsr, 2, 11);
6353 GEN_VXFORM(vpkuhum, 7, 0);
6354 GEN_VXFORM(vpkuwum, 7, 1);
6355 GEN_VXFORM(vpkuhus, 7, 2);
6356 GEN_VXFORM(vpkuwus, 7, 3);
6357 GEN_VXFORM(vpkshus, 7, 4);
6358 GEN_VXFORM(vpkswus, 7, 5);
6359 GEN_VXFORM(vpkshss, 7, 6);
6360 GEN_VXFORM(vpkswss, 7, 7);
6361 GEN_VXFORM(vpkpx, 7, 12);
6362 GEN_VXFORM(vsum4ubs, 4, 24);
6363 GEN_VXFORM(vsum4sbs, 4, 28);
6364 GEN_VXFORM(vsum4shs, 4, 25);
6365 GEN_VXFORM(vsum2sws, 4, 26);
6366 GEN_VXFORM(vsumsws, 4, 30);
6367 GEN_VXFORM(vaddfp, 5, 0);
6368 GEN_VXFORM(vsubfp, 5, 1);
6369 GEN_VXFORM(vmaxfp, 5, 16);
6370 GEN_VXFORM(vminfp, 5, 17);
6371
6372 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
6373 GEN_HANDLER2(name, str, 0x4, opc2, opc3, 0x00000000, PPC_ALTIVEC) \
6374 { \
6375 TCGv_ptr ra, rb, rd; \
6376 if (unlikely(!ctx->altivec_enabled)) { \
6377 gen_exception(ctx, POWERPC_EXCP_VPU); \
6378 return; \
6379 } \
6380 ra = gen_avr_ptr(rA(ctx->opcode)); \
6381 rb = gen_avr_ptr(rB(ctx->opcode)); \
6382 rd = gen_avr_ptr(rD(ctx->opcode)); \
6383 gen_helper_##opname (rd, ra, rb); \
6384 tcg_temp_free_ptr(ra); \
6385 tcg_temp_free_ptr(rb); \
6386 tcg_temp_free_ptr(rd); \
6387 }
6388
6389 #define GEN_VXRFORM(name, opc2, opc3) \
6390 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
6391 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
6392
6393 GEN_VXRFORM(vcmpequb, 3, 0)
6394 GEN_VXRFORM(vcmpequh, 3, 1)
6395 GEN_VXRFORM(vcmpequw, 3, 2)
6396 GEN_VXRFORM(vcmpgtsb, 3, 12)
6397 GEN_VXRFORM(vcmpgtsh, 3, 13)
6398 GEN_VXRFORM(vcmpgtsw, 3, 14)
6399 GEN_VXRFORM(vcmpgtub, 3, 8)
6400 GEN_VXRFORM(vcmpgtuh, 3, 9)
6401 GEN_VXRFORM(vcmpgtuw, 3, 10)
6402 GEN_VXRFORM(vcmpeqfp, 3, 3)
6403 GEN_VXRFORM(vcmpgefp, 3, 7)
6404 GEN_VXRFORM(vcmpgtfp, 3, 11)
6405 GEN_VXRFORM(vcmpbfp, 3, 15)
6406
6407 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
6408 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) \
6409 { \
6410 TCGv_ptr rd; \
6411 TCGv_i32 simm; \
6412 if (unlikely(!ctx->altivec_enabled)) { \
6413 gen_exception(ctx, POWERPC_EXCP_VPU); \
6414 return; \
6415 } \
6416 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
6417 rd = gen_avr_ptr(rD(ctx->opcode)); \
6418 gen_helper_##name (rd, simm); \
6419 tcg_temp_free_i32(simm); \
6420 tcg_temp_free_ptr(rd); \
6421 }
6422
6423 GEN_VXFORM_SIMM(vspltisb, 6, 12);
6424 GEN_VXFORM_SIMM(vspltish, 6, 13);
6425 GEN_VXFORM_SIMM(vspltisw, 6, 14);
6426
6427 #define GEN_VXFORM_NOA(name, opc2, opc3) \
6428 GEN_HANDLER(name, 0x04, opc2, opc3, 0x001f0000, PPC_ALTIVEC) \
6429 { \
6430 TCGv_ptr rb, rd; \
6431 if (unlikely(!ctx->altivec_enabled)) { \
6432 gen_exception(ctx, POWERPC_EXCP_VPU); \
6433 return; \
6434 } \
6435 rb = gen_avr_ptr(rB(ctx->opcode)); \
6436 rd = gen_avr_ptr(rD(ctx->opcode)); \
6437 gen_helper_##name (rd, rb); \
6438 tcg_temp_free_ptr(rb); \
6439 tcg_temp_free_ptr(rd); \
6440 }
6441
6442 GEN_VXFORM_NOA(vupkhsb, 7, 8);
6443 GEN_VXFORM_NOA(vupkhsh, 7, 9);
6444 GEN_VXFORM_NOA(vupklsb, 7, 10);
6445 GEN_VXFORM_NOA(vupklsh, 7, 11);
6446 GEN_VXFORM_NOA(vupkhpx, 7, 13);
6447 GEN_VXFORM_NOA(vupklpx, 7, 15);
6448 GEN_VXFORM_NOA(vrefp, 5, 4);
6449 GEN_VXFORM_NOA(vrsqrtefp, 5, 5);
6450 GEN_VXFORM_NOA(vlogefp, 5, 7);
6451 GEN_VXFORM_NOA(vrfim, 5, 8);
6452 GEN_VXFORM_NOA(vrfin, 5, 9);
6453 GEN_VXFORM_NOA(vrfip, 5, 10);
6454 GEN_VXFORM_NOA(vrfiz, 5, 11);
6455
6456 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
6457 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) \
6458 { \
6459 TCGv_ptr rd; \
6460 TCGv_i32 simm; \
6461 if (unlikely(!ctx->altivec_enabled)) { \
6462 gen_exception(ctx, POWERPC_EXCP_VPU); \
6463 return; \
6464 } \
6465 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
6466 rd = gen_avr_ptr(rD(ctx->opcode)); \
6467 gen_helper_##name (rd, simm); \
6468 tcg_temp_free_i32(simm); \
6469 tcg_temp_free_ptr(rd); \
6470 }
6471
6472 #define GEN_VXFORM_UIMM(name, opc2, opc3) \
6473 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) \
6474 { \
6475 TCGv_ptr rb, rd; \
6476 TCGv_i32 uimm; \
6477 if (unlikely(!ctx->altivec_enabled)) { \
6478 gen_exception(ctx, POWERPC_EXCP_VPU); \
6479 return; \
6480 } \
6481 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
6482 rb = gen_avr_ptr(rB(ctx->opcode)); \
6483 rd = gen_avr_ptr(rD(ctx->opcode)); \
6484 gen_helper_##name (rd, rb, uimm); \
6485 tcg_temp_free_i32(uimm); \
6486 tcg_temp_free_ptr(rb); \
6487 tcg_temp_free_ptr(rd); \
6488 }
6489
6490 GEN_VXFORM_UIMM(vspltb, 6, 8);
6491 GEN_VXFORM_UIMM(vsplth, 6, 9);
6492 GEN_VXFORM_UIMM(vspltw, 6, 10);
6493 GEN_VXFORM_UIMM(vcfux, 5, 12);
6494 GEN_VXFORM_UIMM(vcfsx, 5, 13);
6495 GEN_VXFORM_UIMM(vctuxs, 5, 14);
6496 GEN_VXFORM_UIMM(vctsxs, 5, 15);
6497
6498 GEN_HANDLER(vsldoi, 0x04, 0x16, 0xFF, 0x00000400, PPC_ALTIVEC)
6499 {
6500 TCGv_ptr ra, rb, rd;
6501 TCGv_i32 sh;
6502 if (unlikely(!ctx->altivec_enabled)) {
6503 gen_exception(ctx, POWERPC_EXCP_VPU);
6504 return;
6505 }
6506 ra = gen_avr_ptr(rA(ctx->opcode));
6507 rb = gen_avr_ptr(rB(ctx->opcode));
6508 rd = gen_avr_ptr(rD(ctx->opcode));
6509 sh = tcg_const_i32(VSH(ctx->opcode));
6510 gen_helper_vsldoi (rd, ra, rb, sh);
6511 tcg_temp_free_ptr(ra);
6512 tcg_temp_free_ptr(rb);
6513 tcg_temp_free_ptr(rd);
6514 tcg_temp_free_i32(sh);
6515 }
6516
6517 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
6518 GEN_HANDLER(name0##_##name1, 0x04, opc2, 0xFF, 0x00000000, PPC_ALTIVEC) \
6519 { \
6520 TCGv_ptr ra, rb, rc, rd; \
6521 if (unlikely(!ctx->altivec_enabled)) { \
6522 gen_exception(ctx, POWERPC_EXCP_VPU); \
6523 return; \
6524 } \
6525 ra = gen_avr_ptr(rA(ctx->opcode)); \
6526 rb = gen_avr_ptr(rB(ctx->opcode)); \
6527 rc = gen_avr_ptr(rC(ctx->opcode)); \
6528 rd = gen_avr_ptr(rD(ctx->opcode)); \
6529 if (Rc(ctx->opcode)) { \
6530 gen_helper_##name1 (rd, ra, rb, rc); \
6531 } else { \
6532 gen_helper_##name0 (rd, ra, rb, rc); \
6533 } \
6534 tcg_temp_free_ptr(ra); \
6535 tcg_temp_free_ptr(rb); \
6536 tcg_temp_free_ptr(rc); \
6537 tcg_temp_free_ptr(rd); \
6538 }
6539
6540 GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16)
6541
6542 GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC)
6543 {
6544 TCGv_ptr ra, rb, rc, rd;
6545 if (unlikely(!ctx->altivec_enabled)) {
6546 gen_exception(ctx, POWERPC_EXCP_VPU);
6547 return;
6548 }
6549 ra = gen_avr_ptr(rA(ctx->opcode));
6550 rb = gen_avr_ptr(rB(ctx->opcode));
6551 rc = gen_avr_ptr(rC(ctx->opcode));
6552 rd = gen_avr_ptr(rD(ctx->opcode));
6553 gen_helper_vmladduhm(rd, ra, rb, rc);
6554 tcg_temp_free_ptr(ra);
6555 tcg_temp_free_ptr(rb);
6556 tcg_temp_free_ptr(rc);
6557 tcg_temp_free_ptr(rd);
6558 }
6559
6560 GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18)
6561 GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19)
6562 GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20)
6563 GEN_VAFORM_PAIRED(vsel, vperm, 21)
6564 GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23)
6565
6566 /*** SPE extension ***/
6567 /* Register moves */
6568
6569 static always_inline void gen_load_gpr64(TCGv_i64 t, int reg) {
6570 #if defined(TARGET_PPC64)
6571 tcg_gen_mov_i64(t, cpu_gpr[reg]);
6572 #else
6573 tcg_gen_concat_i32_i64(t, cpu_gpr[reg], cpu_gprh[reg]);
6574 #endif
6575 }
6576
6577 static always_inline void gen_store_gpr64(int reg, TCGv_i64 t) {
6578 #if defined(TARGET_PPC64)
6579 tcg_gen_mov_i64(cpu_gpr[reg], t);
6580 #else
6581 TCGv_i64 tmp = tcg_temp_new_i64();
6582 tcg_gen_trunc_i64_i32(cpu_gpr[reg], t);
6583 tcg_gen_shri_i64(tmp, t, 32);
6584 tcg_gen_trunc_i64_i32(cpu_gprh[reg], tmp);
6585 tcg_temp_free_i64(tmp);
6586 #endif
6587 }
6588
6589 #define GEN_SPE(name0, name1, opc2, opc3, inval, type) \
6590 GEN_HANDLER(name0##_##name1, 0x04, opc2, opc3, inval, type) \
6591 { \
6592 if (Rc(ctx->opcode)) \
6593 gen_##name1(ctx); \
6594 else \
6595 gen_##name0(ctx); \
6596 }
6597
6598 /* Handler for undefined SPE opcodes */
6599 static always_inline void gen_speundef (DisasContext *ctx)
6600 {
6601 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6602 }
6603
6604 /* SPE logic */
6605 #if defined(TARGET_PPC64)
6606 #define GEN_SPEOP_LOGIC2(name, tcg_op) \
6607 static always_inline void gen_##name (DisasContext *ctx) \
6608 { \
6609 if (unlikely(!ctx->spe_enabled)) { \
6610 gen_exception(ctx, POWERPC_EXCP_APU); \
6611 return; \
6612 } \
6613 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6614 cpu_gpr[rB(ctx->opcode)]); \
6615 }
6616 #else
6617 #define GEN_SPEOP_LOGIC2(name, tcg_op) \
6618 static always_inline void gen_##name (DisasContext *ctx) \
6619 { \
6620 if (unlikely(!ctx->spe_enabled)) { \
6621 gen_exception(ctx, POWERPC_EXCP_APU); \
6622 return; \
6623 } \
6624 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6625 cpu_gpr[rB(ctx->opcode)]); \
6626 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
6627 cpu_gprh[rB(ctx->opcode)]); \
6628 }
6629 #endif
6630
6631 GEN_SPEOP_LOGIC2(evand, tcg_gen_and_tl);
6632 GEN_SPEOP_LOGIC2(evandc, tcg_gen_andc_tl);
6633 GEN_SPEOP_LOGIC2(evxor, tcg_gen_xor_tl);
6634 GEN_SPEOP_LOGIC2(evor, tcg_gen_or_tl);
6635 GEN_SPEOP_LOGIC2(evnor, tcg_gen_nor_tl);
6636 GEN_SPEOP_LOGIC2(eveqv, tcg_gen_eqv_tl);
6637 GEN_SPEOP_LOGIC2(evorc, tcg_gen_orc_tl);
6638 GEN_SPEOP_LOGIC2(evnand, tcg_gen_nand_tl);
6639
6640 /* SPE logic immediate */
6641 #if defined(TARGET_PPC64)
6642 #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
6643 static always_inline void gen_##name (DisasContext *ctx) \
6644 { \
6645 if (unlikely(!ctx->spe_enabled)) { \
6646 gen_exception(ctx, POWERPC_EXCP_APU); \
6647 return; \
6648 } \
6649 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6650 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6651 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
6652 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6653 tcg_opi(t0, t0, rB(ctx->opcode)); \
6654 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
6655 tcg_gen_trunc_i64_i32(t1, t2); \
6656 tcg_temp_free_i64(t2); \
6657 tcg_opi(t1, t1, rB(ctx->opcode)); \
6658 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
6659 tcg_temp_free_i32(t0); \
6660 tcg_temp_free_i32(t1); \
6661 }
6662 #else
6663 #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
6664 static always_inline void gen_##name (DisasContext *ctx) \
6665 { \
6666 if (unlikely(!ctx->spe_enabled)) { \
6667 gen_exception(ctx, POWERPC_EXCP_APU); \
6668 return; \
6669 } \
6670 tcg_opi(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6671 rB(ctx->opcode)); \
6672 tcg_opi(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
6673 rB(ctx->opcode)); \
6674 }
6675 #endif
6676 GEN_SPEOP_TCG_LOGIC_IMM2(evslwi, tcg_gen_shli_i32);
6677 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwiu, tcg_gen_shri_i32);
6678 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwis, tcg_gen_sari_i32);
6679 GEN_SPEOP_TCG_LOGIC_IMM2(evrlwi, tcg_gen_rotli_i32);
6680
6681 /* SPE arithmetic */
6682 #if defined(TARGET_PPC64)
6683 #define GEN_SPEOP_ARITH1(name, tcg_op) \
6684 static always_inline void gen_##name (DisasContext *ctx) \
6685 { \
6686 if (unlikely(!ctx->spe_enabled)) { \
6687 gen_exception(ctx, POWERPC_EXCP_APU); \
6688 return; \
6689 } \
6690 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6691 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6692 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
6693 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6694 tcg_op(t0, t0); \
6695 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
6696 tcg_gen_trunc_i64_i32(t1, t2); \
6697 tcg_temp_free_i64(t2); \
6698 tcg_op(t1, t1); \
6699 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
6700 tcg_temp_free_i32(t0); \
6701 tcg_temp_free_i32(t1); \
6702 }
6703 #else
6704 #define GEN_SPEOP_ARITH1(name, tcg_op) \
6705 static always_inline void gen_##name (DisasContext *ctx) \
6706 { \
6707 if (unlikely(!ctx->spe_enabled)) { \
6708 gen_exception(ctx, POWERPC_EXCP_APU); \
6709 return; \
6710 } \
6711 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); \
6712 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); \
6713 }
6714 #endif
6715
6716 static always_inline void gen_op_evabs (TCGv_i32 ret, TCGv_i32 arg1)
6717 {
6718 int l1 = gen_new_label();
6719 int l2 = gen_new_label();
6720
6721 tcg_gen_brcondi_i32(TCG_COND_GE, arg1, 0, l1);
6722 tcg_gen_neg_i32(ret, arg1);
6723 tcg_gen_br(l2);
6724 gen_set_label(l1);
6725 tcg_gen_mov_i32(ret, arg1);
6726 gen_set_label(l2);
6727 }
6728 GEN_SPEOP_ARITH1(evabs, gen_op_evabs);
6729 GEN_SPEOP_ARITH1(evneg, tcg_gen_neg_i32);
6730 GEN_SPEOP_ARITH1(evextsb, tcg_gen_ext8s_i32);
6731 GEN_SPEOP_ARITH1(evextsh, tcg_gen_ext16s_i32);
6732 static always_inline void gen_op_evrndw (TCGv_i32 ret, TCGv_i32 arg1)
6733 {
6734 tcg_gen_addi_i32(ret, arg1, 0x8000);
6735 tcg_gen_ext16u_i32(ret, ret);
6736 }
6737 GEN_SPEOP_ARITH1(evrndw, gen_op_evrndw);
6738 GEN_SPEOP_ARITH1(evcntlsw, gen_helper_cntlsw32);
6739 GEN_SPEOP_ARITH1(evcntlzw, gen_helper_cntlzw32);
6740
6741 #if defined(TARGET_PPC64)
6742 #define GEN_SPEOP_ARITH2(name, tcg_op) \
6743 static always_inline void gen_##name (DisasContext *ctx) \
6744 { \
6745 if (unlikely(!ctx->spe_enabled)) { \
6746 gen_exception(ctx, POWERPC_EXCP_APU); \
6747 return; \
6748 } \
6749 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6750 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6751 TCGv_i32 t2 = tcg_temp_local_new_i32(); \
6752 TCGv_i64 t3 = tcg_temp_local_new_i64(); \
6753 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6754 tcg_gen_trunc_i64_i32(t2, cpu_gpr[rB(ctx->opcode)]); \
6755 tcg_op(t0, t0, t2); \
6756 tcg_gen_shri_i64(t3, cpu_gpr[rA(ctx->opcode)], 32); \
6757 tcg_gen_trunc_i64_i32(t1, t3); \
6758 tcg_gen_shri_i64(t3, cpu_gpr[rB(ctx->opcode)], 32); \
6759 tcg_gen_trunc_i64_i32(t2, t3); \
6760 tcg_temp_free_i64(t3); \
6761 tcg_op(t1, t1, t2); \
6762 tcg_temp_free_i32(t2); \
6763 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
6764 tcg_temp_free_i32(t0); \
6765 tcg_temp_free_i32(t1); \
6766 }
6767 #else
6768 #define GEN_SPEOP_ARITH2(name, tcg_op) \
6769 static always_inline void gen_##name (DisasContext *ctx) \
6770 { \
6771 if (unlikely(!ctx->spe_enabled)) { \
6772 gen_exception(ctx, POWERPC_EXCP_APU); \
6773 return; \
6774 } \
6775 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6776 cpu_gpr[rB(ctx->opcode)]); \
6777 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
6778 cpu_gprh[rB(ctx->opcode)]); \
6779 }
6780 #endif
6781
6782 static always_inline void gen_op_evsrwu (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
6783 {
6784 TCGv_i32 t0;
6785 int l1, l2;
6786
6787 l1 = gen_new_label();
6788 l2 = gen_new_label();
6789 t0 = tcg_temp_local_new_i32();
6790 /* No error here: 6 bits are used */
6791 tcg_gen_andi_i32(t0, arg2, 0x3F);
6792 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
6793 tcg_gen_shr_i32(ret, arg1, t0);
6794 tcg_gen_br(l2);
6795 gen_set_label(l1);
6796 tcg_gen_movi_i32(ret, 0);
6797 tcg_gen_br(l2);
6798 tcg_temp_free_i32(t0);
6799 }
6800 GEN_SPEOP_ARITH2(evsrwu, gen_op_evsrwu);
6801 static always_inline void gen_op_evsrws (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
6802 {
6803 TCGv_i32 t0;
6804 int l1, l2;
6805
6806 l1 = gen_new_label();
6807 l2 = gen_new_label();
6808 t0 = tcg_temp_local_new_i32();
6809 /* No error here: 6 bits are used */
6810 tcg_gen_andi_i32(t0, arg2, 0x3F);
6811 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
6812 tcg_gen_sar_i32(ret, arg1, t0);
6813 tcg_gen_br(l2);
6814 gen_set_label(l1);
6815 tcg_gen_movi_i32(ret, 0);
6816 tcg_gen_br(l2);
6817 tcg_temp_free_i32(t0);
6818 }
6819 GEN_SPEOP_ARITH2(evsrws, gen_op_evsrws);
6820 static always_inline void gen_op_evslw (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
6821 {
6822 TCGv_i32 t0;
6823 int l1, l2;
6824
6825 l1 = gen_new_label();
6826 l2 = gen_new_label();
6827 t0 = tcg_temp_local_new_i32();
6828 /* No error here: 6 bits are used */
6829 tcg_gen_andi_i32(t0, arg2, 0x3F);
6830 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
6831 tcg_gen_shl_i32(ret, arg1, t0);
6832 tcg_gen_br(l2);
6833 gen_set_label(l1);
6834 tcg_gen_movi_i32(ret, 0);
6835 tcg_gen_br(l2);
6836 tcg_temp_free_i32(t0);
6837 }
6838 GEN_SPEOP_ARITH2(evslw, gen_op_evslw);
6839 static always_inline void gen_op_evrlw (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
6840 {
6841 TCGv_i32 t0 = tcg_temp_new_i32();
6842 tcg_gen_andi_i32(t0, arg2, 0x1F);
6843 tcg_gen_rotl_i32(ret, arg1, t0);
6844 tcg_temp_free_i32(t0);
6845 }
6846 GEN_SPEOP_ARITH2(evrlw, gen_op_evrlw);
6847 static always_inline void gen_evmergehi (DisasContext *ctx)
6848 {
6849 if (unlikely(!ctx->spe_enabled)) {
6850 gen_exception(ctx, POWERPC_EXCP_APU);
6851 return;
6852 }
6853 #if defined(TARGET_PPC64)
6854 TCGv t0 = tcg_temp_new();
6855 TCGv t1 = tcg_temp_new();
6856 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32);
6857 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL);
6858 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
6859 tcg_temp_free(t0);
6860 tcg_temp_free(t1);
6861 #else
6862 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
6863 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
6864 #endif
6865 }
6866 GEN_SPEOP_ARITH2(evaddw, tcg_gen_add_i32);
6867 static always_inline void gen_op_evsubf (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
6868 {
6869 tcg_gen_sub_i32(ret, arg2, arg1);
6870 }
6871 GEN_SPEOP_ARITH2(evsubfw, gen_op_evsubf);
6872
6873 /* SPE arithmetic immediate */
6874 #if defined(TARGET_PPC64)
6875 #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
6876 static always_inline void gen_##name (DisasContext *ctx) \
6877 { \
6878 if (unlikely(!ctx->spe_enabled)) { \
6879 gen_exception(ctx, POWERPC_EXCP_APU); \
6880 return; \
6881 } \
6882 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6883 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6884 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
6885 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
6886 tcg_op(t0, t0, rA(ctx->opcode)); \
6887 tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
6888 tcg_gen_trunc_i64_i32(t1, t2); \
6889 tcg_temp_free_i64(t2); \
6890 tcg_op(t1, t1, rA(ctx->opcode)); \
6891 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
6892 tcg_temp_free_i32(t0); \
6893 tcg_temp_free_i32(t1); \
6894 }
6895 #else
6896 #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
6897 static always_inline void gen_##name (DisasContext *ctx) \
6898 { \
6899 if (unlikely(!ctx->spe_enabled)) { \
6900 gen_exception(ctx, POWERPC_EXCP_APU); \
6901 return; \
6902 } \
6903 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
6904 rA(ctx->opcode)); \
6905 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)], \
6906 rA(ctx->opcode)); \
6907 }
6908 #endif
6909 GEN_SPEOP_ARITH_IMM2(evaddiw, tcg_gen_addi_i32);
6910 GEN_SPEOP_ARITH_IMM2(evsubifw, tcg_gen_subi_i32);
6911
6912 /* SPE comparison */
6913 #if defined(TARGET_PPC64)
6914 #define GEN_SPEOP_COMP(name, tcg_cond) \
6915 static always_inline void gen_##name (DisasContext *ctx) \
6916 { \
6917 if (unlikely(!ctx->spe_enabled)) { \
6918 gen_exception(ctx, POWERPC_EXCP_APU); \
6919 return; \
6920 } \
6921 int l1 = gen_new_label(); \
6922 int l2 = gen_new_label(); \
6923 int l3 = gen_new_label(); \
6924 int l4 = gen_new_label(); \
6925 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6926 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6927 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
6928 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6929 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
6930 tcg_gen_brcond_i32(tcg_cond, t0, t1, l1); \
6931 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0); \
6932 tcg_gen_br(l2); \
6933 gen_set_label(l1); \
6934 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
6935 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
6936 gen_set_label(l2); \
6937 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
6938 tcg_gen_trunc_i64_i32(t0, t2); \
6939 tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
6940 tcg_gen_trunc_i64_i32(t1, t2); \
6941 tcg_temp_free_i64(t2); \
6942 tcg_gen_brcond_i32(tcg_cond, t0, t1, l3); \
6943 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
6944 ~(CRF_CH | CRF_CH_AND_CL)); \
6945 tcg_gen_br(l4); \
6946 gen_set_label(l3); \
6947 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
6948 CRF_CH | CRF_CH_OR_CL); \
6949 gen_set_label(l4); \
6950 tcg_temp_free_i32(t0); \
6951 tcg_temp_free_i32(t1); \
6952 }
6953 #else
6954 #define GEN_SPEOP_COMP(name, tcg_cond) \
6955 static always_inline void gen_##name (DisasContext *ctx) \
6956 { \
6957 if (unlikely(!ctx->spe_enabled)) { \
6958 gen_exception(ctx, POWERPC_EXCP_APU); \
6959 return; \
6960 } \
6961 int l1 = gen_new_label(); \
6962 int l2 = gen_new_label(); \
6963 int l3 = gen_new_label(); \
6964 int l4 = gen_new_label(); \
6965 \
6966 tcg_gen_brcond_i32(tcg_cond, cpu_gpr[rA(ctx->opcode)], \
6967 cpu_gpr[rB(ctx->opcode)], l1); \
6968 tcg_gen_movi_tl(cpu_crf[crfD(ctx->opcode)], 0); \
6969 tcg_gen_br(l2); \
6970 gen_set_label(l1); \
6971 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
6972 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
6973 gen_set_label(l2); \
6974 tcg_gen_brcond_i32(tcg_cond, cpu_gprh[rA(ctx->opcode)], \
6975 cpu_gprh[rB(ctx->opcode)], l3); \
6976 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
6977 ~(CRF_CH | CRF_CH_AND_CL)); \
6978 tcg_gen_br(l4); \
6979 gen_set_label(l3); \
6980 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
6981 CRF_CH | CRF_CH_OR_CL); \
6982 gen_set_label(l4); \
6983 }
6984 #endif
6985 GEN_SPEOP_COMP(evcmpgtu, TCG_COND_GTU);
6986 GEN_SPEOP_COMP(evcmpgts, TCG_COND_GT);
6987 GEN_SPEOP_COMP(evcmpltu, TCG_COND_LTU);
6988 GEN_SPEOP_COMP(evcmplts, TCG_COND_LT);
6989 GEN_SPEOP_COMP(evcmpeq, TCG_COND_EQ);
6990
6991 /* SPE misc */
6992 static always_inline void gen_brinc (DisasContext *ctx)
6993 {
6994 /* Note: brinc is usable even if SPE is disabled */
6995 gen_helper_brinc(cpu_gpr[rD(ctx->opcode)],
6996 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
6997 }
6998 static always_inline void gen_evmergelo (DisasContext *ctx)
6999 {
7000 if (unlikely(!ctx->spe_enabled)) {
7001 gen_exception(ctx, POWERPC_EXCP_APU);
7002 return;
7003 }
7004 #if defined(TARGET_PPC64)
7005 TCGv t0 = tcg_temp_new();
7006 TCGv t1 = tcg_temp_new();
7007 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x00000000FFFFFFFFLL);
7008 tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32);
7009 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
7010 tcg_temp_free(t0);
7011 tcg_temp_free(t1);
7012 #else
7013 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7014 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
7015 #endif
7016 }
7017 static always_inline void gen_evmergehilo (DisasContext *ctx)
7018 {
7019 if (unlikely(!ctx->spe_enabled)) {
7020 gen_exception(ctx, POWERPC_EXCP_APU);
7021 return;
7022 }
7023 #if defined(TARGET_PPC64)
7024 TCGv t0 = tcg_temp_new();
7025 TCGv t1 = tcg_temp_new();
7026 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x00000000FFFFFFFFLL);
7027 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL);
7028 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
7029 tcg_temp_free(t0);
7030 tcg_temp_free(t1);
7031 #else
7032 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7033 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
7034 #endif
7035 }
7036 static always_inline void gen_evmergelohi (DisasContext *ctx)
7037 {
7038 if (unlikely(!ctx->spe_enabled)) {
7039 gen_exception(ctx, POWERPC_EXCP_APU);
7040 return;
7041 }
7042 #if defined(TARGET_PPC64)
7043 TCGv t0 = tcg_temp_new();
7044 TCGv t1 = tcg_temp_new();
7045 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32);
7046 tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32);
7047 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
7048 tcg_temp_free(t0);
7049 tcg_temp_free(t1);
7050 #else
7051 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
7052 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
7053 #endif
7054 }
7055 static always_inline void gen_evsplati (DisasContext *ctx)
7056 {
7057 uint64_t imm = ((int32_t)(rA(ctx->opcode) << 11)) >> 27;
7058
7059 #if defined(TARGET_PPC64)
7060 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm);
7061 #else
7062 tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm);
7063 tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm);
7064 #endif
7065 }
7066 static always_inline void gen_evsplatfi (DisasContext *ctx)
7067 {
7068 uint64_t imm = rA(ctx->opcode) << 11;
7069
7070 #if defined(TARGET_PPC64)
7071 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm);
7072 #else
7073 tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm);
7074 tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm);
7075 #endif
7076 }
7077
7078 static always_inline void gen_evsel (DisasContext *ctx)
7079 {
7080 int l1 = gen_new_label();
7081 int l2 = gen_new_label();
7082 int l3 = gen_new_label();
7083 int l4 = gen_new_label();
7084 TCGv_i32 t0 = tcg_temp_local_new_i32();
7085 #if defined(TARGET_PPC64)
7086 TCGv t1 = tcg_temp_local_new();
7087 TCGv t2 = tcg_temp_local_new();
7088 #endif
7089 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 3);
7090 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
7091 #if defined(TARGET_PPC64)
7092 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF00000000ULL);
7093 #else
7094 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
7095 #endif
7096 tcg_gen_br(l2);
7097 gen_set_label(l1);
7098 #if defined(TARGET_PPC64)
7099 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0xFFFFFFFF00000000ULL);
7100 #else
7101 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
7102 #endif
7103 gen_set_label(l2);
7104 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 2);
7105 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l3);
7106 #if defined(TARGET_PPC64)
7107 tcg_gen_andi_tl(t2, cpu_gpr[rA(ctx->opcode)], 0x00000000FFFFFFFFULL);
7108 #else
7109 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
7110 #endif
7111 tcg_gen_br(l4);
7112 gen_set_label(l3);
7113 #if defined(TARGET_PPC64)
7114 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x00000000FFFFFFFFULL);
7115 #else
7116 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7117 #endif
7118 gen_set_label(l4);
7119 tcg_temp_free_i32(t0);
7120 #if defined(TARGET_PPC64)
7121 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t1, t2);
7122 tcg_temp_free(t1);
7123 tcg_temp_free(t2);
7124 #endif
7125 }
7126 GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE)
7127 {
7128 gen_evsel(ctx);
7129 }
7130 GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE)
7131 {
7132 gen_evsel(ctx);
7133 }
7134 GEN_HANDLER2(evsel2, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE)
7135 {
7136 gen_evsel(ctx);
7137 }
7138 GEN_HANDLER2(evsel3, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE)
7139 {
7140 gen_evsel(ctx);
7141 }
7142
7143 GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, PPC_SPE); ////
7144 GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, PPC_SPE);
7145 GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, PPC_SPE); ////
7146 GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, PPC_SPE);
7147 GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, PPC_SPE); ////
7148 GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, PPC_SPE); ////
7149 GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, PPC_SPE); ////
7150 GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x00000000, PPC_SPE); //
7151 GEN_SPE(speundef, evand, 0x08, 0x08, 0x00000000, PPC_SPE); ////
7152 GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, PPC_SPE); ////
7153 GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, PPC_SPE); ////
7154 GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, PPC_SPE); ////
7155 GEN_SPE(speundef, evorc, 0x0D, 0x08, 0x00000000, PPC_SPE); ////
7156 GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, PPC_SPE); ////
7157 GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, PPC_SPE); ////
7158 GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, PPC_SPE);
7159 GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, PPC_SPE); ////
7160 GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, PPC_SPE);
7161 GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, PPC_SPE); //
7162 GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, PPC_SPE);
7163 GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, PPC_SPE); ////
7164 GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, PPC_SPE); ////
7165 GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, PPC_SPE); ////
7166 GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, PPC_SPE); ////
7167 GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, PPC_SPE); ////
7168
7169 /* SPE load and stores */
7170 static always_inline void gen_addr_spe_imm_index (DisasContext *ctx, TCGv EA, int sh)
7171 {
7172 target_ulong uimm = rB(ctx->opcode);
7173
7174 if (rA(ctx->opcode) == 0) {
7175 tcg_gen_movi_tl(EA, uimm << sh);
7176 } else {
7177 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], uimm << sh);
7178 #if defined(TARGET_PPC64)
7179 if (!ctx->sf_mode) {
7180 tcg_gen_ext32u_tl(EA, EA);
7181 }
7182 #endif
7183 }
7184 }
7185
7186 static always_inline void gen_op_evldd(DisasContext *ctx, TCGv addr)
7187 {
7188 #if defined(TARGET_PPC64)
7189 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7190 #else
7191 TCGv_i64 t0 = tcg_temp_new_i64();
7192 gen_qemu_ld64(ctx, t0, addr);
7193 tcg_gen_trunc_i64_i32(cpu_gpr[rD(ctx->opcode)], t0);
7194 tcg_gen_shri_i64(t0, t0, 32);
7195 tcg_gen_trunc_i64_i32(cpu_gprh[rD(ctx->opcode)], t0);
7196 tcg_temp_free_i64(t0);
7197 #endif
7198 }
7199
7200 static always_inline void gen_op_evldw(DisasContext *ctx, TCGv addr)
7201 {
7202 #if defined(TARGET_PPC64)
7203 TCGv t0 = tcg_temp_new();
7204 gen_qemu_ld32u(ctx, t0, addr);
7205 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7206 gen_addr_add(ctx, addr, addr, 4);
7207 gen_qemu_ld32u(ctx, t0, addr);
7208 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7209 tcg_temp_free(t0);
7210 #else
7211 gen_qemu_ld32u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
7212 gen_addr_add(ctx, addr, addr, 4);
7213 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7214 #endif
7215 }
7216
7217 static always_inline void gen_op_evldh(DisasContext *ctx, TCGv addr)
7218 {
7219 TCGv t0 = tcg_temp_new();
7220 #if defined(TARGET_PPC64)
7221 gen_qemu_ld16u(ctx, t0, addr);
7222 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7223 gen_addr_add(ctx, addr, addr, 2);
7224 gen_qemu_ld16u(ctx, t0, addr);
7225 tcg_gen_shli_tl(t0, t0, 32);
7226 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7227 gen_addr_add(ctx, addr, addr, 2);
7228 gen_qemu_ld16u(ctx, t0, addr);
7229 tcg_gen_shli_tl(t0, t0, 16);
7230 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7231 gen_addr_add(ctx, addr, addr, 2);
7232 gen_qemu_ld16u(ctx, t0, addr);
7233 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7234 #else
7235 gen_qemu_ld16u(ctx, t0, addr);
7236 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
7237 gen_addr_add(ctx, addr, addr, 2);
7238 gen_qemu_ld16u(ctx, t0, addr);
7239 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
7240 gen_addr_add(ctx, addr, addr, 2);
7241 gen_qemu_ld16u(ctx, t0, addr);
7242 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
7243 gen_addr_add(ctx, addr, addr, 2);
7244 gen_qemu_ld16u(ctx, t0, addr);
7245 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7246 #endif
7247 tcg_temp_free(t0);
7248 }
7249
7250 static always_inline void gen_op_evlhhesplat(DisasContext *ctx, TCGv addr)
7251 {
7252 TCGv t0 = tcg_temp_new();
7253 gen_qemu_ld16u(ctx, t0, addr);
7254 #if defined(TARGET_PPC64)
7255 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7256 tcg_gen_shli_tl(t0, t0, 16);
7257 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7258 #else
7259 tcg_gen_shli_tl(t0, t0, 16);
7260 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7261 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7262 #endif
7263 tcg_temp_free(t0);
7264 }
7265
7266 static always_inline void gen_op_evlhhousplat(DisasContext *ctx, TCGv addr)
7267 {
7268 TCGv t0 = tcg_temp_new();
7269 gen_qemu_ld16u(ctx, t0, addr);
7270 #if defined(TARGET_PPC64)
7271 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7272 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7273 #else
7274 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7275 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7276 #endif
7277 tcg_temp_free(t0);
7278 }
7279
7280 static always_inline void gen_op_evlhhossplat(DisasContext *ctx, TCGv addr)
7281 {
7282 TCGv t0 = tcg_temp_new();
7283 gen_qemu_ld16s(ctx, t0, addr);
7284 #if defined(TARGET_PPC64)
7285 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7286 tcg_gen_ext32u_tl(t0, t0);
7287 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7288 #else
7289 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7290 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7291 #endif
7292 tcg_temp_free(t0);
7293 }
7294
7295 static always_inline void gen_op_evlwhe(DisasContext *ctx, TCGv addr)
7296 {
7297 TCGv t0 = tcg_temp_new();
7298 #if defined(TARGET_PPC64)
7299 gen_qemu_ld16u(ctx, t0, addr);
7300 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7301 gen_addr_add(ctx, addr, addr, 2);
7302 gen_qemu_ld16u(ctx, t0, addr);
7303 tcg_gen_shli_tl(t0, t0, 16);
7304 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7305 #else
7306 gen_qemu_ld16u(ctx, t0, addr);
7307 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
7308 gen_addr_add(ctx, addr, addr, 2);
7309 gen_qemu_ld16u(ctx, t0, addr);
7310 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
7311 #endif
7312 tcg_temp_free(t0);
7313 }
7314
7315 static always_inline void gen_op_evlwhou(DisasContext *ctx, TCGv addr)
7316 {
7317 #if defined(TARGET_PPC64)
7318 TCGv t0 = tcg_temp_new();
7319 gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7320 gen_addr_add(ctx, addr, addr, 2);
7321 gen_qemu_ld16u(ctx, t0, addr);
7322 tcg_gen_shli_tl(t0, t0, 32);
7323 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7324 tcg_temp_free(t0);
7325 #else
7326 gen_qemu_ld16u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
7327 gen_addr_add(ctx, addr, addr, 2);
7328 gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7329 #endif
7330 }
7331
7332 static always_inline void gen_op_evlwhos(DisasContext *ctx, TCGv addr)
7333 {
7334 #if defined(TARGET_PPC64)
7335 TCGv t0 = tcg_temp_new();
7336 gen_qemu_ld16s(ctx, t0, addr);
7337 tcg_gen_ext32u_tl(cpu_gpr[rD(ctx->opcode)], t0);
7338 gen_addr_add(ctx, addr, addr, 2);
7339 gen_qemu_ld16s(ctx, t0, addr);
7340 tcg_gen_shli_tl(t0, t0, 32);
7341 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7342 tcg_temp_free(t0);
7343 #else
7344 gen_qemu_ld16s(ctx, cpu_gprh[rD(ctx->opcode)], addr);
7345 gen_addr_add(ctx, addr, addr, 2);
7346 gen_qemu_ld16s(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7347 #endif
7348 }
7349
7350 static always_inline void gen_op_evlwwsplat(DisasContext *ctx, TCGv addr)
7351 {
7352 TCGv t0 = tcg_temp_new();
7353 gen_qemu_ld32u(ctx, t0, addr);
7354 #if defined(TARGET_PPC64)
7355 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7356 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7357 #else
7358 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7359 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7360 #endif
7361 tcg_temp_free(t0);
7362 }
7363
7364 static always_inline void gen_op_evlwhsplat(DisasContext *ctx, TCGv addr)
7365 {
7366 TCGv t0 = tcg_temp_new();
7367 #if defined(TARGET_PPC64)
7368 gen_qemu_ld16u(ctx, t0, addr);
7369 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7370 tcg_gen_shli_tl(t0, t0, 32);
7371 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7372 gen_addr_add(ctx, addr, addr, 2);
7373 gen_qemu_ld16u(ctx, t0, addr);
7374 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7375 tcg_gen_shli_tl(t0, t0, 16);
7376 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7377 #else
7378 gen_qemu_ld16u(ctx, t0, addr);
7379 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
7380 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
7381 gen_addr_add(ctx, addr, addr, 2);
7382 gen_qemu_ld16u(ctx, t0, addr);
7383 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
7384 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
7385 #endif
7386 tcg_temp_free(t0);
7387 }
7388
7389 static always_inline void gen_op_evstdd(DisasContext *ctx, TCGv addr)
7390 {
7391 #if defined(TARGET_PPC64)
7392 gen_qemu_st64(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7393 #else
7394 TCGv_i64 t0 = tcg_temp_new_i64();
7395 tcg_gen_concat_i32_i64(t0, cpu_gpr[rS(ctx->opcode)], cpu_gprh[rS(ctx->opcode)]);
7396 gen_qemu_st64(ctx, t0, addr);
7397 tcg_temp_free_i64(t0);
7398 #endif
7399 }
7400
7401 static always_inline void gen_op_evstdw(DisasContext *ctx, TCGv addr)
7402 {
7403 #if defined(TARGET_PPC64)
7404 TCGv t0 = tcg_temp_new();
7405 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
7406 gen_qemu_st32(ctx, t0, addr);
7407 tcg_temp_free(t0);
7408 #else
7409 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
7410 #endif
7411 gen_addr_add(ctx, addr, addr, 4);
7412 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7413 }
7414
7415 static always_inline void gen_op_evstdh(DisasContext *ctx, TCGv addr)
7416 {
7417 TCGv t0 = tcg_temp_new();
7418 #if defined(TARGET_PPC64)
7419 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48);
7420 #else
7421 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
7422 #endif
7423 gen_qemu_st16(ctx, t0, addr);
7424 gen_addr_add(ctx, addr, addr, 2);
7425 #if defined(TARGET_PPC64)
7426 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
7427 gen_qemu_st16(ctx, t0, addr);
7428 #else
7429 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
7430 #endif
7431 gen_addr_add(ctx, addr, addr, 2);
7432 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
7433 gen_qemu_st16(ctx, t0, addr);
7434 tcg_temp_free(t0);
7435 gen_addr_add(ctx, addr, addr, 2);
7436 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7437 }
7438
7439 static always_inline void gen_op_evstwhe(DisasContext *ctx, TCGv addr)
7440 {
7441 TCGv t0 = tcg_temp_new();
7442 #if defined(TARGET_PPC64)
7443 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48);
7444 #else
7445 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
7446 #endif
7447 gen_qemu_st16(ctx, t0, addr);
7448 gen_addr_add(ctx, addr, addr, 2);
7449 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
7450 gen_qemu_st16(ctx, t0, addr);
7451 tcg_temp_free(t0);
7452 }
7453
7454 static always_inline void gen_op_evstwho(DisasContext *ctx, TCGv addr)
7455 {
7456 #if defined(TARGET_PPC64)
7457 TCGv t0 = tcg_temp_new();
7458 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
7459 gen_qemu_st16(ctx, t0, addr);
7460 tcg_temp_free(t0);
7461 #else
7462 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
7463 #endif
7464 gen_addr_add(ctx, addr, addr, 2);
7465 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7466 }
7467
7468 static always_inline void gen_op_evstwwe(DisasContext *ctx, TCGv addr)
7469 {
7470 #if defined(TARGET_PPC64)
7471 TCGv t0 = tcg_temp_new();
7472 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
7473 gen_qemu_st32(ctx, t0, addr);
7474 tcg_temp_free(t0);
7475 #else
7476 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
7477 #endif
7478 }
7479
7480 static always_inline void gen_op_evstwwo(DisasContext *ctx, TCGv addr)
7481 {
7482 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7483 }
7484
7485 #define GEN_SPEOP_LDST(name, opc2, sh) \
7486 GEN_HANDLER(name, 0x04, opc2, 0x0C, 0x00000000, PPC_SPE) \
7487 { \
7488 TCGv t0; \
7489 if (unlikely(!ctx->spe_enabled)) { \
7490 gen_exception(ctx, POWERPC_EXCP_APU); \
7491 return; \
7492 } \
7493 gen_set_access_type(ctx, ACCESS_INT); \
7494 t0 = tcg_temp_new(); \
7495 if (Rc(ctx->opcode)) { \
7496 gen_addr_spe_imm_index(ctx, t0, sh); \
7497 } else { \
7498 gen_addr_reg_index(ctx, t0); \
7499 } \
7500 gen_op_##name(ctx, t0); \
7501 tcg_temp_free(t0); \
7502 }
7503
7504 GEN_SPEOP_LDST(evldd, 0x00, 3);
7505 GEN_SPEOP_LDST(evldw, 0x01, 3);
7506 GEN_SPEOP_LDST(evldh, 0x02, 3);
7507 GEN_SPEOP_LDST(evlhhesplat, 0x04, 1);
7508 GEN_SPEOP_LDST(evlhhousplat, 0x06, 1);
7509 GEN_SPEOP_LDST(evlhhossplat, 0x07, 1);
7510 GEN_SPEOP_LDST(evlwhe, 0x08, 2);
7511 GEN_SPEOP_LDST(evlwhou, 0x0A, 2);
7512 GEN_SPEOP_LDST(evlwhos, 0x0B, 2);
7513 GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2);
7514 GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2);
7515
7516 GEN_SPEOP_LDST(evstdd, 0x10, 3);
7517 GEN_SPEOP_LDST(evstdw, 0x11, 3);
7518 GEN_SPEOP_LDST(evstdh, 0x12, 3);
7519 GEN_SPEOP_LDST(evstwhe, 0x18, 2);
7520 GEN_SPEOP_LDST(evstwho, 0x1A, 2);
7521 GEN_SPEOP_LDST(evstwwe, 0x1C, 2);
7522 GEN_SPEOP_LDST(evstwwo, 0x1E, 2);
7523
7524 /* Multiply and add - TODO */
7525 #if 0
7526 GEN_SPE(speundef, evmhessf, 0x01, 0x10, 0x00000000, PPC_SPE);
7527 GEN_SPE(speundef, evmhossf, 0x03, 0x10, 0x00000000, PPC_SPE);
7528 GEN_SPE(evmheumi, evmhesmi, 0x04, 0x10, 0x00000000, PPC_SPE);
7529 GEN_SPE(speundef, evmhesmf, 0x05, 0x10, 0x00000000, PPC_SPE);
7530 GEN_SPE(evmhoumi, evmhosmi, 0x06, 0x10, 0x00000000, PPC_SPE);
7531 GEN_SPE(speundef, evmhosmf, 0x07, 0x10, 0x00000000, PPC_SPE);
7532 GEN_SPE(speundef, evmhessfa, 0x11, 0x10, 0x00000000, PPC_SPE);
7533 GEN_SPE(speundef, evmhossfa, 0x13, 0x10, 0x00000000, PPC_SPE);
7534 GEN_SPE(evmheumia, evmhesmia, 0x14, 0x10, 0x00000000, PPC_SPE);
7535 GEN_SPE(speundef, evmhesmfa, 0x15, 0x10, 0x00000000, PPC_SPE);
7536 GEN_SPE(evmhoumia, evmhosmia, 0x16, 0x10, 0x00000000, PPC_SPE);
7537 GEN_SPE(speundef, evmhosmfa, 0x17, 0x10, 0x00000000, PPC_SPE);
7538
7539 GEN_SPE(speundef, evmwhssf, 0x03, 0x11, 0x00000000, PPC_SPE);
7540 GEN_SPE(evmwlumi, speundef, 0x04, 0x11, 0x00000000, PPC_SPE);
7541 GEN_SPE(evmwhumi, evmwhsmi, 0x06, 0x11, 0x00000000, PPC_SPE);
7542 GEN_SPE(speundef, evmwhsmf, 0x07, 0x11, 0x00000000, PPC_SPE);
7543 GEN_SPE(speundef, evmwssf, 0x09, 0x11, 0x00000000, PPC_SPE);
7544 GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, PPC_SPE);
7545 GEN_SPE(speundef, evmwsmf, 0x0D, 0x11, 0x00000000, PPC_SPE);
7546 GEN_SPE(speundef, evmwhssfa, 0x13, 0x11, 0x00000000, PPC_SPE);
7547 GEN_SPE(evmwlumia, speundef, 0x14, 0x11, 0x00000000, PPC_SPE);
7548 GEN_SPE(evmwhumia, evmwhsmia, 0x16, 0x11, 0x00000000, PPC_SPE);
7549 GEN_SPE(speundef, evmwhsmfa, 0x17, 0x11, 0x00000000, PPC_SPE);
7550 GEN_SPE(speundef, evmwssfa, 0x19, 0x11, 0x00000000, PPC_SPE);
7551 GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, PPC_SPE);
7552 GEN_SPE(speundef, evmwsmfa, 0x1D, 0x11, 0x00000000, PPC_SPE);
7553
7554 GEN_SPE(evadduiaaw, evaddsiaaw, 0x00, 0x13, 0x0000F800, PPC_SPE);
7555 GEN_SPE(evsubfusiaaw, evsubfssiaaw, 0x01, 0x13, 0x0000F800, PPC_SPE);
7556 GEN_SPE(evaddumiaaw, evaddsmiaaw, 0x04, 0x13, 0x0000F800, PPC_SPE);
7557 GEN_SPE(evsubfumiaaw, evsubfsmiaaw, 0x05, 0x13, 0x0000F800, PPC_SPE);
7558 GEN_SPE(evdivws, evdivwu, 0x06, 0x13, 0x00000000, PPC_SPE);
7559 GEN_SPE(evmra, speundef, 0x07, 0x13, 0x0000F800, PPC_SPE);
7560
7561 GEN_SPE(evmheusiaaw, evmhessiaaw, 0x00, 0x14, 0x00000000, PPC_SPE);
7562 GEN_SPE(speundef, evmhessfaaw, 0x01, 0x14, 0x00000000, PPC_SPE);
7563 GEN_SPE(evmhousiaaw, evmhossiaaw, 0x02, 0x14, 0x00000000, PPC_SPE);
7564 GEN_SPE(speundef, evmhossfaaw, 0x03, 0x14, 0x00000000, PPC_SPE);
7565 GEN_SPE(evmheumiaaw, evmhesmiaaw, 0x04, 0x14, 0x00000000, PPC_SPE);
7566 GEN_SPE(speundef, evmhesmfaaw, 0x05, 0x14, 0x00000000, PPC_SPE);
7567 GEN_SPE(evmhoumiaaw, evmhosmiaaw, 0x06, 0x14, 0x00000000, PPC_SPE);
7568 GEN_SPE(speundef, evmhosmfaaw, 0x07, 0x14, 0x00000000, PPC_SPE);
7569 GEN_SPE(evmhegumiaa, evmhegsmiaa, 0x14, 0x14, 0x00000000, PPC_SPE);
7570 GEN_SPE(speundef, evmhegsmfaa, 0x15, 0x14, 0x00000000, PPC_SPE);
7571 GEN_SPE(evmhogumiaa, evmhogsmiaa, 0x16, 0x14, 0x00000000, PPC_SPE);
7572 GEN_SPE(speundef, evmhogsmfaa, 0x17, 0x14, 0x00000000, PPC_SPE);
7573
7574 GEN_SPE(evmwlusiaaw, evmwlssiaaw, 0x00, 0x15, 0x00000000, PPC_SPE);
7575 GEN_SPE(evmwlumiaaw, evmwlsmiaaw, 0x04, 0x15, 0x00000000, PPC_SPE);
7576 GEN_SPE(speundef, evmwssfaa, 0x09, 0x15, 0x00000000, PPC_SPE);
7577 GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, PPC_SPE);
7578 GEN_SPE(speundef, evmwsmfaa, 0x0D, 0x15, 0x00000000, PPC_SPE);
7579
7580 GEN_SPE(evmheusianw, evmhessianw, 0x00, 0x16, 0x00000000, PPC_SPE);
7581 GEN_SPE(speundef, evmhessfanw, 0x01, 0x16, 0x00000000, PPC_SPE);
7582 GEN_SPE(evmhousianw, evmhossianw, 0x02, 0x16, 0x00000000, PPC_SPE);
7583 GEN_SPE(speundef, evmhossfanw, 0x03, 0x16, 0x00000000, PPC_SPE);
7584 GEN_SPE(evmheumianw, evmhesmianw, 0x04, 0x16, 0x00000000, PPC_SPE);
7585 GEN_SPE(speundef, evmhesmfanw, 0x05, 0x16, 0x00000000, PPC_SPE);
7586 GEN_SPE(evmhoumianw, evmhosmianw, 0x06, 0x16, 0x00000000, PPC_SPE);
7587 GEN_SPE(speundef, evmhosmfanw, 0x07, 0x16, 0x00000000, PPC_SPE);
7588 GEN_SPE(evmhegumian, evmhegsmian, 0x14, 0x16, 0x00000000, PPC_SPE);
7589 GEN_SPE(speundef, evmhegsmfan, 0x15, 0x16, 0x00000000, PPC_SPE);
7590 GEN_SPE(evmhigumian, evmhigsmian, 0x16, 0x16, 0x00000000, PPC_SPE);
7591 GEN_SPE(speundef, evmhogsmfan, 0x17, 0x16, 0x00000000, PPC_SPE);
7592
7593 GEN_SPE(evmwlusianw, evmwlssianw, 0x00, 0x17, 0x00000000, PPC_SPE);
7594 GEN_SPE(evmwlumianw, evmwlsmianw, 0x04, 0x17, 0x00000000, PPC_SPE);
7595 GEN_SPE(speundef, evmwssfan, 0x09, 0x17, 0x00000000, PPC_SPE);
7596 GEN_SPE(evmwumian, evmwsmian, 0x0C, 0x17, 0x00000000, PPC_SPE);
7597 GEN_SPE(speundef, evmwsmfan, 0x0D, 0x17, 0x00000000, PPC_SPE);
7598 #endif
7599
7600 /*** SPE floating-point extension ***/
7601 #if defined(TARGET_PPC64)
7602 #define GEN_SPEFPUOP_CONV_32_32(name) \
7603 static always_inline void gen_##name (DisasContext *ctx) \
7604 { \
7605 TCGv_i32 t0; \
7606 TCGv t1; \
7607 t0 = tcg_temp_new_i32(); \
7608 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
7609 gen_helper_##name(t0, t0); \
7610 t1 = tcg_temp_new(); \
7611 tcg_gen_extu_i32_tl(t1, t0); \
7612 tcg_temp_free_i32(t0); \
7613 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
7614 0xFFFFFFFF00000000ULL); \
7615 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \
7616 tcg_temp_free(t1); \
7617 }
7618 #define GEN_SPEFPUOP_CONV_32_64(name) \
7619 static always_inline void gen_##name (DisasContext *ctx) \
7620 { \
7621 TCGv_i32 t0; \
7622 TCGv t1; \
7623 t0 = tcg_temp_new_i32(); \
7624 gen_helper_##name(t0, cpu_gpr[rB(ctx->opcode)]); \
7625 t1 = tcg_temp_new(); \
7626 tcg_gen_extu_i32_tl(t1, t0); \
7627 tcg_temp_free_i32(t0); \
7628 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
7629 0xFFFFFFFF00000000ULL); \
7630 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \
7631 tcg_temp_free(t1); \
7632 }
7633 #define GEN_SPEFPUOP_CONV_64_32(name) \
7634 static always_inline void gen_##name (DisasContext *ctx) \
7635 { \
7636 TCGv_i32 t0 = tcg_temp_new_i32(); \
7637 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
7638 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], t0); \
7639 tcg_temp_free_i32(t0); \
7640 }
7641 #define GEN_SPEFPUOP_CONV_64_64(name) \
7642 static always_inline void gen_##name (DisasContext *ctx) \
7643 { \
7644 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
7645 }
7646 #define GEN_SPEFPUOP_ARITH2_32_32(name) \
7647 static always_inline void gen_##name (DisasContext *ctx) \
7648 { \
7649 TCGv_i32 t0, t1; \
7650 TCGv_i64 t2; \
7651 if (unlikely(!ctx->spe_enabled)) { \
7652 gen_exception(ctx, POWERPC_EXCP_APU); \
7653 return; \
7654 } \
7655 t0 = tcg_temp_new_i32(); \
7656 t1 = tcg_temp_new_i32(); \
7657 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
7658 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
7659 gen_helper_##name(t0, t0, t1); \
7660 tcg_temp_free_i32(t1); \
7661 t2 = tcg_temp_new(); \
7662 tcg_gen_extu_i32_tl(t2, t0); \
7663 tcg_temp_free_i32(t0); \
7664 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
7665 0xFFFFFFFF00000000ULL); \
7666 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t2); \
7667 tcg_temp_free(t2); \
7668 }
7669 #define GEN_SPEFPUOP_ARITH2_64_64(name) \
7670 static always_inline void gen_##name (DisasContext *ctx) \
7671 { \
7672 if (unlikely(!ctx->spe_enabled)) { \
7673 gen_exception(ctx, POWERPC_EXCP_APU); \
7674 return; \
7675 } \
7676 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
7677 cpu_gpr[rB(ctx->opcode)]); \
7678 }
7679 #define GEN_SPEFPUOP_COMP_32(name) \
7680 static always_inline void gen_##name (DisasContext *ctx) \
7681 { \
7682 TCGv_i32 t0, t1; \
7683 if (unlikely(!ctx->spe_enabled)) { \
7684 gen_exception(ctx, POWERPC_EXCP_APU); \
7685 return; \
7686 } \
7687 t0 = tcg_temp_new_i32(); \
7688 t1 = tcg_temp_new_i32(); \
7689 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
7690 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
7691 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], t0, t1); \
7692 tcg_temp_free_i32(t0); \
7693 tcg_temp_free_i32(t1); \
7694 }
7695 #define GEN_SPEFPUOP_COMP_64(name) \
7696 static always_inline void gen_##name (DisasContext *ctx) \
7697 { \
7698 if (unlikely(!ctx->spe_enabled)) { \
7699 gen_exception(ctx, POWERPC_EXCP_APU); \
7700 return; \
7701 } \
7702 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
7703 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
7704 }
7705 #else
7706 #define GEN_SPEFPUOP_CONV_32_32(name) \
7707 static always_inline void gen_##name (DisasContext *ctx) \
7708 { \
7709 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
7710 }
7711 #define GEN_SPEFPUOP_CONV_32_64(name) \
7712 static always_inline void gen_##name (DisasContext *ctx) \
7713 { \
7714 TCGv_i64 t0 = tcg_temp_new_i64(); \
7715 gen_load_gpr64(t0, rB(ctx->opcode)); \
7716 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], t0); \
7717 tcg_temp_free_i64(t0); \
7718 }
7719 #define GEN_SPEFPUOP_CONV_64_32(name) \
7720 static always_inline void gen_##name (DisasContext *ctx) \
7721 { \
7722 TCGv_i64 t0 = tcg_temp_new_i64(); \
7723 gen_helper_##name(t0, cpu_gpr[rB(ctx->opcode)]); \
7724 gen_store_gpr64(rD(ctx->opcode), t0); \
7725 tcg_temp_free_i64(t0); \
7726 }
7727 #define GEN_SPEFPUOP_CONV_64_64(name) \
7728 static always_inline void gen_##name (DisasContext *ctx) \
7729 { \
7730 TCGv_i64 t0 = tcg_temp_new_i64(); \
7731 gen_load_gpr64(t0, rB(ctx->opcode)); \
7732 gen_helper_##name(t0, t0); \
7733 gen_store_gpr64(rD(ctx->opcode), t0); \
7734 tcg_temp_free_i64(t0); \
7735 }
7736 #define GEN_SPEFPUOP_ARITH2_32_32(name) \
7737 static always_inline void gen_##name (DisasContext *ctx) \
7738 { \
7739 if (unlikely(!ctx->spe_enabled)) { \
7740 gen_exception(ctx, POWERPC_EXCP_APU); \
7741 return; \
7742 } \
7743 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], \
7744 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
7745 }
7746 #define GEN_SPEFPUOP_ARITH2_64_64(name) \
7747 static always_inline void gen_##name (DisasContext *ctx) \
7748 { \
7749 TCGv_i64 t0, t1; \
7750 if (unlikely(!ctx->spe_enabled)) { \
7751 gen_exception(ctx, POWERPC_EXCP_APU); \
7752 return; \
7753 } \
7754 t0 = tcg_temp_new_i64(); \
7755 t1 = tcg_temp_new_i64(); \
7756 gen_load_gpr64(t0, rA(ctx->opcode)); \
7757 gen_load_gpr64(t1, rB(ctx->opcode)); \
7758 gen_helper_##name(t0, t0, t1); \
7759 gen_store_gpr64(rD(ctx->opcode), t0); \
7760 tcg_temp_free_i64(t0); \
7761 tcg_temp_free_i64(t1); \
7762 }
7763 #define GEN_SPEFPUOP_COMP_32(name) \
7764 static always_inline void gen_##name (DisasContext *ctx) \
7765 { \
7766 if (unlikely(!ctx->spe_enabled)) { \
7767 gen_exception(ctx, POWERPC_EXCP_APU); \
7768 return; \
7769 } \
7770 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
7771 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
7772 }
7773 #define GEN_SPEFPUOP_COMP_64(name) \
7774 static always_inline void gen_##name (DisasContext *ctx) \
7775 { \
7776 TCGv_i64 t0, t1; \
7777 if (unlikely(!ctx->spe_enabled)) { \
7778 gen_exception(ctx, POWERPC_EXCP_APU); \
7779 return; \
7780 } \
7781 t0 = tcg_temp_new_i64(); \
7782 t1 = tcg_temp_new_i64(); \
7783 gen_load_gpr64(t0, rA(ctx->opcode)); \
7784 gen_load_gpr64(t1, rB(ctx->opcode)); \
7785 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], t0, t1); \
7786 tcg_temp_free_i64(t0); \
7787 tcg_temp_free_i64(t1); \
7788 }
7789 #endif
7790
7791 /* Single precision floating-point vectors operations */
7792 /* Arithmetic */
7793 GEN_SPEFPUOP_ARITH2_64_64(evfsadd);
7794 GEN_SPEFPUOP_ARITH2_64_64(evfssub);
7795 GEN_SPEFPUOP_ARITH2_64_64(evfsmul);
7796 GEN_SPEFPUOP_ARITH2_64_64(evfsdiv);
7797 static always_inline void gen_evfsabs (DisasContext *ctx)
7798 {
7799 if (unlikely(!ctx->spe_enabled)) {
7800 gen_exception(ctx, POWERPC_EXCP_APU);
7801 return;
7802 }
7803 #if defined(TARGET_PPC64)
7804 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000080000000LL);
7805 #else
7806 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x80000000);
7807 tcg_gen_andi_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000);
7808 #endif
7809 }
7810 static always_inline void gen_evfsnabs (DisasContext *ctx)
7811 {
7812 if (unlikely(!ctx->spe_enabled)) {
7813 gen_exception(ctx, POWERPC_EXCP_APU);
7814 return;
7815 }
7816 #if defined(TARGET_PPC64)
7817 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL);
7818 #else
7819 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
7820 tcg_gen_ori_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
7821 #endif
7822 }
7823 static always_inline void gen_evfsneg (DisasContext *ctx)
7824 {
7825 if (unlikely(!ctx->spe_enabled)) {
7826 gen_exception(ctx, POWERPC_EXCP_APU);
7827 return;
7828 }
7829 #if defined(TARGET_PPC64)
7830 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL);
7831 #else
7832 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
7833 tcg_gen_xori_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
7834 #endif
7835 }
7836
7837 /* Conversion */
7838 GEN_SPEFPUOP_CONV_64_64(evfscfui);
7839 GEN_SPEFPUOP_CONV_64_64(evfscfsi);
7840 GEN_SPEFPUOP_CONV_64_64(evfscfuf);
7841 GEN_SPEFPUOP_CONV_64_64(evfscfsf);
7842 GEN_SPEFPUOP_CONV_64_64(evfsctui);
7843 GEN_SPEFPUOP_CONV_64_64(evfsctsi);
7844 GEN_SPEFPUOP_CONV_64_64(evfsctuf);
7845 GEN_SPEFPUOP_CONV_64_64(evfsctsf);
7846 GEN_SPEFPUOP_CONV_64_64(evfsctuiz);
7847 GEN_SPEFPUOP_CONV_64_64(evfsctsiz);
7848
7849 /* Comparison */
7850 GEN_SPEFPUOP_COMP_64(evfscmpgt);
7851 GEN_SPEFPUOP_COMP_64(evfscmplt);
7852 GEN_SPEFPUOP_COMP_64(evfscmpeq);
7853 GEN_SPEFPUOP_COMP_64(evfststgt);
7854 GEN_SPEFPUOP_COMP_64(evfststlt);
7855 GEN_SPEFPUOP_COMP_64(evfststeq);
7856
7857 /* Opcodes definitions */
7858 GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, PPC_SPE_SINGLE); //
7859 GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, PPC_SPE_SINGLE); //
7860 GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, PPC_SPE_SINGLE); //
7861 GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, PPC_SPE_SINGLE); //
7862 GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, PPC_SPE_SINGLE); //
7863 GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, PPC_SPE_SINGLE); //
7864 GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, PPC_SPE_SINGLE); //
7865 GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, PPC_SPE_SINGLE); //
7866 GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, PPC_SPE_SINGLE); //
7867 GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, PPC_SPE_SINGLE); //
7868 GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, PPC_SPE_SINGLE); //
7869 GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, PPC_SPE_SINGLE); //
7870 GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, PPC_SPE_SINGLE); //
7871 GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, PPC_SPE_SINGLE); //
7872
7873 /* Single precision floating-point operations */
7874 /* Arithmetic */
7875 GEN_SPEFPUOP_ARITH2_32_32(efsadd);
7876 GEN_SPEFPUOP_ARITH2_32_32(efssub);
7877 GEN_SPEFPUOP_ARITH2_32_32(efsmul);
7878 GEN_SPEFPUOP_ARITH2_32_32(efsdiv);
7879 static always_inline void gen_efsabs (DisasContext *ctx)
7880 {
7881 if (unlikely(!ctx->spe_enabled)) {
7882 gen_exception(ctx, POWERPC_EXCP_APU);
7883 return;
7884 }
7885 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], (target_long)~0x80000000LL);
7886 }
7887 static always_inline void gen_efsnabs (DisasContext *ctx)
7888 {
7889 if (unlikely(!ctx->spe_enabled)) {
7890 gen_exception(ctx, POWERPC_EXCP_APU);
7891 return;
7892 }
7893 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
7894 }
7895 static always_inline void gen_efsneg (DisasContext *ctx)
7896 {
7897 if (unlikely(!ctx->spe_enabled)) {
7898 gen_exception(ctx, POWERPC_EXCP_APU);
7899 return;
7900 }
7901 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
7902 }
7903
7904 /* Conversion */
7905 GEN_SPEFPUOP_CONV_32_32(efscfui);
7906 GEN_SPEFPUOP_CONV_32_32(efscfsi);
7907 GEN_SPEFPUOP_CONV_32_32(efscfuf);
7908 GEN_SPEFPUOP_CONV_32_32(efscfsf);
7909 GEN_SPEFPUOP_CONV_32_32(efsctui);
7910 GEN_SPEFPUOP_CONV_32_32(efsctsi);
7911 GEN_SPEFPUOP_CONV_32_32(efsctuf);
7912 GEN_SPEFPUOP_CONV_32_32(efsctsf);
7913 GEN_SPEFPUOP_CONV_32_32(efsctuiz);
7914 GEN_SPEFPUOP_CONV_32_32(efsctsiz);
7915 GEN_SPEFPUOP_CONV_32_64(efscfd);
7916
7917 /* Comparison */
7918 GEN_SPEFPUOP_COMP_32(efscmpgt);
7919 GEN_SPEFPUOP_COMP_32(efscmplt);
7920 GEN_SPEFPUOP_COMP_32(efscmpeq);
7921 GEN_SPEFPUOP_COMP_32(efststgt);
7922 GEN_SPEFPUOP_COMP_32(efststlt);
7923 GEN_SPEFPUOP_COMP_32(efststeq);
7924
7925 /* Opcodes definitions */
7926 GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, PPC_SPE_SINGLE); //
7927 GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, PPC_SPE_SINGLE); //
7928 GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, PPC_SPE_SINGLE); //
7929 GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, PPC_SPE_SINGLE); //
7930 GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, PPC_SPE_SINGLE); //
7931 GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, PPC_SPE_SINGLE); //
7932 GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, PPC_SPE_SINGLE); //
7933 GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, PPC_SPE_SINGLE); //
7934 GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, PPC_SPE_SINGLE); //
7935 GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, PPC_SPE_SINGLE); //
7936 GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, PPC_SPE_SINGLE); //
7937 GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, PPC_SPE_SINGLE); //
7938 GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, PPC_SPE_SINGLE); //
7939 GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, PPC_SPE_SINGLE); //
7940
7941 /* Double precision floating-point operations */
7942 /* Arithmetic */
7943 GEN_SPEFPUOP_ARITH2_64_64(efdadd);
7944 GEN_SPEFPUOP_ARITH2_64_64(efdsub);
7945 GEN_SPEFPUOP_ARITH2_64_64(efdmul);
7946 GEN_SPEFPUOP_ARITH2_64_64(efddiv);
7947 static always_inline void gen_efdabs (DisasContext *ctx)
7948 {
7949 if (unlikely(!ctx->spe_enabled)) {
7950 gen_exception(ctx, POWERPC_EXCP_APU);
7951 return;
7952 }
7953 #if defined(TARGET_PPC64)
7954 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000000000000LL);
7955 #else
7956 tcg_gen_andi_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000);
7957 #endif
7958 }
7959 static always_inline void gen_efdnabs (DisasContext *ctx)
7960 {
7961 if (unlikely(!ctx->spe_enabled)) {
7962 gen_exception(ctx, POWERPC_EXCP_APU);
7963 return;
7964 }
7965 #if defined(TARGET_PPC64)
7966 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL);
7967 #else
7968 tcg_gen_ori_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
7969 #endif
7970 }
7971 static always_inline void gen_efdneg (DisasContext *ctx)
7972 {
7973 if (unlikely(!ctx->spe_enabled)) {
7974 gen_exception(ctx, POWERPC_EXCP_APU);
7975 return;
7976 }
7977 #if defined(TARGET_PPC64)
7978 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL);
7979 #else
7980 tcg_gen_xori_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
7981 #endif
7982 }
7983
7984 /* Conversion */
7985 GEN_SPEFPUOP_CONV_64_32(efdcfui);
7986 GEN_SPEFPUOP_CONV_64_32(efdcfsi);
7987 GEN_SPEFPUOP_CONV_64_32(efdcfuf);
7988 GEN_SPEFPUOP_CONV_64_32(efdcfsf);
7989 GEN_SPEFPUOP_CONV_32_64(efdctui);
7990 GEN_SPEFPUOP_CONV_32_64(efdctsi);
7991 GEN_SPEFPUOP_CONV_32_64(efdctuf);
7992 GEN_SPEFPUOP_CONV_32_64(efdctsf);
7993 GEN_SPEFPUOP_CONV_32_64(efdctuiz);
7994 GEN_SPEFPUOP_CONV_32_64(efdctsiz);
7995 GEN_SPEFPUOP_CONV_64_32(efdcfs);
7996 GEN_SPEFPUOP_CONV_64_64(efdcfuid);
7997 GEN_SPEFPUOP_CONV_64_64(efdcfsid);
7998 GEN_SPEFPUOP_CONV_64_64(efdctuidz);
7999 GEN_SPEFPUOP_CONV_64_64(efdctsidz);
8000
8001 /* Comparison */
8002 GEN_SPEFPUOP_COMP_64(efdcmpgt);
8003 GEN_SPEFPUOP_COMP_64(efdcmplt);
8004 GEN_SPEFPUOP_COMP_64(efdcmpeq);
8005 GEN_SPEFPUOP_COMP_64(efdtstgt);
8006 GEN_SPEFPUOP_COMP_64(efdtstlt);
8007 GEN_SPEFPUOP_COMP_64(efdtsteq);
8008
8009 /* Opcodes definitions */
8010 GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, PPC_SPE_DOUBLE); //
8011 GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, PPC_SPE_DOUBLE); //
8012 GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, PPC_SPE_DOUBLE); //
8013 GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, PPC_SPE_DOUBLE); //
8014 GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, PPC_SPE_DOUBLE); //
8015 GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, PPC_SPE_DOUBLE); //
8016 GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, PPC_SPE_DOUBLE); //
8017 GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, PPC_SPE_DOUBLE); //
8018 GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, PPC_SPE_DOUBLE); //
8019 GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, PPC_SPE_DOUBLE); //
8020 GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, PPC_SPE_DOUBLE); //
8021 GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, PPC_SPE_DOUBLE); //
8022 GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, PPC_SPE_DOUBLE); //
8023 GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, PPC_SPE_DOUBLE); //
8024 GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, PPC_SPE_DOUBLE); //
8025 GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, PPC_SPE_DOUBLE); //
8026
8027 /* End opcode list */
8028 GEN_OPCODE_MARK(end);
8029
8030 #include "translate_init.c"
8031 #include "helper_regs.h"
8032
8033 /*****************************************************************************/
8034 /* Misc PowerPC helpers */
8035 void cpu_dump_state (CPUState *env, FILE *f,
8036 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
8037 int flags)
8038 {
8039 #define RGPL 4
8040 #define RFPL 4
8041
8042 int i;
8043
8044 cpu_fprintf(f, "NIP " ADDRX " LR " ADDRX " CTR " ADDRX " XER %08x\n",
8045 env->nip, env->lr, env->ctr, env->xer);
8046 cpu_fprintf(f, "MSR " ADDRX " HID0 " ADDRX " HF " ADDRX " idx %d\n",
8047 env->msr, env->spr[SPR_HID0], env->hflags, env->mmu_idx);
8048 #if !defined(NO_TIMER_DUMP)
8049 cpu_fprintf(f, "TB %08x %08x "
8050 #if !defined(CONFIG_USER_ONLY)
8051 "DECR %08x"
8052 #endif
8053 "\n",
8054 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
8055 #if !defined(CONFIG_USER_ONLY)
8056 , cpu_ppc_load_decr(env)
8057 #endif
8058 );
8059 #endif
8060 for (i = 0; i < 32; i++) {
8061 if ((i & (RGPL - 1)) == 0)
8062 cpu_fprintf(f, "GPR%02d", i);
8063 cpu_fprintf(f, " " REGX, ppc_dump_gpr(env, i));
8064 if ((i & (RGPL - 1)) == (RGPL - 1))
8065 cpu_fprintf(f, "\n");
8066 }
8067 cpu_fprintf(f, "CR ");
8068 for (i = 0; i < 8; i++)
8069 cpu_fprintf(f, "%01x", env->crf[i]);
8070 cpu_fprintf(f, " [");
8071 for (i = 0; i < 8; i++) {
8072 char a = '-';
8073 if (env->crf[i] & 0x08)
8074 a = 'L';
8075 else if (env->crf[i] & 0x04)
8076 a = 'G';
8077 else if (env->crf[i] & 0x02)
8078 a = 'E';
8079 cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
8080 }
8081 cpu_fprintf(f, " ] RES " ADDRX "\n", env->reserve);
8082 for (i = 0; i < 32; i++) {
8083 if ((i & (RFPL - 1)) == 0)
8084 cpu_fprintf(f, "FPR%02d", i);
8085 cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
8086 if ((i & (RFPL - 1)) == (RFPL - 1))
8087 cpu_fprintf(f, "\n");
8088 }
8089 cpu_fprintf(f, "FPSCR %08x\n", env->fpscr);
8090 #if !defined(CONFIG_USER_ONLY)
8091 cpu_fprintf(f, "SRR0 " ADDRX " SRR1 " ADDRX " SDR1 " ADDRX "\n",
8092 env->spr[SPR_SRR0], env->spr[SPR_SRR1], env->sdr1);
8093 #endif
8094
8095 #undef RGPL
8096 #undef RFPL
8097 }
8098
8099 void cpu_dump_statistics (CPUState *env, FILE*f,
8100 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
8101 int flags)
8102 {
8103 #if defined(DO_PPC_STATISTICS)
8104 opc_handler_t **t1, **t2, **t3, *handler;
8105 int op1, op2, op3;
8106
8107 t1 = env->opcodes;
8108 for (op1 = 0; op1 < 64; op1++) {
8109 handler = t1[op1];
8110 if (is_indirect_opcode(handler)) {
8111 t2 = ind_table(handler);
8112 for (op2 = 0; op2 < 32; op2++) {
8113 handler = t2[op2];
8114 if (is_indirect_opcode(handler)) {
8115 t3 = ind_table(handler);
8116 for (op3 = 0; op3 < 32; op3++) {
8117 handler = t3[op3];
8118 if (handler->count == 0)
8119 continue;
8120 cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: "
8121 "%016llx %lld\n",
8122 op1, op2, op3, op1, (op3 << 5) | op2,
8123 handler->oname,
8124 handler->count, handler->count);
8125 }
8126 } else {
8127 if (handler->count == 0)
8128 continue;
8129 cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: "
8130 "%016llx %lld\n",
8131 op1, op2, op1, op2, handler->oname,
8132 handler->count, handler->count);
8133 }
8134 }
8135 } else {
8136 if (handler->count == 0)
8137 continue;
8138 cpu_fprintf(f, "%02x (%02x ) %16s: %016llx %lld\n",
8139 op1, op1, handler->oname,
8140 handler->count, handler->count);
8141 }
8142 }
8143 #endif
8144 }
8145
8146 /*****************************************************************************/
8147 static always_inline void gen_intermediate_code_internal (CPUState *env,
8148 TranslationBlock *tb,
8149 int search_pc)
8150 {
8151 DisasContext ctx, *ctxp = &ctx;
8152 opc_handler_t **table, *handler;
8153 target_ulong pc_start;
8154 uint16_t *gen_opc_end;
8155 CPUBreakpoint *bp;
8156 int j, lj = -1;
8157 int num_insns;
8158 int max_insns;
8159
8160 pc_start = tb->pc;
8161 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
8162 ctx.nip = pc_start;
8163 ctx.tb = tb;
8164 ctx.exception = POWERPC_EXCP_NONE;
8165 ctx.spr_cb = env->spr_cb;
8166 ctx.mem_idx = env->mmu_idx;
8167 ctx.access_type = -1;
8168 ctx.le_mode = env->hflags & (1 << MSR_LE) ? 1 : 0;
8169 #if defined(TARGET_PPC64)
8170 ctx.sf_mode = msr_sf;
8171 #endif
8172 ctx.fpu_enabled = msr_fp;
8173 if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
8174 ctx.spe_enabled = msr_spe;
8175 else
8176 ctx.spe_enabled = 0;
8177 if ((env->flags & POWERPC_FLAG_VRE) && msr_vr)
8178 ctx.altivec_enabled = msr_vr;
8179 else
8180 ctx.altivec_enabled = 0;
8181 if ((env->flags & POWERPC_FLAG_SE) && msr_se)
8182 ctx.singlestep_enabled = CPU_SINGLE_STEP;
8183 else
8184 ctx.singlestep_enabled = 0;
8185 if ((env->flags & POWERPC_FLAG_BE) && msr_be)
8186 ctx.singlestep_enabled |= CPU_BRANCH_STEP;
8187 if (unlikely(env->singlestep_enabled))
8188 ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP;
8189 #if defined (DO_SINGLE_STEP) && 0
8190 /* Single step trace mode */
8191 msr_se = 1;
8192 #endif
8193 num_insns = 0;
8194 max_insns = tb->cflags & CF_COUNT_MASK;
8195 if (max_insns == 0)
8196 max_insns = CF_COUNT_MASK;
8197
8198 gen_icount_start();
8199 /* Set env in case of segfault during code fetch */
8200 while (ctx.exception == POWERPC_EXCP_NONE && gen_opc_ptr < gen_opc_end) {
8201 if (unlikely(!TAILQ_EMPTY(&env->breakpoints))) {
8202 TAILQ_FOREACH(bp, &env->breakpoints, entry) {
8203 if (bp->pc == ctx.nip) {
8204 gen_debug_exception(ctxp);
8205 break;
8206 }
8207 }
8208 }
8209 if (unlikely(search_pc)) {
8210 j = gen_opc_ptr - gen_opc_buf;
8211 if (lj < j) {
8212 lj++;
8213 while (lj < j)
8214 gen_opc_instr_start[lj++] = 0;
8215 }
8216 gen_opc_pc[lj] = ctx.nip;
8217 gen_opc_instr_start[lj] = 1;
8218 gen_opc_icount[lj] = num_insns;
8219 }
8220 LOG_DISAS("----------------\n");
8221 LOG_DISAS("nip=" ADDRX " super=%d ir=%d\n",
8222 ctx.nip, ctx.mem_idx, (int)msr_ir);
8223 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
8224 gen_io_start();
8225 if (unlikely(ctx.le_mode)) {
8226 ctx.opcode = bswap32(ldl_code(ctx.nip));
8227 } else {
8228 ctx.opcode = ldl_code(ctx.nip);
8229 }
8230 LOG_DISAS("translate opcode %08x (%02x %02x %02x) (%s)\n",
8231 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
8232 opc3(ctx.opcode), little_endian ? "little" : "big");
8233 ctx.nip += 4;
8234 table = env->opcodes;
8235 num_insns++;
8236 handler = table[opc1(ctx.opcode)];
8237 if (is_indirect_opcode(handler)) {
8238 table = ind_table(handler);
8239 handler = table[opc2(ctx.opcode)];
8240 if (is_indirect_opcode(handler)) {
8241 table = ind_table(handler);
8242 handler = table[opc3(ctx.opcode)];
8243 }
8244 }
8245 /* Is opcode *REALLY* valid ? */
8246 if (unlikely(handler->handler == &gen_invalid)) {
8247 if (qemu_log_enabled()) {
8248 qemu_log("invalid/unsupported opcode: "
8249 "%02x - %02x - %02x (%08x) " ADDRX " %d\n",
8250 opc1(ctx.opcode), opc2(ctx.opcode),
8251 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
8252 } else {
8253 printf("invalid/unsupported opcode: "
8254 "%02x - %02x - %02x (%08x) " ADDRX " %d\n",
8255 opc1(ctx.opcode), opc2(ctx.opcode),
8256 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
8257 }
8258 } else {
8259 if (unlikely((ctx.opcode & handler->inval) != 0)) {
8260 if (qemu_log_enabled()) {
8261 qemu_log("invalid bits: %08x for opcode: "
8262 "%02x - %02x - %02x (%08x) " ADDRX "\n",
8263 ctx.opcode & handler->inval, opc1(ctx.opcode),
8264 opc2(ctx.opcode), opc3(ctx.opcode),
8265 ctx.opcode, ctx.nip - 4);
8266 } else {
8267 printf("invalid bits: %08x for opcode: "
8268 "%02x - %02x - %02x (%08x) " ADDRX "\n",
8269 ctx.opcode & handler->inval, opc1(ctx.opcode),
8270 opc2(ctx.opcode), opc3(ctx.opcode),
8271 ctx.opcode, ctx.nip - 4);
8272 }
8273 gen_inval_exception(ctxp, POWERPC_EXCP_INVAL_INVAL);
8274 break;
8275 }
8276 }
8277 (*(handler->handler))(&ctx);
8278 #if defined(DO_PPC_STATISTICS)
8279 handler->count++;
8280 #endif
8281 /* Check trace mode exceptions */
8282 if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP &&
8283 (ctx.nip <= 0x100 || ctx.nip > 0xF00) &&
8284 ctx.exception != POWERPC_SYSCALL &&
8285 ctx.exception != POWERPC_EXCP_TRAP &&
8286 ctx.exception != POWERPC_EXCP_BRANCH)) {
8287 gen_exception(ctxp, POWERPC_EXCP_TRACE);
8288 } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) ||
8289 (env->singlestep_enabled) ||
8290 singlestep ||
8291 num_insns >= max_insns)) {
8292 /* if we reach a page boundary or are single stepping, stop
8293 * generation
8294 */
8295 break;
8296 }
8297 }
8298 if (tb->cflags & CF_LAST_IO)
8299 gen_io_end();
8300 if (ctx.exception == POWERPC_EXCP_NONE) {
8301 gen_goto_tb(&ctx, 0, ctx.nip);
8302 } else if (ctx.exception != POWERPC_EXCP_BRANCH) {
8303 if (unlikely(env->singlestep_enabled)) {
8304 gen_debug_exception(ctxp);
8305 }
8306 /* Generate the return instruction */
8307 tcg_gen_exit_tb(0);
8308 }
8309 gen_icount_end(tb, num_insns);
8310 *gen_opc_ptr = INDEX_op_end;
8311 if (unlikely(search_pc)) {
8312 j = gen_opc_ptr - gen_opc_buf;
8313 lj++;
8314 while (lj <= j)
8315 gen_opc_instr_start[lj++] = 0;
8316 } else {
8317 tb->size = ctx.nip - pc_start;
8318 tb->icount = num_insns;
8319 }
8320 #if defined(DEBUG_DISAS)
8321 qemu_log_mask(CPU_LOG_TB_CPU, "---------------- excp: %04x\n", ctx.exception);
8322 log_cpu_state_mask(CPU_LOG_TB_CPU, env, 0);
8323 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
8324 int flags;
8325 flags = env->bfd_mach;
8326 flags |= ctx.le_mode << 16;
8327 qemu_log("IN: %s\n", lookup_symbol(pc_start));
8328 log_target_disas(pc_start, ctx.nip - pc_start, flags);
8329 qemu_log("\n");
8330 }
8331 #endif
8332 }
8333
8334 void gen_intermediate_code (CPUState *env, struct TranslationBlock *tb)
8335 {
8336 gen_intermediate_code_internal(env, tb, 0);
8337 }
8338
8339 void gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb)
8340 {
8341 gen_intermediate_code_internal(env, tb, 1);
8342 }
8343
8344 void gen_pc_load(CPUState *env, TranslationBlock *tb,
8345 unsigned long searched_pc, int pc_pos, void *puc)
8346 {
8347 env->nip = gen_opc_pc[pc_pos];
8348 }
Patches shipped by Fedora