2 * PXA270-based Intel Mainstone platforms.
4 * Copyright (c) 2007 by Armin Kuster <akuster@kama-aina.net> or
7 * Code based on spitz platform by Andrzej Zaborowski <balrog@zabor.org>
9 * This code is licensed under the GNU GPL v2.
17 #include "mainstone.h"
21 static struct keymap map
[0xE0] = {
22 [0 ... 0xDF] = { -1, -1 },
23 [0x1e] = {0,0}, /* a */
24 [0x30] = {0,1}, /* b */
25 [0x2e] = {0,2}, /* c */
26 [0x20] = {0,3}, /* d */
27 [0x12] = {0,4}, /* e */
28 [0x21] = {0,5}, /* f */
29 [0x22] = {1,0}, /* g */
30 [0x23] = {1,1}, /* h */
31 [0x17] = {1,2}, /* i */
32 [0x24] = {1,3}, /* j */
33 [0x25] = {1,4}, /* k */
34 [0x26] = {1,5}, /* l */
35 [0x32] = {2,0}, /* m */
36 [0x31] = {2,1}, /* n */
37 [0x18] = {2,2}, /* o */
38 [0x19] = {2,3}, /* p */
39 [0x10] = {2,4}, /* q */
40 [0x13] = {2,5}, /* r */
41 [0x1f] = {3,0}, /* s */
42 [0x14] = {3,1}, /* t */
43 [0x16] = {3,2}, /* u */
44 [0x2f] = {3,3}, /* v */
45 [0x11] = {3,4}, /* w */
46 [0x2d] = {3,5}, /* x */
47 [0x15] = {4,2}, /* y */
48 [0x2c] = {4,3}, /* z */
49 [0xc7] = {5,0}, /* Home */
50 [0x2a] = {5,1}, /* shift */
51 [0x39] = {5,2}, /* space */
52 [0x39] = {5,3}, /* space */
53 [0x1c] = {5,5}, /* enter */
54 [0xc8] = {6,0}, /* up */
55 [0xd0] = {6,1}, /* down */
56 [0xcb] = {6,2}, /* left */
57 [0xcd] = {6,3}, /* right */
60 enum mainstone_model_e
{ mainstone
};
62 #define MAINSTONE_RAM 0x04000000
63 #define MAINSTONE_ROM 0x00800000
64 #define MAINSTONE_FLASH 0x02000000
66 static struct arm_boot_info mainstone_binfo
= {
67 .loader_start
= PXA2XX_SDRAM_BASE
,
68 .ram_size
= 0x04000000,
71 static void mainstone_common_init(ram_addr_t ram_size
, int vga_ram_size
,
72 const char *kernel_filename
,
73 const char *kernel_cmdline
, const char *initrd_filename
,
74 const char *cpu_model
, enum mainstone_model_e model
, int arm_id
)
76 uint32_t sector_len
= 256 * 1024;
77 target_phys_addr_t mainstone_flash_base
[] = { MST_FLASH_0
, MST_FLASH_1
};
78 struct pxa2xx_state_s
*cpu
;
83 cpu_model
= "pxa270-c5";
85 /* Setup CPU & memory */
86 if (ram_size
< MAINSTONE_RAM
+ MAINSTONE_ROM
+ 2 * MAINSTONE_FLASH
+
87 PXA2XX_INTERNAL_SIZE
) {
88 fprintf(stderr
, "This platform requires %i bytes of memory\n",
89 MAINSTONE_RAM
+ MAINSTONE_ROM
+ 2 * MAINSTONE_FLASH
+
90 PXA2XX_INTERNAL_SIZE
);
94 cpu
= pxa270_init(mainstone_binfo
.ram_size
, cpu_model
);
95 cpu_register_physical_memory(0, MAINSTONE_ROM
,
96 qemu_ram_alloc(MAINSTONE_ROM
) | IO_MEM_ROM
);
98 /* Setup initial (reset) machine state */
99 cpu
->env
->regs
[15] = mainstone_binfo
.loader_start
;
101 /* There are two 32MiB flash devices on the board */
102 for (i
= 0; i
< 2; i
++) {
103 index
= drive_get_index(IF_PFLASH
, 0, i
);
105 fprintf(stderr
, "Two flash images must be given with the "
106 "'pflash' parameter\n");
110 if (!pflash_cfi01_register(mainstone_flash_base
[i
],
111 qemu_ram_alloc(MAINSTONE_FLASH
),
112 drives_table
[index
].bdrv
, sector_len
,
113 MAINSTONE_FLASH
/ sector_len
, 4, 0, 0, 0, 0)) {
114 fprintf(stderr
, "qemu: Error registering flash memory.\n");
119 mst_irq
= mst_irq_init(cpu
, MST_FPGA_PHYS
, PXA2XX_PIC_GPIO_0
);
122 printf("map addr %p\n", &map
);
123 pxa27x_register_keypad(cpu
->kp
, map
, 0xe0);
126 pxa2xx_mmci_handlers(cpu
->mmc
, NULL
, mst_irq
[MMC_IRQ
]);
128 smc91c111_init(&nd_table
[0], MST_ETH_PHYS
, mst_irq
[ETHERNET_IRQ
]);
130 mainstone_binfo
.kernel_filename
= kernel_filename
;
131 mainstone_binfo
.kernel_cmdline
= kernel_cmdline
;
132 mainstone_binfo
.initrd_filename
= initrd_filename
;
133 mainstone_binfo
.board_id
= arm_id
;
134 arm_load_kernel(cpu
->env
, &mainstone_binfo
);
137 static void mainstone_init(ram_addr_t ram_size
, int vga_ram_size
,
138 const char *boot_device
,
139 const char *kernel_filename
, const char *kernel_cmdline
,
140 const char *initrd_filename
, const char *cpu_model
)
142 mainstone_common_init(ram_size
, vga_ram_size
, kernel_filename
,
143 kernel_cmdline
, initrd_filename
, cpu_model
, mainstone
, 0x196);
146 QEMUMachine mainstone2_machine
= {
148 .desc
= "Mainstone II (PXA27x)",
149 .init
= mainstone_init
,
150 .ram_require
= (MAINSTONE_RAM
+ MAINSTONE_ROM
+ 2 * MAINSTONE_FLASH
+
151 PXA2XX_INTERNAL_SIZE
) | RAMSIZE_FIXED
,