exec-all.h

   1 /*
   2  * internal execution defines for qemu
   3  *
   4  *  Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  19  */
  20
  21 /* allow to see translation results - the slowdown should be negligible, so we leave it */
  22 #define DEBUG_DISAS
  23
  24 /* is_jmp field values */
  25 #define DISAS_NEXT    0 /* next instruction can be analyzed */
  26 #define DISAS_JUMP    1 /* only pc was modified dynamically */
  27 #define DISAS_UPDATE  2 /* cpu state was modified dynamically */
  28 #define DISAS_TB_JUMP 3 /* only pc was modified statically */
  29
  30 typedef struct TranslationBlock TranslationBlock;
  31
  32 /* XXX: make safe guess about sizes */
  33 #define MAX_OP_PER_INSTR 64
  34 /* A Call op needs up to 6 + 2N parameters (N = number of arguments).  */
  35 #define MAX_OPC_PARAM 10
  36 #define OPC_BUF_SIZE 512
  37 #define OPC_MAX_SIZE (OPC_BUF_SIZE - MAX_OP_PER_INSTR)
  38
  39 /* Maximum size a TCG op can expand to.  This is complicated because a
  40    single op may require several host instructions and regirster reloads.
  41    For now take a wild guess at 128 bytes, which should allow at least
  42    a couple of fixup instructions per argument.  */
  43 #define TCG_MAX_OP_SIZE 128
  44
  45 #define OPPARAM_BUF_SIZE (OPC_BUF_SIZE * MAX_OPC_PARAM)
  46
  47 extern target_ulong gen_opc_pc[OPC_BUF_SIZE];
  48 extern target_ulong gen_opc_npc[OPC_BUF_SIZE];
  49 extern uint8_t gen_opc_cc_op[OPC_BUF_SIZE];
  50 extern uint8_t gen_opc_instr_start[OPC_BUF_SIZE];
  51 extern uint16_t gen_opc_icount[OPC_BUF_SIZE];
  52 extern target_ulong gen_opc_jump_pc[2];
  53 extern uint32_t gen_opc_hflags[OPC_BUF_SIZE];
  54
  55 typedef void (GenOpFunc)(void);
  56 typedef void (GenOpFunc1)(long);
  57 typedef void (GenOpFunc2)(long, long);
  58 typedef void (GenOpFunc3)(long, long, long);
  59
  60 extern FILE *logfile;
  61 extern int loglevel;
  62
  63 void gen_intermediate_code(CPUState *env, struct TranslationBlock *tb);
  64 void gen_intermediate_code_pc(CPUState *env, struct TranslationBlock *tb);
  65 void gen_pc_load(CPUState *env, struct TranslationBlock *tb,
  66                  unsigned long searched_pc, int pc_pos, void *puc);
  67
  68 unsigned long code_gen_max_block_size(void);
  69 void cpu_gen_init(void);
  70 int cpu_gen_code(CPUState *env, struct TranslationBlock *tb,
  71                  int *gen_code_size_ptr);
  72 int cpu_restore_state(struct TranslationBlock *tb,
  73                       CPUState *env, unsigned long searched_pc,
  74                       void *puc);
  75 int cpu_restore_state_copy(struct TranslationBlock *tb,
  76                            CPUState *env, unsigned long searched_pc,
  77                            void *puc);
  78 void cpu_resume_from_signal(CPUState *env1, void *puc);
  79 void cpu_io_recompile(CPUState *env, void *retaddr);
  80 TranslationBlock *tb_gen_code(CPUState *env,
  81                               target_ulong pc, target_ulong cs_base, int flags,
  82                               int cflags);
  83 void cpu_exec_init(CPUState *env);
  84 int page_unprotect(target_ulong address, unsigned long pc, void *puc);
  85 void tb_invalidate_phys_page_range(target_phys_addr_t start, target_phys_addr_t end,
  86                                    int is_cpu_write_access);
  87 void tb_invalidate_page_range(target_ulong start, target_ulong end);
  88 void tlb_flush_page(CPUState *env, target_ulong addr);
  89 void tlb_flush(CPUState *env, int flush_global);
  90 int tlb_set_page_exec(CPUState *env, target_ulong vaddr,
  91                       target_phys_addr_t paddr, int prot,
  92                       int mmu_idx, int is_softmmu);
  93 static inline int tlb_set_page(CPUState *env1, target_ulong vaddr,
  94                                target_phys_addr_t paddr, int prot,
  95                                int mmu_idx, int is_softmmu)
  96 {
  97     if (prot & PAGE_READ)
  98         prot |= PAGE_EXEC;
  99     return tlb_set_page_exec(env1, vaddr, paddr, prot, mmu_idx, is_softmmu);
 100 }
 101
 102 #define CODE_GEN_ALIGN           16 /* must be >= of the size of a icache line */
 103
 104 #define CODE_GEN_PHYS_HASH_BITS     15
 105 #define CODE_GEN_PHYS_HASH_SIZE     (1 << CODE_GEN_PHYS_HASH_BITS)
 106
 107 #define MIN_CODE_GEN_BUFFER_SIZE     (1024 * 1024)
 108
 109 /* estimated block size for TB allocation */
 110 /* XXX: use a per code average code fragment size and modulate it
 111    according to the host CPU */
 112 #if defined(CONFIG_SOFTMMU)
 113 #define CODE_GEN_AVG_BLOCK_SIZE 128
 114 #else
 115 #define CODE_GEN_AVG_BLOCK_SIZE 64
 116 #endif
 117
 118 #if defined(__powerpc__) || defined(__x86_64__) || defined(__arm__)
 119 #define USE_DIRECT_JUMP
 120 #endif
 121 #if defined(__i386__) && !defined(_WIN32)
 122 #define USE_DIRECT_JUMP
 123 #endif
 124
 125 struct TranslationBlock {
 126     target_ulong pc;   /* simulated PC corresponding to this block (EIP + CS base) */
 127     target_ulong cs_base; /* CS base for this block */
 128     uint64_t flags; /* flags defining in which context the code was generated */
 129     uint16_t size;      /* size of target code for this block (1 <=
 130                            size <= TARGET_PAGE_SIZE) */
 131     uint16_t cflags;    /* compile flags */
 132 #define CF_COUNT_MASK  0x7fff
 133 #define CF_LAST_IO     0x8000 /* Last insn may be an IO access.  */
 134
 135     uint8_t *tc_ptr;    /* pointer to the translated code */
 136     /* next matching tb for physical address. */
 137     struct TranslationBlock *phys_hash_next;
 138     /* first and second physical page containing code. The lower bit
 139        of the pointer tells the index in page_next[] */
 140     struct TranslationBlock *page_next[2];
 141     target_ulong page_addr[2];
 142
 143     /* the following data are used to directly call another TB from
 144        the code of this one. */
 145     uint16_t tb_next_offset[2]; /* offset of original jump target */
 146 #ifdef USE_DIRECT_JUMP
 147     uint16_t tb_jmp_offset[4]; /* offset of jump instruction */
 148 #else
 149     unsigned long tb_next[2]; /* address of jump generated code */
 150 #endif
 151     /* list of TBs jumping to this one. This is a circular list using
 152        the two least significant bits of the pointers to tell what is
 153        the next pointer: 0 = jmp_next[0], 1 = jmp_next[1], 2 =
 154        jmp_first */
 155     struct TranslationBlock *jmp_next[2];
 156     struct TranslationBlock *jmp_first;
 157     uint32_t icount;
 158 };
 159
 160 static inline unsigned int tb_jmp_cache_hash_page(target_ulong pc)
 161 {
 162     target_ulong tmp;
 163     tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS));
 164     return (tmp >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)) & TB_JMP_PAGE_MASK;
 165 }
 166
 167 static inline unsigned int tb_jmp_cache_hash_func(target_ulong pc)
 168 {
 169     target_ulong tmp;
 170     tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS));
 171     return (((tmp >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)) & TB_JMP_PAGE_MASK)
 172             | (tmp & TB_JMP_ADDR_MASK));
 173 }
 174
 175 static inline unsigned int tb_phys_hash_func(unsigned long pc)
 176 {
 177     return pc & (CODE_GEN_PHYS_HASH_SIZE - 1);
 178 }
 179
 180 TranslationBlock *tb_alloc(target_ulong pc);
 181 void tb_free(TranslationBlock *tb);
 182 void tb_flush(CPUState *env);
 183 void tb_link_phys(TranslationBlock *tb,
 184                   target_ulong phys_pc, target_ulong phys_page2);
 185 void tb_phys_invalidate(TranslationBlock *tb, target_ulong page_addr);
 186
 187 extern TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE];
 188 extern uint8_t *code_gen_ptr;
 189 extern int code_gen_max_blocks;
 190
 191 #if defined(USE_DIRECT_JUMP)
 192
 193 #if defined(__powerpc__)
 194 #if defined(__powerpc64__)
 195 extern void ppc_tb_set_jmp_target(unsigned long jmp_addr, unsigned long addr);
 196 #define tb_set_jmp_target1 ppc_tb_set_jmp_target
 197 #else
 198 static inline void flush_icache_range(unsigned long start, unsigned long stop);
 199 static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr)
 200 {
 201     /* This must be in concord with INDEX_op_goto_tb inside tcg_out_op */
 202     uint32_t *ptr;
 203     long disp = addr - jmp_addr;
 204     unsigned long patch_size;
 205
 206     ptr = (uint32_t *)jmp_addr;
 207
 208     if ((disp << 6) >> 6 != disp) {
 209         ptr[0] = 0x3c000000 | (addr >> 16);    /* lis 0,addr@ha */
 210         ptr[1] = 0x60000000 | (addr & 0xffff); /* la  0,addr@l(0) */
 211         ptr[2] = 0x7c0903a6;                   /* mtctr 0 */
 212         ptr[3] = 0x4e800420;                   /* brctr */
 213         patch_size = 16;
 214     } else {
 215         /* patch the branch destination */
 216         if (disp != 16) {
 217             *ptr = 0x48000000 | (disp & 0x03fffffc); /* b disp */
 218             patch_size = 4;
 219         } else {
 220             ptr[0] = 0x60000000; /* nop */
 221             ptr[1] = 0x60000000;
 222             ptr[2] = 0x60000000;
 223             ptr[3] = 0x60000000;
 224             patch_size = 16;
 225         }
 226     }
 227     /* flush icache */
 228     flush_icache_range(jmp_addr, jmp_addr + patch_size);
 229 }
 230 #endif
 231 #elif defined(__i386__) || defined(__x86_64__)
 232 static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr)
 233 {
 234     /* patch the branch destination */
 235     *(uint32_t *)jmp_addr = addr - (jmp_addr + 4);
 236     /* no need to flush icache explicitly */
 237 }
 238 #elif defined(__arm__)
 239 static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr)
 240 {
 241     register unsigned long _beg __asm ("a1");
 242     register unsigned long _end __asm ("a2");
 243     register unsigned long _flg __asm ("a3");
 244
 245     /* we could use a ldr pc, [pc, #-4] kind of branch and avoid the flush */
 246     *(uint32_t *)jmp_addr |= ((addr - (jmp_addr + 8)) >> 2) & 0xffffff;
 247
 248     /* flush icache */
 249     _beg = jmp_addr;
 250     _end = jmp_addr + 4;
 251     _flg = 0;
 252     __asm __volatile__ ("swi 0x9f0002" : : "r" (_beg), "r" (_end), "r" (_flg));
 253 }
 254 #endif
 255
 256 static inline void tb_set_jmp_target(TranslationBlock *tb,
 257                                      int n, unsigned long addr)
 258 {
 259     unsigned long offset;
 260
 261     offset = tb->tb_jmp_offset[n];
 262     tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr);
 263     offset = tb->tb_jmp_offset[n + 2];
 264     if (offset != 0xffff)
 265         tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr);
 266 }
 267
 268 #else
 269
 270 /* set the jump target */
 271 static inline void tb_set_jmp_target(TranslationBlock *tb,
 272                                      int n, unsigned long addr)
 273 {
 274     tb->tb_next[n] = addr;
 275 }
 276
 277 #endif
 278
 279 static inline void tb_add_jump(TranslationBlock *tb, int n,
 280                                TranslationBlock *tb_next)
 281 {
 282     /* NOTE: this test is only needed for thread safety */
 283     if (!tb->jmp_next[n]) {
 284         /* patch the native jump address */
 285         tb_set_jmp_target(tb, n, (unsigned long)tb_next->tc_ptr);
 286
 287         /* add in TB jmp circular list */
 288         tb->jmp_next[n] = tb_next->jmp_first;
 289         tb_next->jmp_first = (TranslationBlock *)((long)(tb) | (n));
 290     }
 291 }
 292
 293 TranslationBlock *tb_find_pc(unsigned long pc_ptr);
 294
 295 #ifndef offsetof
 296 #define offsetof(type, field) ((size_t) &((type *)0)->field)
 297 #endif
 298
 299 #if defined(_WIN32)
 300 #define ASM_DATA_SECTION ".section \".data\"\n"
 301 #define ASM_PREVIOUS_SECTION ".section .text\n"
 302 #elif defined(__APPLE__)
 303 #define ASM_DATA_SECTION ".data\n"
 304 #define ASM_PREVIOUS_SECTION ".text\n"
 305 #else
 306 #define ASM_DATA_SECTION ".section \".data\"\n"
 307 #define ASM_PREVIOUS_SECTION ".previous\n"
 308 #endif
 309
 310 #define ASM_OP_LABEL_NAME(n, opname) \
 311     ASM_NAME(__op_label) #n "." ASM_NAME(opname)
 312
 313 extern CPUWriteMemoryFunc *io_mem_write[IO_MEM_NB_ENTRIES][4];
 314 extern CPUReadMemoryFunc *io_mem_read[IO_MEM_NB_ENTRIES][4];
 315 extern void *io_mem_opaque[IO_MEM_NB_ENTRIES];
 316
 317 #include "qemu-lock.h"
 318
 319 extern spinlock_t tb_lock;
 320
 321 extern int tb_invalidated_flag;
 322
 323 #if !defined(CONFIG_USER_ONLY)
 324
 325 void tlb_fill(target_ulong addr, int is_write, int mmu_idx,
 326               void *retaddr);
 327
 328 #define ACCESS_TYPE (NB_MMU_MODES + 1)
 329 #define MEMSUFFIX _code
 330 #define env cpu_single_env
 331
 332 #define DATA_SIZE 1
 333 #include "softmmu_header.h"
 334
 335 #define DATA_SIZE 2
 336 #include "softmmu_header.h"
 337
 338 #define DATA_SIZE 4
 339 #include "softmmu_header.h"
 340
 341 #define DATA_SIZE 8
 342 #include "softmmu_header.h"
 343
 344 #undef ACCESS_TYPE
 345 #undef MEMSUFFIX
 346 #undef env
 347
 348 #endif
 349
 350 #if defined(CONFIG_USER_ONLY)
 351 static inline target_ulong get_phys_addr_code(CPUState *env1, target_ulong addr)
 352 {
 353     return addr;
 354 }
 355 #else
 356 /* NOTE: this function can trigger an exception */
 357 /* NOTE2: the returned address is not exactly the physical address: it
 358    is the offset relative to phys_ram_base */
 359 static inline target_ulong get_phys_addr_code(CPUState *env1, target_ulong addr)
 360 {
 361     int mmu_idx, page_index, pd;
 362
 363     page_index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
 364     mmu_idx = cpu_mmu_index(env1);
 365     if (unlikely(env1->tlb_table[mmu_idx][page_index].addr_code !=
 366                  (addr & TARGET_PAGE_MASK))) {
 367         ldub_code(addr);
 368     }
 369     pd = env1->tlb_table[mmu_idx][page_index].addr_code & ~TARGET_PAGE_MASK;
 370     if (pd > IO_MEM_ROM && !(pd & IO_MEM_ROMD)) {
 371 #if defined(TARGET_SPARC) || defined(TARGET_MIPS)
 372         do_unassigned_access(addr, 0, 1, 0);
 373 #else
 374         cpu_abort(env1, "Trying to execute code outside RAM or ROM at 0x" TARGET_FMT_lx "\n", addr);
 375 #endif
 376     }
 377     return addr + env1->tlb_table[mmu_idx][page_index].addend - (unsigned long)phys_ram_base;
 378 }
 379
 380 /* Deterministic execution requires that IO only be performed on the last
 381    instruction of a TB so that interrupts take effect immediately.  */
 382 static inline int can_do_io(CPUState *env)
 383 {
 384     if (!use_icount)
 385         return 1;
 386
 387     /* If not executing code then assume we are ok.  */
 388     if (!env->current_tb)
 389         return 1;
 390
 391     return env->can_do_io != 0;
 392 }
 393 #endif
 394
 395 #ifdef USE_KQEMU
 396 #define KQEMU_MODIFY_PAGE_MASK (0xff & ~(VGA_DIRTY_FLAG | CODE_DIRTY_FLAG))
 397
 398 #define MSR_QPI_COMMBASE 0xfabe0010
 399
 400 int kqemu_init(CPUState *env);
 401 int kqemu_cpu_exec(CPUState *env);
 402 void kqemu_flush_page(CPUState *env, target_ulong addr);
 403 void kqemu_flush(CPUState *env, int global);
 404 void kqemu_set_notdirty(CPUState *env, ram_addr_t ram_addr);
 405 void kqemu_modify_page(CPUState *env, ram_addr_t ram_addr);
 406 void kqemu_set_phys_mem(uint64_t start_addr, ram_addr_t size,
 407                         ram_addr_t phys_offset);
 408 void kqemu_cpu_interrupt(CPUState *env);
 409 void kqemu_record_dump(void);
 410
 411 extern uint32_t kqemu_comm_base;
 412
 413 static inline int kqemu_is_ok(CPUState *env)
 414 {
 415     return(env->kqemu_enabled &&
 416            (env->cr[0] & CR0_PE_MASK) &&
 417            !(env->hflags & HF_INHIBIT_IRQ_MASK) &&
 418            (env->eflags & IF_MASK) &&
 419            !(env->eflags & VM_MASK) &&
 420            (env->kqemu_enabled == 2 ||
 421             ((env->hflags & HF_CPL_MASK) == 3 &&
 422              (env->eflags & IOPL_MASK) != IOPL_MASK)));
 423 }
 424
 425 #endif