target-sparc/cpu.h

   1 #ifndef CPU_SPARC_H
   2 #define CPU_SPARC_H
   3
   4 #include "config.h"
   5
   6 #if !defined(TARGET_SPARC64)
   7 #define TARGET_LONG_BITS 32
   8 #define TARGET_FPREGS 32
   9 #define TARGET_PAGE_BITS 12 /* 4k */
  10 #else
  11 #define TARGET_LONG_BITS 64
  12 #define TARGET_FPREGS 64
  13 #define TARGET_PAGE_BITS 13 /* 8k */
  14 #endif
  15
  16 #define TARGET_PHYS_ADDR_BITS 64
  17
  18 #include "cpu-defs.h"
  19
  20 #include "softfloat.h"
  21
  22 #define TARGET_HAS_ICE 1
  23
  24 #if !defined(TARGET_SPARC64)
  25 #define ELF_MACHINE     EM_SPARC
  26 #else
  27 #define ELF_MACHINE     EM_SPARCV9
  28 #endif
  29
  30 /*#define EXCP_INTERRUPT 0x100*/
  31
  32 /* trap definitions */
  33 #ifndef TARGET_SPARC64
  34 #define TT_TFAULT   0x01
  35 #define TT_ILL_INSN 0x02
  36 #define TT_PRIV_INSN 0x03
  37 #define TT_NFPU_INSN 0x04
  38 #define TT_WIN_OVF  0x05
  39 #define TT_WIN_UNF  0x06
  40 #define TT_UNALIGNED 0x07
  41 #define TT_FP_EXCP  0x08
  42 #define TT_DFAULT   0x09
  43 #define TT_TOVF     0x0a
  44 #define TT_EXTINT   0x10
  45 #define TT_CODE_ACCESS 0x21
  46 #define TT_UNIMP_FLUSH 0x25
  47 #define TT_DATA_ACCESS 0x29
  48 #define TT_DIV_ZERO 0x2a
  49 #define TT_NCP_INSN 0x24
  50 #define TT_TRAP     0x80
  51 #else
  52 #define TT_TFAULT   0x08
  53 #define TT_CODE_ACCESS 0x0a
  54 #define TT_ILL_INSN 0x10
  55 #define TT_UNIMP_FLUSH TT_ILL_INSN
  56 #define TT_PRIV_INSN 0x11
  57 #define TT_NFPU_INSN 0x20
  58 #define TT_FP_EXCP  0x21
  59 #define TT_TOVF     0x23
  60 #define TT_CLRWIN   0x24
  61 #define TT_DIV_ZERO 0x28
  62 #define TT_DFAULT   0x30
  63 #define TT_DATA_ACCESS 0x32
  64 #define TT_UNALIGNED 0x34
  65 #define TT_PRIV_ACT 0x37
  66 #define TT_EXTINT   0x40
  67 #define TT_IVEC     0x60
  68 #define TT_TMISS    0x64
  69 #define TT_DMISS    0x68
  70 #define TT_DPROT    0x6c
  71 #define TT_SPILL    0x80
  72 #define TT_FILL     0xc0
  73 #define TT_WOTHER   0x10
  74 #define TT_TRAP     0x100
  75 #endif
  76
  77 #define PSR_NEG_SHIFT 23
  78 #define PSR_NEG   (1 << PSR_NEG_SHIFT)
  79 #define PSR_ZERO_SHIFT 22
  80 #define PSR_ZERO  (1 << PSR_ZERO_SHIFT)
  81 #define PSR_OVF_SHIFT 21
  82 #define PSR_OVF   (1 << PSR_OVF_SHIFT)
  83 #define PSR_CARRY_SHIFT 20
  84 #define PSR_CARRY (1 << PSR_CARRY_SHIFT)
  85 #define PSR_ICC   (PSR_NEG|PSR_ZERO|PSR_OVF|PSR_CARRY)
  86 #define PSR_EF    (1<<12)
  87 #define PSR_PIL   0xf00
  88 #define PSR_S     (1<<7)
  89 #define PSR_PS    (1<<6)
  90 #define PSR_ET    (1<<5)
  91 #define PSR_CWP   0x1f
  92
  93 /* Trap base register */
  94 #define TBR_BASE_MASK 0xfffff000
  95
  96 #if defined(TARGET_SPARC64)
  97 #define PS_IG    (1<<11)
  98 #define PS_MG    (1<<10)
  99 #define PS_RMO   (1<<7)
 100 #define PS_RED   (1<<5)
 101 #define PS_PEF   (1<<4)
 102 #define PS_AM    (1<<3)
 103 #define PS_PRIV  (1<<2)
 104 #define PS_IE    (1<<1)
 105 #define PS_AG    (1<<0)
 106
 107 #define FPRS_FEF (1<<2)
 108
 109 #define HS_PRIV  (1<<2)
 110 #endif
 111
 112 /* Fcc */
 113 #define FSR_RD1        (1<<31)
 114 #define FSR_RD0        (1<<30)
 115 #define FSR_RD_MASK    (FSR_RD1 | FSR_RD0)
 116 #define FSR_RD_NEAREST 0
 117 #define FSR_RD_ZERO    FSR_RD0
 118 #define FSR_RD_POS     FSR_RD1
 119 #define FSR_RD_NEG     (FSR_RD1 | FSR_RD0)
 120
 121 #define FSR_NVM   (1<<27)
 122 #define FSR_OFM   (1<<26)
 123 #define FSR_UFM   (1<<25)
 124 #define FSR_DZM   (1<<24)
 125 #define FSR_NXM   (1<<23)
 126 #define FSR_TEM_MASK (FSR_NVM | FSR_OFM | FSR_UFM | FSR_DZM | FSR_NXM)
 127
 128 #define FSR_NVA   (1<<9)
 129 #define FSR_OFA   (1<<8)
 130 #define FSR_UFA   (1<<7)
 131 #define FSR_DZA   (1<<6)
 132 #define FSR_NXA   (1<<5)
 133 #define FSR_AEXC_MASK (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA)
 134
 135 #define FSR_NVC   (1<<4)
 136 #define FSR_OFC   (1<<3)
 137 #define FSR_UFC   (1<<2)
 138 #define FSR_DZC   (1<<1)
 139 #define FSR_NXC   (1<<0)
 140 #define FSR_CEXC_MASK (FSR_NVC | FSR_OFC | FSR_UFC | FSR_DZC | FSR_NXC)
 141
 142 #define FSR_FTT2   (1<<16)
 143 #define FSR_FTT1   (1<<15)
 144 #define FSR_FTT0   (1<<14)
 145 #define FSR_FTT_MASK (FSR_FTT2 | FSR_FTT1 | FSR_FTT0)
 146 #define FSR_FTT_IEEE_EXCP (1 << 14)
 147 #define FSR_FTT_UNIMPFPOP (3 << 14)
 148 #define FSR_FTT_SEQ_ERROR (4 << 14)
 149 #define FSR_FTT_INVAL_FPR (6 << 14)
 150
 151 #define FSR_FCC1_SHIFT 11
 152 #define FSR_FCC1  (1 << FSR_FCC1_SHIFT)
 153 #define FSR_FCC0_SHIFT 10
 154 #define FSR_FCC0  (1 << FSR_FCC0_SHIFT)
 155
 156 /* MMU */
 157 #define MMU_E     (1<<0)
 158 #define MMU_NF    (1<<1)
 159
 160 #define PTE_ENTRYTYPE_MASK 3
 161 #define PTE_ACCESS_MASK    0x1c
 162 #define PTE_ACCESS_SHIFT   2
 163 #define PTE_PPN_SHIFT      7
 164 #define PTE_ADDR_MASK      0xffffff00
 165
 166 #define PG_ACCESSED_BIT 5
 167 #define PG_MODIFIED_BIT 6
 168 #define PG_CACHE_BIT    7
 169
 170 #define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT)
 171 #define PG_MODIFIED_MASK (1 << PG_MODIFIED_BIT)
 172 #define PG_CACHE_MASK    (1 << PG_CACHE_BIT)
 173
 174 /* 3 <= NWINDOWS <= 32. */
 175 #define MIN_NWINDOWS 3
 176 #define MAX_NWINDOWS 32
 177
 178 #if !defined(TARGET_SPARC64)
 179 #define NB_MMU_MODES 2
 180 #else
 181 #define NB_MMU_MODES 3
 182 typedef struct trap_state {
 183     uint64_t tpc;
 184     uint64_t tnpc;
 185     uint64_t tstate;
 186     uint32_t tt;
 187 } trap_state;
 188 #endif
 189
 190 typedef struct CPUSPARCState {
 191     target_ulong gregs[8]; /* general registers */
 192     target_ulong *regwptr; /* pointer to current register window */
 193     target_ulong pc;       /* program counter */
 194     target_ulong npc;      /* next program counter */
 195     target_ulong y;        /* multiply/divide register */
 196
 197     /* emulator internal flags handling */
 198     target_ulong cc_src, cc_src2;
 199     target_ulong cc_dst;
 200
 201     target_ulong t0, t1; /* temporaries live across basic blocks */
 202     target_ulong cond; /* conditional branch result (XXX: save it in a
 203                           temporary register when possible) */
 204
 205     uint32_t psr;      /* processor state register */
 206     target_ulong fsr;      /* FPU state register */
 207     float32 fpr[TARGET_FPREGS];  /* floating point registers */
 208     uint32_t cwp;      /* index of current register window (extracted
 209                           from PSR) */
 210     uint32_t wim;      /* window invalid mask */
 211     target_ulong tbr;  /* trap base register */
 212     int      psrs;     /* supervisor mode (extracted from PSR) */
 213     int      psrps;    /* previous supervisor mode */
 214     int      psret;    /* enable traps */
 215     uint32_t psrpil;   /* interrupt blocking level */
 216     uint32_t pil_in;   /* incoming interrupt level bitmap */
 217     int      psref;    /* enable fpu */
 218     target_ulong version;
 219     int interrupt_index;
 220     uint32_t mmu_bm;
 221     uint32_t mmu_ctpr_mask;
 222     uint32_t mmu_cxr_mask;
 223     uint32_t mmu_sfsr_mask;
 224     uint32_t mmu_trcr_mask;
 225     uint32_t nwindows;
 226     /* NOTE: we allow 8 more registers to handle wrapping */
 227     target_ulong regbase[MAX_NWINDOWS * 16 + 8];
 228
 229     CPU_COMMON
 230
 231     /* MMU regs */
 232 #if defined(TARGET_SPARC64)
 233     uint64_t lsu;
 234 #define DMMU_E 0x8
 235 #define IMMU_E 0x4
 236     uint64_t immuregs[16];
 237     uint64_t dmmuregs[16];
 238     uint64_t itlb_tag[64];
 239     uint64_t itlb_tte[64];
 240     uint64_t dtlb_tag[64];
 241     uint64_t dtlb_tte[64];
 242     uint32_t mmu_version;
 243 #else
 244     uint32_t mmuregs[32];
 245     uint64_t mxccdata[4];
 246     uint64_t mxccregs[8];
 247     uint64_t prom_addr;
 248 #endif
 249     /* temporary float registers */
 250     float32 ft0, ft1;
 251     float64 dt0, dt1;
 252     float128 qt0, qt1;
 253     float_status fp_status;
 254 #if defined(TARGET_SPARC64)
 255 #define MAXTL_MAX 8
 256 #define MAXTL_MASK (MAXTL_MAX - 1)
 257     trap_state *tsptr;
 258     trap_state ts[MAXTL_MAX];
 259     uint32_t xcc;               /* Extended integer condition codes */
 260     uint32_t asi;
 261     uint32_t pstate;
 262     uint32_t tl;
 263     uint32_t maxtl;
 264     uint32_t cansave, canrestore, otherwin, wstate, cleanwin;
 265     uint64_t agregs[8]; /* alternate general registers */
 266     uint64_t bgregs[8]; /* backup for normal global registers */
 267     uint64_t igregs[8]; /* interrupt general registers */
 268     uint64_t mgregs[8]; /* mmu general registers */
 269     uint64_t fprs;
 270     uint64_t tick_cmpr, stick_cmpr;
 271     void *tick, *stick;
 272     uint64_t gsr;
 273     uint32_t gl; // UA2005
 274     /* UA 2005 hyperprivileged registers */
 275     uint64_t hpstate, htstate[MAXTL_MAX], hintp, htba, hver, hstick_cmpr, ssr;
 276     void *hstick; // UA 2005
 277 #endif
 278     uint32_t features;
 279 } CPUSPARCState;
 280
 281 #define CPU_FEATURE_FLOAT    (1 << 0)
 282 #define CPU_FEATURE_FLOAT128 (1 << 1)
 283 #define CPU_FEATURE_SWAP     (1 << 2)
 284 #define CPU_FEATURE_MUL      (1 << 3)
 285 #define CPU_FEATURE_DIV      (1 << 4)
 286 #define CPU_FEATURE_FLUSH    (1 << 5)
 287 #define CPU_FEATURE_FSQRT    (1 << 6)
 288 #define CPU_FEATURE_FMUL     (1 << 7)
 289 #define CPU_FEATURE_VIS1     (1 << 8)
 290 #define CPU_FEATURE_VIS2     (1 << 9)
 291 #define CPU_FEATURE_FSMULD   (1 << 10)
 292 #define CPU_FEATURE_HYPV     (1 << 11)
 293 #define CPU_FEATURE_CMT      (1 << 12)
 294 #define CPU_FEATURE_GL       (1 << 13)
 295 #ifndef TARGET_SPARC64
 296 #define CPU_DEFAULT_FEATURES (CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP |  \
 297                               CPU_FEATURE_MUL | CPU_FEATURE_DIV |     \
 298                               CPU_FEATURE_FLUSH | CPU_FEATURE_FSQRT | \
 299                               CPU_FEATURE_FMUL | CPU_FEATURE_FSMULD)
 300 #else
 301 #define CPU_DEFAULT_FEATURES (CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP |  \
 302                               CPU_FEATURE_MUL | CPU_FEATURE_DIV |     \
 303                               CPU_FEATURE_FLUSH | CPU_FEATURE_FSQRT | \
 304                               CPU_FEATURE_FMUL | CPU_FEATURE_VIS1 |   \
 305                               CPU_FEATURE_VIS2 | CPU_FEATURE_FSMULD)
 306 enum {
 307     mmu_us_12, // Ultrasparc < III (64 entry TLB)
 308     mmu_us_3,  // Ultrasparc III (512 entry TLB)
 309     mmu_us_4,  // Ultrasparc IV (several TLBs, 32 and 256MB pages)
 310     mmu_sun4v, // T1, T2
 311 };
 312 #endif
 313
 314 #if defined(TARGET_SPARC64)
 315 #define GET_FSR32(env) (env->fsr & 0xcfc1ffff)
 316 #define PUT_FSR32(env, val) do { uint32_t _tmp = val;                   \
 317         env->fsr = (_tmp & 0xcfc1c3ff) | (env->fsr & 0x3f00000000ULL);  \
 318     } while (0)
 319 #define GET_FSR64(env) (env->fsr & 0x3fcfc1ffffULL)
 320 #define PUT_FSR64(env, val) do { uint64_t _tmp = val;   \
 321         env->fsr = _tmp & 0x3fcfc1c3ffULL;              \
 322     } while (0)
 323 #else
 324 #define GET_FSR32(env) (env->fsr)
 325 #define PUT_FSR32(env, val) do { uint32_t _tmp = val;                   \
 326         env->fsr = (_tmp & 0xcfc1dfff) | (env->fsr & 0x000e0000);       \
 327     } while (0)
 328 #endif
 329
 330 CPUSPARCState *cpu_sparc_init(const char *cpu_model);
 331 void gen_intermediate_code_init(CPUSPARCState *env);
 332 int cpu_sparc_exec(CPUSPARCState *s);
 333 void sparc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt,
 334                                                  ...));
 335 void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu);
 336
 337 #define GET_PSR(env) (env->version | (env->psr & PSR_ICC) |             \
 338                       (env->psref? PSR_EF : 0) |                        \
 339                       (env->psrpil << 8) |                              \
 340                       (env->psrs? PSR_S : 0) |                          \
 341                       (env->psrps? PSR_PS : 0) |                        \
 342                       (env->psret? PSR_ET : 0) | env->cwp)
 343
 344 #ifndef NO_CPU_IO_DEFS
 345 void cpu_set_cwp(CPUSPARCState *env1, int new_cwp);
 346
 347 static inline int cpu_cwp_inc(CPUSPARCState *env1, int cwp)
 348 {
 349     if (unlikely(cwp >= env1->nwindows))
 350         cwp -= env1->nwindows;
 351     return cwp;
 352 }
 353
 354 static inline int cpu_cwp_dec(CPUSPARCState *env1, int cwp)
 355 {
 356     if (unlikely(cwp < 0))
 357         cwp += env1->nwindows;
 358     return cwp;
 359 }
 360 #endif
 361
 362 #define PUT_PSR(env, val) do { int _tmp = val;                          \
 363         env->psr = _tmp & PSR_ICC;                                      \
 364         env->psref = (_tmp & PSR_EF)? 1 : 0;                            \
 365         env->psrpil = (_tmp & PSR_PIL) >> 8;                            \
 366         env->psrs = (_tmp & PSR_S)? 1 : 0;                              \
 367         env->psrps = (_tmp & PSR_PS)? 1 : 0;                            \
 368         env->psret = (_tmp & PSR_ET)? 1 : 0;                            \
 369         cpu_set_cwp(env, _tmp & PSR_CWP);                               \
 370     } while (0)
 371
 372 #ifdef TARGET_SPARC64
 373 #define GET_CCR(env) (((env->xcc >> 20) << 4) | ((env->psr & PSR_ICC) >> 20))
 374 #define PUT_CCR(env, val) do { int _tmp = val;                          \
 375         env->xcc = (_tmp >> 4) << 20;                                   \
 376         env->psr = (_tmp & 0xf) << 20;                                  \
 377     } while (0)
 378 #define GET_CWP64(env) (env->nwindows - 1 - (env)->cwp)
 379
 380 #ifndef NO_CPU_IO_DEFS
 381 static inline void PUT_CWP64(CPUSPARCState *env1, int cwp)
 382 {
 383     if (unlikely(cwp >= env1->nwindows || cwp < 0))
 384         cwp = 0;
 385     cpu_set_cwp(env1, env1->nwindows - 1 - cwp);
 386 }
 387 #endif
 388 #endif
 389
 390 int cpu_sparc_signal_handler(int host_signum, void *pinfo, void *puc);
 391 void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
 392                           int is_asi);
 393 void cpu_check_irqs(CPUSPARCState *env);
 394
 395 #define CPUState CPUSPARCState
 396 #define cpu_init cpu_sparc_init
 397 #define cpu_exec cpu_sparc_exec
 398 #define cpu_gen_code cpu_sparc_gen_code
 399 #define cpu_signal_handler cpu_sparc_signal_handler
 400 #define cpu_list sparc_cpu_list
 401
 402 #define CPU_SAVE_VERSION 5
 403
 404 /* MMU modes definitions */
 405 #define MMU_MODE0_SUFFIX _user
 406 #define MMU_MODE1_SUFFIX _kernel
 407 #ifdef TARGET_SPARC64
 408 #define MMU_MODE2_SUFFIX _hypv
 409 #endif
 410 #define MMU_USER_IDX   0
 411 #define MMU_KERNEL_IDX 1
 412 #define MMU_HYPV_IDX   2
 413
 414 static inline int cpu_mmu_index(CPUState *env1)
 415 {
 416 #if defined(CONFIG_USER_ONLY)
 417     return MMU_USER_IDX;
 418 #elif !defined(TARGET_SPARC64)
 419     return env1->psrs;
 420 #else
 421     if (!env1->psrs)
 422         return MMU_USER_IDX;
 423     else if ((env1->hpstate & HS_PRIV) == 0)
 424         return MMU_KERNEL_IDX;
 425     else
 426         return MMU_HYPV_IDX;
 427 #endif
 428 }
 429
 430 static inline int cpu_fpu_enabled(CPUState *env1)
 431 {
 432 #if defined(CONFIG_USER_ONLY)
 433     return 1;
 434 #elif !defined(TARGET_SPARC64)
 435     return env1->psref;
 436 #else
 437     return ((env1->pstate & PS_PEF) != 0) && ((env1->fprs & FPRS_FEF) != 0);
 438 #endif
 439 }
 440
 441 #if defined(CONFIG_USER_ONLY)
 442 static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
 443 {
 444     if (newsp)
 445         env->regwptr[22] = newsp;
 446     env->regwptr[0] = 0;
 447     /* FIXME: Do we also need to clear CF?  */
 448     /* XXXXX */
 449     printf ("HELPME: %s:%d\n", __FILE__, __LINE__);
 450 }
 451 #endif
 452
 453 #define CPU_PC_FROM_TB(env, tb) do { \
 454     env->pc = tb->pc; \
 455     env->npc = tb->cs_base; \
 456     } while(0)
 457
 458 #include "cpu-all.h"
 459
 460 #endif