2 * ColdFire Fast Ethernet Controller emulation.
4 * Copyright (c) 2007 CodeSourcery.
6 * This code is licenced under the GPL
17 #define DPRINTF(fmt, args...) \
18 do { printf("mcf_fec: " fmt , ##args); } while (0)
20 #define DPRINTF(fmt, args...) do {} while(0)
23 #define FEC_MAX_FRAME_SIZE 2032
33 uint32_t rx_descriptor
;
34 uint32_t tx_descriptor
;
48 #define FEC_INT_HB 0x80000000
49 #define FEC_INT_BABR 0x40000000
50 #define FEC_INT_BABT 0x20000000
51 #define FEC_INT_GRA 0x10000000
52 #define FEC_INT_TXF 0x08000000
53 #define FEC_INT_TXB 0x04000000
54 #define FEC_INT_RXF 0x02000000
55 #define FEC_INT_RXB 0x01000000
56 #define FEC_INT_MII 0x00800000
57 #define FEC_INT_EB 0x00400000
58 #define FEC_INT_LC 0x00200000
59 #define FEC_INT_RL 0x00100000
60 #define FEC_INT_UN 0x00080000
65 /* Map interrupt flags onto IRQ lines. */
66 #define FEC_NUM_IRQ 13
67 static const uint32_t mcf_fec_irq_map
[FEC_NUM_IRQ
] = {
83 /* Buffer Descriptor. */
90 #define FEC_BD_R 0x8000
91 #define FEC_BD_E 0x8000
92 #define FEC_BD_O1 0x4000
93 #define FEC_BD_W 0x2000
94 #define FEC_BD_O2 0x1000
95 #define FEC_BD_L 0x0800
96 #define FEC_BD_TC 0x0400
97 #define FEC_BD_ABC 0x0200
98 #define FEC_BD_M 0x0100
99 #define FEC_BD_BC 0x0080
100 #define FEC_BD_MC 0x0040
101 #define FEC_BD_LG 0x0020
102 #define FEC_BD_NO 0x0010
103 #define FEC_BD_CR 0x0004
104 #define FEC_BD_OV 0x0002
105 #define FEC_BD_TR 0x0001
107 static void mcf_fec_read_bd(mcf_fec_bd
*bd
, uint32_t addr
)
109 cpu_physical_memory_read(addr
, (uint8_t *)bd
, sizeof(*bd
));
110 be16_to_cpus(&bd
->flags
);
111 be16_to_cpus(&bd
->length
);
112 be32_to_cpus(&bd
->data
);
115 static void mcf_fec_write_bd(mcf_fec_bd
*bd
, uint32_t addr
)
118 tmp
.flags
= cpu_to_be16(bd
->flags
);
119 tmp
.length
= cpu_to_be16(bd
->length
);
120 tmp
.data
= cpu_to_be32(bd
->data
);
121 cpu_physical_memory_write(addr
, (uint8_t *)&tmp
, sizeof(tmp
));
124 static void mcf_fec_update(mcf_fec_state
*s
)
131 active
= s
->eir
& s
->eimr
;
132 changed
= active
^s
->irq_state
;
133 for (i
= 0; i
< FEC_NUM_IRQ
; i
++) {
134 mask
= mcf_fec_irq_map
[i
];
135 if (changed
& mask
) {
136 DPRINTF("IRQ %d = %d\n", i
, (active
& mask
) != 0);
137 qemu_set_irq(s
->irq
[i
], (active
& mask
) != 0);
140 s
->irq_state
= active
;
143 static void mcf_fec_do_tx(mcf_fec_state
*s
)
149 uint8_t frame
[FEC_MAX_FRAME_SIZE
];
155 addr
= s
->tx_descriptor
;
157 mcf_fec_read_bd(&bd
, addr
);
158 DPRINTF("tx_bd %x flags %04x len %d data %08x\n",
159 addr
, bd
.flags
, bd
.length
, bd
.data
);
160 if ((bd
.flags
& FEC_BD_R
) == 0) {
161 /* Run out of descriptors to transmit. */
165 if (frame_size
+ len
> FEC_MAX_FRAME_SIZE
) {
166 len
= FEC_MAX_FRAME_SIZE
- frame_size
;
167 s
->eir
|= FEC_INT_BABT
;
169 cpu_physical_memory_read(bd
.data
, ptr
, len
);
172 if (bd
.flags
& FEC_BD_L
) {
173 /* Last buffer in frame. */
174 DPRINTF("Sending packet\n");
175 qemu_send_packet(s
->vc
, frame
, len
);
178 s
->eir
|= FEC_INT_TXF
;
180 s
->eir
|= FEC_INT_TXB
;
181 bd
.flags
&= ~FEC_BD_R
;
182 /* Write back the modified descriptor. */
183 mcf_fec_write_bd(&bd
, addr
);
184 /* Advance to the next descriptor. */
185 if ((bd
.flags
& FEC_BD_W
) != 0) {
191 s
->tx_descriptor
= addr
;
194 static void mcf_fec_enable_rx(mcf_fec_state
*s
)
198 mcf_fec_read_bd(&bd
, s
->rx_descriptor
);
199 s
->rx_enabled
= ((bd
.flags
& FEC_BD_E
) != 0);
201 DPRINTF("RX buffer full\n");
204 static void mcf_fec_reset(mcf_fec_state
*s
)
217 static uint32_t mcf_fec_read(void *opaque
, target_phys_addr_t addr
)
219 mcf_fec_state
*s
= (mcf_fec_state
*)opaque
;
220 switch (addr
& 0x3ff) {
221 case 0x004: return s
->eir
;
222 case 0x008: return s
->eimr
;
223 case 0x010: return s
->rx_enabled
? (1 << 24) : 0; /* RDAR */
224 case 0x014: return 0; /* TDAR */
225 case 0x024: return s
->ecr
;
226 case 0x040: return s
->mmfr
;
227 case 0x044: return s
->mscr
;
228 case 0x064: return 0; /* MIBC */
229 case 0x084: return s
->rcr
;
230 case 0x0c4: return s
->tcr
;
231 case 0x0e4: /* PALR */
232 return (s
->macaddr
[0] << 24) | (s
->macaddr
[1] << 16)
233 | (s
->macaddr
[2] << 8) | s
->macaddr
[3];
235 case 0x0e8: /* PAUR */
236 return (s
->macaddr
[4] << 24) | (s
->macaddr
[5] << 16) | 0x8808;
237 case 0x0ec: return 0x10000; /* OPD */
238 case 0x118: return 0;
239 case 0x11c: return 0;
240 case 0x120: return 0;
241 case 0x124: return 0;
242 case 0x144: return s
->tfwr
;
243 case 0x14c: return 0x600;
244 case 0x150: return s
->rfsr
;
245 case 0x180: return s
->erdsr
;
246 case 0x184: return s
->etdsr
;
247 case 0x188: return s
->emrbr
;
249 cpu_abort(cpu_single_env
, "mcf_fec_read: Bad address 0x%x\n",
255 static void mcf_fec_write(void *opaque
, target_phys_addr_t addr
, uint32_t value
)
257 mcf_fec_state
*s
= (mcf_fec_state
*)opaque
;
258 switch (addr
& 0x3ff) {
265 case 0x010: /* RDAR */
266 if ((s
->ecr
& FEC_EN
) && !s
->rx_enabled
) {
267 DPRINTF("RX enable\n");
268 mcf_fec_enable_rx(s
);
271 case 0x014: /* TDAR */
272 if (s
->ecr
& FEC_EN
) {
278 if (value
& FEC_RESET
) {
282 if ((s
->ecr
& FEC_EN
) == 0) {
287 /* TODO: Implement MII. */
291 s
->mscr
= value
& 0xfe;
294 /* TODO: Implement MIB. */
297 s
->rcr
= value
& 0x07ff003f;
298 /* TODO: Implement LOOP mode. */
300 case 0x0c4: /* TCR */
301 /* We transmit immediately, so raise GRA immediately. */
304 s
->eir
|= FEC_INT_GRA
;
306 case 0x0e4: /* PALR */
307 s
->macaddr
[0] = value
>> 24;
308 s
->macaddr
[1] = value
>> 16;
309 s
->macaddr
[2] = value
>> 8;
310 s
->macaddr
[3] = value
;
312 case 0x0e8: /* PAUR */
313 s
->macaddr
[4] = value
>> 24;
314 s
->macaddr
[5] = value
>> 16;
323 /* TODO: implement MAC hash filtering. */
329 /* FRBR writes ignored. */
332 s
->rfsr
= (value
& 0x3fc) | 0x400;
335 s
->erdsr
= value
& ~3;
336 s
->rx_descriptor
= s
->erdsr
;
339 s
->etdsr
= value
& ~3;
340 s
->tx_descriptor
= s
->etdsr
;
343 s
->emrbr
= value
& 0x7f0;
346 cpu_abort(cpu_single_env
, "mcf_fec_write Bad address 0x%x\n",
352 static int mcf_fec_can_receive(void *opaque
)
354 mcf_fec_state
*s
= (mcf_fec_state
*)opaque
;
355 return s
->rx_enabled
;
358 static void mcf_fec_receive(void *opaque
, const uint8_t *buf
, int size
)
360 mcf_fec_state
*s
= (mcf_fec_state
*)opaque
;
367 unsigned int buf_len
;
369 DPRINTF("do_rx len %d\n", size
);
370 if (!s
->rx_enabled
) {
371 fprintf(stderr
, "mcf_fec_receive: Unexpected packet\n");
373 /* 4 bytes for the CRC. */
375 crc
= cpu_to_be32(crc32(~0, buf
, size
));
376 crc_ptr
= (uint8_t *)&crc
;
377 /* Huge frames are truncted. */
378 if (size
> FEC_MAX_FRAME_SIZE
) {
379 size
= FEC_MAX_FRAME_SIZE
;
380 flags
|= FEC_BD_TR
| FEC_BD_LG
;
382 /* Frames larger than the user limit just set error flags. */
383 if (size
> (s
->rcr
>> 16)) {
386 addr
= s
->rx_descriptor
;
388 mcf_fec_read_bd(&bd
, addr
);
389 if ((bd
.flags
& FEC_BD_E
) == 0) {
390 /* No descriptors available. Bail out. */
391 /* FIXME: This is wrong. We should probably either save the
392 remainder for when more RX buffers are available, or
394 fprintf(stderr
, "mcf_fec: Lost end of frame\n");
397 buf_len
= (size
<= s
->emrbr
) ? size
: s
->emrbr
;
400 DPRINTF("rx_bd %x length %d\n", addr
, bd
.length
);
401 /* The last 4 bytes are the CRC. */
405 cpu_physical_memory_write(buf_addr
, buf
, buf_len
);
408 cpu_physical_memory_write(buf_addr
+ buf_len
, crc_ptr
, 4 - size
);
411 bd
.flags
&= ~FEC_BD_E
;
413 /* Last buffer in frame. */
414 bd
.flags
|= flags
| FEC_BD_L
;
415 DPRINTF("rx frame flags %04x\n", bd
.flags
);
416 s
->eir
|= FEC_INT_RXF
;
418 s
->eir
|= FEC_INT_RXB
;
420 mcf_fec_write_bd(&bd
, addr
);
421 /* Advance to the next descriptor. */
422 if ((bd
.flags
& FEC_BD_W
) != 0) {
428 s
->rx_descriptor
= addr
;
429 mcf_fec_enable_rx(s
);
433 static CPUReadMemoryFunc
*mcf_fec_readfn
[] = {
439 static CPUWriteMemoryFunc
*mcf_fec_writefn
[] = {
445 static void mcf_fec_cleanup(VLANClientState
*vc
)
447 mcf_fec_state
*s
= vc
->opaque
;
449 cpu_unregister_io_memory(s
->mmio_index
);
454 void mcf_fec_init(NICInfo
*nd
, target_phys_addr_t base
, qemu_irq
*irq
)
458 qemu_check_nic_model(nd
, "mcf_fec");
460 s
= (mcf_fec_state
*)qemu_mallocz(sizeof(mcf_fec_state
));
462 s
->mmio_index
= cpu_register_io_memory(0, mcf_fec_readfn
,
464 cpu_register_physical_memory(base
, 0x400, s
->mmio_index
);
466 s
->vc
= qemu_new_vlan_client(nd
->vlan
, nd
->model
, nd
->name
,
467 mcf_fec_receive
, mcf_fec_can_receive
,
469 memcpy(s
->macaddr
, nd
->macaddr
, 6);
470 qemu_format_nic_info_str(s
->vc
, s
->macaddr
);