2 * QEMU TCX Frame buffer
4 * Copyright (c) 2003-2005 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
27 #include "pixel_ops.h"
31 #define TCX_DAC_NREGS 16
32 #define TCX_THC_NREGS_8 0x081c
33 #define TCX_THC_NREGS_24 0x1000
34 #define TCX_TEC_NREGS 0x1000
36 typedef struct TCXState
{
37 target_phys_addr_t addr
;
40 uint32_t *vram24
, *cplane
;
41 ram_addr_t vram_offset
, vram24_offset
, cplane_offset
;
42 uint16_t width
, height
, depth
;
43 uint8_t r
[256], g
[256], b
[256];
44 uint32_t palette
[256];
45 uint8_t dac_index
, dac_state
;
48 static void tcx_screen_dump(void *opaque
, const char *filename
);
49 static void tcx24_screen_dump(void *opaque
, const char *filename
);
50 static void tcx_invalidate_display(void *opaque
);
51 static void tcx24_invalidate_display(void *opaque
);
53 static void update_palette_entries(TCXState
*s
, int start
, int end
)
56 for(i
= start
; i
< end
; i
++) {
57 switch(s
->ds
->depth
) {
60 s
->palette
[i
] = rgb_to_pixel8(s
->r
[i
], s
->g
[i
], s
->b
[i
]);
64 s
->palette
[i
] = rgb_to_pixel15bgr(s
->r
[i
], s
->g
[i
], s
->b
[i
]);
66 s
->palette
[i
] = rgb_to_pixel15(s
->r
[i
], s
->g
[i
], s
->b
[i
]);
70 s
->palette
[i
] = rgb_to_pixel16bgr(s
->r
[i
], s
->g
[i
], s
->b
[i
]);
72 s
->palette
[i
] = rgb_to_pixel16(s
->r
[i
], s
->g
[i
], s
->b
[i
]);
76 s
->palette
[i
] = rgb_to_pixel32bgr(s
->r
[i
], s
->g
[i
], s
->b
[i
]);
78 s
->palette
[i
] = rgb_to_pixel32(s
->r
[i
], s
->g
[i
], s
->b
[i
]);
83 tcx24_invalidate_display(s
);
85 tcx_invalidate_display(s
);
88 static void tcx_draw_line32(TCXState
*s1
, uint8_t *d
,
89 const uint8_t *s
, int width
)
93 uint32_t *p
= (uint32_t *)d
;
95 for(x
= 0; x
< width
; x
++) {
97 *p
++ = s1
->palette
[val
];
101 static void tcx_draw_line16(TCXState
*s1
, uint8_t *d
,
102 const uint8_t *s
, int width
)
106 uint16_t *p
= (uint16_t *)d
;
108 for(x
= 0; x
< width
; x
++) {
110 *p
++ = s1
->palette
[val
];
114 static void tcx_draw_line8(TCXState
*s1
, uint8_t *d
,
115 const uint8_t *s
, int width
)
120 for(x
= 0; x
< width
; x
++) {
122 *d
++ = s1
->palette
[val
];
126 static inline void tcx24_draw_line32(TCXState
*s1
, uint8_t *d
,
127 const uint8_t *s
, int width
,
128 const uint32_t *cplane
,
133 uint32_t *p
= (uint32_t *)d
;
136 for(x
= 0; x
< width
; x
++, s
++, s24
++) {
137 if ((bswap32(*cplane
++) & 0xff000000) == 0x03000000) { // 24-bit direct
138 dval
= bswap32(*s24
) & 0x00ffffff;
141 dval
= s1
->palette
[val
];
147 static inline int check_dirty(ram_addr_t page
, ram_addr_t page24
,
153 ret
= cpu_physical_memory_get_dirty(page
, VGA_DIRTY_FLAG
);
154 for (off
= 0; off
< TARGET_PAGE_SIZE
* 4; off
+= TARGET_PAGE_SIZE
) {
155 ret
|= cpu_physical_memory_get_dirty(page24
+ off
, VGA_DIRTY_FLAG
);
156 ret
|= cpu_physical_memory_get_dirty(cpage
+ off
, VGA_DIRTY_FLAG
);
161 static inline void reset_dirty(TCXState
*ts
, ram_addr_t page_min
,
162 ram_addr_t page_max
, ram_addr_t page24
,
165 cpu_physical_memory_reset_dirty(page_min
, page_max
+ TARGET_PAGE_SIZE
,
167 page_min
-= ts
->vram_offset
;
168 page_max
-= ts
->vram_offset
;
169 cpu_physical_memory_reset_dirty(page24
+ page_min
* 4,
170 page24
+ page_max
* 4 + TARGET_PAGE_SIZE
,
172 cpu_physical_memory_reset_dirty(cpage
+ page_min
* 4,
173 cpage
+ page_max
* 4 + TARGET_PAGE_SIZE
,
177 /* Fixed line length 1024 allows us to do nice tricks not possible on
179 static void tcx_update_display(void *opaque
)
181 TCXState
*ts
= opaque
;
182 ram_addr_t page
, page_min
, page_max
;
183 int y
, y_start
, dd
, ds
;
185 void (*f
)(TCXState
*s1
, uint8_t *dst
, const uint8_t *src
, int width
);
187 if (ts
->ds
->depth
== 0)
189 if (ts
->ds
->width
!= ts
->width
|| ts
->ds
->height
!= ts
->height
)
190 dpy_resize(ts
->ds
, ts
->width
, ts
->height
);
191 page
= ts
->vram_offset
;
193 page_min
= 0xffffffff;
197 dd
= ts
->ds
->linesize
;
200 switch (ts
->ds
->depth
) {
216 for(y
= 0; y
< ts
->height
; y
+= 4, page
+= TARGET_PAGE_SIZE
) {
217 if (cpu_physical_memory_get_dirty(page
, VGA_DIRTY_FLAG
)) {
224 f(ts
, d
, s
, ts
->width
);
227 f(ts
, d
, s
, ts
->width
);
230 f(ts
, d
, s
, ts
->width
);
233 f(ts
, d
, s
, ts
->width
);
238 /* flush to display */
239 dpy_update(ts
->ds
, 0, y_start
,
240 ts
->width
, y
- y_start
);
248 /* flush to display */
249 dpy_update(ts
->ds
, 0, y_start
,
250 ts
->width
, y
- y_start
);
252 /* reset modified pages */
253 if (page_min
<= page_max
) {
254 cpu_physical_memory_reset_dirty(page_min
, page_max
+ TARGET_PAGE_SIZE
,
259 static void tcx24_update_display(void *opaque
)
261 TCXState
*ts
= opaque
;
262 ram_addr_t page
, page_min
, page_max
, cpage
, page24
;
263 int y
, y_start
, dd
, ds
;
265 uint32_t *cptr
, *s24
;
267 if (ts
->ds
->depth
!= 32)
269 if (ts
->ds
->width
!= ts
->width
|| ts
->ds
->height
!= ts
->height
)
270 dpy_resize(ts
->ds
, ts
->width
, ts
->height
);
271 page
= ts
->vram_offset
;
272 page24
= ts
->vram24_offset
;
273 cpage
= ts
->cplane_offset
;
275 page_min
= 0xffffffff;
281 dd
= ts
->ds
->linesize
;
284 for(y
= 0; y
< ts
->height
; y
+= 4, page
+= TARGET_PAGE_SIZE
,
285 page24
+= TARGET_PAGE_SIZE
, cpage
+= TARGET_PAGE_SIZE
) {
286 if (check_dirty(page
, page24
, cpage
)) {
293 tcx24_draw_line32(ts
, d
, s
, ts
->width
, cptr
, s24
);
298 tcx24_draw_line32(ts
, d
, s
, ts
->width
, cptr
, s24
);
303 tcx24_draw_line32(ts
, d
, s
, ts
->width
, cptr
, s24
);
308 tcx24_draw_line32(ts
, d
, s
, ts
->width
, cptr
, s24
);
315 /* flush to display */
316 dpy_update(ts
->ds
, 0, y_start
,
317 ts
->width
, y
- y_start
);
327 /* flush to display */
328 dpy_update(ts
->ds
, 0, y_start
,
329 ts
->width
, y
- y_start
);
331 /* reset modified pages */
332 if (page_min
<= page_max
) {
333 reset_dirty(ts
, page_min
, page_max
, page24
, cpage
);
337 static void tcx_invalidate_display(void *opaque
)
339 TCXState
*s
= opaque
;
342 for (i
= 0; i
< MAXX
*MAXY
; i
+= TARGET_PAGE_SIZE
) {
343 cpu_physical_memory_set_dirty(s
->vram_offset
+ i
);
347 static void tcx24_invalidate_display(void *opaque
)
349 TCXState
*s
= opaque
;
352 tcx_invalidate_display(s
);
353 for (i
= 0; i
< MAXX
*MAXY
* 4; i
+= TARGET_PAGE_SIZE
) {
354 cpu_physical_memory_set_dirty(s
->vram24_offset
+ i
);
355 cpu_physical_memory_set_dirty(s
->cplane_offset
+ i
);
359 static void tcx_save(QEMUFile
*f
, void *opaque
)
361 TCXState
*s
= opaque
;
363 qemu_put_be16s(f
, (uint16_t *)&s
->height
);
364 qemu_put_be16s(f
, (uint16_t *)&s
->width
);
365 qemu_put_be16s(f
, (uint16_t *)&s
->depth
);
366 qemu_put_buffer(f
, s
->r
, 256);
367 qemu_put_buffer(f
, s
->g
, 256);
368 qemu_put_buffer(f
, s
->b
, 256);
369 qemu_put_8s(f
, &s
->dac_index
);
370 qemu_put_8s(f
, &s
->dac_state
);
373 static int tcx_load(QEMUFile
*f
, void *opaque
, int version_id
)
375 TCXState
*s
= opaque
;
378 if (version_id
!= 3 && version_id
!= 4)
381 if (version_id
== 3) {
382 qemu_get_be32s(f
, (uint32_t *)&dummy
);
383 qemu_get_be32s(f
, (uint32_t *)&dummy
);
384 qemu_get_be32s(f
, (uint32_t *)&dummy
);
386 qemu_get_be16s(f
, (uint16_t *)&s
->height
);
387 qemu_get_be16s(f
, (uint16_t *)&s
->width
);
388 qemu_get_be16s(f
, (uint16_t *)&s
->depth
);
389 qemu_get_buffer(f
, s
->r
, 256);
390 qemu_get_buffer(f
, s
->g
, 256);
391 qemu_get_buffer(f
, s
->b
, 256);
392 qemu_get_8s(f
, &s
->dac_index
);
393 qemu_get_8s(f
, &s
->dac_state
);
394 update_palette_entries(s
, 0, 256);
396 tcx24_invalidate_display(s
);
398 tcx_invalidate_display(s
);
403 static void tcx_reset(void *opaque
)
405 TCXState
*s
= opaque
;
407 /* Initialize palette */
408 memset(s
->r
, 0, 256);
409 memset(s
->g
, 0, 256);
410 memset(s
->b
, 0, 256);
411 s
->r
[255] = s
->g
[255] = s
->b
[255] = 255;
412 update_palette_entries(s
, 0, 256);
413 memset(s
->vram
, 0, MAXX
*MAXY
);
414 cpu_physical_memory_reset_dirty(s
->vram_offset
, s
->vram_offset
+
415 MAXX
* MAXY
* (1 + 4 + 4), VGA_DIRTY_FLAG
);
420 static uint32_t tcx_dac_readl(void *opaque
, target_phys_addr_t addr
)
425 static void tcx_dac_writel(void *opaque
, target_phys_addr_t addr
, uint32_t val
)
427 TCXState
*s
= opaque
;
430 saddr
= (addr
& (TCX_DAC_NREGS
- 1)) >> 2;
433 s
->dac_index
= val
>> 24;
437 switch (s
->dac_state
) {
439 s
->r
[s
->dac_index
] = val
>> 24;
440 update_palette_entries(s
, s
->dac_index
, s
->dac_index
+ 1);
444 s
->g
[s
->dac_index
] = val
>> 24;
445 update_palette_entries(s
, s
->dac_index
, s
->dac_index
+ 1);
449 s
->b
[s
->dac_index
] = val
>> 24;
450 update_palette_entries(s
, s
->dac_index
, s
->dac_index
+ 1);
451 s
->dac_index
= (s
->dac_index
+ 1) & 255; // Index autoincrement
463 static CPUReadMemoryFunc
*tcx_dac_read
[3] = {
469 static CPUWriteMemoryFunc
*tcx_dac_write
[3] = {
475 static uint32_t tcx_dummy_readl(void *opaque
, target_phys_addr_t addr
)
480 static void tcx_dummy_writel(void *opaque
, target_phys_addr_t addr
,
485 static CPUReadMemoryFunc
*tcx_dummy_read
[3] = {
491 static CPUWriteMemoryFunc
*tcx_dummy_write
[3] = {
497 void tcx_init(DisplayState
*ds
, target_phys_addr_t addr
, uint8_t *vram_base
,
498 unsigned long vram_offset
, int vram_size
, int width
, int height
,
502 int io_memory
, dummy_memory
;
505 s
= qemu_mallocz(sizeof(TCXState
));
510 s
->vram_offset
= vram_offset
;
518 cpu_register_physical_memory(addr
+ 0x00800000ULL
, size
, vram_offset
);
522 io_memory
= cpu_register_io_memory(0, tcx_dac_read
, tcx_dac_write
, s
);
523 cpu_register_physical_memory(addr
+ 0x00200000ULL
, TCX_DAC_NREGS
,
526 dummy_memory
= cpu_register_io_memory(0, tcx_dummy_read
, tcx_dummy_write
,
528 cpu_register_physical_memory(addr
+ 0x00700000ULL
, TCX_TEC_NREGS
,
532 size
= vram_size
* 4;
533 s
->vram24
= (uint32_t *)vram_base
;
534 s
->vram24_offset
= vram_offset
;
535 cpu_register_physical_memory(addr
+ 0x02000000ULL
, size
, vram_offset
);
540 size
= vram_size
* 4;
541 s
->cplane
= (uint32_t *)vram_base
;
542 s
->cplane_offset
= vram_offset
;
543 cpu_register_physical_memory(addr
+ 0x0a000000ULL
, size
, vram_offset
);
544 graphic_console_init(s
->ds
, tcx24_update_display
,
545 tcx24_invalidate_display
,
546 tcx24_screen_dump
, NULL
, s
);
548 cpu_register_physical_memory(addr
+ 0x00300000ULL
, TCX_THC_NREGS_8
,
550 graphic_console_init(s
->ds
, tcx_update_display
, tcx_invalidate_display
,
551 tcx_screen_dump
, NULL
, s
);
553 // NetBSD writes here even with 8-bit display
554 cpu_register_physical_memory(addr
+ 0x00301000ULL
, TCX_THC_NREGS_24
,
557 register_savevm("tcx", addr
, 4, tcx_save
, tcx_load
, s
);
558 qemu_register_reset(tcx_reset
, s
);
560 dpy_resize(s
->ds
, width
, height
);
563 static void tcx_screen_dump(void *opaque
, const char *filename
)
565 TCXState
*s
= opaque
;
570 f
= fopen(filename
, "wb");
573 fprintf(f
, "P6\n%d %d\n%d\n", s
->width
, s
->height
, 255);
575 for(y
= 0; y
< s
->height
; y
++) {
577 for(x
= 0; x
< s
->width
; x
++) {
590 static void tcx24_screen_dump(void *opaque
, const char *filename
)
592 TCXState
*s
= opaque
;
595 uint32_t *s24
, *cptr
, dval
;
598 f
= fopen(filename
, "wb");
601 fprintf(f
, "P6\n%d %d\n%d\n", s
->width
, s
->height
, 255);
605 for(y
= 0; y
< s
->height
; y
++) {
607 for(x
= 0; x
< s
->width
; x
++, d
++, s24
++) {
608 if ((*cptr
++ & 0xff000000) == 0x03000000) { // 24-bit direct
609 dval
= *s24
& 0x00ffffff;
610 fputc((dval
>> 16) & 0xff, f
);
611 fputc((dval
>> 8) & 0xff, f
);
612 fputc(dval
& 0xff, f
);