2 * QEMU Sun4u System Emulator
4 * Copyright (c) 2005 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
30 #include "qemu-timer.h"
33 #include "firmware_abi.h"
35 #define KERNEL_LOAD_ADDR 0x00404000
36 #define CMDLINE_ADDR 0x003ff000
37 #define INITRD_LOAD_ADDR 0x00300000
38 #define PROM_SIZE_MAX (4 * 1024 * 1024)
39 #define PROM_ADDR 0x1fff0000000ULL
40 #define PROM_VADDR 0x000ffd00000ULL
41 #define APB_SPECIAL_BASE 0x1fe00000000ULL
42 #define APB_MEM_BASE 0x1ff00000000ULL
43 #define VGA_BASE (APB_MEM_BASE + 0x400000ULL)
44 #define PROM_FILENAME "openbios-sparc64"
45 #define NVRAM_SIZE 0x2000
48 int DMA_get_channel_mode (int nchan
)
52 int DMA_read_memory (int nchan
, void *buf
, int pos
, int size
)
56 int DMA_write_memory (int nchan
, void *buf
, int pos
, int size
)
60 void DMA_hold_DREQ (int nchan
) {}
61 void DMA_release_DREQ (int nchan
) {}
62 void DMA_schedule(int nchan
) {}
63 void DMA_run (void) {}
64 void DMA_init (int high_page_enable
) {}
65 void DMA_register_channel (int nchan
,
66 DMA_transfer_handler transfer_handler
,
71 static int nvram_boot_set(void *opaque
, const char *boot_device
)
74 uint8_t image
[sizeof(ohwcfg_v3_t
)];
75 ohwcfg_v3_t
*header
= (ohwcfg_v3_t
*)&image
;
76 m48t59_t
*nvram
= (m48t59_t
*)opaque
;
78 for (i
= 0; i
< sizeof(image
); i
++)
79 image
[i
] = m48t59_read(nvram
, i
) & 0xff;
81 strcpy((char *)header
->boot_devices
, boot_device
);
82 header
->nboot_devices
= strlen(boot_device
) & 0xff;
83 header
->crc
= cpu_to_be16(OHW_compute_crc(header
, 0x00, 0xF8));
85 for (i
= 0; i
< sizeof(image
); i
++)
86 m48t59_write(nvram
, i
, image
[i
]);
93 static int sun4u_NVRAM_set_params (m48t59_t
*nvram
, uint16_t NVRAM_size
,
96 const char *boot_devices
,
97 uint32_t kernel_image
, uint32_t kernel_size
,
99 uint32_t initrd_image
, uint32_t initrd_size
,
100 uint32_t NVRAM_image
,
101 int width
, int height
, int depth
)
105 uint8_t image
[0x1ff0];
106 ohwcfg_v3_t
*header
= (ohwcfg_v3_t
*)&image
;
107 struct sparc_arch_cfg
*sparc_header
;
108 struct OpenBIOS_nvpart_v1
*part_header
;
110 memset(image
, '\0', sizeof(image
));
112 // Try to match PPC NVRAM
113 strcpy((char *)header
->struct_ident
, "QEMU_BIOS");
114 header
->struct_version
= cpu_to_be32(3); /* structure v3 */
116 header
->nvram_size
= cpu_to_be16(NVRAM_size
);
117 header
->nvram_arch_ptr
= cpu_to_be16(sizeof(ohwcfg_v3_t
));
118 header
->nvram_arch_size
= cpu_to_be16(sizeof(struct sparc_arch_cfg
));
119 strcpy((char *)header
->arch
, arch
);
120 header
->nb_cpus
= smp_cpus
& 0xff;
121 header
->RAM0_base
= 0;
122 header
->RAM0_size
= cpu_to_be64((uint64_t)RAM_size
);
123 strcpy((char *)header
->boot_devices
, boot_devices
);
124 header
->nboot_devices
= strlen(boot_devices
) & 0xff;
125 header
->kernel_image
= cpu_to_be64((uint64_t)kernel_image
);
126 header
->kernel_size
= cpu_to_be64((uint64_t)kernel_size
);
128 pstrcpy_targphys(CMDLINE_ADDR
, TARGET_PAGE_SIZE
, cmdline
);
129 header
->cmdline
= cpu_to_be64((uint64_t)CMDLINE_ADDR
);
130 header
->cmdline_size
= cpu_to_be64((uint64_t)strlen(cmdline
));
132 header
->initrd_image
= cpu_to_be64((uint64_t)initrd_image
);
133 header
->initrd_size
= cpu_to_be64((uint64_t)initrd_size
);
134 header
->NVRAM_image
= cpu_to_be64((uint64_t)NVRAM_image
);
136 header
->width
= cpu_to_be16(width
);
137 header
->height
= cpu_to_be16(height
);
138 header
->depth
= cpu_to_be16(depth
);
140 header
->graphic_flags
= cpu_to_be16(OHW_GF_NOGRAPHICS
);
142 header
->crc
= cpu_to_be16(OHW_compute_crc(header
, 0x00, 0xF8));
144 // Architecture specific header
145 start
= sizeof(ohwcfg_v3_t
);
146 sparc_header
= (struct sparc_arch_cfg
*)&image
[start
];
147 sparc_header
->valid
= 0;
148 start
+= sizeof(struct sparc_arch_cfg
);
150 // OpenBIOS nvram variables
151 // Variable partition
152 part_header
= (struct OpenBIOS_nvpart_v1
*)&image
[start
];
153 part_header
->signature
= OPENBIOS_PART_SYSTEM
;
154 strcpy(part_header
->name
, "system");
156 end
= start
+ sizeof(struct OpenBIOS_nvpart_v1
);
157 for (i
= 0; i
< nb_prom_envs
; i
++)
158 end
= OpenBIOS_set_var(image
, end
, prom_envs
[i
]);
163 end
= start
+ ((end
- start
+ 15) & ~15);
164 OpenBIOS_finish_partition(part_header
, end
- start
);
168 part_header
= (struct OpenBIOS_nvpart_v1
*)&image
[start
];
169 part_header
->signature
= OPENBIOS_PART_FREE
;
170 strcpy(part_header
->name
, "free");
173 OpenBIOS_finish_partition(part_header
, end
- start
);
175 for (i
= 0; i
< sizeof(image
); i
++)
176 m48t59_write(nvram
, i
, image
[i
]);
178 qemu_register_boot_set(nvram_boot_set
, nvram
);
191 void qemu_system_powerdown(void)
195 static void main_cpu_reset(void *opaque
)
197 CPUState
*env
= opaque
;
200 ptimer_set_limit(env
->tick
, 0x7fffffffffffffffULL
, 1);
201 ptimer_run(env
->tick
, 0);
202 ptimer_set_limit(env
->stick
, 0x7fffffffffffffffULL
, 1);
203 ptimer_run(env
->stick
, 0);
204 ptimer_set_limit(env
->hstick
, 0x7fffffffffffffffULL
, 1);
205 ptimer_run(env
->hstick
, 0);
208 static void tick_irq(void *opaque
)
210 CPUState
*env
= opaque
;
212 cpu_interrupt(env
, CPU_INTERRUPT_TIMER
);
215 static void stick_irq(void *opaque
)
217 CPUState
*env
= opaque
;
219 cpu_interrupt(env
, CPU_INTERRUPT_TIMER
);
222 static void hstick_irq(void *opaque
)
224 CPUState
*env
= opaque
;
226 cpu_interrupt(env
, CPU_INTERRUPT_TIMER
);
229 static void dummy_cpu_set_irq(void *opaque
, int irq
, int level
)
233 static const int ide_iobase
[2] = { 0x1f0, 0x170 };
234 static const int ide_iobase2
[2] = { 0x3f6, 0x376 };
235 static const int ide_irq
[2] = { 14, 15 };
237 static const int serial_io
[MAX_SERIAL_PORTS
] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 };
238 static const int serial_irq
[MAX_SERIAL_PORTS
] = { 4, 3, 4, 3 };
240 static const int parallel_io
[MAX_PARALLEL_PORTS
] = { 0x378, 0x278, 0x3bc };
241 static const int parallel_irq
[MAX_PARALLEL_PORTS
] = { 7, 7, 7 };
243 static fdctrl_t
*floppy_controller
;
245 /* Sun4u hardware initialisation */
246 static void sun4u_init(ram_addr_t RAM_size
, int vga_ram_size
,
247 const char *boot_devices
, DisplayState
*ds
,
248 const char *kernel_filename
, const char *kernel_cmdline
,
249 const char *initrd_filename
, const char *cpu_model
)
256 long prom_offset
, initrd_size
, kernel_size
;
261 BlockDriverState
*hd
[MAX_IDE_BUS
* MAX_IDE_DEVS
];
262 BlockDriverState
*fd
[MAX_FD
];
264 linux_boot
= (kernel_filename
!= NULL
);
267 if (cpu_model
== NULL
)
268 cpu_model
= "TI UltraSparc II";
269 env
= cpu_init(cpu_model
);
271 fprintf(stderr
, "Unable to find Sparc CPU definition\n");
274 bh
= qemu_bh_new(tick_irq
, env
);
275 env
->tick
= ptimer_init(bh
);
276 ptimer_set_period(env
->tick
, 1ULL);
278 bh
= qemu_bh_new(stick_irq
, env
);
279 env
->stick
= ptimer_init(bh
);
280 ptimer_set_period(env
->stick
, 1ULL);
282 bh
= qemu_bh_new(hstick_irq
, env
);
283 env
->hstick
= ptimer_init(bh
);
284 ptimer_set_period(env
->hstick
, 1ULL);
285 register_savevm("cpu", 0, 4, cpu_save
, cpu_load
, env
);
286 qemu_register_reset(main_cpu_reset
, env
);
290 cpu_register_physical_memory(0, RAM_size
, 0);
292 prom_offset
= RAM_size
+ vga_ram_size
;
293 cpu_register_physical_memory(PROM_ADDR
,
294 (PROM_SIZE_MAX
+ TARGET_PAGE_SIZE
) &
296 prom_offset
| IO_MEM_ROM
);
298 if (bios_name
== NULL
)
299 bios_name
= PROM_FILENAME
;
300 snprintf(buf
, sizeof(buf
), "%s/%s", bios_dir
, bios_name
);
301 ret
= load_elf(buf
, PROM_ADDR
- PROM_VADDR
, NULL
, NULL
, NULL
);
303 fprintf(stderr
, "qemu: could not load prom '%s'\n",
311 /* XXX: put correct offset */
312 kernel_size
= load_elf(kernel_filename
, 0, NULL
, NULL
, NULL
);
314 kernel_size
= load_aout(kernel_filename
, KERNEL_LOAD_ADDR
,
315 ram_size
- KERNEL_LOAD_ADDR
);
317 kernel_size
= load_image_targphys(kernel_filename
,
319 ram_size
- KERNEL_LOAD_ADDR
);
320 if (kernel_size
< 0) {
321 fprintf(stderr
, "qemu: could not load kernel '%s'\n",
327 if (initrd_filename
) {
328 initrd_size
= load_image_targphys(initrd_filename
,
330 ram_size
- INITRD_LOAD_ADDR
);
331 if (initrd_size
< 0) {
332 fprintf(stderr
, "qemu: could not load initial ram disk '%s'\n",
337 if (initrd_size
> 0) {
338 for (i
= 0; i
< 64 * TARGET_PAGE_SIZE
; i
+= TARGET_PAGE_SIZE
) {
339 if (ldl_phys(KERNEL_LOAD_ADDR
+ i
) == 0x48647253) { // HdrS
340 stl_phys(KERNEL_LOAD_ADDR
+ i
+ 16, INITRD_LOAD_ADDR
);
341 stl_phys(KERNEL_LOAD_ADDR
+ i
+ 20, initrd_size
);
347 pci_bus
= pci_apb_init(APB_SPECIAL_BASE
, APB_MEM_BASE
, NULL
);
348 isa_mem_base
= VGA_BASE
;
349 pci_cirrus_vga_init(pci_bus
, ds
, phys_ram_base
+ RAM_size
, RAM_size
,
352 for(i
= 0; i
< MAX_SERIAL_PORTS
; i
++) {
354 serial_init(serial_io
[i
], NULL
/*serial_irq[i]*/, 115200,
359 for(i
= 0; i
< MAX_PARALLEL_PORTS
; i
++) {
360 if (parallel_hds
[i
]) {
361 parallel_init(parallel_io
[i
], NULL
/*parallel_irq[i]*/,
366 for(i
= 0; i
< nb_nics
; i
++) {
367 if (!nd_table
[i
].model
)
368 nd_table
[i
].model
= "ne2k_pci";
369 if (!pci_nic_init(pci_bus
, &nd_table
[i
], -1))
373 irq
= qemu_allocate_irqs(dummy_cpu_set_irq
, NULL
, 32);
374 if (drive_get_max_bus(IF_IDE
) >= MAX_IDE_BUS
) {
375 fprintf(stderr
, "qemu: too many IDE bus\n");
378 for(i
= 0; i
< MAX_IDE_BUS
* MAX_IDE_DEVS
; i
++) {
379 drive_index
= drive_get_index(IF_IDE
, i
/ MAX_IDE_DEVS
,
381 if (drive_index
!= -1)
382 hd
[i
] = drives_table
[drive_index
].bdrv
;
387 // XXX pci_cmd646_ide_init(pci_bus, hd, 1);
388 pci_piix3_ide_init(pci_bus
, hd
, -1, irq
);
389 /* FIXME: wire up interrupts. */
390 i8042_init(NULL
/*1*/, NULL
/*12*/, 0x60);
391 for(i
= 0; i
< MAX_FD
; i
++) {
392 drive_index
= drive_get_index(IF_FLOPPY
, 0, i
);
393 if (drive_index
!= -1)
394 fd
[i
] = drives_table
[drive_index
].bdrv
;
398 floppy_controller
= fdctrl_init(NULL
/*6*/, 2, 0, 0x3f0, fd
);
399 nvram
= m48t59_init(NULL
/*8*/, 0, 0x0074, NVRAM_SIZE
, 59);
400 sun4u_NVRAM_set_params(nvram
, NVRAM_SIZE
, "Sun4u", RAM_size
, boot_devices
,
401 KERNEL_LOAD_ADDR
, kernel_size
,
403 INITRD_LOAD_ADDR
, initrd_size
,
404 /* XXX: need an option to load a NVRAM image */
406 graphic_width
, graphic_height
, graphic_depth
);
410 QEMUMachine sun4u_machine
= {
414 PROM_SIZE_MAX
+ VGA_RAM_SIZE
,