4 /* PCI includes legacy ISA access. */
7 /* imported from <linux/pci.h> */
8 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f)
9 #define PCI_FUNC(devfn) ((devfn) & 0x07)
12 extern target_phys_addr_t pci_mem_base
;
14 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07))
15 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f)
16 #define PCI_FUNC(devfn) ((devfn) & 0x07)
18 /* Device classes and subclasses */
20 #define PCI_BASE_CLASS_STORAGE 0x01
21 #define PCI_BASE_CLASS_NETWORK 0x02
23 #define PCI_CLASS_STORAGE_SCSI 0x0100
24 #define PCI_CLASS_STORAGE_IDE 0x0101
25 #define PCI_CLASS_STORAGE_OTHER 0x0180
27 #define PCI_CLASS_NETWORK_ETHERNET 0x0200
29 #define PCI_CLASS_DISPLAY_VGA 0x0300
30 #define PCI_CLASS_DISPLAY_OTHER 0x0380
32 #define PCI_CLASS_MULTIMEDIA_AUDIO 0x0401
34 #define PCI_CLASS_MEMORY_RAM 0x0500
36 #define PCI_CLASS_SYSTEM_OTHER 0x0880
38 #define PCI_CLASS_SERIAL_USB 0x0c03
40 #define PCI_CLASS_BRIDGE_HOST 0x0600
41 #define PCI_CLASS_BRIDGE_ISA 0x0601
42 #define PCI_CLASS_BRIDGE_PCI 0x0604
43 #define PCI_CLASS_BRIDGE_OTHER 0x0680
45 #define PCI_CLASS_PROCESSOR_CO 0x0b40
47 #define PCI_CLASS_OTHERS 0xff
49 /* Vendors and devices. */
51 #define PCI_VENDOR_ID_LSI_LOGIC 0x1000
52 #define PCI_DEVICE_ID_LSI_53C895A 0x0012
54 #define PCI_VENDOR_ID_DEC 0x1011
55 #define PCI_DEVICE_ID_DEC_21154 0x0026
57 #define PCI_VENDOR_ID_CIRRUS 0x1013
59 #define PCI_VENDOR_ID_IBM 0x1014
60 #define PCI_DEVICE_ID_IBM_OPENPIC2 0xffff
62 #define PCI_VENDOR_ID_AMD 0x1022
63 #define PCI_DEVICE_ID_AMD_LANCE 0x2000
65 #define PCI_VENDOR_ID_HITACHI 0x1054
67 #define PCI_VENDOR_ID_MOTOROLA 0x1057
68 #define PCI_DEVICE_ID_MOTOROLA_MPC106 0x0002
69 #define PCI_DEVICE_ID_MOTOROLA_RAVEN 0x4801
71 #define PCI_VENDOR_ID_APPLE 0x106b
72 #define PCI_DEVICE_ID_APPLE_343S1201 0x0010
73 #define PCI_DEVICE_ID_APPLE_UNI_N_I_PCI 0x001e
74 #define PCI_DEVICE_ID_APPLE_UNI_N_PCI 0x001f
75 #define PCI_DEVICE_ID_APPLE_UNI_N_AGP 0x0020
76 #define PCI_DEVICE_ID_APPLE_UNI_N_KEYL 0x0022
78 #define PCI_VENDOR_ID_SUN 0x108e
79 #define PCI_DEVICE_ID_SUN_EBUS 0x1000
80 #define PCI_DEVICE_ID_SUN_SIMBA 0x5000
81 #define PCI_DEVICE_ID_SUN_SABRE 0xa000
83 #define PCI_VENDOR_ID_CMD 0x1095
84 #define PCI_DEVICE_ID_CMD_646 0x0646
86 #define PCI_VENDOR_ID_REALTEK 0x10ec
87 #define PCI_DEVICE_ID_REALTEK_RTL8029 0x8029
88 #define PCI_DEVICE_ID_REALTEK_8139 0x8139
90 #define PCI_VENDOR_ID_XILINX 0x10ee
92 #define PCI_VENDOR_ID_MARVELL 0x11ab
94 #define PCI_VENDOR_ID_QEMU 0x1234
95 #define PCI_DEVICE_ID_QEMU_VGA 0x1111
97 #define PCI_VENDOR_ID_ENSONIQ 0x1274
98 #define PCI_DEVICE_ID_ENSONIQ_ES1370 0x5000
100 #define PCI_VENDOR_ID_VMWARE 0x15ad
101 #define PCI_DEVICE_ID_VMWARE_SVGA2 0x0405
102 #define PCI_DEVICE_ID_VMWARE_SVGA 0x0710
103 #define PCI_DEVICE_ID_VMWARE_NET 0x0720
104 #define PCI_DEVICE_ID_VMWARE_SCSI 0x0730
105 #define PCI_DEVICE_ID_VMWARE_IDE 0x1729
107 #define PCI_VENDOR_ID_INTEL 0x8086
108 #define PCI_DEVICE_ID_INTEL_82441 0x1237
109 #define PCI_DEVICE_ID_INTEL_82801AA_5 0x2415
110 #define PCI_DEVICE_ID_INTEL_82371SB_0 0x7000
111 #define PCI_DEVICE_ID_INTEL_82371SB_1 0x7010
112 #define PCI_DEVICE_ID_INTEL_82371SB_2 0x7020
113 #define PCI_DEVICE_ID_INTEL_82371AB_0 0x7110
114 #define PCI_DEVICE_ID_INTEL_82371AB 0x7111
115 #define PCI_DEVICE_ID_INTEL_82371AB_2 0x7112
116 #define PCI_DEVICE_ID_INTEL_82371AB_3 0x7113
118 /* Red Hat / Qumranet (for QEMU) -- see pci-ids.txt */
119 #define PCI_VENDOR_ID_REDHAT_QUMRANET 0x1af4
120 #define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4
121 #define PCI_SUBDEVICE_ID_QEMU 0x1100
123 #define PCI_DEVICE_ID_VIRTIO_NET 0x1000
124 #define PCI_DEVICE_ID_VIRTIO_BLOCK 0x1001
125 #define PCI_DEVICE_ID_VIRTIO_BALLOON 0x1002
126 #define PCI_DEVICE_ID_VIRTIO_CONSOLE 0x1003
128 typedef void PCIConfigWriteFunc(PCIDevice
*pci_dev
,
129 uint32_t address
, uint32_t data
, int len
);
130 typedef uint32_t PCIConfigReadFunc(PCIDevice
*pci_dev
,
131 uint32_t address
, int len
);
132 typedef void PCIMapIORegionFunc(PCIDevice
*pci_dev
, int region_num
,
133 uint32_t addr
, uint32_t size
, int type
);
134 typedef int PCIUnregisterFunc(PCIDevice
*pci_dev
);
136 #define PCI_ADDRESS_SPACE_MEM 0x00
137 #define PCI_ADDRESS_SPACE_IO 0x01
138 #define PCI_ADDRESS_SPACE_MEM_PREFETCH 0x08
140 typedef struct PCIIORegion
{
141 uint32_t addr
; /* current PCI mapping address. -1 means not mapped */
144 PCIMapIORegionFunc
*map_func
;
147 #define PCI_ROM_SLOT 6
148 #define PCI_NUM_REGIONS 7
150 #define PCI_DEVICES_MAX 64
152 #define PCI_VENDOR_ID 0x00 /* 16 bits */
153 #define PCI_DEVICE_ID 0x02 /* 16 bits */
154 #define PCI_COMMAND 0x04 /* 16 bits */
155 #define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
156 #define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
157 #define PCI_REVISION 0x08
158 #define PCI_CLASS_DEVICE 0x0a /* Device class */
159 #define PCI_SUBVENDOR_ID 0x2c /* 16 bits */
160 #define PCI_SUBDEVICE_ID 0x2e /* 16 bits */
161 #define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
162 #define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
163 #define PCI_MIN_GNT 0x3e /* 8 bits */
164 #define PCI_MAX_LAT 0x3f /* 8 bits */
166 /* Bits in the PCI Status Register (PCI 2.3 spec) */
167 #define PCI_STATUS_RESERVED1 0x007
168 #define PCI_STATUS_INT_STATUS 0x008
169 #define PCI_STATUS_CAPABILITIES 0x010
170 #define PCI_STATUS_66MHZ 0x020
171 #define PCI_STATUS_RESERVED2 0x040
172 #define PCI_STATUS_FAST_BACK 0x080
173 #define PCI_STATUS_DEVSEL 0x600
175 #define PCI_STATUS_RESERVED_MASK_LO (PCI_STATUS_RESERVED1 | \
176 PCI_STATUS_INT_STATUS | PCI_STATUS_CAPABILITIES | \
177 PCI_STATUS_66MHZ | PCI_STATUS_RESERVED2 | PCI_STATUS_FAST_BACK)
179 #define PCI_STATUS_RESERVED_MASK_HI (PCI_STATUS_DEVSEL >> 8)
181 /* Bits in the PCI Command Register (PCI 2.3 spec) */
182 #define PCI_COMMAND_RESERVED 0xf800
184 #define PCI_COMMAND_RESERVED_MASK_HI (PCI_COMMAND_RESERVED >> 8)
187 /* PCI config space */
190 /* the following fields are read only */
194 PCIIORegion io_regions
[PCI_NUM_REGIONS
];
196 /* do not access the following fields */
197 PCIConfigReadFunc
*config_read
;
198 PCIConfigWriteFunc
*config_write
;
199 PCIUnregisterFunc
*unregister
;
200 /* ??? This is a PC-specific hack, and should be removed. */
203 /* IRQ objects for the INTA-INTD pins. */
206 /* Current IRQ levels. Used internally by the generic PCI code. */
210 PCIDevice
*pci_register_device(PCIBus
*bus
, const char *name
,
211 int instance_size
, int devfn
,
212 PCIConfigReadFunc
*config_read
,
213 PCIConfigWriteFunc
*config_write
);
214 int pci_unregister_device(PCIDevice
*pci_dev
);
216 void pci_register_io_region(PCIDevice
*pci_dev
, int region_num
,
217 uint32_t size
, int type
,
218 PCIMapIORegionFunc
*map_func
);
220 int pci_map_irq(PCIDevice
*pci_dev
, int pin
);
221 uint32_t pci_default_read_config(PCIDevice
*d
,
222 uint32_t address
, int len
);
223 void pci_default_write_config(PCIDevice
*d
,
224 uint32_t address
, uint32_t val
, int len
);
225 void pci_device_save(PCIDevice
*s
, QEMUFile
*f
);
226 int pci_device_load(PCIDevice
*s
, QEMUFile
*f
);
228 typedef void (*pci_set_irq_fn
)(qemu_irq
*pic
, int irq_num
, int level
);
229 typedef int (*pci_map_irq_fn
)(PCIDevice
*pci_dev
, int irq_num
);
230 PCIBus
*pci_register_bus(pci_set_irq_fn set_irq
, pci_map_irq_fn map_irq
,
231 qemu_irq
*pic
, int devfn_min
, int nirq
);
233 PCIDevice
*pci_nic_init(PCIBus
*bus
, NICInfo
*nd
, int devfn
,
234 const char *default_model
);
235 void pci_data_write(void *opaque
, uint32_t addr
, uint32_t val
, int len
);
236 uint32_t pci_data_read(void *opaque
, uint32_t addr
, int len
);
237 int pci_bus_num(PCIBus
*s
);
238 void pci_for_each_device(int bus_num
, void (*fn
)(PCIDevice
*d
));
239 PCIBus
*pci_find_bus(int bus_num
);
240 PCIDevice
*pci_find_device(int bus_num
, int slot
, int function
);
242 int pci_read_devaddr(const char *addr
, int *domp
, int *busp
, unsigned *slotp
);
243 int pci_assign_devaddr(const char *addr
, int *domp
, int *busp
, unsigned *slotp
);
246 PCIBus
*pci_bridge_init(PCIBus
*bus
, int devfn
, uint16_t vid
, uint16_t did
,
247 pci_map_irq_fn map_irq
, const char *name
);
250 pci_config_set_vendor_id(uint8_t *pci_config
, uint16_t val
)
252 cpu_to_le16wu((uint16_t *)&pci_config
[PCI_VENDOR_ID
], val
);
256 pci_config_set_device_id(uint8_t *pci_config
, uint16_t val
)
258 cpu_to_le16wu((uint16_t *)&pci_config
[PCI_DEVICE_ID
], val
);
262 pci_config_set_class(uint8_t *pci_config
, uint16_t val
)
264 cpu_to_le16wu((uint16_t *)&pci_config
[PCI_CLASS_DEVICE
], val
);
268 #define LSI_MAX_DEVS 7
269 void lsi_scsi_attach(void *opaque
, BlockDriverState
*bd
, int id
);
270 void *lsi_scsi_init(PCIBus
*bus
, int devfn
);
273 void pci_vmsvga_init(PCIBus
*bus
, uint8_t *vga_ram_base
,
274 unsigned long vga_ram_offset
, int vga_ram_size
);
277 void usb_uhci_piix3_init(PCIBus
*bus
, int devfn
);
278 void usb_uhci_piix4_init(PCIBus
*bus
, int devfn
);
281 void usb_ohci_init_pci(struct PCIBus
*bus
, int num_ports
, int devfn
);
285 PCIDevice
*pci_i82551_init(PCIBus
*bus
, NICInfo
*nd
, int devfn
);
286 PCIDevice
*pci_i82557b_init(PCIBus
*bus
, NICInfo
*nd
, int devfn
);
287 PCIDevice
*pci_i82559er_init(PCIBus
*bus
, NICInfo
*nd
, int devfn
);
291 PCIDevice
*pci_ne2000_init(PCIBus
*bus
, NICInfo
*nd
, int devfn
);
295 PCIDevice
*pci_rtl8139_init(PCIBus
*bus
, NICInfo
*nd
, int devfn
);
298 PCIDevice
*pci_e1000_init(PCIBus
*bus
, NICInfo
*nd
, int devfn
);
301 PCIDevice
*pci_pcnet_init(PCIBus
*bus
, NICInfo
*nd
, int devfn
);
304 PCIBus
*pci_prep_init(qemu_irq
*pic
);
307 PCIBus
*pci_apb_init(target_phys_addr_t special_base
,
308 target_phys_addr_t mem_base
,
309 qemu_irq
*pic
, PCIBus
**bus2
, PCIBus
**bus3
);
312 PCIBus
*sh_pci_register_bus(pci_set_irq_fn set_irq
, pci_map_irq_fn map_irq
,
313 qemu_irq
*pic
, int devfn_min
, int nirq
);