hw/ioapic.c

   1 /*
   2  *  ioapic.c IOAPIC emulation logic
   3  *
   4  *  Copyright (c) 2004-2005 Fabrice Bellard
   5  *
   6  *  Split the ioapic logic from apic.c
   7  *  Xiantao Zhang <xiantao.zhang@intel.com>
   8  *
   9  * This library is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU Lesser General Public
  11  * License as published by the Free Software Foundation; either
  12  * version 2 of the License, or (at your option) any later version.
  13  *
  14  * This library is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  17  * Lesser General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU Lesser General Public
  20  * License along with this library; if not, write to the Free Software
  21  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA  02110-1301 USA
  22  */
  23
  24 #include "hw.h"
  25 #include "pc.h"
  26 #include "qemu-timer.h"
  27 #include "host-utils.h"
  28
  29 #include "qemu-kvm.h"
  30
  31 //#define DEBUG_IOAPIC
  32
  33 #define IOAPIC_NUM_PINS                 0x18
  34 #define IOAPIC_DEFAULT_BASE_ADDRESS  0xfec00000
  35 #define IOAPIC_LVT_MASKED               (1<<16)
  36
  37 #define IOAPIC_TRIGGER_EDGE             0
  38 #define IOAPIC_TRIGGER_LEVEL            1
  39
  40 /*io{apic,sapic} delivery mode*/
  41 #define IOAPIC_DM_FIXED                 0x0
  42 #define IOAPIC_DM_LOWEST_PRIORITY       0x1
  43 #define IOAPIC_DM_PMI                   0x2
  44 #define IOAPIC_DM_NMI                   0x4
  45 #define IOAPIC_DM_INIT                  0x5
  46 #define IOAPIC_DM_SIPI                  0x5
  47 #define IOAPIC_DM_EXTINT                0x7
  48
  49 struct IOAPICState {
  50     uint8_t id;
  51     uint8_t ioregsel;
  52     uint64_t base_address;
  53
  54     uint32_t irr;
  55     uint64_t ioredtbl[IOAPIC_NUM_PINS];
  56 };
  57
  58 static void ioapic_service(IOAPICState *s)
  59 {
  60     uint8_t i;
  61     uint8_t trig_mode;
  62     uint8_t vector;
  63     uint8_t delivery_mode;
  64     uint32_t mask;
  65     uint64_t entry;
  66     uint8_t dest;
  67     uint8_t dest_mode;
  68     uint8_t polarity;
  69
  70     for (i = 0; i < IOAPIC_NUM_PINS; i++) {
  71         mask = 1 << i;
  72         if (s->irr & mask) {
  73             entry = s->ioredtbl[i];
  74             if (!(entry & IOAPIC_LVT_MASKED)) {
  75                 trig_mode = ((entry >> 15) & 1);
  76                 dest = entry >> 56;
  77                 dest_mode = (entry >> 11) & 1;
  78                 delivery_mode = (entry >> 8) & 7;
  79                 polarity = (entry >> 13) & 1;
  80                 if (trig_mode == IOAPIC_TRIGGER_EDGE)
  81                     s->irr &= ~mask;
  82                 if (delivery_mode == IOAPIC_DM_EXTINT)
  83                     vector = pic_read_irq(isa_pic);
  84                 else
  85                     vector = entry & 0xff;
  86
  87                 apic_deliver_irq(dest, dest_mode, delivery_mode,
  88                                  vector, polarity, trig_mode);
  89             }
  90         }
  91     }
  92 }
  93
  94 void ioapic_set_irq(void *opaque, int vector, int level)
  95 {
  96     IOAPICState *s = opaque;
  97
  98 #if 0
  99     /* ISA IRQs map to GSI 1-1 except for IRQ0 which maps
 100      * to GSI 2.  GSI maps to ioapic 1-1.  This is not
 101      * the cleanest way of doing it but it should work. */
 102
 103     if (vector == 0)
 104         vector = 2;
 105 #endif
 106
 107     if (vector >= 0 && vector < IOAPIC_NUM_PINS) {
 108         uint32_t mask = 1 << vector;
 109         uint64_t entry = s->ioredtbl[vector];
 110
 111         if ((entry >> 15) & 1) {
 112             /* level triggered */
 113             if (level) {
 114                 s->irr |= mask;
 115                 ioapic_service(s);
 116             } else {
 117                 s->irr &= ~mask;
 118             }
 119         } else {
 120             /* edge triggered */
 121             if (level) {
 122                 s->irr |= mask;
 123                 ioapic_service(s);
 124             }
 125         }
 126     }
 127 }
 128
 129 static uint32_t ioapic_mem_readl(void *opaque, target_phys_addr_t addr)
 130 {
 131     IOAPICState *s = opaque;
 132     int index;
 133     uint32_t val = 0;
 134
 135     addr &= 0xff;
 136     if (addr == 0x00) {
 137         val = s->ioregsel;
 138     } else if (addr == 0x10) {
 139         switch (s->ioregsel) {
 140             case 0x00:
 141                 val = s->id << 24;
 142                 break;
 143             case 0x01:
 144                 val = 0x11 | ((IOAPIC_NUM_PINS - 1) << 16); /* version 0x11 */
 145                 break;
 146             case 0x02:
 147                 val = 0;
 148                 break;
 149             default:
 150                 index = (s->ioregsel - 0x10) >> 1;
 151                 if (index >= 0 && index < IOAPIC_NUM_PINS) {
 152                     if (s->ioregsel & 1)
 153                         val = s->ioredtbl[index] >> 32;
 154                     else
 155                         val = s->ioredtbl[index] & 0xffffffff;
 156                 }
 157         }
 158 #ifdef DEBUG_IOAPIC
 159         printf("I/O APIC read: %08x = %08x\n", s->ioregsel, val);
 160 #endif
 161     }
 162     return val;
 163 }
 164
 165 static void ioapic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
 166 {
 167     IOAPICState *s = opaque;
 168     int index;
 169
 170     addr &= 0xff;
 171     if (addr == 0x00)  {
 172         s->ioregsel = val;
 173         return;
 174     } else if (addr == 0x10) {
 175 #ifdef DEBUG_IOAPIC
 176         printf("I/O APIC write: %08x = %08x\n", s->ioregsel, val);
 177 #endif
 178         switch (s->ioregsel) {
 179             case 0x00:
 180                 s->id = (val >> 24) & 0xff;
 181                 return;
 182             case 0x01:
 183             case 0x02:
 184                 return;
 185             default:
 186                 index = (s->ioregsel - 0x10) >> 1;
 187                 if (index >= 0 && index < IOAPIC_NUM_PINS) {
 188                     if (s->ioregsel & 1) {
 189                         s->ioredtbl[index] &= 0xffffffff;
 190                         s->ioredtbl[index] |= (uint64_t)val << 32;
 191                     } else {
 192                         s->ioredtbl[index] &= ~0xffffffffULL;
 193                         s->ioredtbl[index] |= val;
 194                     }
 195                     ioapic_service(s);
 196                 }
 197         }
 198     }
 199 }
 200
 201 static void kvm_kernel_ioapic_save_to_user(IOAPICState *s)
 202 {
 203 #if defined(KVM_CAP_IRQCHIP) && defined(TARGET_I386)
 204     struct kvm_irqchip chip;
 205     struct kvm_ioapic_state *kioapic;
 206     int i;
 207
 208     chip.chip_id = KVM_IRQCHIP_IOAPIC;
 209     kvm_get_irqchip(kvm_context, &chip);
 210     kioapic = &chip.chip.ioapic;
 211
 212     s->id = kioapic->id;
 213     s->ioregsel = kioapic->ioregsel;
 214     s->base_address = kioapic->base_address;
 215     s->irr = kioapic->irr;
 216     for (i = 0; i < IOAPIC_NUM_PINS; i++) {
 217         s->ioredtbl[i] = kioapic->redirtbl[i].bits;
 218     }
 219 #endif
 220 }
 221
 222 static void kvm_kernel_ioapic_load_from_user(IOAPICState *s)
 223 {
 224 #if defined(KVM_CAP_IRQCHIP) && defined(TARGET_I386)
 225     struct kvm_irqchip chip;
 226     struct kvm_ioapic_state *kioapic;
 227     int i;
 228
 229     chip.chip_id = KVM_IRQCHIP_IOAPIC;
 230     kioapic = &chip.chip.ioapic;
 231
 232     kioapic->id = s->id;
 233     kioapic->ioregsel = s->ioregsel;
 234     kioapic->base_address = s->base_address;
 235     kioapic->irr = s->irr;
 236     for (i = 0; i < IOAPIC_NUM_PINS; i++) {
 237         kioapic->redirtbl[i].bits = s->ioredtbl[i];
 238     }
 239
 240     kvm_set_irqchip(kvm_context, &chip);
 241 #endif
 242 }
 243
 244 static void ioapic_save(QEMUFile *f, void *opaque)
 245 {
 246     IOAPICState *s = opaque;
 247     int i;
 248
 249     if (kvm_enabled() && qemu_kvm_irqchip_in_kernel()) {
 250         kvm_kernel_ioapic_save_to_user(s);
 251     }
 252
 253     qemu_put_8s(f, &s->id);
 254     qemu_put_8s(f, &s->ioregsel);
 255     qemu_put_be64s(f, &s->base_address);
 256     qemu_put_be32s(f, &s->irr);
 257     for (i = 0; i < IOAPIC_NUM_PINS; i++) {
 258         qemu_put_be64s(f, &s->ioredtbl[i]);
 259     }
 260 }
 261
 262 static int ioapic_load(QEMUFile *f, void *opaque, int version_id)
 263 {
 264     IOAPICState *s = opaque;
 265     int i;
 266
 267     if (version_id < 1 || version_id > 2)
 268         return -EINVAL;
 269
 270     qemu_get_8s(f, &s->id);
 271     qemu_get_8s(f, &s->ioregsel);
 272     if (version_id == 2) {
 273       /* for version 2, we get this data off of the wire */
 274       qemu_get_be64s(f, &s->base_address);
 275       qemu_get_be32s(f, &s->irr);
 276     }
 277     else {
 278       /* in case we are doing version 1, we just set these to sane values */
 279       s->base_address = IOAPIC_DEFAULT_BASE_ADDRESS;
 280       s->irr = 0;
 281     }
 282     for (i = 0; i < IOAPIC_NUM_PINS; i++) {
 283         qemu_get_be64s(f, &s->ioredtbl[i]);
 284     }
 285
 286     if (kvm_enabled() && qemu_kvm_irqchip_in_kernel()) {
 287         kvm_kernel_ioapic_load_from_user(s);
 288     }
 289
 290     return 0;
 291 }
 292
 293 static void ioapic_reset(void *opaque)
 294 {
 295     IOAPICState *s = opaque;
 296     int i;
 297
 298     memset(s, 0, sizeof(*s));
 299     s->base_address = IOAPIC_DEFAULT_BASE_ADDRESS;
 300     for(i = 0; i < IOAPIC_NUM_PINS; i++)
 301         s->ioredtbl[i] = 1 << 16; /* mask LVT */
 302 #ifdef KVM_CAP_IRQCHIP
 303     if (kvm_enabled() && qemu_kvm_irqchip_in_kernel()) {
 304         kvm_kernel_ioapic_load_from_user(s);
 305     }
 306 #endif
 307 }
 308
 309 static CPUReadMemoryFunc *ioapic_mem_read[3] = {
 310     ioapic_mem_readl,
 311     ioapic_mem_readl,
 312     ioapic_mem_readl,
 313 };
 314
 315 static CPUWriteMemoryFunc *ioapic_mem_write[3] = {
 316     ioapic_mem_writel,
 317     ioapic_mem_writel,
 318     ioapic_mem_writel,
 319 };
 320
 321 IOAPICState *ioapic_init(void)
 322 {
 323     IOAPICState *s;
 324     int io_memory;
 325
 326     s = qemu_mallocz(sizeof(IOAPICState));
 327     ioapic_reset(s);
 328
 329     io_memory = cpu_register_io_memory(0, ioapic_mem_read,
 330                                        ioapic_mem_write, s);
 331     cpu_register_physical_memory(0xfec00000, 0x1000, io_memory);
 332
 333     register_savevm("ioapic", 0, 2, ioapic_save, ioapic_load, s);
 334     qemu_register_reset(ioapic_reset, s);
 335
 336     return s;
 337 }