hw/sun4u.c

   1 /*
   2  * QEMU Sun4u System Emulator
   3  *
   4  * Copyright (c) 2005 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "pci.h"
  26 #include "pc.h"
  27 #include "nvram.h"
  28 #include "fdc.h"
  29 #include "net.h"
  30 #include "qemu-timer.h"
  31 #include "sysemu.h"
  32 #include "boards.h"
  33 #include "firmware_abi.h"
  34
  35 #define KERNEL_LOAD_ADDR     0x00404000
  36 #define CMDLINE_ADDR         0x003ff000
  37 #define INITRD_LOAD_ADDR     0x00300000
  38 #define PROM_SIZE_MAX        (4 * 1024 * 1024)
  39 #define PROM_ADDR            0x1fff0000000ULL
  40 #define PROM_VADDR           0x000ffd00000ULL
  41 #define APB_SPECIAL_BASE     0x1fe00000000ULL
  42 #define APB_MEM_BASE         0x1ff00000000ULL
  43 #define VGA_BASE             (APB_MEM_BASE + 0x400000ULL)
  44 #define PROM_FILENAME        "openbios-sparc64"
  45 #define NVRAM_SIZE           0x2000
  46 #define MAX_IDE_BUS          2
  47
  48 int DMA_get_channel_mode (int nchan)
  49 {
  50     return 0;
  51 }
  52 int DMA_read_memory (int nchan, void *buf, int pos, int size)
  53 {
  54     return 0;
  55 }
  56 int DMA_write_memory (int nchan, void *buf, int pos, int size)
  57 {
  58     return 0;
  59 }
  60 void DMA_hold_DREQ (int nchan) {}
  61 void DMA_release_DREQ (int nchan) {}
  62 void DMA_schedule(int nchan) {}
  63 void DMA_run (void) {}
  64 void DMA_init (int high_page_enable) {}
  65 void DMA_register_channel (int nchan,
  66                            DMA_transfer_handler transfer_handler,
  67                            void *opaque)
  68 {
  69 }
  70
  71 static int nvram_boot_set(void *opaque, const char *boot_device)
  72 {
  73     unsigned int i;
  74     uint8_t image[sizeof(ohwcfg_v3_t)];
  75     ohwcfg_v3_t *header = (ohwcfg_v3_t *)&image;
  76     m48t59_t *nvram = (m48t59_t *)opaque;
  77
  78     for (i = 0; i < sizeof(image); i++)
  79         image[i] = m48t59_read(nvram, i) & 0xff;
  80
  81     strcpy((char *)header->boot_devices, boot_device);
  82     header->nboot_devices = strlen(boot_device) & 0xff;
  83     header->crc = cpu_to_be16(OHW_compute_crc(header, 0x00, 0xF8));
  84
  85     for (i = 0; i < sizeof(image); i++)
  86         m48t59_write(nvram, i, image[i]);
  87
  88     return 0;
  89 }
  90
  91 extern int nographic;
  92
  93 static int sun4u_NVRAM_set_params (m48t59_t *nvram, uint16_t NVRAM_size,
  94                                    const char *arch,
  95                                    ram_addr_t RAM_size,
  96                                    const char *boot_devices,
  97                                    uint32_t kernel_image, uint32_t kernel_size,
  98                                    const char *cmdline,
  99                                    uint32_t initrd_image, uint32_t initrd_size,
 100                                    uint32_t NVRAM_image,
 101                                    int width, int height, int depth)
 102 {
 103     unsigned int i;
 104     uint32_t start, end;
 105     uint8_t image[0x1ff0];
 106     ohwcfg_v3_t *header = (ohwcfg_v3_t *)&image;
 107     struct sparc_arch_cfg *sparc_header;
 108     struct OpenBIOS_nvpart_v1 *part_header;
 109
 110     memset(image, '\0', sizeof(image));
 111
 112     // Try to match PPC NVRAM
 113     strcpy((char *)header->struct_ident, "QEMU_BIOS");
 114     header->struct_version = cpu_to_be32(3); /* structure v3 */
 115
 116     header->nvram_size = cpu_to_be16(NVRAM_size);
 117     header->nvram_arch_ptr = cpu_to_be16(sizeof(ohwcfg_v3_t));
 118     header->nvram_arch_size = cpu_to_be16(sizeof(struct sparc_arch_cfg));
 119     strcpy((char *)header->arch, arch);
 120     header->nb_cpus = smp_cpus & 0xff;
 121     header->RAM0_base = 0;
 122     header->RAM0_size = cpu_to_be64((uint64_t)RAM_size);
 123     strcpy((char *)header->boot_devices, boot_devices);
 124     header->nboot_devices = strlen(boot_devices) & 0xff;
 125     header->kernel_image = cpu_to_be64((uint64_t)kernel_image);
 126     header->kernel_size = cpu_to_be64((uint64_t)kernel_size);
 127     if (cmdline) {
 128         pstrcpy_targphys(CMDLINE_ADDR, TARGET_PAGE_SIZE, cmdline);
 129         header->cmdline = cpu_to_be64((uint64_t)CMDLINE_ADDR);
 130         header->cmdline_size = cpu_to_be64((uint64_t)strlen(cmdline));
 131     }
 132     header->initrd_image = cpu_to_be64((uint64_t)initrd_image);
 133     header->initrd_size = cpu_to_be64((uint64_t)initrd_size);
 134     header->NVRAM_image = cpu_to_be64((uint64_t)NVRAM_image);
 135
 136     header->width = cpu_to_be16(width);
 137     header->height = cpu_to_be16(height);
 138     header->depth = cpu_to_be16(depth);
 139     if (nographic)
 140         header->graphic_flags = cpu_to_be16(OHW_GF_NOGRAPHICS);
 141
 142     header->crc = cpu_to_be16(OHW_compute_crc(header, 0x00, 0xF8));
 143
 144     // Architecture specific header
 145     start = sizeof(ohwcfg_v3_t);
 146     sparc_header = (struct sparc_arch_cfg *)&image[start];
 147     sparc_header->valid = 0;
 148     start += sizeof(struct sparc_arch_cfg);
 149
 150     // OpenBIOS nvram variables
 151     // Variable partition
 152     part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
 153     part_header->signature = OPENBIOS_PART_SYSTEM;
 154     strcpy(part_header->name, "system");
 155
 156     end = start + sizeof(struct OpenBIOS_nvpart_v1);
 157     for (i = 0; i < nb_prom_envs; i++)
 158         end = OpenBIOS_set_var(image, end, prom_envs[i]);
 159
 160     // End marker
 161     image[end++] = '\0';
 162
 163     end = start + ((end - start + 15) & ~15);
 164     OpenBIOS_finish_partition(part_header, end - start);
 165
 166     // free partition
 167     start = end;
 168     part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
 169     part_header->signature = OPENBIOS_PART_FREE;
 170     strcpy(part_header->name, "free");
 171
 172     end = 0x1fd0;
 173     OpenBIOS_finish_partition(part_header, end - start);
 174
 175     for (i = 0; i < sizeof(image); i++)
 176         m48t59_write(nvram, i, image[i]);
 177
 178     qemu_register_boot_set(nvram_boot_set, nvram);
 179
 180     return 0;
 181 }
 182
 183 void pic_info(void)
 184 {
 185 }
 186
 187 void irq_info(void)
 188 {
 189 }
 190
 191 void qemu_system_powerdown(void)
 192 {
 193 }
 194
 195 static void main_cpu_reset(void *opaque)
 196 {
 197     CPUState *env = opaque;
 198
 199     cpu_reset(env);
 200     ptimer_set_limit(env->tick, 0x7fffffffffffffffULL, 1);
 201     ptimer_run(env->tick, 0);
 202     ptimer_set_limit(env->stick, 0x7fffffffffffffffULL, 1);
 203     ptimer_run(env->stick, 0);
 204     ptimer_set_limit(env->hstick, 0x7fffffffffffffffULL, 1);
 205     ptimer_run(env->hstick, 0);
 206 }
 207
 208 static void tick_irq(void *opaque)
 209 {
 210     CPUState *env = opaque;
 211
 212     cpu_interrupt(env, CPU_INTERRUPT_TIMER);
 213 }
 214
 215 static void stick_irq(void *opaque)
 216 {
 217     CPUState *env = opaque;
 218
 219     cpu_interrupt(env, CPU_INTERRUPT_TIMER);
 220 }
 221
 222 static void hstick_irq(void *opaque)
 223 {
 224     CPUState *env = opaque;
 225
 226     cpu_interrupt(env, CPU_INTERRUPT_TIMER);
 227 }
 228
 229 static void dummy_cpu_set_irq(void *opaque, int irq, int level)
 230 {
 231 }
 232
 233 static const int ide_iobase[2] = { 0x1f0, 0x170 };
 234 static const int ide_iobase2[2] = { 0x3f6, 0x376 };
 235 static const int ide_irq[2] = { 14, 15 };
 236
 237 static const int serial_io[MAX_SERIAL_PORTS] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 };
 238 static const int serial_irq[MAX_SERIAL_PORTS] = { 4, 3, 4, 3 };
 239
 240 static const int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc };
 241 static const int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 };
 242
 243 static fdctrl_t *floppy_controller;
 244
 245 /* Sun4u hardware initialisation */
 246 static void sun4u_init(ram_addr_t RAM_size, int vga_ram_size,
 247                        const char *boot_devices, DisplayState *ds,
 248                        const char *kernel_filename, const char *kernel_cmdline,
 249                        const char *initrd_filename, const char *cpu_model)
 250 {
 251     CPUState *env;
 252     char buf[1024];
 253     m48t59_t *nvram;
 254     int ret, linux_boot;
 255     unsigned int i;
 256     long prom_offset, initrd_size, kernel_size;
 257     PCIBus *pci_bus;
 258     QEMUBH *bh;
 259     qemu_irq *irq;
 260     int drive_index;
 261     BlockDriverState *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
 262     BlockDriverState *fd[MAX_FD];
 263
 264     linux_boot = (kernel_filename != NULL);
 265
 266     /* init CPUs */
 267     if (cpu_model == NULL)
 268         cpu_model = "TI UltraSparc II";
 269     env = cpu_init(cpu_model);
 270     if (!env) {
 271         fprintf(stderr, "Unable to find Sparc CPU definition\n");
 272         exit(1);
 273     }
 274     bh = qemu_bh_new(tick_irq, env);
 275     env->tick = ptimer_init(bh);
 276     ptimer_set_period(env->tick, 1ULL);
 277
 278     bh = qemu_bh_new(stick_irq, env);
 279     env->stick = ptimer_init(bh);
 280     ptimer_set_period(env->stick, 1ULL);
 281
 282     bh = qemu_bh_new(hstick_irq, env);
 283     env->hstick = ptimer_init(bh);
 284     ptimer_set_period(env->hstick, 1ULL);
 285     qemu_register_reset(main_cpu_reset, env);
 286     main_cpu_reset(env);
 287
 288     /* allocate RAM */
 289     cpu_register_physical_memory(0, RAM_size, 0);
 290
 291     prom_offset = RAM_size + vga_ram_size;
 292     cpu_register_physical_memory(PROM_ADDR,
 293                                  (PROM_SIZE_MAX + TARGET_PAGE_SIZE) &
 294                                  TARGET_PAGE_MASK,
 295                                  prom_offset | IO_MEM_ROM);
 296
 297     if (bios_name == NULL)
 298         bios_name = PROM_FILENAME;
 299     snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
 300     ret = load_elf(buf, PROM_ADDR - PROM_VADDR, NULL, NULL, NULL);
 301     if (ret < 0) {
 302         fprintf(stderr, "qemu: could not load prom '%s'\n",
 303                 buf);
 304         exit(1);
 305     }
 306
 307     kernel_size = 0;
 308     initrd_size = 0;
 309     if (linux_boot) {
 310         /* XXX: put correct offset */
 311         kernel_size = load_elf(kernel_filename, 0, NULL, NULL, NULL);
 312         if (kernel_size < 0)
 313             kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR,
 314                                     ram_size - KERNEL_LOAD_ADDR);
 315         if (kernel_size < 0)
 316             kernel_size = load_image_targphys(kernel_filename,
 317                                               KERNEL_LOAD_ADDR,
 318                                               ram_size - KERNEL_LOAD_ADDR);
 319         if (kernel_size < 0) {
 320             fprintf(stderr, "qemu: could not load kernel '%s'\n",
 321                     kernel_filename);
 322             exit(1);
 323         }
 324
 325         /* load initrd */
 326         if (initrd_filename) {
 327             initrd_size = load_image_targphys(initrd_filename,
 328                                               INITRD_LOAD_ADDR,
 329                                               ram_size - INITRD_LOAD_ADDR);
 330             if (initrd_size < 0) {
 331                 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
 332                         initrd_filename);
 333                 exit(1);
 334             }
 335         }
 336         if (initrd_size > 0) {
 337             for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
 338                 if (ldl_phys(KERNEL_LOAD_ADDR + i) == 0x48647253) { // HdrS
 339                     stl_phys(KERNEL_LOAD_ADDR + i + 16, INITRD_LOAD_ADDR);
 340                     stl_phys(KERNEL_LOAD_ADDR + i + 20, initrd_size);
 341                     break;
 342                 }
 343             }
 344         }
 345     }
 346     pci_bus = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE, NULL);
 347     isa_mem_base = VGA_BASE;
 348     pci_cirrus_vga_init(pci_bus, ds, phys_ram_base + RAM_size, RAM_size,
 349                         vga_ram_size);
 350
 351     for(i = 0; i < MAX_SERIAL_PORTS; i++) {
 352         if (serial_hds[i]) {
 353             serial_init(serial_io[i], NULL/*serial_irq[i]*/, 115200,
 354                         serial_hds[i]);
 355         }
 356     }
 357
 358     for(i = 0; i < MAX_PARALLEL_PORTS; i++) {
 359         if (parallel_hds[i]) {
 360             parallel_init(parallel_io[i], NULL/*parallel_irq[i]*/,
 361                           parallel_hds[i]);
 362         }
 363     }
 364
 365     for(i = 0; i < nb_nics; i++) {
 366         if (!nd_table[i].model)
 367             nd_table[i].model = "ne2k_pci";
 368         if (!pci_nic_init(pci_bus, &nd_table[i], -1))
 369             exit(1);
 370     }
 371
 372     irq = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, 32);
 373     if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) {
 374         fprintf(stderr, "qemu: too many IDE bus\n");
 375         exit(1);
 376     }
 377     for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) {
 378         drive_index = drive_get_index(IF_IDE, i / MAX_IDE_DEVS,
 379                                       i % MAX_IDE_DEVS);
 380        if (drive_index != -1)
 381            hd[i] = drives_table[drive_index].bdrv;
 382        else
 383            hd[i] = NULL;
 384     }
 385
 386     // XXX pci_cmd646_ide_init(pci_bus, hd, 1);
 387     pci_piix3_ide_init(pci_bus, hd, -1, irq);
 388     /* FIXME: wire up interrupts.  */
 389     i8042_init(NULL/*1*/, NULL/*12*/, 0x60);
 390     for(i = 0; i < MAX_FD; i++) {
 391         drive_index = drive_get_index(IF_FLOPPY, 0, i);
 392        if (drive_index != -1)
 393            fd[i] = drives_table[drive_index].bdrv;
 394        else
 395            fd[i] = NULL;
 396     }
 397     floppy_controller = fdctrl_init(NULL/*6*/, 2, 0, 0x3f0, fd);
 398     nvram = m48t59_init(NULL/*8*/, 0, 0x0074, NVRAM_SIZE, 59);
 399     sun4u_NVRAM_set_params(nvram, NVRAM_SIZE, "Sun4u", RAM_size, boot_devices,
 400                          KERNEL_LOAD_ADDR, kernel_size,
 401                          kernel_cmdline,
 402                          INITRD_LOAD_ADDR, initrd_size,
 403                          /* XXX: need an option to load a NVRAM image */
 404                          0,
 405                          graphic_width, graphic_height, graphic_depth);
 406
 407 }
 408
 409 QEMUMachine sun4u_machine = {
 410     "sun4u",
 411     "Sun4u platform",
 412     sun4u_init,
 413     PROM_SIZE_MAX + VGA_RAM_SIZE,
 414 };