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kvm: external module: fix anon_inodes for 2.6.22
[qemu-kvm/fedora.git] / hw / mips_malta.c
blob1d6532624dd9c594e216b84e065f66e97eab4c62
1 /*
2 * QEMU Malta board support
3 *
4 * Copyright (c) 2006 Aurelien Jarno
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #include "hw.h"
26 #include "pc.h"
27 #include "fdc.h"
28 #include "net.h"
29 #include "boards.h"
30 #include "smbus.h"
31 #include "block.h"
32 #include "flash.h"
33 #include "mips.h"
34 #include "pci.h"
35 #include "qemu-char.h"
36 #include "sysemu.h"
37 #include "audio/audio.h"
38 #include "boards.h"
39
40 //#define DEBUG_BOARD_INIT
41
42 #ifdef TARGET_WORDS_BIGENDIAN
43 #define BIOS_FILENAME "mips_bios.bin"
44 #else
45 #define BIOS_FILENAME "mipsel_bios.bin"
46 #endif
47
48 #ifdef TARGET_MIPS64
49 #define PHYS_TO_VIRT(x) ((x) | ~0x7fffffffULL)
50 #else
51 #define PHYS_TO_VIRT(x) ((x) | ~0x7fffffffU)
52 #endif
53
54 #define ENVP_ADDR (int32_t)0x80002000
55 #define VIRT_TO_PHYS_ADDEND (-((int64_t)(int32_t)0x80000000))
56
57 #define ENVP_NB_ENTRIES 16
58 #define ENVP_ENTRY_SIZE 256
59
60 #define MAX_IDE_BUS 2
61
62 extern FILE *logfile;
63
64 typedef struct {
65 uint32_t leds;
66 uint32_t brk;
67 uint32_t gpout;
68 uint32_t i2cin;
69 uint32_t i2coe;
70 uint32_t i2cout;
71 uint32_t i2csel;
72 CharDriverState *display;
73 char display_text[9];
74 SerialState *uart;
75 } MaltaFPGAState;
76
77 static PITState *pit;
78
79 static struct _loaderparams {
80 int ram_size;
81 const char *kernel_filename;
82 const char *kernel_cmdline;
83 const char *initrd_filename;
84 } loaderparams;
85
86 /* Malta FPGA */
87 static void malta_fpga_update_display(void *opaque)
88 {
89 char leds_text[9];
90 int i;
91 MaltaFPGAState *s = opaque;
92
93 for (i = 7 ; i >= 0 ; i--) {
94 if (s->leds & (1 << i))
95 leds_text[i] = '#';
96 else
97 leds_text[i] = ' ';
98 }
99 leds_text[8] = '\0';
100
101 qemu_chr_printf(s->display, "\e[H\n\n|\e[32m%-8.8s\e[00m|\r\n", leds_text);
102 qemu_chr_printf(s->display, "\n\n\n\n|\e[31m%-8.8s\e[00m|", s->display_text);
103 }
104
105 /*
106 * EEPROM 24C01 / 24C02 emulation.
107 *
108 * Emulation for serial EEPROMs:
109 * 24C01 - 1024 bit (128 x 8)
110 * 24C02 - 2048 bit (256 x 8)
111 *
112 * Typical device names include Microchip 24C02SC or SGS Thomson ST24C02.
113 */
114
115 //~ #define DEBUG
116
117 #if defined(DEBUG)
118 # define logout(fmt, args...) fprintf(stderr, "MALTA\t%-24s" fmt, __func__, ##args)
119 #else
120 # define logout(fmt, args...) ((void)0)
121 #endif
122
123 struct _eeprom24c0x_t {
124 uint8_t tick;
125 uint8_t address;
126 uint8_t command;
127 uint8_t ack;
128 uint8_t scl;
129 uint8_t sda;
130 uint8_t data;
131 //~ uint16_t size;
132 uint8_t contents[256];
133 };
134
135 typedef struct _eeprom24c0x_t eeprom24c0x_t;
136
137 static eeprom24c0x_t eeprom = {
138 contents: {
139 /* 00000000: */ 0x80,0x08,0x04,0x0D,0x0A,0x01,0x40,0x00,
140 /* 00000008: */ 0x01,0x75,0x54,0x00,0x82,0x08,0x00,0x01,
141 /* 00000010: */ 0x8F,0x04,0x02,0x01,0x01,0x00,0x0E,0x00,
142 /* 00000018: */ 0x00,0x00,0x00,0x14,0x0F,0x14,0x2D,0x40,
143 /* 00000020: */ 0x15,0x08,0x15,0x08,0x00,0x00,0x00,0x00,
144 /* 00000028: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
145 /* 00000030: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
146 /* 00000038: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x12,0xD0,
147 /* 00000040: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
148 /* 00000048: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
149 /* 00000050: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
150 /* 00000058: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
151 /* 00000060: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
152 /* 00000068: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
153 /* 00000070: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
154 /* 00000078: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x64,0xF4,
155 },
156 };
157
158 static uint8_t eeprom24c0x_read()
159 {
160 logout("%u: scl = %u, sda = %u, data = 0x%02x\n",
161 eeprom.tick, eeprom.scl, eeprom.sda, eeprom.data);
162 return eeprom.sda;
163 }
164
165 static void eeprom24c0x_write(int scl, int sda)
166 {
167 if (eeprom.scl && scl && (eeprom.sda != sda)) {
168 logout("%u: scl = %u->%u, sda = %u->%u i2c %s\n",
169 eeprom.tick, eeprom.scl, scl, eeprom.sda, sda, sda ? "stop" : "start");
170 if (!sda) {
171 eeprom.tick = 1;
172 eeprom.command = 0;
173 }
174 } else if (eeprom.tick == 0 && !eeprom.ack) {
175 /* Waiting for start. */
176 logout("%u: scl = %u->%u, sda = %u->%u wait for i2c start\n",
177 eeprom.tick, eeprom.scl, scl, eeprom.sda, sda);
178 } else if (!eeprom.scl && scl) {
179 logout("%u: scl = %u->%u, sda = %u->%u trigger bit\n",
180 eeprom.tick, eeprom.scl, scl, eeprom.sda, sda);
181 if (eeprom.ack) {
182 logout("\ti2c ack bit = 0\n");
183 sda = 0;
184 eeprom.ack = 0;
185 } else if (eeprom.sda == sda) {
186 uint8_t bit = (sda != 0);
187 logout("\ti2c bit = %d\n", bit);
188 if (eeprom.tick < 9) {
189 eeprom.command <<= 1;
190 eeprom.command += bit;
191 eeprom.tick++;
192 if (eeprom.tick == 9) {
193 logout("\tcommand 0x%04x, %s\n", eeprom.command, bit ? "read" : "write");
194 eeprom.ack = 1;
195 }
196 } else if (eeprom.tick < 17) {
197 if (eeprom.command & 1) {
198 sda = ((eeprom.data & 0x80) != 0);
199 }
200 eeprom.address <<= 1;
201 eeprom.address += bit;
202 eeprom.tick++;
203 eeprom.data <<= 1;
204 if (eeprom.tick == 17) {
205 eeprom.data = eeprom.contents[eeprom.address];
206 logout("\taddress 0x%04x, data 0x%02x\n", eeprom.address, eeprom.data);
207 eeprom.ack = 1;
208 eeprom.tick = 0;
209 }
210 } else if (eeprom.tick >= 17) {
211 sda = 0;
212 }
213 } else {
214 logout("\tsda changed with raising scl\n");
215 }
216 } else {
217 logout("%u: scl = %u->%u, sda = %u->%u\n", eeprom.tick, eeprom.scl, scl, eeprom.sda, sda);
218 }
219 eeprom.scl = scl;
220 eeprom.sda = sda;
221 }
222
223 static uint32_t malta_fpga_readl(void *opaque, target_phys_addr_t addr)
224 {
225 MaltaFPGAState *s = opaque;
226 uint32_t val = 0;
227 uint32_t saddr;
228
229 saddr = (addr & 0xfffff);
230
231 switch (saddr) {
232
233 /* SWITCH Register */
234 case 0x00200:
235 val = 0x00000000; /* All switches closed */
236 break;
237
238 /* STATUS Register */
239 case 0x00208:
240 #ifdef TARGET_WORDS_BIGENDIAN
241 val = 0x00000012;
242 #else
243 val = 0x00000010;
244 #endif
245 break;
246
247 /* JMPRS Register */
248 case 0x00210:
249 val = 0x00;
250 break;
251
252 /* LEDBAR Register */
253 case 0x00408:
254 val = s->leds;
255 break;
256
257 /* BRKRES Register */
258 case 0x00508:
259 val = s->brk;
260 break;
261
262 /* UART Registers are handled directly by the serial device */
263
264 /* GPOUT Register */
265 case 0x00a00:
266 val = s->gpout;
267 break;
268
269 /* XXX: implement a real I2C controller */
270
271 /* GPINP Register */
272 case 0x00a08:
273 /* IN = OUT until a real I2C control is implemented */
274 if (s->i2csel)
275 val = s->i2cout;
276 else
277 val = 0x00;
278 break;
279
280 /* I2CINP Register */
281 case 0x00b00:
282 val = ((s->i2cin & ~1) | eeprom24c0x_read());
283 break;
284
285 /* I2COE Register */
286 case 0x00b08:
287 val = s->i2coe;
288 break;
289
290 /* I2COUT Register */
291 case 0x00b10:
292 val = s->i2cout;
293 break;
294
295 /* I2CSEL Register */
296 case 0x00b18:
297 val = s->i2csel;
298 break;
299
300 default:
301 #if 0
302 printf ("malta_fpga_read: Bad register offset 0x" TARGET_FMT_lx "\n",
303 addr);
304 #endif
305 break;
306 }
307 return val;
308 }
309
310 static void malta_fpga_writel(void *opaque, target_phys_addr_t addr,
311 uint32_t val)
312 {
313 MaltaFPGAState *s = opaque;
314 uint32_t saddr;
315
316 saddr = (addr & 0xfffff);
317
318 switch (saddr) {
319
320 /* SWITCH Register */
321 case 0x00200:
322 break;
323
324 /* JMPRS Register */
325 case 0x00210:
326 break;
327
328 /* LEDBAR Register */
329 /* XXX: implement a 8-LED array */
330 case 0x00408:
331 s->leds = val & 0xff;
332 break;
333
334 /* ASCIIWORD Register */
335 case 0x00410:
336 snprintf(s->display_text, 9, "%08X", val);
337 malta_fpga_update_display(s);
338 break;
339
340 /* ASCIIPOS0 to ASCIIPOS7 Registers */
341 case 0x00418:
342 case 0x00420:
343 case 0x00428:
344 case 0x00430:
345 case 0x00438:
346 case 0x00440:
347 case 0x00448:
348 case 0x00450:
349 s->display_text[(saddr - 0x00418) >> 3] = (char) val;
350 malta_fpga_update_display(s);
351 break;
352
353 /* SOFTRES Register */
354 case 0x00500:
355 if (val == 0x42)
356 qemu_system_reset_request ();
357 break;
358
359 /* BRKRES Register */
360 case 0x00508:
361 s->brk = val & 0xff;
362 break;
363
364 /* UART Registers are handled directly by the serial device */
365
366 /* GPOUT Register */
367 case 0x00a00:
368 s->gpout = val & 0xff;
369 break;
370
371 /* I2COE Register */
372 case 0x00b08:
373 s->i2coe = val & 0x03;
374 break;
375
376 /* I2COUT Register */
377 case 0x00b10:
378 eeprom24c0x_write(val & 0x02, val & 0x01);
379 s->i2cout = val;
380 break;
381
382 /* I2CSEL Register */
383 case 0x00b18:
384 s->i2csel = val & 0x01;
385 break;
386
387 default:
388 #if 0
389 printf ("malta_fpga_write: Bad register offset 0x" TARGET_FMT_lx "\n",
390 addr);
391 #endif
392 break;
393 }
394 }
395
396 static CPUReadMemoryFunc *malta_fpga_read[] = {
397 malta_fpga_readl,
398 malta_fpga_readl,
399 malta_fpga_readl
400 };
401
402 static CPUWriteMemoryFunc *malta_fpga_write[] = {
403 malta_fpga_writel,
404 malta_fpga_writel,
405 malta_fpga_writel
406 };
407
408 static void malta_fpga_reset(void *opaque)
409 {
410 MaltaFPGAState *s = opaque;
411
412 s->leds = 0x00;
413 s->brk = 0x0a;
414 s->gpout = 0x00;
415 s->i2cin = 0x3;
416 s->i2coe = 0x0;
417 s->i2cout = 0x3;
418 s->i2csel = 0x1;
419
420 s->display_text[8] = '\0';
421 snprintf(s->display_text, 9, " ");
422 malta_fpga_update_display(s);
423 }
424
425 static MaltaFPGAState *malta_fpga_init(target_phys_addr_t base, CPUState *env)
426 {
427 MaltaFPGAState *s;
428 CharDriverState *uart_chr;
429 int malta;
430
431 s = (MaltaFPGAState *)qemu_mallocz(sizeof(MaltaFPGAState));
432
433 malta = cpu_register_io_memory(0, malta_fpga_read,
434 malta_fpga_write, s);
435
436 cpu_register_physical_memory(base, 0x900, malta);
437 cpu_register_physical_memory(base + 0xa00, 0x100000 - 0xa00, malta);
438
439 s->display = qemu_chr_open("vc:320x200");
440 qemu_chr_printf(s->display, "\e[HMalta LEDBAR\r\n");
441 qemu_chr_printf(s->display, "+--------+\r\n");
442 qemu_chr_printf(s->display, "+ +\r\n");
443 qemu_chr_printf(s->display, "+--------+\r\n");
444 qemu_chr_printf(s->display, "\n");
445 qemu_chr_printf(s->display, "Malta ASCII\r\n");
446 qemu_chr_printf(s->display, "+--------+\r\n");
447 qemu_chr_printf(s->display, "+ +\r\n");
448 qemu_chr_printf(s->display, "+--------+\r\n");
449
450 uart_chr = qemu_chr_open("vc:80Cx24C");
451 qemu_chr_printf(uart_chr, "CBUS UART\r\n");
452 s->uart =
453 serial_mm_init(base + 0x900, 3, env->irq[2], 230400, uart_chr, 1);
454
455 malta_fpga_reset(s);
456 qemu_register_reset(malta_fpga_reset, s);
457
458 return s;
459 }
460
461 /* Audio support */
462 #ifdef HAS_AUDIO
463 static void audio_init (PCIBus *pci_bus)
464 {
465 struct soundhw *c;
466 int audio_enabled = 0;
467
468 for (c = soundhw; !audio_enabled && c->name; ++c) {
469 audio_enabled = c->enabled;
470 }
471
472 if (audio_enabled) {
473 AudioState *s;
474
475 s = AUD_init ();
476 if (s) {
477 for (c = soundhw; c->name; ++c) {
478 if (c->enabled)
479 c->init.init_pci (pci_bus, s);
480 }
481 }
482 }
483 }
484 #endif
485
486 /* Network support */
487 static void network_init (PCIBus *pci_bus)
488 {
489 int i;
490 NICInfo *nd;
491
492 for(i = 0; i < nb_nics; i++) {
493 nd = &nd_table[i];
494 if (!nd->model) {
495 nd->model = "pcnet";
496 }
497 if (i == 0 && strcmp(nd->model, "pcnet") == 0) {
498 /* The malta board has a PCNet card using PCI SLOT 11 */
499 if (!pci_nic_init(pci_bus, nd, 88))
500 exit(1);
501 } else {
502 if (!pci_nic_init(pci_bus, nd, -1))
503 exit(1);
504 }
505 }
506 }
507
508 /* ROM and pseudo bootloader
509
510 The following code implements a very very simple bootloader. It first
511 loads the registers a0 to a3 to the values expected by the OS, and
512 then jump at the kernel address.
513
514 The bootloader should pass the locations of the kernel arguments and
515 environment variables tables. Those tables contain the 32-bit address
516 of NULL terminated strings. The environment variables table should be
517 terminated by a NULL address.
518
519 For a simpler implementation, the number of kernel arguments is fixed
520 to two (the name of the kernel and the command line), and the two
521 tables are actually the same one.
522
523 The registers a0 to a3 should contain the following values:
524 a0 - number of kernel arguments
525 a1 - 32-bit address of the kernel arguments table
526 a2 - 32-bit address of the environment variables table
527 a3 - RAM size in bytes
528 */
529
530 static void write_bootloader (CPUState *env, unsigned long bios_offset, int64_t kernel_entry)
531 {
532 uint32_t *p;
533
534 /* Small bootloader */
535 p = (uint32_t *) (phys_ram_base + bios_offset);
536 stl_raw(p++, 0x0bf00160); /* j 0x1fc00580 */
537 stl_raw(p++, 0x00000000); /* nop */
538
539 /* YAMON service vector */
540 stl_raw(phys_ram_base + bios_offset + 0x500, 0xbfc00580); /* start: */
541 stl_raw(phys_ram_base + bios_offset + 0x504, 0xbfc0083c); /* print_count: */
542 stl_raw(phys_ram_base + bios_offset + 0x520, 0xbfc00580); /* start: */
543 stl_raw(phys_ram_base + bios_offset + 0x52c, 0xbfc00800); /* flush_cache: */
544 stl_raw(phys_ram_base + bios_offset + 0x534, 0xbfc00808); /* print: */
545 stl_raw(phys_ram_base + bios_offset + 0x538, 0xbfc00800); /* reg_cpu_isr: */
546 stl_raw(phys_ram_base + bios_offset + 0x53c, 0xbfc00800); /* unred_cpu_isr: */
547 stl_raw(phys_ram_base + bios_offset + 0x540, 0xbfc00800); /* reg_ic_isr: */
548 stl_raw(phys_ram_base + bios_offset + 0x544, 0xbfc00800); /* unred_ic_isr: */
549 stl_raw(phys_ram_base + bios_offset + 0x548, 0xbfc00800); /* reg_esr: */
550 stl_raw(phys_ram_base + bios_offset + 0x54c, 0xbfc00800); /* unreg_esr: */
551 stl_raw(phys_ram_base + bios_offset + 0x550, 0xbfc00800); /* getchar: */
552 stl_raw(phys_ram_base + bios_offset + 0x554, 0xbfc00800); /* syscon_read: */
553
554
555 /* Second part of the bootloader */
556 p = (uint32_t *) (phys_ram_base + bios_offset + 0x580);
557 stl_raw(p++, 0x24040002); /* addiu a0, zero, 2 */
558 stl_raw(p++, 0x3c1d0000 | (((ENVP_ADDR - 64) >> 16) & 0xffff)); /* lui sp, high(ENVP_ADDR) */
559 stl_raw(p++, 0x37bd0000 | ((ENVP_ADDR - 64) & 0xffff)); /* ori sp, sp, low(ENVP_ADDR) */
560 stl_raw(p++, 0x3c050000 | ((ENVP_ADDR >> 16) & 0xffff)); /* lui a1, high(ENVP_ADDR) */
561 stl_raw(p++, 0x34a50000 | (ENVP_ADDR & 0xffff)); /* ori a1, a1, low(ENVP_ADDR) */
562 stl_raw(p++, 0x3c060000 | (((ENVP_ADDR + 8) >> 16) & 0xffff)); /* lui a2, high(ENVP_ADDR + 8) */
563 stl_raw(p++, 0x34c60000 | ((ENVP_ADDR + 8) & 0xffff)); /* ori a2, a2, low(ENVP_ADDR + 8) */
564 stl_raw(p++, 0x3c070000 | (loaderparams.ram_size >> 16)); /* lui a3, high(ram_size) */
565 stl_raw(p++, 0x34e70000 | (loaderparams.ram_size & 0xffff)); /* ori a3, a3, low(ram_size) */
566
567 /* Load BAR registers as done by YAMON */
568 stl_raw(p++, 0x3c09b400); /* lui t1, 0xb400 */
569
570 #ifdef TARGET_WORDS_BIGENDIAN
571 stl_raw(p++, 0x3c08df00); /* lui t0, 0xdf00 */
572 #else
573 stl_raw(p++, 0x340800df); /* ori t0, r0, 0x00df */
574 #endif
575 stl_raw(p++, 0xad280068); /* sw t0, 0x0068(t1) */
576
577 stl_raw(p++, 0x3c09bbe0); /* lui t1, 0xbbe0 */
578
579 #ifdef TARGET_WORDS_BIGENDIAN
580 stl_raw(p++, 0x3c08c000); /* lui t0, 0xc000 */
581 #else
582 stl_raw(p++, 0x340800c0); /* ori t0, r0, 0x00c0 */
583 #endif
584 stl_raw(p++, 0xad280048); /* sw t0, 0x0048(t1) */
585 #ifdef TARGET_WORDS_BIGENDIAN
586 stl_raw(p++, 0x3c084000); /* lui t0, 0x4000 */
587 #else
588 stl_raw(p++, 0x34080040); /* ori t0, r0, 0x0040 */
589 #endif
590 stl_raw(p++, 0xad280050); /* sw t0, 0x0050(t1) */
591
592 #ifdef TARGET_WORDS_BIGENDIAN
593 stl_raw(p++, 0x3c088000); /* lui t0, 0x8000 */
594 #else
595 stl_raw(p++, 0x34080080); /* ori t0, r0, 0x0080 */
596 #endif
597 stl_raw(p++, 0xad280058); /* sw t0, 0x0058(t1) */
598 #ifdef TARGET_WORDS_BIGENDIAN
599 stl_raw(p++, 0x3c083f00); /* lui t0, 0x3f00 */
600 #else
601 stl_raw(p++, 0x3408003f); /* ori t0, r0, 0x003f */
602 #endif
603 stl_raw(p++, 0xad280060); /* sw t0, 0x0060(t1) */
604
605 #ifdef TARGET_WORDS_BIGENDIAN
606 stl_raw(p++, 0x3c08c100); /* lui t0, 0xc100 */
607 #else
608 stl_raw(p++, 0x340800c1); /* ori t0, r0, 0x00c1 */
609 #endif
610 stl_raw(p++, 0xad280080); /* sw t0, 0x0080(t1) */
611 #ifdef TARGET_WORDS_BIGENDIAN
612 stl_raw(p++, 0x3c085e00); /* lui t0, 0x5e00 */
613 #else
614 stl_raw(p++, 0x3408005e); /* ori t0, r0, 0x005e */
615 #endif
616 stl_raw(p++, 0xad280088); /* sw t0, 0x0088(t1) */
617
618 /* Jump to kernel code */
619 stl_raw(p++, 0x3c1f0000 | ((kernel_entry >> 16) & 0xffff)); /* lui ra, high(kernel_entry) */
620 stl_raw(p++, 0x37ff0000 | (kernel_entry & 0xffff)); /* ori ra, ra, low(kernel_entry) */
621 stl_raw(p++, 0x03e00008); /* jr ra */
622 stl_raw(p++, 0x00000000); /* nop */
623
624 /* YAMON subroutines */
625 p = (uint32_t *) (phys_ram_base + bios_offset + 0x800);
626 stl_raw(p++, 0x03e00008); /* jr ra */
627 stl_raw(p++, 0x24020000); /* li v0,0 */
628 /* 808 YAMON print */
629 stl_raw(p++, 0x03e06821); /* move t5,ra */
630 stl_raw(p++, 0x00805821); /* move t3,a0 */
631 stl_raw(p++, 0x00a05021); /* move t2,a1 */
632 stl_raw(p++, 0x91440000); /* lbu a0,0(t2) */
633 stl_raw(p++, 0x254a0001); /* addiu t2,t2,1 */
634 stl_raw(p++, 0x10800005); /* beqz a0,834 */
635 stl_raw(p++, 0x00000000); /* nop */
636 stl_raw(p++, 0x0ff0021c); /* jal 870 */
637 stl_raw(p++, 0x00000000); /* nop */
638 stl_raw(p++, 0x08000205); /* j 814 */
639 stl_raw(p++, 0x00000000); /* nop */
640 stl_raw(p++, 0x01a00008); /* jr t5 */
641 stl_raw(p++, 0x01602021); /* move a0,t3 */
642 /* 0x83c YAMON print_count */
643 stl_raw(p++, 0x03e06821); /* move t5,ra */
644 stl_raw(p++, 0x00805821); /* move t3,a0 */
645 stl_raw(p++, 0x00a05021); /* move t2,a1 */
646 stl_raw(p++, 0x00c06021); /* move t4,a2 */
647 stl_raw(p++, 0x91440000); /* lbu a0,0(t2) */
648 stl_raw(p++, 0x0ff0021c); /* jal 870 */
649 stl_raw(p++, 0x00000000); /* nop */
650 stl_raw(p++, 0x254a0001); /* addiu t2,t2,1 */
651 stl_raw(p++, 0x258cffff); /* addiu t4,t4,-1 */
652 stl_raw(p++, 0x1580fffa); /* bnez t4,84c */
653 stl_raw(p++, 0x00000000); /* nop */
654 stl_raw(p++, 0x01a00008); /* jr t5 */
655 stl_raw(p++, 0x01602021); /* move a0,t3 */
656 /* 0x870 */
657 stl_raw(p++, 0x3c08b800); /* lui t0,0xb400 */
658 stl_raw(p++, 0x350803f8); /* ori t0,t0,0x3f8 */
659 stl_raw(p++, 0x91090005); /* lbu t1,5(t0) */
660 stl_raw(p++, 0x00000000); /* nop */
661 stl_raw(p++, 0x31290040); /* andi t1,t1,0x40 */
662 stl_raw(p++, 0x1120fffc); /* beqz t1,878 <outch+0x8> */
663 stl_raw(p++, 0x00000000); /* nop */
664 stl_raw(p++, 0x03e00008); /* jr ra */
665 stl_raw(p++, 0xa1040000); /* sb a0,0(t0) */
666
667 }
668
669 static void prom_set(int index, const char *string, ...)
670 {
671 va_list ap;
672 int32_t *p;
673 int32_t table_addr;
674 char *s;
675
676 if (index >= ENVP_NB_ENTRIES)
677 return;
678
679 p = (int32_t *) (phys_ram_base + ENVP_ADDR + VIRT_TO_PHYS_ADDEND);
680 p += index;
681
682 if (string == NULL) {
683 stl_raw(p, 0);
684 return;
685 }
686
687 table_addr = ENVP_ADDR + sizeof(int32_t) * ENVP_NB_ENTRIES + index * ENVP_ENTRY_SIZE;
688 s = (char *) (phys_ram_base + VIRT_TO_PHYS_ADDEND + table_addr);
689
690 stl_raw(p, table_addr);
691
692 va_start(ap, string);
693 vsnprintf (s, ENVP_ENTRY_SIZE, string, ap);
694 va_end(ap);
695 }
696
697 /* Kernel */
698 static int64_t load_kernel (CPUState *env)
699 {
700 int64_t kernel_entry, kernel_low, kernel_high;
701 int index = 0;
702 long initrd_size;
703 ram_addr_t initrd_offset;
704
705 if (load_elf(loaderparams.kernel_filename, VIRT_TO_PHYS_ADDEND,
706 &kernel_entry, &kernel_low, &kernel_high) < 0) {
707 fprintf(stderr, "qemu: could not load kernel '%s'\n",
708 loaderparams.kernel_filename);
709 exit(1);
710 }
711
712 /* load initrd */
713 initrd_size = 0;
714 initrd_offset = 0;
715 if (loaderparams.initrd_filename) {
716 initrd_size = get_image_size (loaderparams.initrd_filename);
717 if (initrd_size > 0) {
718 initrd_offset = (kernel_high + ~TARGET_PAGE_MASK) & TARGET_PAGE_MASK;
719 if (initrd_offset + initrd_size > ram_size) {
720 fprintf(stderr,
721 "qemu: memory too small for initial ram disk '%s'\n",
722 loaderparams.initrd_filename);
723 exit(1);
724 }
725 initrd_size = load_image(loaderparams.initrd_filename,
726 phys_ram_base + initrd_offset);
727 }
728 if (initrd_size == (target_ulong) -1) {
729 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
730 loaderparams.initrd_filename);
731 exit(1);
732 }
733 }
734
735 /* Store command line. */
736 prom_set(index++, loaderparams.kernel_filename);
737 if (initrd_size > 0)
738 prom_set(index++, "rd_start=0x" TARGET_FMT_lx " rd_size=%li %s",
739 PHYS_TO_VIRT(initrd_offset), initrd_size,
740 loaderparams.kernel_cmdline);
741 else
742 prom_set(index++, loaderparams.kernel_cmdline);
743
744 /* Setup minimum environment variables */
745 prom_set(index++, "memsize");
746 prom_set(index++, "%i", loaderparams.ram_size);
747 prom_set(index++, "modetty0");
748 prom_set(index++, "38400n8r");
749 prom_set(index++, NULL);
750
751 return kernel_entry;
752 }
753
754 static void main_cpu_reset(void *opaque)
755 {
756 CPUState *env = opaque;
757 cpu_reset(env);
758
759 /* The bootload does not need to be rewritten as it is located in a
760 read only location. The kernel location and the arguments table
761 location does not change. */
762 if (loaderparams.kernel_filename) {
763 env->CP0_Status &= ~((1 << CP0St_BEV) | (1 << CP0St_ERL));
764 load_kernel (env);
765 }
766 }
767
768 static
769 void mips_malta_init (ram_addr_t ram_size, int vga_ram_size,
770 const char *boot_device, DisplayState *ds,
771 const char *kernel_filename, const char *kernel_cmdline,
772 const char *initrd_filename, const char *cpu_model)
773 {
774 char buf[1024];
775 unsigned long bios_offset;
776 target_long bios_size;
777 int64_t kernel_entry;
778 PCIBus *pci_bus;
779 CPUState *env;
780 RTCState *rtc_state;
781 fdctrl_t *floppy_controller;
782 MaltaFPGAState *malta_fpga;
783 qemu_irq *i8259;
784 int piix4_devfn;
785 uint8_t *eeprom_buf;
786 i2c_bus *smbus;
787 int i;
788 int index;
789 BlockDriverState *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
790 BlockDriverState *fd[MAX_FD];
791 int fl_idx = 0;
792 int fl_sectors = 0;
793
794 /* init CPUs */
795 if (cpu_model == NULL) {
796 #ifdef TARGET_MIPS64
797 cpu_model = "20Kc";
798 #else
799 cpu_model = "24Kf";
800 #endif
801 }
802 env = cpu_init(cpu_model);
803 if (!env) {
804 fprintf(stderr, "Unable to find CPU definition\n");
805 exit(1);
806 }
807 qemu_register_reset(main_cpu_reset, env);
808
809 /* allocate RAM */
810 cpu_register_physical_memory(0, ram_size, IO_MEM_RAM);
811
812 /* Map the bios at two physical locations, as on the real board. */
813 bios_offset = ram_size + vga_ram_size;
814 cpu_register_physical_memory(0x1e000000LL,
815 BIOS_SIZE, bios_offset | IO_MEM_ROM);
816 cpu_register_physical_memory(0x1fc00000LL,
817 BIOS_SIZE, bios_offset | IO_MEM_ROM);
818
819 /* FPGA */
820 malta_fpga = malta_fpga_init(0x1f000000LL, env);
821
822 /* Load firmware in flash / BIOS unless we boot directly into a kernel. */
823 if (kernel_filename) {
824 /* Write a small bootloader to the flash location. */
825 loaderparams.ram_size = ram_size;
826 loaderparams.kernel_filename = kernel_filename;
827 loaderparams.kernel_cmdline = kernel_cmdline;
828 loaderparams.initrd_filename = initrd_filename;
829 kernel_entry = load_kernel(env);
830 env->CP0_Status &= ~((1 << CP0St_BEV) | (1 << CP0St_ERL));
831 write_bootloader(env, bios_offset, kernel_entry);
832 } else {
833 index = drive_get_index(IF_PFLASH, 0, fl_idx);
834 if (index != -1) {
835 /* Load firmware from flash. */
836 bios_size = 0x400000;
837 fl_sectors = bios_size >> 16;
838 #ifdef DEBUG_BOARD_INIT
839 printf("Register parallel flash %d size " TARGET_FMT_lx " at "
840 "offset %08lx addr %08llx '%s' %x\n",
841 fl_idx, bios_size, bios_offset, 0x1e000000LL,
842 bdrv_get_device_name(drives_table[index].bdrv), fl_sectors);
843 #endif
844 pflash_cfi01_register(0x1e000000LL, bios_offset,
845 drives_table[index].bdrv, 65536, fl_sectors,
846 4, 0x0000, 0x0000, 0x0000, 0x0000);
847 fl_idx++;
848 } else {
849 /* Load a BIOS image. */
850 if (bios_name == NULL)
851 bios_name = BIOS_FILENAME;
852 snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
853 bios_size = load_image(buf, phys_ram_base + bios_offset);
854 if ((bios_size < 0 || bios_size > BIOS_SIZE) && !kernel_filename) {
855 fprintf(stderr,
856 "qemu: Could not load MIPS bios '%s', and no -kernel argument was specified\n",
857 buf);
858 exit(1);
859 }
860 }
861 /* In little endian mode the 32bit words in the bios are swapped,
862 a neat trick which allows bi-endian firmware. */
863 #ifndef TARGET_WORDS_BIGENDIAN
864 {
865 uint32_t *addr;
866 for (addr = (uint32_t *)(phys_ram_base + bios_offset);
867 addr < (uint32_t *)(phys_ram_base + bios_offset + bios_size);
868 addr++) {
869 *addr = bswap32(*addr);
870 }
871 }
872 #endif
873 }
874
875 /* Board ID = 0x420 (Malta Board with CoreLV)
876 XXX: theoretically 0x1e000010 should map to flash and 0x1fc00010 should
877 map to the board ID. */
878 stl_raw(phys_ram_base + bios_offset + 0x10, 0x00000420);
879
880 /* Init internal devices */
881 cpu_mips_irq_init_cpu(env);
882 cpu_mips_clock_init(env);
883 cpu_mips_irqctrl_init();
884
885 /* Interrupt controller */
886 /* The 8259 is attached to the MIPS CPU INT0 pin, ie interrupt 2 */
887 i8259 = i8259_init(env->irq[2]);
888
889 /* Northbridge */
890 pci_bus = pci_gt64120_init(i8259);
891
892 /* Southbridge */
893
894 if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) {
895 fprintf(stderr, "qemu: too many IDE bus\n");
896 exit(1);
897 }
898
899 for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) {
900 index = drive_get_index(IF_IDE, i / MAX_IDE_DEVS, i % MAX_IDE_DEVS);
901 if (index != -1)
902 hd[i] = drives_table[index].bdrv;
903 else
904 hd[i] = NULL;
905 }
906
907 piix4_devfn = piix4_init(pci_bus, 80);
908 pci_piix4_ide_init(pci_bus, hd, piix4_devfn + 1, i8259);
909 usb_uhci_piix4_init(pci_bus, piix4_devfn + 2);
910 smbus = piix4_pm_init(pci_bus, piix4_devfn + 3, 0x1100, i8259[9]);
911 eeprom_buf = qemu_mallocz(8 * 256); /* XXX: make this persistent */
912 for (i = 0; i < 8; i++) {
913 /* TODO: Populate SPD eeprom data. */
914 smbus_eeprom_device_init(smbus, 0x50 + i, eeprom_buf + (i * 256));
915 }
916 pit = pit_init(0x40, i8259[0]);
917 DMA_init(0);
918
919 /* Super I/O */
920 i8042_init(i8259[1], i8259[12], 0x60);
921 rtc_state = rtc_init(0x70, i8259[8]);
922 if (serial_hds[0])
923 serial_init(0x3f8, i8259[4], 115200, serial_hds[0]);
924 if (serial_hds[1])
925 serial_init(0x2f8, i8259[3], 115200, serial_hds[1]);
926 if (parallel_hds[0])
927 parallel_init(0x378, i8259[7], parallel_hds[0]);
928 for(i = 0; i < MAX_FD; i++) {
929 index = drive_get_index(IF_FLOPPY, 0, i);
930 if (index != -1)
931 fd[i] = drives_table[index].bdrv;
932 else
933 fd[i] = NULL;
934 }
935 floppy_controller = fdctrl_init(i8259[6], 2, 0, 0x3f0, fd);
936
937 /* Sound card */
938 #ifdef HAS_AUDIO
939 audio_init(pci_bus);
940 #endif
941
942 /* Network card */
943 network_init(pci_bus);
944
945 /* Optional PCI video card */
946 pci_cirrus_vga_init(pci_bus, ds, phys_ram_base + ram_size,
947 ram_size, vga_ram_size);
948 }
949
950 QEMUMachine mips_malta_machine = {
951 "malta",
952 "MIPS Malta Core LV",
953 mips_malta_init,
954 VGA_RAM_SIZE + BIOS_SIZE,
955 };
Patches shipped by Fedora