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kvm: external module: fix anon_inodes for 2.6.22
[qemu-kvm/fedora.git] / hw / cirrus_vga.c
blobc7e8f2cba82397487ab56271e8075958811916c8
1 /*
2 * QEMU Cirrus CLGD 54xx VGA Emulator.
3 *
4 * Copyright (c) 2004 Fabrice Bellard
5 * Copyright (c) 2004 Makoto Suzuki (suzu)
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
25 /*
26 * Reference: Finn Thogersons' VGADOC4b
27 * available at http://home.worldonline.dk/~finth/
28 */
29 #include "hw.h"
30 #include "pc.h"
31 #include "pci.h"
32 #include "console.h"
33 #include "vga_int.h"
34 #ifndef _WIN32
35 #include <sys/mman.h>
36 #endif
37 #include "qemu-kvm.h"
38
39 /*
40 * TODO:
41 * - destination write mask support not complete (bits 5..7)
42 * - optimize linear mappings
43 * - optimize bitblt functions
44 */
45
46 //#define DEBUG_CIRRUS
47 //#define DEBUG_BITBLT
48
49 /***************************************
50 *
51 * definitions
52 *
53 ***************************************/
54
55 #define qemu_MIN(a,b) ((a) < (b) ? (a) : (b))
56
57 // ID
58 #define CIRRUS_ID_CLGD5422 (0x23<<2)
59 #define CIRRUS_ID_CLGD5426 (0x24<<2)
60 #define CIRRUS_ID_CLGD5424 (0x25<<2)
61 #define CIRRUS_ID_CLGD5428 (0x26<<2)
62 #define CIRRUS_ID_CLGD5430 (0x28<<2)
63 #define CIRRUS_ID_CLGD5434 (0x2A<<2)
64 #define CIRRUS_ID_CLGD5436 (0x2B<<2)
65 #define CIRRUS_ID_CLGD5446 (0x2E<<2)
66
67 // sequencer 0x07
68 #define CIRRUS_SR7_BPP_VGA 0x00
69 #define CIRRUS_SR7_BPP_SVGA 0x01
70 #define CIRRUS_SR7_BPP_MASK 0x0e
71 #define CIRRUS_SR7_BPP_8 0x00
72 #define CIRRUS_SR7_BPP_16_DOUBLEVCLK 0x02
73 #define CIRRUS_SR7_BPP_24 0x04
74 #define CIRRUS_SR7_BPP_16 0x06
75 #define CIRRUS_SR7_BPP_32 0x08
76 #define CIRRUS_SR7_ISAADDR_MASK 0xe0
77
78 // sequencer 0x0f
79 #define CIRRUS_MEMSIZE_512k 0x08
80 #define CIRRUS_MEMSIZE_1M 0x10
81 #define CIRRUS_MEMSIZE_2M 0x18
82 #define CIRRUS_MEMFLAGS_BANKSWITCH 0x80 // bank switching is enabled.
83
84 // sequencer 0x12
85 #define CIRRUS_CURSOR_SHOW 0x01
86 #define CIRRUS_CURSOR_HIDDENPEL 0x02
87 #define CIRRUS_CURSOR_LARGE 0x04 // 64x64 if set, 32x32 if clear
88
89 // sequencer 0x17
90 #define CIRRUS_BUSTYPE_VLBFAST 0x10
91 #define CIRRUS_BUSTYPE_PCI 0x20
92 #define CIRRUS_BUSTYPE_VLBSLOW 0x30
93 #define CIRRUS_BUSTYPE_ISA 0x38
94 #define CIRRUS_MMIO_ENABLE 0x04
95 #define CIRRUS_MMIO_USE_PCIADDR 0x40 // 0xb8000 if cleared.
96 #define CIRRUS_MEMSIZEEXT_DOUBLE 0x80
97
98 // control 0x0b
99 #define CIRRUS_BANKING_DUAL 0x01
100 #define CIRRUS_BANKING_GRANULARITY_16K 0x20 // set:16k, clear:4k
101
102 // control 0x30
103 #define CIRRUS_BLTMODE_BACKWARDS 0x01
104 #define CIRRUS_BLTMODE_MEMSYSDEST 0x02
105 #define CIRRUS_BLTMODE_MEMSYSSRC 0x04
106 #define CIRRUS_BLTMODE_TRANSPARENTCOMP 0x08
107 #define CIRRUS_BLTMODE_PATTERNCOPY 0x40
108 #define CIRRUS_BLTMODE_COLOREXPAND 0x80
109 #define CIRRUS_BLTMODE_PIXELWIDTHMASK 0x30
110 #define CIRRUS_BLTMODE_PIXELWIDTH8 0x00
111 #define CIRRUS_BLTMODE_PIXELWIDTH16 0x10
112 #define CIRRUS_BLTMODE_PIXELWIDTH24 0x20
113 #define CIRRUS_BLTMODE_PIXELWIDTH32 0x30
114
115 // control 0x31
116 #define CIRRUS_BLT_BUSY 0x01
117 #define CIRRUS_BLT_START 0x02
118 #define CIRRUS_BLT_RESET 0x04
119 #define CIRRUS_BLT_FIFOUSED 0x10
120 #define CIRRUS_BLT_AUTOSTART 0x80
121
122 // control 0x32
123 #define CIRRUS_ROP_0 0x00
124 #define CIRRUS_ROP_SRC_AND_DST 0x05
125 #define CIRRUS_ROP_NOP 0x06
126 #define CIRRUS_ROP_SRC_AND_NOTDST 0x09
127 #define CIRRUS_ROP_NOTDST 0x0b
128 #define CIRRUS_ROP_SRC 0x0d
129 #define CIRRUS_ROP_1 0x0e
130 #define CIRRUS_ROP_NOTSRC_AND_DST 0x50
131 #define CIRRUS_ROP_SRC_XOR_DST 0x59
132 #define CIRRUS_ROP_SRC_OR_DST 0x6d
133 #define CIRRUS_ROP_NOTSRC_OR_NOTDST 0x90
134 #define CIRRUS_ROP_SRC_NOTXOR_DST 0x95
135 #define CIRRUS_ROP_SRC_OR_NOTDST 0xad
136 #define CIRRUS_ROP_NOTSRC 0xd0
137 #define CIRRUS_ROP_NOTSRC_OR_DST 0xd6
138 #define CIRRUS_ROP_NOTSRC_AND_NOTDST 0xda
139
140 #define CIRRUS_ROP_NOP_INDEX 2
141 #define CIRRUS_ROP_SRC_INDEX 5
142
143 // control 0x33
144 #define CIRRUS_BLTMODEEXT_SOLIDFILL 0x04
145 #define CIRRUS_BLTMODEEXT_COLOREXPINV 0x02
146 #define CIRRUS_BLTMODEEXT_DWORDGRANULARITY 0x01
147
148 // memory-mapped IO
149 #define CIRRUS_MMIO_BLTBGCOLOR 0x00 // dword
150 #define CIRRUS_MMIO_BLTFGCOLOR 0x04 // dword
151 #define CIRRUS_MMIO_BLTWIDTH 0x08 // word
152 #define CIRRUS_MMIO_BLTHEIGHT 0x0a // word
153 #define CIRRUS_MMIO_BLTDESTPITCH 0x0c // word
154 #define CIRRUS_MMIO_BLTSRCPITCH 0x0e // word
155 #define CIRRUS_MMIO_BLTDESTADDR 0x10 // dword
156 #define CIRRUS_MMIO_BLTSRCADDR 0x14 // dword
157 #define CIRRUS_MMIO_BLTWRITEMASK 0x17 // byte
158 #define CIRRUS_MMIO_BLTMODE 0x18 // byte
159 #define CIRRUS_MMIO_BLTROP 0x1a // byte
160 #define CIRRUS_MMIO_BLTMODEEXT 0x1b // byte
161 #define CIRRUS_MMIO_BLTTRANSPARENTCOLOR 0x1c // word?
162 #define CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK 0x20 // word?
163 #define CIRRUS_MMIO_LINEARDRAW_START_X 0x24 // word
164 #define CIRRUS_MMIO_LINEARDRAW_START_Y 0x26 // word
165 #define CIRRUS_MMIO_LINEARDRAW_END_X 0x28 // word
166 #define CIRRUS_MMIO_LINEARDRAW_END_Y 0x2a // word
167 #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_INC 0x2c // byte
168 #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_ROLLOVER 0x2d // byte
169 #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_MASK 0x2e // byte
170 #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_ACCUM 0x2f // byte
171 #define CIRRUS_MMIO_BRESENHAM_K1 0x30 // word
172 #define CIRRUS_MMIO_BRESENHAM_K3 0x32 // word
173 #define CIRRUS_MMIO_BRESENHAM_ERROR 0x34 // word
174 #define CIRRUS_MMIO_BRESENHAM_DELTA_MAJOR 0x36 // word
175 #define CIRRUS_MMIO_BRESENHAM_DIRECTION 0x38 // byte
176 #define CIRRUS_MMIO_LINEDRAW_MODE 0x39 // byte
177 #define CIRRUS_MMIO_BLTSTATUS 0x40 // byte
178
179 // PCI 0x00: vendor, 0x02: device
180 #define PCI_VENDOR_CIRRUS 0x1013
181 #define PCI_DEVICE_CLGD5462 0x00d0
182 #define PCI_DEVICE_CLGD5465 0x00d6
183
184 // PCI 0x04: command(word), 0x06(word): status
185 #define PCI_COMMAND_IOACCESS 0x0001
186 #define PCI_COMMAND_MEMACCESS 0x0002
187 #define PCI_COMMAND_BUSMASTER 0x0004
188 #define PCI_COMMAND_SPECIALCYCLE 0x0008
189 #define PCI_COMMAND_MEMWRITEINVALID 0x0010
190 #define PCI_COMMAND_PALETTESNOOPING 0x0020
191 #define PCI_COMMAND_PARITYDETECTION 0x0040
192 #define PCI_COMMAND_ADDRESSDATASTEPPING 0x0080
193 #define PCI_COMMAND_SERR 0x0100
194 #define PCI_COMMAND_BACKTOBACKTRANS 0x0200
195 // PCI 0x08, 0xff000000 (0x09-0x0b:class,0x08:rev)
196 #define PCI_CLASS_BASE_DISPLAY 0x03
197 // PCI 0x08, 0x00ff0000
198 #define PCI_CLASS_SUB_VGA 0x00
199 // PCI 0x0c, 0x00ff0000 (0x0c:cacheline,0x0d:latency,0x0e:headertype,0x0f:Built-in self test)
200 #define PCI_CLASS_HEADERTYPE_00h 0x00
201 // 0x10-0x3f (headertype 00h)
202 // PCI 0x10,0x14,0x18,0x1c,0x20,0x24: base address mapping registers
203 // 0x10: MEMBASE, 0x14: IOBASE(hard-coded in XFree86 3.x)
204 #define PCI_MAP_MEM 0x0
205 #define PCI_MAP_IO 0x1
206 #define PCI_MAP_MEM_ADDR_MASK (~0xf)
207 #define PCI_MAP_IO_ADDR_MASK (~0x3)
208 #define PCI_MAP_MEMFLAGS_32BIT 0x0
209 #define PCI_MAP_MEMFLAGS_32BIT_1M 0x1
210 #define PCI_MAP_MEMFLAGS_64BIT 0x4
211 #define PCI_MAP_MEMFLAGS_CACHEABLE 0x8
212 // PCI 0x28: cardbus CIS pointer
213 // PCI 0x2c: subsystem vendor id, 0x2e: subsystem id
214 // PCI 0x30: expansion ROM base address
215 #define PCI_ROMBIOS_ENABLED 0x1
216 // PCI 0x34: 0xffffff00=reserved, 0x000000ff=capabilities pointer
217 // PCI 0x38: reserved
218 // PCI 0x3c: 0x3c=int-line, 0x3d=int-pin, 0x3e=min-gnt, 0x3f=maax-lat
219
220 #define CIRRUS_PNPMMIO_SIZE 0x1000
221
222
223 /* I/O and memory hook */
224 #define CIRRUS_HOOK_NOT_HANDLED 0
225 #define CIRRUS_HOOK_HANDLED 1
226
227 #define BLTUNSAFE(s) \
228 ( \
229 ( /* check dst is within bounds */ \
230 (s)->cirrus_blt_height * (s)->cirrus_blt_dstpitch \
231 + ((s)->cirrus_blt_dstaddr & (s)->cirrus_addr_mask) > \
232 (s)->vram_size \
233 ) || \
234 ( /* check src is within bounds */ \
235 (s)->cirrus_blt_height * (s)->cirrus_blt_srcpitch \
236 + ((s)->cirrus_blt_srcaddr & (s)->cirrus_addr_mask) > \
237 (s)->vram_size \
238 ) \
239 )
240
241 struct CirrusVGAState;
242 typedef void (*cirrus_bitblt_rop_t) (struct CirrusVGAState *s,
243 uint8_t * dst, const uint8_t * src,
244 int dstpitch, int srcpitch,
245 int bltwidth, int bltheight);
246 typedef void (*cirrus_fill_t)(struct CirrusVGAState *s,
247 uint8_t *dst, int dst_pitch, int width, int height);
248
249 typedef struct CirrusVGAState {
250 VGA_STATE_COMMON
251
252 int cirrus_linear_io_addr;
253 int cirrus_linear_bitblt_io_addr;
254 int cirrus_mmio_io_addr;
255 unsigned long cirrus_lfb_addr;
256 unsigned long cirrus_lfb_end;
257 uint32_t cirrus_addr_mask;
258 uint32_t linear_mmio_mask;
259 uint8_t cirrus_shadow_gr0;
260 uint8_t cirrus_shadow_gr1;
261 uint8_t cirrus_hidden_dac_lockindex;
262 uint8_t cirrus_hidden_dac_data;
263 uint32_t cirrus_bank_base[2];
264 uint32_t cirrus_bank_limit[2];
265 uint8_t cirrus_hidden_palette[48];
266 uint32_t hw_cursor_x;
267 uint32_t hw_cursor_y;
268 int cirrus_blt_pixelwidth;
269 int cirrus_blt_width;
270 int cirrus_blt_height;
271 int cirrus_blt_dstpitch;
272 int cirrus_blt_srcpitch;
273 uint32_t cirrus_blt_fgcol;
274 uint32_t cirrus_blt_bgcol;
275 uint32_t cirrus_blt_dstaddr;
276 uint32_t cirrus_blt_srcaddr;
277 uint8_t cirrus_blt_mode;
278 uint8_t cirrus_blt_modeext;
279 cirrus_bitblt_rop_t cirrus_rop;
280 #define CIRRUS_BLTBUFSIZE (2048 * 4) /* one line width */
281 uint8_t cirrus_bltbuf[CIRRUS_BLTBUFSIZE];
282 uint8_t *cirrus_srcptr;
283 uint8_t *cirrus_srcptr_end;
284 uint32_t cirrus_srccounter;
285 /* hwcursor display state */
286 int last_hw_cursor_size;
287 int last_hw_cursor_x;
288 int last_hw_cursor_y;
289 int last_hw_cursor_y_start;
290 int last_hw_cursor_y_end;
291 int real_vram_size; /* XXX: suppress that */
292 CPUWriteMemoryFunc **cirrus_linear_write;
293 } CirrusVGAState;
294
295 typedef struct PCICirrusVGAState {
296 PCIDevice dev;
297 CirrusVGAState cirrus_vga;
298 } PCICirrusVGAState;
299
300 static uint8_t rop_to_index[256];
301
302 /***************************************
303 *
304 * prototypes.
305 *
306 ***************************************/
307
308
309 static void cirrus_bitblt_reset(CirrusVGAState *s);
310 static void cirrus_update_memory_access(CirrusVGAState *s);
311
312 /***************************************
313 *
314 * raster operations
315 *
316 ***************************************/
317
318 static void cirrus_bitblt_rop_nop(CirrusVGAState *s,
319 uint8_t *dst,const uint8_t *src,
320 int dstpitch,int srcpitch,
321 int bltwidth,int bltheight)
322 {
323 }
324
325 static void cirrus_bitblt_fill_nop(CirrusVGAState *s,
326 uint8_t *dst,
327 int dstpitch, int bltwidth,int bltheight)
328 {
329 }
330
331 #define ROP_NAME 0
332 #define ROP_OP(d, s) d = 0
333 #include "cirrus_vga_rop.h"
334
335 #define ROP_NAME src_and_dst
336 #define ROP_OP(d, s) d = (s) & (d)
337 #include "cirrus_vga_rop.h"
338
339 #define ROP_NAME src_and_notdst
340 #define ROP_OP(d, s) d = (s) & (~(d))
341 #include "cirrus_vga_rop.h"
342
343 #define ROP_NAME notdst
344 #define ROP_OP(d, s) d = ~(d)
345 #include "cirrus_vga_rop.h"
346
347 #define ROP_NAME src
348 #define ROP_OP(d, s) d = s
349 #include "cirrus_vga_rop.h"
350
351 #define ROP_NAME 1
352 #define ROP_OP(d, s) d = ~0
353 #include "cirrus_vga_rop.h"
354
355 #define ROP_NAME notsrc_and_dst
356 #define ROP_OP(d, s) d = (~(s)) & (d)
357 #include "cirrus_vga_rop.h"
358
359 #define ROP_NAME src_xor_dst
360 #define ROP_OP(d, s) d = (s) ^ (d)
361 #include "cirrus_vga_rop.h"
362
363 #define ROP_NAME src_or_dst
364 #define ROP_OP(d, s) d = (s) | (d)
365 #include "cirrus_vga_rop.h"
366
367 #define ROP_NAME notsrc_or_notdst
368 #define ROP_OP(d, s) d = (~(s)) | (~(d))
369 #include "cirrus_vga_rop.h"
370
371 #define ROP_NAME src_notxor_dst
372 #define ROP_OP(d, s) d = ~((s) ^ (d))
373 #include "cirrus_vga_rop.h"
374
375 #define ROP_NAME src_or_notdst
376 #define ROP_OP(d, s) d = (s) | (~(d))
377 #include "cirrus_vga_rop.h"
378
379 #define ROP_NAME notsrc
380 #define ROP_OP(d, s) d = (~(s))
381 #include "cirrus_vga_rop.h"
382
383 #define ROP_NAME notsrc_or_dst
384 #define ROP_OP(d, s) d = (~(s)) | (d)
385 #include "cirrus_vga_rop.h"
386
387 #define ROP_NAME notsrc_and_notdst
388 #define ROP_OP(d, s) d = (~(s)) & (~(d))
389 #include "cirrus_vga_rop.h"
390
391 static const cirrus_bitblt_rop_t cirrus_fwd_rop[16] = {
392 cirrus_bitblt_rop_fwd_0,
393 cirrus_bitblt_rop_fwd_src_and_dst,
394 cirrus_bitblt_rop_nop,
395 cirrus_bitblt_rop_fwd_src_and_notdst,
396 cirrus_bitblt_rop_fwd_notdst,
397 cirrus_bitblt_rop_fwd_src,
398 cirrus_bitblt_rop_fwd_1,
399 cirrus_bitblt_rop_fwd_notsrc_and_dst,
400 cirrus_bitblt_rop_fwd_src_xor_dst,
401 cirrus_bitblt_rop_fwd_src_or_dst,
402 cirrus_bitblt_rop_fwd_notsrc_or_notdst,
403 cirrus_bitblt_rop_fwd_src_notxor_dst,
404 cirrus_bitblt_rop_fwd_src_or_notdst,
405 cirrus_bitblt_rop_fwd_notsrc,
406 cirrus_bitblt_rop_fwd_notsrc_or_dst,
407 cirrus_bitblt_rop_fwd_notsrc_and_notdst,
408 };
409
410 static const cirrus_bitblt_rop_t cirrus_bkwd_rop[16] = {
411 cirrus_bitblt_rop_bkwd_0,
412 cirrus_bitblt_rop_bkwd_src_and_dst,
413 cirrus_bitblt_rop_nop,
414 cirrus_bitblt_rop_bkwd_src_and_notdst,
415 cirrus_bitblt_rop_bkwd_notdst,
416 cirrus_bitblt_rop_bkwd_src,
417 cirrus_bitblt_rop_bkwd_1,
418 cirrus_bitblt_rop_bkwd_notsrc_and_dst,
419 cirrus_bitblt_rop_bkwd_src_xor_dst,
420 cirrus_bitblt_rop_bkwd_src_or_dst,
421 cirrus_bitblt_rop_bkwd_notsrc_or_notdst,
422 cirrus_bitblt_rop_bkwd_src_notxor_dst,
423 cirrus_bitblt_rop_bkwd_src_or_notdst,
424 cirrus_bitblt_rop_bkwd_notsrc,
425 cirrus_bitblt_rop_bkwd_notsrc_or_dst,
426 cirrus_bitblt_rop_bkwd_notsrc_and_notdst,
427 };
428
429 #define TRANSP_ROP(name) {\
430 name ## _8,\
431 name ## _16,\
432 }
433 #define TRANSP_NOP(func) {\
434 func,\
435 func,\
436 }
437
438 static const cirrus_bitblt_rop_t cirrus_fwd_transp_rop[16][2] = {
439 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_0),
440 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_and_dst),
441 TRANSP_NOP(cirrus_bitblt_rop_nop),
442 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_and_notdst),
443 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notdst),
444 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src),
445 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_1),
446 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_and_dst),
447 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_xor_dst),
448 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_or_dst),
449 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_or_notdst),
450 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_notxor_dst),
451 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_or_notdst),
452 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc),
453 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_or_dst),
454 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_and_notdst),
455 };
456
457 static const cirrus_bitblt_rop_t cirrus_bkwd_transp_rop[16][2] = {
458 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_0),
459 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_and_dst),
460 TRANSP_NOP(cirrus_bitblt_rop_nop),
461 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_and_notdst),
462 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notdst),
463 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src),
464 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_1),
465 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_and_dst),
466 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_xor_dst),
467 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_or_dst),
468 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_or_notdst),
469 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_notxor_dst),
470 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_or_notdst),
471 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc),
472 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_or_dst),
473 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_and_notdst),
474 };
475
476 #define ROP2(name) {\
477 name ## _8,\
478 name ## _16,\
479 name ## _24,\
480 name ## _32,\
481 }
482
483 #define ROP_NOP2(func) {\
484 func,\
485 func,\
486 func,\
487 func,\
488 }
489
490 static const cirrus_bitblt_rop_t cirrus_patternfill[16][4] = {
491 ROP2(cirrus_patternfill_0),
492 ROP2(cirrus_patternfill_src_and_dst),
493 ROP_NOP2(cirrus_bitblt_rop_nop),
494 ROP2(cirrus_patternfill_src_and_notdst),
495 ROP2(cirrus_patternfill_notdst),
496 ROP2(cirrus_patternfill_src),
497 ROP2(cirrus_patternfill_1),
498 ROP2(cirrus_patternfill_notsrc_and_dst),
499 ROP2(cirrus_patternfill_src_xor_dst),
500 ROP2(cirrus_patternfill_src_or_dst),
501 ROP2(cirrus_patternfill_notsrc_or_notdst),
502 ROP2(cirrus_patternfill_src_notxor_dst),
503 ROP2(cirrus_patternfill_src_or_notdst),
504 ROP2(cirrus_patternfill_notsrc),
505 ROP2(cirrus_patternfill_notsrc_or_dst),
506 ROP2(cirrus_patternfill_notsrc_and_notdst),
507 };
508
509 static const cirrus_bitblt_rop_t cirrus_colorexpand_transp[16][4] = {
510 ROP2(cirrus_colorexpand_transp_0),
511 ROP2(cirrus_colorexpand_transp_src_and_dst),
512 ROP_NOP2(cirrus_bitblt_rop_nop),
513 ROP2(cirrus_colorexpand_transp_src_and_notdst),
514 ROP2(cirrus_colorexpand_transp_notdst),
515 ROP2(cirrus_colorexpand_transp_src),
516 ROP2(cirrus_colorexpand_transp_1),
517 ROP2(cirrus_colorexpand_transp_notsrc_and_dst),
518 ROP2(cirrus_colorexpand_transp_src_xor_dst),
519 ROP2(cirrus_colorexpand_transp_src_or_dst),
520 ROP2(cirrus_colorexpand_transp_notsrc_or_notdst),
521 ROP2(cirrus_colorexpand_transp_src_notxor_dst),
522 ROP2(cirrus_colorexpand_transp_src_or_notdst),
523 ROP2(cirrus_colorexpand_transp_notsrc),
524 ROP2(cirrus_colorexpand_transp_notsrc_or_dst),
525 ROP2(cirrus_colorexpand_transp_notsrc_and_notdst),
526 };
527
528 static const cirrus_bitblt_rop_t cirrus_colorexpand[16][4] = {
529 ROP2(cirrus_colorexpand_0),
530 ROP2(cirrus_colorexpand_src_and_dst),
531 ROP_NOP2(cirrus_bitblt_rop_nop),
532 ROP2(cirrus_colorexpand_src_and_notdst),
533 ROP2(cirrus_colorexpand_notdst),
534 ROP2(cirrus_colorexpand_src),
535 ROP2(cirrus_colorexpand_1),
536 ROP2(cirrus_colorexpand_notsrc_and_dst),
537 ROP2(cirrus_colorexpand_src_xor_dst),
538 ROP2(cirrus_colorexpand_src_or_dst),
539 ROP2(cirrus_colorexpand_notsrc_or_notdst),
540 ROP2(cirrus_colorexpand_src_notxor_dst),
541 ROP2(cirrus_colorexpand_src_or_notdst),
542 ROP2(cirrus_colorexpand_notsrc),
543 ROP2(cirrus_colorexpand_notsrc_or_dst),
544 ROP2(cirrus_colorexpand_notsrc_and_notdst),
545 };
546
547 static const cirrus_bitblt_rop_t cirrus_colorexpand_pattern_transp[16][4] = {
548 ROP2(cirrus_colorexpand_pattern_transp_0),
549 ROP2(cirrus_colorexpand_pattern_transp_src_and_dst),
550 ROP_NOP2(cirrus_bitblt_rop_nop),
551 ROP2(cirrus_colorexpand_pattern_transp_src_and_notdst),
552 ROP2(cirrus_colorexpand_pattern_transp_notdst),
553 ROP2(cirrus_colorexpand_pattern_transp_src),
554 ROP2(cirrus_colorexpand_pattern_transp_1),
555 ROP2(cirrus_colorexpand_pattern_transp_notsrc_and_dst),
556 ROP2(cirrus_colorexpand_pattern_transp_src_xor_dst),
557 ROP2(cirrus_colorexpand_pattern_transp_src_or_dst),
558 ROP2(cirrus_colorexpand_pattern_transp_notsrc_or_notdst),
559 ROP2(cirrus_colorexpand_pattern_transp_src_notxor_dst),
560 ROP2(cirrus_colorexpand_pattern_transp_src_or_notdst),
561 ROP2(cirrus_colorexpand_pattern_transp_notsrc),
562 ROP2(cirrus_colorexpand_pattern_transp_notsrc_or_dst),
563 ROP2(cirrus_colorexpand_pattern_transp_notsrc_and_notdst),
564 };
565
566 static const cirrus_bitblt_rop_t cirrus_colorexpand_pattern[16][4] = {
567 ROP2(cirrus_colorexpand_pattern_0),
568 ROP2(cirrus_colorexpand_pattern_src_and_dst),
569 ROP_NOP2(cirrus_bitblt_rop_nop),
570 ROP2(cirrus_colorexpand_pattern_src_and_notdst),
571 ROP2(cirrus_colorexpand_pattern_notdst),
572 ROP2(cirrus_colorexpand_pattern_src),
573 ROP2(cirrus_colorexpand_pattern_1),
574 ROP2(cirrus_colorexpand_pattern_notsrc_and_dst),
575 ROP2(cirrus_colorexpand_pattern_src_xor_dst),
576 ROP2(cirrus_colorexpand_pattern_src_or_dst),
577 ROP2(cirrus_colorexpand_pattern_notsrc_or_notdst),
578 ROP2(cirrus_colorexpand_pattern_src_notxor_dst),
579 ROP2(cirrus_colorexpand_pattern_src_or_notdst),
580 ROP2(cirrus_colorexpand_pattern_notsrc),
581 ROP2(cirrus_colorexpand_pattern_notsrc_or_dst),
582 ROP2(cirrus_colorexpand_pattern_notsrc_and_notdst),
583 };
584
585 static const cirrus_fill_t cirrus_fill[16][4] = {
586 ROP2(cirrus_fill_0),
587 ROP2(cirrus_fill_src_and_dst),
588 ROP_NOP2(cirrus_bitblt_fill_nop),
589 ROP2(cirrus_fill_src_and_notdst),
590 ROP2(cirrus_fill_notdst),
591 ROP2(cirrus_fill_src),
592 ROP2(cirrus_fill_1),
593 ROP2(cirrus_fill_notsrc_and_dst),
594 ROP2(cirrus_fill_src_xor_dst),
595 ROP2(cirrus_fill_src_or_dst),
596 ROP2(cirrus_fill_notsrc_or_notdst),
597 ROP2(cirrus_fill_src_notxor_dst),
598 ROP2(cirrus_fill_src_or_notdst),
599 ROP2(cirrus_fill_notsrc),
600 ROP2(cirrus_fill_notsrc_or_dst),
601 ROP2(cirrus_fill_notsrc_and_notdst),
602 };
603
604 static inline void cirrus_bitblt_fgcol(CirrusVGAState *s)
605 {
606 unsigned int color;
607 switch (s->cirrus_blt_pixelwidth) {
608 case 1:
609 s->cirrus_blt_fgcol = s->cirrus_shadow_gr1;
610 break;
611 case 2:
612 color = s->cirrus_shadow_gr1 | (s->gr[0x11] << 8);
613 s->cirrus_blt_fgcol = le16_to_cpu(color);
614 break;
615 case 3:
616 s->cirrus_blt_fgcol = s->cirrus_shadow_gr1 |
617 (s->gr[0x11] << 8) | (s->gr[0x13] << 16);
618 break;
619 default:
620 case 4:
621 color = s->cirrus_shadow_gr1 | (s->gr[0x11] << 8) |
622 (s->gr[0x13] << 16) | (s->gr[0x15] << 24);
623 s->cirrus_blt_fgcol = le32_to_cpu(color);
624 break;
625 }
626 }
627
628 static inline void cirrus_bitblt_bgcol(CirrusVGAState *s)
629 {
630 unsigned int color;
631 switch (s->cirrus_blt_pixelwidth) {
632 case 1:
633 s->cirrus_blt_bgcol = s->cirrus_shadow_gr0;
634 break;
635 case 2:
636 color = s->cirrus_shadow_gr0 | (s->gr[0x10] << 8);
637 s->cirrus_blt_bgcol = le16_to_cpu(color);
638 break;
639 case 3:
640 s->cirrus_blt_bgcol = s->cirrus_shadow_gr0 |
641 (s->gr[0x10] << 8) | (s->gr[0x12] << 16);
642 break;
643 default:
644 case 4:
645 color = s->cirrus_shadow_gr0 | (s->gr[0x10] << 8) |
646 (s->gr[0x12] << 16) | (s->gr[0x14] << 24);
647 s->cirrus_blt_bgcol = le32_to_cpu(color);
648 break;
649 }
650 }
651
652 static void cirrus_invalidate_region(CirrusVGAState * s, int off_begin,
653 int off_pitch, int bytesperline,
654 int lines)
655 {
656 int y;
657 int off_cur;
658 int off_cur_end;
659
660 for (y = 0; y < lines; y++) {
661 off_cur = off_begin;
662 off_cur_end = (off_cur + bytesperline) & s->cirrus_addr_mask;
663 off_cur &= TARGET_PAGE_MASK;
664 while (off_cur < off_cur_end) {
665 cpu_physical_memory_set_dirty(s->vram_offset + off_cur);
666 off_cur += TARGET_PAGE_SIZE;
667 }
668 off_begin += off_pitch;
669 }
670 }
671
672 static int cirrus_bitblt_common_patterncopy(CirrusVGAState * s,
673 const uint8_t * src)
674 {
675 uint8_t *dst;
676
677 dst = s->vram_ptr + (s->cirrus_blt_dstaddr & s->cirrus_addr_mask);
678
679 if (BLTUNSAFE(s))
680 return 0;
681
682 (*s->cirrus_rop) (s, dst, src,
683 s->cirrus_blt_dstpitch, 0,
684 s->cirrus_blt_width, s->cirrus_blt_height);
685 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
686 s->cirrus_blt_dstpitch, s->cirrus_blt_width,
687 s->cirrus_blt_height);
688 return 1;
689 }
690
691 /* fill */
692
693 static int cirrus_bitblt_solidfill(CirrusVGAState *s, int blt_rop)
694 {
695 cirrus_fill_t rop_func;
696
697 if (BLTUNSAFE(s))
698 return 0;
699 rop_func = cirrus_fill[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
700 rop_func(s, s->vram_ptr + (s->cirrus_blt_dstaddr & s->cirrus_addr_mask),
701 s->cirrus_blt_dstpitch,
702 s->cirrus_blt_width, s->cirrus_blt_height);
703 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
704 s->cirrus_blt_dstpitch, s->cirrus_blt_width,
705 s->cirrus_blt_height);
706 cirrus_bitblt_reset(s);
707 return 1;
708 }
709
710 /***************************************
711 *
712 * bitblt (video-to-video)
713 *
714 ***************************************/
715
716 static int cirrus_bitblt_videotovideo_patterncopy(CirrusVGAState * s)
717 {
718 return cirrus_bitblt_common_patterncopy(s,
719 s->vram_ptr + ((s->cirrus_blt_srcaddr & ~7) &
720 s->cirrus_addr_mask));
721 }
722
723 static void cirrus_do_copy(CirrusVGAState *s, int dst, int src, int w, int h)
724 {
725 int sx, sy;
726 int dx, dy;
727 int width, height;
728 int depth;
729 int notify = 0;
730
731 depth = s->get_bpp((VGAState *)s) / 8;
732 s->get_resolution((VGAState *)s, &width, &height);
733
734 /* extra x, y */
735 sx = (src % (width * depth)) / depth;
736 sy = (src / (width * depth));
737 dx = (dst % (width *depth)) / depth;
738 dy = (dst / (width * depth));
739
740 /* normalize width */
741 w /= depth;
742
743 /* if we're doing a backward copy, we have to adjust
744 our x/y to be the upper left corner (instead of the lower
745 right corner) */
746 if (s->cirrus_blt_dstpitch < 0) {
747 sx -= (s->cirrus_blt_width / depth) - 1;
748 dx -= (s->cirrus_blt_width / depth) - 1;
749 sy -= s->cirrus_blt_height - 1;
750 dy -= s->cirrus_blt_height - 1;
751 }
752
753 /* are we in the visible portion of memory? */
754 if (sx >= 0 && sy >= 0 && dx >= 0 && dy >= 0 &&
755 (sx + w) <= width && (sy + h) <= height &&
756 (dx + w) <= width && (dy + h) <= height) {
757 notify = 1;
758 }
759
760 /* make to sure only copy if it's a plain copy ROP */
761 if (*s->cirrus_rop != cirrus_bitblt_rop_fwd_src &&
762 *s->cirrus_rop != cirrus_bitblt_rop_bkwd_src)
763 notify = 0;
764
765 /* we have to flush all pending changes so that the copy
766 is generated at the appropriate moment in time */
767 if (notify)
768 vga_hw_update();
769
770 (*s->cirrus_rop) (s, s->vram_ptr +
771 (s->cirrus_blt_dstaddr & s->cirrus_addr_mask),
772 s->vram_ptr +
773 (s->cirrus_blt_srcaddr & s->cirrus_addr_mask),
774 s->cirrus_blt_dstpitch, s->cirrus_blt_srcpitch,
775 s->cirrus_blt_width, s->cirrus_blt_height);
776
777 if (notify)
778 s->ds->dpy_copy(s->ds,
779 sx, sy, dx, dy,
780 s->cirrus_blt_width / depth,
781 s->cirrus_blt_height);
782
783 /* we don't have to notify the display that this portion has
784 changed since dpy_copy implies this */
785
786 if (!notify)
787 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
788 s->cirrus_blt_dstpitch, s->cirrus_blt_width,
789 s->cirrus_blt_height);
790 }
791
792 static int cirrus_bitblt_videotovideo_copy(CirrusVGAState * s)
793 {
794 if (s->ds->dpy_copy) {
795 cirrus_do_copy(s, s->cirrus_blt_dstaddr - s->start_addr,
796 s->cirrus_blt_srcaddr - s->start_addr,
797 s->cirrus_blt_width, s->cirrus_blt_height);
798 } else {
799
800 if (BLTUNSAFE(s))
801 return 0;
802
803 (*s->cirrus_rop) (s, s->vram_ptr +
804 (s->cirrus_blt_dstaddr & s->cirrus_addr_mask),
805 s->vram_ptr +
806 (s->cirrus_blt_srcaddr & s->cirrus_addr_mask),
807 s->cirrus_blt_dstpitch, s->cirrus_blt_srcpitch,
808 s->cirrus_blt_width, s->cirrus_blt_height);
809
810 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
811 s->cirrus_blt_dstpitch, s->cirrus_blt_width,
812 s->cirrus_blt_height);
813 }
814
815 return 1;
816 }
817
818 /***************************************
819 *
820 * bitblt (cpu-to-video)
821 *
822 ***************************************/
823
824 static void cirrus_bitblt_cputovideo_next(CirrusVGAState * s)
825 {
826 int copy_count;
827 uint8_t *end_ptr;
828
829 if (s->cirrus_srccounter > 0) {
830 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
831 cirrus_bitblt_common_patterncopy(s, s->cirrus_bltbuf);
832 the_end:
833 s->cirrus_srccounter = 0;
834 cirrus_bitblt_reset(s);
835 } else {
836 /* at least one scan line */
837 do {
838 (*s->cirrus_rop)(s, s->vram_ptr +
839 (s->cirrus_blt_dstaddr & s->cirrus_addr_mask),
840 s->cirrus_bltbuf, 0, 0, s->cirrus_blt_width, 1);
841 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr, 0,
842 s->cirrus_blt_width, 1);
843 s->cirrus_blt_dstaddr += s->cirrus_blt_dstpitch;
844 s->cirrus_srccounter -= s->cirrus_blt_srcpitch;
845 if (s->cirrus_srccounter <= 0)
846 goto the_end;
847 /* more bytes than needed can be transfered because of
848 word alignment, so we keep them for the next line */
849 /* XXX: keep alignment to speed up transfer */
850 end_ptr = s->cirrus_bltbuf + s->cirrus_blt_srcpitch;
851 copy_count = s->cirrus_srcptr_end - end_ptr;
852 memmove(s->cirrus_bltbuf, end_ptr, copy_count);
853 s->cirrus_srcptr = s->cirrus_bltbuf + copy_count;
854 s->cirrus_srcptr_end = s->cirrus_bltbuf + s->cirrus_blt_srcpitch;
855 } while (s->cirrus_srcptr >= s->cirrus_srcptr_end);
856 }
857 }
858 }
859
860 /***************************************
861 *
862 * bitblt wrapper
863 *
864 ***************************************/
865
866 static void cirrus_bitblt_reset(CirrusVGAState * s)
867 {
868 s->gr[0x31] &=
869 ~(CIRRUS_BLT_START | CIRRUS_BLT_BUSY | CIRRUS_BLT_FIFOUSED);
870 s->cirrus_srcptr = &s->cirrus_bltbuf[0];
871 s->cirrus_srcptr_end = &s->cirrus_bltbuf[0];
872 s->cirrus_srccounter = 0;
873 cirrus_update_memory_access(s);
874 }
875
876 static int cirrus_bitblt_cputovideo(CirrusVGAState * s)
877 {
878 int w;
879
880 s->cirrus_blt_mode &= ~CIRRUS_BLTMODE_MEMSYSSRC;
881 s->cirrus_srcptr = &s->cirrus_bltbuf[0];
882 s->cirrus_srcptr_end = &s->cirrus_bltbuf[0];
883
884 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
885 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
886 s->cirrus_blt_srcpitch = 8;
887 } else {
888 /* XXX: check for 24 bpp */
889 s->cirrus_blt_srcpitch = 8 * 8 * s->cirrus_blt_pixelwidth;
890 }
891 s->cirrus_srccounter = s->cirrus_blt_srcpitch;
892 } else {
893 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
894 w = s->cirrus_blt_width / s->cirrus_blt_pixelwidth;
895 if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_DWORDGRANULARITY)
896 s->cirrus_blt_srcpitch = ((w + 31) >> 5);
897 else
898 s->cirrus_blt_srcpitch = ((w + 7) >> 3);
899 } else {
900 /* always align input size to 32 bits */
901 s->cirrus_blt_srcpitch = (s->cirrus_blt_width + 3) & ~3;
902 }
903 s->cirrus_srccounter = s->cirrus_blt_srcpitch * s->cirrus_blt_height;
904 }
905 s->cirrus_srcptr = s->cirrus_bltbuf;
906 s->cirrus_srcptr_end = s->cirrus_bltbuf + s->cirrus_blt_srcpitch;
907 cirrus_update_memory_access(s);
908 return 1;
909 }
910
911 static int cirrus_bitblt_videotocpu(CirrusVGAState * s)
912 {
913 /* XXX */
914 #ifdef DEBUG_BITBLT
915 printf("cirrus: bitblt (video to cpu) is not implemented yet\n");
916 #endif
917 return 0;
918 }
919
920 static int cirrus_bitblt_videotovideo(CirrusVGAState * s)
921 {
922 int ret;
923
924 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
925 ret = cirrus_bitblt_videotovideo_patterncopy(s);
926 } else {
927 ret = cirrus_bitblt_videotovideo_copy(s);
928 }
929 if (ret)
930 cirrus_bitblt_reset(s);
931 return ret;
932 }
933
934 static void cirrus_bitblt_start(CirrusVGAState * s)
935 {
936 uint8_t blt_rop;
937
938 s->gr[0x31] |= CIRRUS_BLT_BUSY;
939
940 s->cirrus_blt_width = (s->gr[0x20] | (s->gr[0x21] << 8)) + 1;
941 s->cirrus_blt_height = (s->gr[0x22] | (s->gr[0x23] << 8)) + 1;
942 s->cirrus_blt_dstpitch = (s->gr[0x24] | (s->gr[0x25] << 8));
943 s->cirrus_blt_srcpitch = (s->gr[0x26] | (s->gr[0x27] << 8));
944 s->cirrus_blt_dstaddr =
945 (s->gr[0x28] | (s->gr[0x29] << 8) | (s->gr[0x2a] << 16));
946 s->cirrus_blt_srcaddr =
947 (s->gr[0x2c] | (s->gr[0x2d] << 8) | (s->gr[0x2e] << 16));
948 s->cirrus_blt_mode = s->gr[0x30];
949 s->cirrus_blt_modeext = s->gr[0x33];
950 blt_rop = s->gr[0x32];
951
952 #ifdef DEBUG_BITBLT
953 printf("rop=0x%02x mode=0x%02x modeext=0x%02x w=%d h=%d dpitch=%d spitch=%d daddr=0x%08x saddr=0x%08x writemask=0x%02x\n",
954 blt_rop,
955 s->cirrus_blt_mode,
956 s->cirrus_blt_modeext,
957 s->cirrus_blt_width,
958 s->cirrus_blt_height,
959 s->cirrus_blt_dstpitch,
960 s->cirrus_blt_srcpitch,
961 s->cirrus_blt_dstaddr,
962 s->cirrus_blt_srcaddr,
963 s->gr[0x2f]);
964 #endif
965
966 switch (s->cirrus_blt_mode & CIRRUS_BLTMODE_PIXELWIDTHMASK) {
967 case CIRRUS_BLTMODE_PIXELWIDTH8:
968 s->cirrus_blt_pixelwidth = 1;
969 break;
970 case CIRRUS_BLTMODE_PIXELWIDTH16:
971 s->cirrus_blt_pixelwidth = 2;
972 break;
973 case CIRRUS_BLTMODE_PIXELWIDTH24:
974 s->cirrus_blt_pixelwidth = 3;
975 break;
976 case CIRRUS_BLTMODE_PIXELWIDTH32:
977 s->cirrus_blt_pixelwidth = 4;
978 break;
979 default:
980 #ifdef DEBUG_BITBLT
981 printf("cirrus: bitblt - pixel width is unknown\n");
982 #endif
983 goto bitblt_ignore;
984 }
985 s->cirrus_blt_mode &= ~CIRRUS_BLTMODE_PIXELWIDTHMASK;
986
987 if ((s->
988 cirrus_blt_mode & (CIRRUS_BLTMODE_MEMSYSSRC |
989 CIRRUS_BLTMODE_MEMSYSDEST))
990 == (CIRRUS_BLTMODE_MEMSYSSRC | CIRRUS_BLTMODE_MEMSYSDEST)) {
991 #ifdef DEBUG_BITBLT
992 printf("cirrus: bitblt - memory-to-memory copy is requested\n");
993 #endif
994 goto bitblt_ignore;
995 }
996
997 if ((s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_SOLIDFILL) &&
998 (s->cirrus_blt_mode & (CIRRUS_BLTMODE_MEMSYSDEST |
999 CIRRUS_BLTMODE_TRANSPARENTCOMP |
1000 CIRRUS_BLTMODE_PATTERNCOPY |
1001 CIRRUS_BLTMODE_COLOREXPAND)) ==
1002 (CIRRUS_BLTMODE_PATTERNCOPY | CIRRUS_BLTMODE_COLOREXPAND)) {
1003 cirrus_bitblt_fgcol(s);
1004 cirrus_bitblt_solidfill(s, blt_rop);
1005 } else {
1006 if ((s->cirrus_blt_mode & (CIRRUS_BLTMODE_COLOREXPAND |
1007 CIRRUS_BLTMODE_PATTERNCOPY)) ==
1008 CIRRUS_BLTMODE_COLOREXPAND) {
1009
1010 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
1011 if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_COLOREXPINV)
1012 cirrus_bitblt_bgcol(s);
1013 else
1014 cirrus_bitblt_fgcol(s);
1015 s->cirrus_rop = cirrus_colorexpand_transp[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1016 } else {
1017 cirrus_bitblt_fgcol(s);
1018 cirrus_bitblt_bgcol(s);
1019 s->cirrus_rop = cirrus_colorexpand[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1020 }
1021 } else if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
1022 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
1023 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
1024 if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_COLOREXPINV)
1025 cirrus_bitblt_bgcol(s);
1026 else
1027 cirrus_bitblt_fgcol(s);
1028 s->cirrus_rop = cirrus_colorexpand_pattern_transp[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1029 } else {
1030 cirrus_bitblt_fgcol(s);
1031 cirrus_bitblt_bgcol(s);
1032 s->cirrus_rop = cirrus_colorexpand_pattern[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1033 }
1034 } else {
1035 s->cirrus_rop = cirrus_patternfill[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1036 }
1037 } else {
1038 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
1039 if (s->cirrus_blt_pixelwidth > 2) {
1040 printf("src transparent without colorexpand must be 8bpp or 16bpp\n");
1041 goto bitblt_ignore;
1042 }
1043 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_BACKWARDS) {
1044 s->cirrus_blt_dstpitch = -s->cirrus_blt_dstpitch;
1045 s->cirrus_blt_srcpitch = -s->cirrus_blt_srcpitch;
1046 s->cirrus_rop = cirrus_bkwd_transp_rop[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1047 } else {
1048 s->cirrus_rop = cirrus_fwd_transp_rop[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1049 }
1050 } else {
1051 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_BACKWARDS) {
1052 s->cirrus_blt_dstpitch = -s->cirrus_blt_dstpitch;
1053 s->cirrus_blt_srcpitch = -s->cirrus_blt_srcpitch;
1054 s->cirrus_rop = cirrus_bkwd_rop[rop_to_index[blt_rop]];
1055 } else {
1056 s->cirrus_rop = cirrus_fwd_rop[rop_to_index[blt_rop]];
1057 }
1058 }
1059 }
1060 // setup bitblt engine.
1061 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_MEMSYSSRC) {
1062 if (!cirrus_bitblt_cputovideo(s))
1063 goto bitblt_ignore;
1064 } else if (s->cirrus_blt_mode & CIRRUS_BLTMODE_MEMSYSDEST) {
1065 if (!cirrus_bitblt_videotocpu(s))
1066 goto bitblt_ignore;
1067 } else {
1068 if (!cirrus_bitblt_videotovideo(s))
1069 goto bitblt_ignore;
1070 }
1071 }
1072 return;
1073 bitblt_ignore:;
1074 cirrus_bitblt_reset(s);
1075 }
1076
1077 static void cirrus_write_bitblt(CirrusVGAState * s, unsigned reg_value)
1078 {
1079 unsigned old_value;
1080
1081 old_value = s->gr[0x31];
1082 s->gr[0x31] = reg_value;
1083
1084 if (((old_value & CIRRUS_BLT_RESET) != 0) &&
1085 ((reg_value & CIRRUS_BLT_RESET) == 0)) {
1086 cirrus_bitblt_reset(s);
1087 } else if (((old_value & CIRRUS_BLT_START) == 0) &&
1088 ((reg_value & CIRRUS_BLT_START) != 0)) {
1089 cirrus_bitblt_start(s);
1090 }
1091 }
1092
1093
1094 /***************************************
1095 *
1096 * basic parameters
1097 *
1098 ***************************************/
1099
1100 static void cirrus_get_offsets(VGAState *s1,
1101 uint32_t *pline_offset,
1102 uint32_t *pstart_addr,
1103 uint32_t *pline_compare)
1104 {
1105 CirrusVGAState * s = (CirrusVGAState *)s1;
1106 uint32_t start_addr, line_offset, line_compare;
1107
1108 line_offset = s->cr[0x13]
1109 | ((s->cr[0x1b] & 0x10) << 4);
1110 line_offset <<= 3;
1111 *pline_offset = line_offset;
1112
1113 start_addr = (s->cr[0x0c] << 8)
1114 | s->cr[0x0d]
1115 | ((s->cr[0x1b] & 0x01) << 16)
1116 | ((s->cr[0x1b] & 0x0c) << 15)
1117 | ((s->cr[0x1d] & 0x80) << 12);
1118 *pstart_addr = start_addr;
1119
1120 line_compare = s->cr[0x18] |
1121 ((s->cr[0x07] & 0x10) << 4) |
1122 ((s->cr[0x09] & 0x40) << 3);
1123 *pline_compare = line_compare;
1124 }
1125
1126 static uint32_t cirrus_get_bpp16_depth(CirrusVGAState * s)
1127 {
1128 uint32_t ret = 16;
1129
1130 switch (s->cirrus_hidden_dac_data & 0xf) {
1131 case 0:
1132 ret = 15;
1133 break; /* Sierra HiColor */
1134 case 1:
1135 ret = 16;
1136 break; /* XGA HiColor */
1137 default:
1138 #ifdef DEBUG_CIRRUS
1139 printf("cirrus: invalid DAC value %x in 16bpp\n",
1140 (s->cirrus_hidden_dac_data & 0xf));
1141 #endif
1142 ret = 15; /* XXX */
1143 break;
1144 }
1145 return ret;
1146 }
1147
1148 static int cirrus_get_bpp(VGAState *s1)
1149 {
1150 CirrusVGAState * s = (CirrusVGAState *)s1;
1151 uint32_t ret = 8;
1152
1153 if ((s->sr[0x07] & 0x01) != 0) {
1154 /* Cirrus SVGA */
1155 switch (s->sr[0x07] & CIRRUS_SR7_BPP_MASK) {
1156 case CIRRUS_SR7_BPP_8:
1157 ret = 8;
1158 break;
1159 case CIRRUS_SR7_BPP_16_DOUBLEVCLK:
1160 ret = cirrus_get_bpp16_depth(s);
1161 break;
1162 case CIRRUS_SR7_BPP_24:
1163 ret = 24;
1164 break;
1165 case CIRRUS_SR7_BPP_16:
1166 ret = cirrus_get_bpp16_depth(s);
1167 break;
1168 case CIRRUS_SR7_BPP_32:
1169 ret = 32;
1170 break;
1171 default:
1172 #ifdef DEBUG_CIRRUS
1173 printf("cirrus: unknown bpp - sr7=%x\n", s->sr[0x7]);
1174 #endif
1175 ret = 8;
1176 break;
1177 }
1178 } else {
1179 /* VGA */
1180 ret = 0;
1181 }
1182
1183 return ret;
1184 }
1185
1186 static void cirrus_get_resolution(VGAState *s, int *pwidth, int *pheight)
1187 {
1188 int width, height;
1189
1190 width = (s->cr[0x01] + 1) * 8;
1191 height = s->cr[0x12] |
1192 ((s->cr[0x07] & 0x02) << 7) |
1193 ((s->cr[0x07] & 0x40) << 3);
1194 height = (height + 1);
1195 /* interlace support */
1196 if (s->cr[0x1a] & 0x01)
1197 height = height * 2;
1198 *pwidth = width;
1199 *pheight = height;
1200 }
1201
1202 /***************************************
1203 *
1204 * bank memory
1205 *
1206 ***************************************/
1207
1208 static void cirrus_update_bank_ptr(CirrusVGAState * s, unsigned bank_index)
1209 {
1210 unsigned offset;
1211 unsigned limit;
1212
1213 if ((s->gr[0x0b] & 0x01) != 0) /* dual bank */
1214 offset = s->gr[0x09 + bank_index];
1215 else /* single bank */
1216 offset = s->gr[0x09];
1217
1218 if ((s->gr[0x0b] & 0x20) != 0)
1219 offset <<= 14;
1220 else
1221 offset <<= 12;
1222
1223 if (s->real_vram_size <= offset)
1224 limit = 0;
1225 else
1226 limit = s->real_vram_size - offset;
1227
1228 if (((s->gr[0x0b] & 0x01) == 0) && (bank_index != 0)) {
1229 if (limit > 0x8000) {
1230 offset += 0x8000;
1231 limit -= 0x8000;
1232 } else {
1233 limit = 0;
1234 }
1235 }
1236
1237 if (limit > 0) {
1238 s->cirrus_bank_base[bank_index] = offset;
1239 s->cirrus_bank_limit[bank_index] = limit;
1240 } else {
1241 s->cirrus_bank_base[bank_index] = 0;
1242 s->cirrus_bank_limit[bank_index] = 0;
1243 }
1244 }
1245
1246 /***************************************
1247 *
1248 * I/O access between 0x3c4-0x3c5
1249 *
1250 ***************************************/
1251
1252 static int
1253 cirrus_hook_read_sr(CirrusVGAState * s, unsigned reg_index, int *reg_value)
1254 {
1255 switch (reg_index) {
1256 case 0x00: // Standard VGA
1257 case 0x01: // Standard VGA
1258 case 0x02: // Standard VGA
1259 case 0x03: // Standard VGA
1260 case 0x04: // Standard VGA
1261 return CIRRUS_HOOK_NOT_HANDLED;
1262 case 0x06: // Unlock Cirrus extensions
1263 *reg_value = s->sr[reg_index];
1264 break;
1265 case 0x10:
1266 case 0x30:
1267 case 0x50:
1268 case 0x70: // Graphics Cursor X
1269 case 0x90:
1270 case 0xb0:
1271 case 0xd0:
1272 case 0xf0: // Graphics Cursor X
1273 *reg_value = s->sr[0x10];
1274 break;
1275 case 0x11:
1276 case 0x31:
1277 case 0x51:
1278 case 0x71: // Graphics Cursor Y
1279 case 0x91:
1280 case 0xb1:
1281 case 0xd1:
1282 case 0xf1: // Graphics Cursor Y
1283 *reg_value = s->sr[0x11];
1284 break;
1285 case 0x05: // ???
1286 case 0x07: // Extended Sequencer Mode
1287 case 0x08: // EEPROM Control
1288 case 0x09: // Scratch Register 0
1289 case 0x0a: // Scratch Register 1
1290 case 0x0b: // VCLK 0
1291 case 0x0c: // VCLK 1
1292 case 0x0d: // VCLK 2
1293 case 0x0e: // VCLK 3
1294 case 0x0f: // DRAM Control
1295 case 0x12: // Graphics Cursor Attribute
1296 case 0x13: // Graphics Cursor Pattern Address
1297 case 0x14: // Scratch Register 2
1298 case 0x15: // Scratch Register 3
1299 case 0x16: // Performance Tuning Register
1300 case 0x17: // Configuration Readback and Extended Control
1301 case 0x18: // Signature Generator Control
1302 case 0x19: // Signal Generator Result
1303 case 0x1a: // Signal Generator Result
1304 case 0x1b: // VCLK 0 Denominator & Post
1305 case 0x1c: // VCLK 1 Denominator & Post
1306 case 0x1d: // VCLK 2 Denominator & Post
1307 case 0x1e: // VCLK 3 Denominator & Post
1308 case 0x1f: // BIOS Write Enable and MCLK select
1309 #ifdef DEBUG_CIRRUS
1310 printf("cirrus: handled inport sr_index %02x\n", reg_index);
1311 #endif
1312 *reg_value = s->sr[reg_index];
1313 break;
1314 default:
1315 #ifdef DEBUG_CIRRUS
1316 printf("cirrus: inport sr_index %02x\n", reg_index);
1317 #endif
1318 *reg_value = 0xff;
1319 break;
1320 }
1321
1322 return CIRRUS_HOOK_HANDLED;
1323 }
1324
1325 static int
1326 cirrus_hook_write_sr(CirrusVGAState * s, unsigned reg_index, int reg_value)
1327 {
1328 switch (reg_index) {
1329 case 0x00: // Standard VGA
1330 case 0x01: // Standard VGA
1331 case 0x02: // Standard VGA
1332 case 0x03: // Standard VGA
1333 case 0x04: // Standard VGA
1334 return CIRRUS_HOOK_NOT_HANDLED;
1335 case 0x06: // Unlock Cirrus extensions
1336 reg_value &= 0x17;
1337 if (reg_value == 0x12) {
1338 s->sr[reg_index] = 0x12;
1339 } else {
1340 s->sr[reg_index] = 0x0f;
1341 }
1342 break;
1343 case 0x10:
1344 case 0x30:
1345 case 0x50:
1346 case 0x70: // Graphics Cursor X
1347 case 0x90:
1348 case 0xb0:
1349 case 0xd0:
1350 case 0xf0: // Graphics Cursor X
1351 s->sr[0x10] = reg_value;
1352 s->hw_cursor_x = (reg_value << 3) | (reg_index >> 5);
1353 break;
1354 case 0x11:
1355 case 0x31:
1356 case 0x51:
1357 case 0x71: // Graphics Cursor Y
1358 case 0x91:
1359 case 0xb1:
1360 case 0xd1:
1361 case 0xf1: // Graphics Cursor Y
1362 s->sr[0x11] = reg_value;
1363 s->hw_cursor_y = (reg_value << 3) | (reg_index >> 5);
1364 break;
1365 case 0x07: // Extended Sequencer Mode
1366 case 0x08: // EEPROM Control
1367 case 0x09: // Scratch Register 0
1368 case 0x0a: // Scratch Register 1
1369 case 0x0b: // VCLK 0
1370 case 0x0c: // VCLK 1
1371 case 0x0d: // VCLK 2
1372 case 0x0e: // VCLK 3
1373 case 0x0f: // DRAM Control
1374 case 0x12: // Graphics Cursor Attribute
1375 case 0x13: // Graphics Cursor Pattern Address
1376 case 0x14: // Scratch Register 2
1377 case 0x15: // Scratch Register 3
1378 case 0x16: // Performance Tuning Register
1379 case 0x18: // Signature Generator Control
1380 case 0x19: // Signature Generator Result
1381 case 0x1a: // Signature Generator Result
1382 case 0x1b: // VCLK 0 Denominator & Post
1383 case 0x1c: // VCLK 1 Denominator & Post
1384 case 0x1d: // VCLK 2 Denominator & Post
1385 case 0x1e: // VCLK 3 Denominator & Post
1386 case 0x1f: // BIOS Write Enable and MCLK select
1387 s->sr[reg_index] = reg_value;
1388 #ifdef DEBUG_CIRRUS
1389 printf("cirrus: handled outport sr_index %02x, sr_value %02x\n",
1390 reg_index, reg_value);
1391 #endif
1392 if (reg_index == 0x07)
1393 cirrus_update_memory_access(s);
1394 break;
1395 case 0x17: // Configuration Readback and Extended Control
1396 s->sr[reg_index] = (s->sr[reg_index] & 0x38) | (reg_value & 0xc7);
1397 cirrus_update_memory_access(s);
1398 break;
1399 default:
1400 #ifdef DEBUG_CIRRUS
1401 printf("cirrus: outport sr_index %02x, sr_value %02x\n", reg_index,
1402 reg_value);
1403 #endif
1404 break;
1405 }
1406
1407 return CIRRUS_HOOK_HANDLED;
1408 }
1409
1410 /***************************************
1411 *
1412 * I/O access at 0x3c6
1413 *
1414 ***************************************/
1415
1416 static void cirrus_read_hidden_dac(CirrusVGAState * s, int *reg_value)
1417 {
1418 *reg_value = 0xff;
1419 if (++s->cirrus_hidden_dac_lockindex == 5) {
1420 *reg_value = s->cirrus_hidden_dac_data;
1421 s->cirrus_hidden_dac_lockindex = 0;
1422 }
1423 }
1424
1425 static void cirrus_write_hidden_dac(CirrusVGAState * s, int reg_value)
1426 {
1427 if (s->cirrus_hidden_dac_lockindex == 4) {
1428 s->cirrus_hidden_dac_data = reg_value;
1429 #if defined(DEBUG_CIRRUS)
1430 printf("cirrus: outport hidden DAC, value %02x\n", reg_value);
1431 #endif
1432 }
1433 s->cirrus_hidden_dac_lockindex = 0;
1434 }
1435
1436 /***************************************
1437 *
1438 * I/O access at 0x3c9
1439 *
1440 ***************************************/
1441
1442 static int cirrus_hook_read_palette(CirrusVGAState * s, int *reg_value)
1443 {
1444 if (!(s->sr[0x12] & CIRRUS_CURSOR_HIDDENPEL))
1445 return CIRRUS_HOOK_NOT_HANDLED;
1446 *reg_value =
1447 s->cirrus_hidden_palette[(s->dac_read_index & 0x0f) * 3 +
1448 s->dac_sub_index];
1449 if (++s->dac_sub_index == 3) {
1450 s->dac_sub_index = 0;
1451 s->dac_read_index++;
1452 }
1453 return CIRRUS_HOOK_HANDLED;
1454 }
1455
1456 static int cirrus_hook_write_palette(CirrusVGAState * s, int reg_value)
1457 {
1458 if (!(s->sr[0x12] & CIRRUS_CURSOR_HIDDENPEL))
1459 return CIRRUS_HOOK_NOT_HANDLED;
1460 s->dac_cache[s->dac_sub_index] = reg_value;
1461 if (++s->dac_sub_index == 3) {
1462 memcpy(&s->cirrus_hidden_palette[(s->dac_write_index & 0x0f) * 3],
1463 s->dac_cache, 3);
1464 /* XXX update cursor */
1465 s->dac_sub_index = 0;
1466 s->dac_write_index++;
1467 }
1468 return CIRRUS_HOOK_HANDLED;
1469 }
1470
1471 /***************************************
1472 *
1473 * I/O access between 0x3ce-0x3cf
1474 *
1475 ***************************************/
1476
1477 static int
1478 cirrus_hook_read_gr(CirrusVGAState * s, unsigned reg_index, int *reg_value)
1479 {
1480 switch (reg_index) {
1481 case 0x00: // Standard VGA, BGCOLOR 0x000000ff
1482 *reg_value = s->cirrus_shadow_gr0;
1483 return CIRRUS_HOOK_HANDLED;
1484 case 0x01: // Standard VGA, FGCOLOR 0x000000ff
1485 *reg_value = s->cirrus_shadow_gr1;
1486 return CIRRUS_HOOK_HANDLED;
1487 case 0x02: // Standard VGA
1488 case 0x03: // Standard VGA
1489 case 0x04: // Standard VGA
1490 case 0x06: // Standard VGA
1491 case 0x07: // Standard VGA
1492 case 0x08: // Standard VGA
1493 return CIRRUS_HOOK_NOT_HANDLED;
1494 case 0x05: // Standard VGA, Cirrus extended mode
1495 default:
1496 break;
1497 }
1498
1499 if (reg_index < 0x3a) {
1500 *reg_value = s->gr[reg_index];
1501 } else {
1502 #ifdef DEBUG_CIRRUS
1503 printf("cirrus: inport gr_index %02x\n", reg_index);
1504 #endif
1505 *reg_value = 0xff;
1506 }
1507
1508 return CIRRUS_HOOK_HANDLED;
1509 }
1510
1511 static int
1512 cirrus_hook_write_gr(CirrusVGAState * s, unsigned reg_index, int reg_value)
1513 {
1514 #if defined(DEBUG_BITBLT) && 0
1515 printf("gr%02x: %02x\n", reg_index, reg_value);
1516 #endif
1517 switch (reg_index) {
1518 case 0x00: // Standard VGA, BGCOLOR 0x000000ff
1519 s->cirrus_shadow_gr0 = reg_value;
1520 return CIRRUS_HOOK_NOT_HANDLED;
1521 case 0x01: // Standard VGA, FGCOLOR 0x000000ff
1522 s->cirrus_shadow_gr1 = reg_value;
1523 return CIRRUS_HOOK_NOT_HANDLED;
1524 case 0x02: // Standard VGA
1525 case 0x03: // Standard VGA
1526 case 0x04: // Standard VGA
1527 case 0x06: // Standard VGA
1528 case 0x07: // Standard VGA
1529 case 0x08: // Standard VGA
1530 return CIRRUS_HOOK_NOT_HANDLED;
1531 case 0x05: // Standard VGA, Cirrus extended mode
1532 s->gr[reg_index] = reg_value & 0x7f;
1533 cirrus_update_memory_access(s);
1534 break;
1535 case 0x09: // bank offset #0
1536 case 0x0A: // bank offset #1
1537 s->gr[reg_index] = reg_value;
1538 cirrus_update_bank_ptr(s, 0);
1539 cirrus_update_bank_ptr(s, 1);
1540 cirrus_update_memory_access(s);
1541 break;
1542 case 0x0B:
1543 s->gr[reg_index] = reg_value;
1544 cirrus_update_bank_ptr(s, 0);
1545 cirrus_update_bank_ptr(s, 1);
1546 cirrus_update_memory_access(s);
1547 break;
1548 case 0x10: // BGCOLOR 0x0000ff00
1549 case 0x11: // FGCOLOR 0x0000ff00
1550 case 0x12: // BGCOLOR 0x00ff0000
1551 case 0x13: // FGCOLOR 0x00ff0000
1552 case 0x14: // BGCOLOR 0xff000000
1553 case 0x15: // FGCOLOR 0xff000000
1554 case 0x20: // BLT WIDTH 0x0000ff
1555 case 0x22: // BLT HEIGHT 0x0000ff
1556 case 0x24: // BLT DEST PITCH 0x0000ff
1557 case 0x26: // BLT SRC PITCH 0x0000ff
1558 case 0x28: // BLT DEST ADDR 0x0000ff
1559 case 0x29: // BLT DEST ADDR 0x00ff00
1560 case 0x2c: // BLT SRC ADDR 0x0000ff
1561 case 0x2d: // BLT SRC ADDR 0x00ff00
1562 case 0x2f: // BLT WRITEMASK
1563 case 0x30: // BLT MODE
1564 case 0x32: // RASTER OP
1565 case 0x33: // BLT MODEEXT
1566 case 0x34: // BLT TRANSPARENT COLOR 0x00ff
1567 case 0x35: // BLT TRANSPARENT COLOR 0xff00
1568 case 0x38: // BLT TRANSPARENT COLOR MASK 0x00ff
1569 case 0x39: // BLT TRANSPARENT COLOR MASK 0xff00
1570 s->gr[reg_index] = reg_value;
1571 break;
1572 case 0x21: // BLT WIDTH 0x001f00
1573 case 0x23: // BLT HEIGHT 0x001f00
1574 case 0x25: // BLT DEST PITCH 0x001f00
1575 case 0x27: // BLT SRC PITCH 0x001f00
1576 s->gr[reg_index] = reg_value & 0x1f;
1577 break;
1578 case 0x2a: // BLT DEST ADDR 0x3f0000
1579 s->gr[reg_index] = reg_value & 0x3f;
1580 /* if auto start mode, starts bit blt now */
1581 if (s->gr[0x31] & CIRRUS_BLT_AUTOSTART) {
1582 cirrus_bitblt_start(s);
1583 }
1584 break;
1585 case 0x2e: // BLT SRC ADDR 0x3f0000
1586 s->gr[reg_index] = reg_value & 0x3f;
1587 break;
1588 case 0x31: // BLT STATUS/START
1589 cirrus_write_bitblt(s, reg_value);
1590 break;
1591 default:
1592 #ifdef DEBUG_CIRRUS
1593 printf("cirrus: outport gr_index %02x, gr_value %02x\n", reg_index,
1594 reg_value);
1595 #endif
1596 break;
1597 }
1598
1599 return CIRRUS_HOOK_HANDLED;
1600 }
1601
1602 /***************************************
1603 *
1604 * I/O access between 0x3d4-0x3d5
1605 *
1606 ***************************************/
1607
1608 static int
1609 cirrus_hook_read_cr(CirrusVGAState * s, unsigned reg_index, int *reg_value)
1610 {
1611 switch (reg_index) {
1612 case 0x00: // Standard VGA
1613 case 0x01: // Standard VGA
1614 case 0x02: // Standard VGA
1615 case 0x03: // Standard VGA
1616 case 0x04: // Standard VGA
1617 case 0x05: // Standard VGA
1618 case 0x06: // Standard VGA
1619 case 0x07: // Standard VGA
1620 case 0x08: // Standard VGA
1621 case 0x09: // Standard VGA
1622 case 0x0a: // Standard VGA
1623 case 0x0b: // Standard VGA
1624 case 0x0c: // Standard VGA
1625 case 0x0d: // Standard VGA
1626 case 0x0e: // Standard VGA
1627 case 0x0f: // Standard VGA
1628 case 0x10: // Standard VGA
1629 case 0x11: // Standard VGA
1630 case 0x12: // Standard VGA
1631 case 0x13: // Standard VGA
1632 case 0x14: // Standard VGA
1633 case 0x15: // Standard VGA
1634 case 0x16: // Standard VGA
1635 case 0x17: // Standard VGA
1636 case 0x18: // Standard VGA
1637 return CIRRUS_HOOK_NOT_HANDLED;
1638 case 0x24: // Attribute Controller Toggle Readback (R)
1639 *reg_value = (s->ar_flip_flop << 7);
1640 break;
1641 case 0x19: // Interlace End
1642 case 0x1a: // Miscellaneous Control
1643 case 0x1b: // Extended Display Control
1644 case 0x1c: // Sync Adjust and Genlock
1645 case 0x1d: // Overlay Extended Control
1646 case 0x22: // Graphics Data Latches Readback (R)
1647 case 0x25: // Part Status
1648 case 0x27: // Part ID (R)
1649 *reg_value = s->cr[reg_index];
1650 break;
1651 case 0x26: // Attribute Controller Index Readback (R)
1652 *reg_value = s->ar_index & 0x3f;
1653 break;
1654 default:
1655 #ifdef DEBUG_CIRRUS
1656 printf("cirrus: inport cr_index %02x\n", reg_index);
1657 *reg_value = 0xff;
1658 #endif
1659 break;
1660 }
1661
1662 return CIRRUS_HOOK_HANDLED;
1663 }
1664
1665 static int
1666 cirrus_hook_write_cr(CirrusVGAState * s, unsigned reg_index, int reg_value)
1667 {
1668 switch (reg_index) {
1669 case 0x00: // Standard VGA
1670 case 0x01: // Standard VGA
1671 case 0x02: // Standard VGA
1672 case 0x03: // Standard VGA
1673 case 0x04: // Standard VGA
1674 case 0x05: // Standard VGA
1675 case 0x06: // Standard VGA
1676 case 0x07: // Standard VGA
1677 case 0x08: // Standard VGA
1678 case 0x09: // Standard VGA
1679 case 0x0a: // Standard VGA
1680 case 0x0b: // Standard VGA
1681 case 0x0c: // Standard VGA
1682 case 0x0d: // Standard VGA
1683 case 0x0e: // Standard VGA
1684 case 0x0f: // Standard VGA
1685 case 0x10: // Standard VGA
1686 case 0x11: // Standard VGA
1687 case 0x12: // Standard VGA
1688 case 0x13: // Standard VGA
1689 case 0x14: // Standard VGA
1690 case 0x15: // Standard VGA
1691 case 0x16: // Standard VGA
1692 case 0x17: // Standard VGA
1693 case 0x18: // Standard VGA
1694 return CIRRUS_HOOK_NOT_HANDLED;
1695 case 0x19: // Interlace End
1696 case 0x1a: // Miscellaneous Control
1697 case 0x1b: // Extended Display Control
1698 case 0x1c: // Sync Adjust and Genlock
1699 case 0x1d: // Overlay Extended Control
1700 s->cr[reg_index] = reg_value;
1701 #ifdef DEBUG_CIRRUS
1702 printf("cirrus: handled outport cr_index %02x, cr_value %02x\n",
1703 reg_index, reg_value);
1704 #endif
1705 break;
1706 case 0x22: // Graphics Data Latches Readback (R)
1707 case 0x24: // Attribute Controller Toggle Readback (R)
1708 case 0x26: // Attribute Controller Index Readback (R)
1709 case 0x27: // Part ID (R)
1710 break;
1711 case 0x25: // Part Status
1712 default:
1713 #ifdef DEBUG_CIRRUS
1714 printf("cirrus: outport cr_index %02x, cr_value %02x\n", reg_index,
1715 reg_value);
1716 #endif
1717 break;
1718 }
1719
1720 return CIRRUS_HOOK_HANDLED;
1721 }
1722
1723 /***************************************
1724 *
1725 * memory-mapped I/O (bitblt)
1726 *
1727 ***************************************/
1728
1729 static uint8_t cirrus_mmio_blt_read(CirrusVGAState * s, unsigned address)
1730 {
1731 int value = 0xff;
1732
1733 switch (address) {
1734 case (CIRRUS_MMIO_BLTBGCOLOR + 0):
1735 cirrus_hook_read_gr(s, 0x00, &value);
1736 break;
1737 case (CIRRUS_MMIO_BLTBGCOLOR + 1):
1738 cirrus_hook_read_gr(s, 0x10, &value);
1739 break;
1740 case (CIRRUS_MMIO_BLTBGCOLOR + 2):
1741 cirrus_hook_read_gr(s, 0x12, &value);
1742 break;
1743 case (CIRRUS_MMIO_BLTBGCOLOR + 3):
1744 cirrus_hook_read_gr(s, 0x14, &value);
1745 break;
1746 case (CIRRUS_MMIO_BLTFGCOLOR + 0):
1747 cirrus_hook_read_gr(s, 0x01, &value);
1748 break;
1749 case (CIRRUS_MMIO_BLTFGCOLOR + 1):
1750 cirrus_hook_read_gr(s, 0x11, &value);
1751 break;
1752 case (CIRRUS_MMIO_BLTFGCOLOR + 2):
1753 cirrus_hook_read_gr(s, 0x13, &value);
1754 break;
1755 case (CIRRUS_MMIO_BLTFGCOLOR + 3):
1756 cirrus_hook_read_gr(s, 0x15, &value);
1757 break;
1758 case (CIRRUS_MMIO_BLTWIDTH + 0):
1759 cirrus_hook_read_gr(s, 0x20, &value);
1760 break;
1761 case (CIRRUS_MMIO_BLTWIDTH + 1):
1762 cirrus_hook_read_gr(s, 0x21, &value);
1763 break;
1764 case (CIRRUS_MMIO_BLTHEIGHT + 0):
1765 cirrus_hook_read_gr(s, 0x22, &value);
1766 break;
1767 case (CIRRUS_MMIO_BLTHEIGHT + 1):
1768 cirrus_hook_read_gr(s, 0x23, &value);
1769 break;
1770 case (CIRRUS_MMIO_BLTDESTPITCH + 0):
1771 cirrus_hook_read_gr(s, 0x24, &value);
1772 break;
1773 case (CIRRUS_MMIO_BLTDESTPITCH + 1):
1774 cirrus_hook_read_gr(s, 0x25, &value);
1775 break;
1776 case (CIRRUS_MMIO_BLTSRCPITCH + 0):
1777 cirrus_hook_read_gr(s, 0x26, &value);
1778 break;
1779 case (CIRRUS_MMIO_BLTSRCPITCH + 1):
1780 cirrus_hook_read_gr(s, 0x27, &value);
1781 break;
1782 case (CIRRUS_MMIO_BLTDESTADDR + 0):
1783 cirrus_hook_read_gr(s, 0x28, &value);
1784 break;
1785 case (CIRRUS_MMIO_BLTDESTADDR + 1):
1786 cirrus_hook_read_gr(s, 0x29, &value);
1787 break;
1788 case (CIRRUS_MMIO_BLTDESTADDR + 2):
1789 cirrus_hook_read_gr(s, 0x2a, &value);
1790 break;
1791 case (CIRRUS_MMIO_BLTSRCADDR + 0):
1792 cirrus_hook_read_gr(s, 0x2c, &value);
1793 break;
1794 case (CIRRUS_MMIO_BLTSRCADDR + 1):
1795 cirrus_hook_read_gr(s, 0x2d, &value);
1796 break;
1797 case (CIRRUS_MMIO_BLTSRCADDR + 2):
1798 cirrus_hook_read_gr(s, 0x2e, &value);
1799 break;
1800 case CIRRUS_MMIO_BLTWRITEMASK:
1801 cirrus_hook_read_gr(s, 0x2f, &value);
1802 break;
1803 case CIRRUS_MMIO_BLTMODE:
1804 cirrus_hook_read_gr(s, 0x30, &value);
1805 break;
1806 case CIRRUS_MMIO_BLTROP:
1807 cirrus_hook_read_gr(s, 0x32, &value);
1808 break;
1809 case CIRRUS_MMIO_BLTMODEEXT:
1810 cirrus_hook_read_gr(s, 0x33, &value);
1811 break;
1812 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 0):
1813 cirrus_hook_read_gr(s, 0x34, &value);
1814 break;
1815 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 1):
1816 cirrus_hook_read_gr(s, 0x35, &value);
1817 break;
1818 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 0):
1819 cirrus_hook_read_gr(s, 0x38, &value);
1820 break;
1821 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 1):
1822 cirrus_hook_read_gr(s, 0x39, &value);
1823 break;
1824 case CIRRUS_MMIO_BLTSTATUS:
1825 cirrus_hook_read_gr(s, 0x31, &value);
1826 break;
1827 default:
1828 #ifdef DEBUG_CIRRUS
1829 printf("cirrus: mmio read - address 0x%04x\n", address);
1830 #endif
1831 break;
1832 }
1833
1834 return (uint8_t) value;
1835 }
1836
1837 static void cirrus_mmio_blt_write(CirrusVGAState * s, unsigned address,
1838 uint8_t value)
1839 {
1840 switch (address) {
1841 case (CIRRUS_MMIO_BLTBGCOLOR + 0):
1842 cirrus_hook_write_gr(s, 0x00, value);
1843 break;
1844 case (CIRRUS_MMIO_BLTBGCOLOR + 1):
1845 cirrus_hook_write_gr(s, 0x10, value);
1846 break;
1847 case (CIRRUS_MMIO_BLTBGCOLOR + 2):
1848 cirrus_hook_write_gr(s, 0x12, value);
1849 break;
1850 case (CIRRUS_MMIO_BLTBGCOLOR + 3):
1851 cirrus_hook_write_gr(s, 0x14, value);
1852 break;
1853 case (CIRRUS_MMIO_BLTFGCOLOR + 0):
1854 cirrus_hook_write_gr(s, 0x01, value);
1855 break;
1856 case (CIRRUS_MMIO_BLTFGCOLOR + 1):
1857 cirrus_hook_write_gr(s, 0x11, value);
1858 break;
1859 case (CIRRUS_MMIO_BLTFGCOLOR + 2):
1860 cirrus_hook_write_gr(s, 0x13, value);
1861 break;
1862 case (CIRRUS_MMIO_BLTFGCOLOR + 3):
1863 cirrus_hook_write_gr(s, 0x15, value);
1864 break;
1865 case (CIRRUS_MMIO_BLTWIDTH + 0):
1866 cirrus_hook_write_gr(s, 0x20, value);
1867 break;
1868 case (CIRRUS_MMIO_BLTWIDTH + 1):
1869 cirrus_hook_write_gr(s, 0x21, value);
1870 break;
1871 case (CIRRUS_MMIO_BLTHEIGHT + 0):
1872 cirrus_hook_write_gr(s, 0x22, value);
1873 break;
1874 case (CIRRUS_MMIO_BLTHEIGHT + 1):
1875 cirrus_hook_write_gr(s, 0x23, value);
1876 break;
1877 case (CIRRUS_MMIO_BLTDESTPITCH + 0):
1878 cirrus_hook_write_gr(s, 0x24, value);
1879 break;
1880 case (CIRRUS_MMIO_BLTDESTPITCH + 1):
1881 cirrus_hook_write_gr(s, 0x25, value);
1882 break;
1883 case (CIRRUS_MMIO_BLTSRCPITCH + 0):
1884 cirrus_hook_write_gr(s, 0x26, value);
1885 break;
1886 case (CIRRUS_MMIO_BLTSRCPITCH + 1):
1887 cirrus_hook_write_gr(s, 0x27, value);
1888 break;
1889 case (CIRRUS_MMIO_BLTDESTADDR + 0):
1890 cirrus_hook_write_gr(s, 0x28, value);
1891 break;
1892 case (CIRRUS_MMIO_BLTDESTADDR + 1):
1893 cirrus_hook_write_gr(s, 0x29, value);
1894 break;
1895 case (CIRRUS_MMIO_BLTDESTADDR + 2):
1896 cirrus_hook_write_gr(s, 0x2a, value);
1897 break;
1898 case (CIRRUS_MMIO_BLTDESTADDR + 3):
1899 /* ignored */
1900 break;
1901 case (CIRRUS_MMIO_BLTSRCADDR + 0):
1902 cirrus_hook_write_gr(s, 0x2c, value);
1903 break;
1904 case (CIRRUS_MMIO_BLTSRCADDR + 1):
1905 cirrus_hook_write_gr(s, 0x2d, value);
1906 break;
1907 case (CIRRUS_MMIO_BLTSRCADDR + 2):
1908 cirrus_hook_write_gr(s, 0x2e, value);
1909 break;
1910 case CIRRUS_MMIO_BLTWRITEMASK:
1911 cirrus_hook_write_gr(s, 0x2f, value);
1912 break;
1913 case CIRRUS_MMIO_BLTMODE:
1914 cirrus_hook_write_gr(s, 0x30, value);
1915 break;
1916 case CIRRUS_MMIO_BLTROP:
1917 cirrus_hook_write_gr(s, 0x32, value);
1918 break;
1919 case CIRRUS_MMIO_BLTMODEEXT:
1920 cirrus_hook_write_gr(s, 0x33, value);
1921 break;
1922 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 0):
1923 cirrus_hook_write_gr(s, 0x34, value);
1924 break;
1925 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 1):
1926 cirrus_hook_write_gr(s, 0x35, value);
1927 break;
1928 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 0):
1929 cirrus_hook_write_gr(s, 0x38, value);
1930 break;
1931 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 1):
1932 cirrus_hook_write_gr(s, 0x39, value);
1933 break;
1934 case CIRRUS_MMIO_BLTSTATUS:
1935 cirrus_hook_write_gr(s, 0x31, value);
1936 break;
1937 default:
1938 #ifdef DEBUG_CIRRUS
1939 printf("cirrus: mmio write - addr 0x%04x val 0x%02x (ignored)\n",
1940 address, value);
1941 #endif
1942 break;
1943 }
1944 }
1945
1946 /***************************************
1947 *
1948 * write mode 4/5
1949 *
1950 * assume TARGET_PAGE_SIZE >= 16
1951 *
1952 ***************************************/
1953
1954 static void cirrus_mem_writeb_mode4and5_8bpp(CirrusVGAState * s,
1955 unsigned mode,
1956 unsigned offset,
1957 uint32_t mem_value)
1958 {
1959 int x;
1960 unsigned val = mem_value;
1961 uint8_t *dst;
1962
1963 dst = s->vram_ptr + (offset &= s->cirrus_addr_mask);
1964 for (x = 0; x < 8; x++) {
1965 if (val & 0x80) {
1966 *dst = s->cirrus_shadow_gr1;
1967 } else if (mode == 5) {
1968 *dst = s->cirrus_shadow_gr0;
1969 }
1970 val <<= 1;
1971 dst++;
1972 }
1973 cpu_physical_memory_set_dirty(s->vram_offset + offset);
1974 cpu_physical_memory_set_dirty(s->vram_offset + offset + 7);
1975 }
1976
1977 static void cirrus_mem_writeb_mode4and5_16bpp(CirrusVGAState * s,
1978 unsigned mode,
1979 unsigned offset,
1980 uint32_t mem_value)
1981 {
1982 int x;
1983 unsigned val = mem_value;
1984 uint8_t *dst;
1985
1986 dst = s->vram_ptr + (offset &= s->cirrus_addr_mask);
1987 for (x = 0; x < 8; x++) {
1988 if (val & 0x80) {
1989 *dst = s->cirrus_shadow_gr1;
1990 *(dst + 1) = s->gr[0x11];
1991 } else if (mode == 5) {
1992 *dst = s->cirrus_shadow_gr0;
1993 *(dst + 1) = s->gr[0x10];
1994 }
1995 val <<= 1;
1996 dst += 2;
1997 }
1998 cpu_physical_memory_set_dirty(s->vram_offset + offset);
1999 cpu_physical_memory_set_dirty(s->vram_offset + offset + 15);
2000 }
2001
2002 /***************************************
2003 *
2004 * memory access between 0xa0000-0xbffff
2005 *
2006 ***************************************/
2007
2008 static uint32_t cirrus_vga_mem_readb(void *opaque, target_phys_addr_t addr)
2009 {
2010 CirrusVGAState *s = opaque;
2011 unsigned bank_index;
2012 unsigned bank_offset;
2013 uint32_t val;
2014
2015 if ((s->sr[0x07] & 0x01) == 0) {
2016 return vga_mem_readb(s, addr);
2017 }
2018
2019 addr &= 0x1ffff;
2020
2021 if (addr < 0x10000) {
2022 /* XXX handle bitblt */
2023 /* video memory */
2024 bank_index = addr >> 15;
2025 bank_offset = addr & 0x7fff;
2026 if (bank_offset < s->cirrus_bank_limit[bank_index]) {
2027 bank_offset += s->cirrus_bank_base[bank_index];
2028 if ((s->gr[0x0B] & 0x14) == 0x14) {
2029 bank_offset <<= 4;
2030 } else if (s->gr[0x0B] & 0x02) {
2031 bank_offset <<= 3;
2032 }
2033 bank_offset &= s->cirrus_addr_mask;
2034 val = *(s->vram_ptr + bank_offset);
2035 } else
2036 val = 0xff;
2037 } else if (addr >= 0x18000 && addr < 0x18100) {
2038 /* memory-mapped I/O */
2039 val = 0xff;
2040 if ((s->sr[0x17] & 0x44) == 0x04) {
2041 val = cirrus_mmio_blt_read(s, addr & 0xff);
2042 }
2043 } else {
2044 val = 0xff;
2045 #ifdef DEBUG_CIRRUS
2046 printf("cirrus: mem_readb %06x\n", addr);
2047 #endif
2048 }
2049 return val;
2050 }
2051
2052 static uint32_t cirrus_vga_mem_readw(void *opaque, target_phys_addr_t addr)
2053 {
2054 uint32_t v;
2055 #ifdef TARGET_WORDS_BIGENDIAN
2056 v = cirrus_vga_mem_readb(opaque, addr) << 8;
2057 v |= cirrus_vga_mem_readb(opaque, addr + 1);
2058 #else
2059 v = cirrus_vga_mem_readb(opaque, addr);
2060 v |= cirrus_vga_mem_readb(opaque, addr + 1) << 8;
2061 #endif
2062 return v;
2063 }
2064
2065 static uint32_t cirrus_vga_mem_readl(void *opaque, target_phys_addr_t addr)
2066 {
2067 uint32_t v;
2068 #ifdef TARGET_WORDS_BIGENDIAN
2069 v = cirrus_vga_mem_readb(opaque, addr) << 24;
2070 v |= cirrus_vga_mem_readb(opaque, addr + 1) << 16;
2071 v |= cirrus_vga_mem_readb(opaque, addr + 2) << 8;
2072 v |= cirrus_vga_mem_readb(opaque, addr + 3);
2073 #else
2074 v = cirrus_vga_mem_readb(opaque, addr);
2075 v |= cirrus_vga_mem_readb(opaque, addr + 1) << 8;
2076 v |= cirrus_vga_mem_readb(opaque, addr + 2) << 16;
2077 v |= cirrus_vga_mem_readb(opaque, addr + 3) << 24;
2078 #endif
2079 return v;
2080 }
2081
2082 static void cirrus_vga_mem_writeb(void *opaque, target_phys_addr_t addr,
2083 uint32_t mem_value)
2084 {
2085 CirrusVGAState *s = opaque;
2086 unsigned bank_index;
2087 unsigned bank_offset;
2088 unsigned mode;
2089
2090 if ((s->sr[0x07] & 0x01) == 0) {
2091 vga_mem_writeb(s, addr, mem_value);
2092 return;
2093 }
2094
2095 addr &= 0x1ffff;
2096
2097 if (addr < 0x10000) {
2098 if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2099 /* bitblt */
2100 *s->cirrus_srcptr++ = (uint8_t) mem_value;
2101 if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
2102 cirrus_bitblt_cputovideo_next(s);
2103 }
2104 } else {
2105 /* video memory */
2106 bank_index = addr >> 15;
2107 bank_offset = addr & 0x7fff;
2108 if (bank_offset < s->cirrus_bank_limit[bank_index]) {
2109 bank_offset += s->cirrus_bank_base[bank_index];
2110 if ((s->gr[0x0B] & 0x14) == 0x14) {
2111 bank_offset <<= 4;
2112 } else if (s->gr[0x0B] & 0x02) {
2113 bank_offset <<= 3;
2114 }
2115 bank_offset &= s->cirrus_addr_mask;
2116 mode = s->gr[0x05] & 0x7;
2117 if (mode < 4 || mode > 5 || ((s->gr[0x0B] & 0x4) == 0)) {
2118 *(s->vram_ptr + bank_offset) = mem_value;
2119 cpu_physical_memory_set_dirty(s->vram_offset +
2120 bank_offset);
2121 } else {
2122 if ((s->gr[0x0B] & 0x14) != 0x14) {
2123 cirrus_mem_writeb_mode4and5_8bpp(s, mode,
2124 bank_offset,
2125 mem_value);
2126 } else {
2127 cirrus_mem_writeb_mode4and5_16bpp(s, mode,
2128 bank_offset,
2129 mem_value);
2130 }
2131 }
2132 }
2133 }
2134 } else if (addr >= 0x18000 && addr < 0x18100) {
2135 /* memory-mapped I/O */
2136 if ((s->sr[0x17] & 0x44) == 0x04) {
2137 cirrus_mmio_blt_write(s, addr & 0xff, mem_value);
2138 }
2139 } else {
2140 #ifdef DEBUG_CIRRUS
2141 printf("cirrus: mem_writeb %06x value %02x\n", addr, mem_value);
2142 #endif
2143 }
2144 }
2145
2146 static void cirrus_vga_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
2147 {
2148 #ifdef TARGET_WORDS_BIGENDIAN
2149 cirrus_vga_mem_writeb(opaque, addr, (val >> 8) & 0xff);
2150 cirrus_vga_mem_writeb(opaque, addr + 1, val & 0xff);
2151 #else
2152 cirrus_vga_mem_writeb(opaque, addr, val & 0xff);
2153 cirrus_vga_mem_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2154 #endif
2155 }
2156
2157 static void cirrus_vga_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
2158 {
2159 #ifdef TARGET_WORDS_BIGENDIAN
2160 cirrus_vga_mem_writeb(opaque, addr, (val >> 24) & 0xff);
2161 cirrus_vga_mem_writeb(opaque, addr + 1, (val >> 16) & 0xff);
2162 cirrus_vga_mem_writeb(opaque, addr + 2, (val >> 8) & 0xff);
2163 cirrus_vga_mem_writeb(opaque, addr + 3, val & 0xff);
2164 #else
2165 cirrus_vga_mem_writeb(opaque, addr, val & 0xff);
2166 cirrus_vga_mem_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2167 cirrus_vga_mem_writeb(opaque, addr + 2, (val >> 16) & 0xff);
2168 cirrus_vga_mem_writeb(opaque, addr + 3, (val >> 24) & 0xff);
2169 #endif
2170 }
2171
2172 static CPUReadMemoryFunc *cirrus_vga_mem_read[3] = {
2173 cirrus_vga_mem_readb,
2174 cirrus_vga_mem_readw,
2175 cirrus_vga_mem_readl,
2176 };
2177
2178 static CPUWriteMemoryFunc *cirrus_vga_mem_write[3] = {
2179 cirrus_vga_mem_writeb,
2180 cirrus_vga_mem_writew,
2181 cirrus_vga_mem_writel,
2182 };
2183
2184 /***************************************
2185 *
2186 * hardware cursor
2187 *
2188 ***************************************/
2189
2190 static inline void invalidate_cursor1(CirrusVGAState *s)
2191 {
2192 if (s->last_hw_cursor_size) {
2193 vga_invalidate_scanlines((VGAState *)s,
2194 s->last_hw_cursor_y + s->last_hw_cursor_y_start,
2195 s->last_hw_cursor_y + s->last_hw_cursor_y_end);
2196 }
2197 }
2198
2199 static inline void cirrus_cursor_compute_yrange(CirrusVGAState *s)
2200 {
2201 const uint8_t *src;
2202 uint32_t content;
2203 int y, y_min, y_max;
2204
2205 src = s->vram_ptr + s->real_vram_size - 16 * 1024;
2206 if (s->sr[0x12] & CIRRUS_CURSOR_LARGE) {
2207 src += (s->sr[0x13] & 0x3c) * 256;
2208 y_min = 64;
2209 y_max = -1;
2210 for(y = 0; y < 64; y++) {
2211 content = ((uint32_t *)src)[0] |
2212 ((uint32_t *)src)[1] |
2213 ((uint32_t *)src)[2] |
2214 ((uint32_t *)src)[3];
2215 if (content) {
2216 if (y < y_min)
2217 y_min = y;
2218 if (y > y_max)
2219 y_max = y;
2220 }
2221 src += 16;
2222 }
2223 } else {
2224 src += (s->sr[0x13] & 0x3f) * 256;
2225 y_min = 32;
2226 y_max = -1;
2227 for(y = 0; y < 32; y++) {
2228 content = ((uint32_t *)src)[0] |
2229 ((uint32_t *)(src + 128))[0];
2230 if (content) {
2231 if (y < y_min)
2232 y_min = y;
2233 if (y > y_max)
2234 y_max = y;
2235 }
2236 src += 4;
2237 }
2238 }
2239 if (y_min > y_max) {
2240 s->last_hw_cursor_y_start = 0;
2241 s->last_hw_cursor_y_end = 0;
2242 } else {
2243 s->last_hw_cursor_y_start = y_min;
2244 s->last_hw_cursor_y_end = y_max + 1;
2245 }
2246 }
2247
2248 /* NOTE: we do not currently handle the cursor bitmap change, so we
2249 update the cursor only if it moves. */
2250 static void cirrus_cursor_invalidate(VGAState *s1)
2251 {
2252 CirrusVGAState *s = (CirrusVGAState *)s1;
2253 int size;
2254
2255 if (!s->sr[0x12] & CIRRUS_CURSOR_SHOW) {
2256 size = 0;
2257 } else {
2258 if (s->sr[0x12] & CIRRUS_CURSOR_LARGE)
2259 size = 64;
2260 else
2261 size = 32;
2262 }
2263 /* invalidate last cursor and new cursor if any change */
2264 if (s->last_hw_cursor_size != size ||
2265 s->last_hw_cursor_x != s->hw_cursor_x ||
2266 s->last_hw_cursor_y != s->hw_cursor_y) {
2267
2268 invalidate_cursor1(s);
2269
2270 s->last_hw_cursor_size = size;
2271 s->last_hw_cursor_x = s->hw_cursor_x;
2272 s->last_hw_cursor_y = s->hw_cursor_y;
2273 /* compute the real cursor min and max y */
2274 cirrus_cursor_compute_yrange(s);
2275 invalidate_cursor1(s);
2276 }
2277 }
2278
2279 static void cirrus_cursor_draw_line(VGAState *s1, uint8_t *d1, int scr_y)
2280 {
2281 CirrusVGAState *s = (CirrusVGAState *)s1;
2282 int w, h, bpp, x1, x2, poffset;
2283 unsigned int color0, color1;
2284 const uint8_t *palette, *src;
2285 uint32_t content;
2286
2287 if (!(s->sr[0x12] & CIRRUS_CURSOR_SHOW))
2288 return;
2289 /* fast test to see if the cursor intersects with the scan line */
2290 if (s->sr[0x12] & CIRRUS_CURSOR_LARGE) {
2291 h = 64;
2292 } else {
2293 h = 32;
2294 }
2295 if (scr_y < s->hw_cursor_y ||
2296 scr_y >= (s->hw_cursor_y + h))
2297 return;
2298
2299 src = s->vram_ptr + s->real_vram_size - 16 * 1024;
2300 if (s->sr[0x12] & CIRRUS_CURSOR_LARGE) {
2301 src += (s->sr[0x13] & 0x3c) * 256;
2302 src += (scr_y - s->hw_cursor_y) * 16;
2303 poffset = 8;
2304 content = ((uint32_t *)src)[0] |
2305 ((uint32_t *)src)[1] |
2306 ((uint32_t *)src)[2] |
2307 ((uint32_t *)src)[3];
2308 } else {
2309 src += (s->sr[0x13] & 0x3f) * 256;
2310 src += (scr_y - s->hw_cursor_y) * 4;
2311 poffset = 128;
2312 content = ((uint32_t *)src)[0] |
2313 ((uint32_t *)(src + 128))[0];
2314 }
2315 /* if nothing to draw, no need to continue */
2316 if (!content)
2317 return;
2318 w = h;
2319
2320 x1 = s->hw_cursor_x;
2321 if (x1 >= s->last_scr_width)
2322 return;
2323 x2 = s->hw_cursor_x + w;
2324 if (x2 > s->last_scr_width)
2325 x2 = s->last_scr_width;
2326 w = x2 - x1;
2327 palette = s->cirrus_hidden_palette;
2328 color0 = s->rgb_to_pixel(c6_to_8(palette[0x0 * 3]),
2329 c6_to_8(palette[0x0 * 3 + 1]),
2330 c6_to_8(palette[0x0 * 3 + 2]));
2331 color1 = s->rgb_to_pixel(c6_to_8(palette[0xf * 3]),
2332 c6_to_8(palette[0xf * 3 + 1]),
2333 c6_to_8(palette[0xf * 3 + 2]));
2334 bpp = ((s->ds->depth + 7) >> 3);
2335 d1 += x1 * bpp;
2336 switch(s->ds->depth) {
2337 default:
2338 break;
2339 case 8:
2340 vga_draw_cursor_line_8(d1, src, poffset, w, color0, color1, 0xff);
2341 break;
2342 case 15:
2343 vga_draw_cursor_line_16(d1, src, poffset, w, color0, color1, 0x7fff);
2344 break;
2345 case 16:
2346 vga_draw_cursor_line_16(d1, src, poffset, w, color0, color1, 0xffff);
2347 break;
2348 case 32:
2349 vga_draw_cursor_line_32(d1, src, poffset, w, color0, color1, 0xffffff);
2350 break;
2351 }
2352 }
2353
2354 /***************************************
2355 *
2356 * LFB memory access
2357 *
2358 ***************************************/
2359
2360 static uint32_t cirrus_linear_readb(void *opaque, target_phys_addr_t addr)
2361 {
2362 CirrusVGAState *s = (CirrusVGAState *) opaque;
2363 uint32_t ret;
2364
2365 addr &= s->cirrus_addr_mask;
2366
2367 if (((s->sr[0x17] & 0x44) == 0x44) &&
2368 ((addr & s->linear_mmio_mask) == s->linear_mmio_mask)) {
2369 /* memory-mapped I/O */
2370 ret = cirrus_mmio_blt_read(s, addr & 0xff);
2371 } else if (0) {
2372 /* XXX handle bitblt */
2373 ret = 0xff;
2374 } else {
2375 /* video memory */
2376 if ((s->gr[0x0B] & 0x14) == 0x14) {
2377 addr <<= 4;
2378 } else if (s->gr[0x0B] & 0x02) {
2379 addr <<= 3;
2380 }
2381 addr &= s->cirrus_addr_mask;
2382 ret = *(s->vram_ptr + addr);
2383 }
2384
2385 return ret;
2386 }
2387
2388 static uint32_t cirrus_linear_readw(void *opaque, target_phys_addr_t addr)
2389 {
2390 uint32_t v;
2391 #ifdef TARGET_WORDS_BIGENDIAN
2392 v = cirrus_linear_readb(opaque, addr) << 8;
2393 v |= cirrus_linear_readb(opaque, addr + 1);
2394 #else
2395 v = cirrus_linear_readb(opaque, addr);
2396 v |= cirrus_linear_readb(opaque, addr + 1) << 8;
2397 #endif
2398 return v;
2399 }
2400
2401 static uint32_t cirrus_linear_readl(void *opaque, target_phys_addr_t addr)
2402 {
2403 uint32_t v;
2404 #ifdef TARGET_WORDS_BIGENDIAN
2405 v = cirrus_linear_readb(opaque, addr) << 24;
2406 v |= cirrus_linear_readb(opaque, addr + 1) << 16;
2407 v |= cirrus_linear_readb(opaque, addr + 2) << 8;
2408 v |= cirrus_linear_readb(opaque, addr + 3);
2409 #else
2410 v = cirrus_linear_readb(opaque, addr);
2411 v |= cirrus_linear_readb(opaque, addr + 1) << 8;
2412 v |= cirrus_linear_readb(opaque, addr + 2) << 16;
2413 v |= cirrus_linear_readb(opaque, addr + 3) << 24;
2414 #endif
2415 return v;
2416 }
2417
2418 static void cirrus_linear_writeb(void *opaque, target_phys_addr_t addr,
2419 uint32_t val)
2420 {
2421 CirrusVGAState *s = (CirrusVGAState *) opaque;
2422 unsigned mode;
2423
2424 addr &= s->cirrus_addr_mask;
2425
2426 if (((s->sr[0x17] & 0x44) == 0x44) &&
2427 ((addr & s->linear_mmio_mask) == s->linear_mmio_mask)) {
2428 /* memory-mapped I/O */
2429 cirrus_mmio_blt_write(s, addr & 0xff, val);
2430 } else if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2431 /* bitblt */
2432 *s->cirrus_srcptr++ = (uint8_t) val;
2433 if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
2434 cirrus_bitblt_cputovideo_next(s);
2435 }
2436 } else {
2437 /* video memory */
2438 if ((s->gr[0x0B] & 0x14) == 0x14) {
2439 addr <<= 4;
2440 } else if (s->gr[0x0B] & 0x02) {
2441 addr <<= 3;
2442 }
2443 addr &= s->cirrus_addr_mask;
2444
2445 mode = s->gr[0x05] & 0x7;
2446 if (mode < 4 || mode > 5 || ((s->gr[0x0B] & 0x4) == 0)) {
2447 *(s->vram_ptr + addr) = (uint8_t) val;
2448 cpu_physical_memory_set_dirty(s->vram_offset + addr);
2449 } else {
2450 if ((s->gr[0x0B] & 0x14) != 0x14) {
2451 cirrus_mem_writeb_mode4and5_8bpp(s, mode, addr, val);
2452 } else {
2453 cirrus_mem_writeb_mode4and5_16bpp(s, mode, addr, val);
2454 }
2455 }
2456 }
2457 }
2458
2459 static void cirrus_linear_writew(void *opaque, target_phys_addr_t addr,
2460 uint32_t val)
2461 {
2462 #ifdef TARGET_WORDS_BIGENDIAN
2463 cirrus_linear_writeb(opaque, addr, (val >> 8) & 0xff);
2464 cirrus_linear_writeb(opaque, addr + 1, val & 0xff);
2465 #else
2466 cirrus_linear_writeb(opaque, addr, val & 0xff);
2467 cirrus_linear_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2468 #endif
2469 }
2470
2471 static void cirrus_linear_writel(void *opaque, target_phys_addr_t addr,
2472 uint32_t val)
2473 {
2474 #ifdef TARGET_WORDS_BIGENDIAN
2475 cirrus_linear_writeb(opaque, addr, (val >> 24) & 0xff);
2476 cirrus_linear_writeb(opaque, addr + 1, (val >> 16) & 0xff);
2477 cirrus_linear_writeb(opaque, addr + 2, (val >> 8) & 0xff);
2478 cirrus_linear_writeb(opaque, addr + 3, val & 0xff);
2479 #else
2480 cirrus_linear_writeb(opaque, addr, val & 0xff);
2481 cirrus_linear_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2482 cirrus_linear_writeb(opaque, addr + 2, (val >> 16) & 0xff);
2483 cirrus_linear_writeb(opaque, addr + 3, (val >> 24) & 0xff);
2484 #endif
2485 }
2486
2487
2488 static CPUReadMemoryFunc *cirrus_linear_read[3] = {
2489 cirrus_linear_readb,
2490 cirrus_linear_readw,
2491 cirrus_linear_readl,
2492 };
2493
2494 static CPUWriteMemoryFunc *cirrus_linear_write[3] = {
2495 cirrus_linear_writeb,
2496 cirrus_linear_writew,
2497 cirrus_linear_writel,
2498 };
2499
2500 static void cirrus_linear_mem_writeb(void *opaque, target_phys_addr_t addr,
2501 uint32_t val)
2502 {
2503 CirrusVGAState *s = (CirrusVGAState *) opaque;
2504
2505 addr &= s->cirrus_addr_mask;
2506 *(s->vram_ptr + addr) = val;
2507 cpu_physical_memory_set_dirty(s->vram_offset + addr);
2508 }
2509
2510 static void cirrus_linear_mem_writew(void *opaque, target_phys_addr_t addr,
2511 uint32_t val)
2512 {
2513 CirrusVGAState *s = (CirrusVGAState *) opaque;
2514
2515 addr &= s->cirrus_addr_mask;
2516 cpu_to_le16w((uint16_t *)(s->vram_ptr + addr), val);
2517 cpu_physical_memory_set_dirty(s->vram_offset + addr);
2518 }
2519
2520 static void cirrus_linear_mem_writel(void *opaque, target_phys_addr_t addr,
2521 uint32_t val)
2522 {
2523 CirrusVGAState *s = (CirrusVGAState *) opaque;
2524
2525 addr &= s->cirrus_addr_mask;
2526 cpu_to_le32w((uint32_t *)(s->vram_ptr + addr), val);
2527 cpu_physical_memory_set_dirty(s->vram_offset + addr);
2528 }
2529
2530 /***************************************
2531 *
2532 * system to screen memory access
2533 *
2534 ***************************************/
2535
2536
2537 static uint32_t cirrus_linear_bitblt_readb(void *opaque, target_phys_addr_t addr)
2538 {
2539 uint32_t ret;
2540
2541 /* XXX handle bitblt */
2542 ret = 0xff;
2543 return ret;
2544 }
2545
2546 static uint32_t cirrus_linear_bitblt_readw(void *opaque, target_phys_addr_t addr)
2547 {
2548 uint32_t v;
2549 #ifdef TARGET_WORDS_BIGENDIAN
2550 v = cirrus_linear_bitblt_readb(opaque, addr) << 8;
2551 v |= cirrus_linear_bitblt_readb(opaque, addr + 1);
2552 #else
2553 v = cirrus_linear_bitblt_readb(opaque, addr);
2554 v |= cirrus_linear_bitblt_readb(opaque, addr + 1) << 8;
2555 #endif
2556 return v;
2557 }
2558
2559 static uint32_t cirrus_linear_bitblt_readl(void *opaque, target_phys_addr_t addr)
2560 {
2561 uint32_t v;
2562 #ifdef TARGET_WORDS_BIGENDIAN
2563 v = cirrus_linear_bitblt_readb(opaque, addr) << 24;
2564 v |= cirrus_linear_bitblt_readb(opaque, addr + 1) << 16;
2565 v |= cirrus_linear_bitblt_readb(opaque, addr + 2) << 8;
2566 v |= cirrus_linear_bitblt_readb(opaque, addr + 3);
2567 #else
2568 v = cirrus_linear_bitblt_readb(opaque, addr);
2569 v |= cirrus_linear_bitblt_readb(opaque, addr + 1) << 8;
2570 v |= cirrus_linear_bitblt_readb(opaque, addr + 2) << 16;
2571 v |= cirrus_linear_bitblt_readb(opaque, addr + 3) << 24;
2572 #endif
2573 return v;
2574 }
2575
2576 static void cirrus_linear_bitblt_writeb(void *opaque, target_phys_addr_t addr,
2577 uint32_t val)
2578 {
2579 CirrusVGAState *s = (CirrusVGAState *) opaque;
2580
2581 if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2582 /* bitblt */
2583 *s->cirrus_srcptr++ = (uint8_t) val;
2584 if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
2585 cirrus_bitblt_cputovideo_next(s);
2586 }
2587 }
2588 }
2589
2590 static void cirrus_linear_bitblt_writew(void *opaque, target_phys_addr_t addr,
2591 uint32_t val)
2592 {
2593 #ifdef TARGET_WORDS_BIGENDIAN
2594 cirrus_linear_bitblt_writeb(opaque, addr, (val >> 8) & 0xff);
2595 cirrus_linear_bitblt_writeb(opaque, addr + 1, val & 0xff);
2596 #else
2597 cirrus_linear_bitblt_writeb(opaque, addr, val & 0xff);
2598 cirrus_linear_bitblt_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2599 #endif
2600 }
2601
2602 static void cirrus_linear_bitblt_writel(void *opaque, target_phys_addr_t addr,
2603 uint32_t val)
2604 {
2605 #ifdef TARGET_WORDS_BIGENDIAN
2606 cirrus_linear_bitblt_writeb(opaque, addr, (val >> 24) & 0xff);
2607 cirrus_linear_bitblt_writeb(opaque, addr + 1, (val >> 16) & 0xff);
2608 cirrus_linear_bitblt_writeb(opaque, addr + 2, (val >> 8) & 0xff);
2609 cirrus_linear_bitblt_writeb(opaque, addr + 3, val & 0xff);
2610 #else
2611 cirrus_linear_bitblt_writeb(opaque, addr, val & 0xff);
2612 cirrus_linear_bitblt_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2613 cirrus_linear_bitblt_writeb(opaque, addr + 2, (val >> 16) & 0xff);
2614 cirrus_linear_bitblt_writeb(opaque, addr + 3, (val >> 24) & 0xff);
2615 #endif
2616 }
2617
2618
2619 static CPUReadMemoryFunc *cirrus_linear_bitblt_read[3] = {
2620 cirrus_linear_bitblt_readb,
2621 cirrus_linear_bitblt_readw,
2622 cirrus_linear_bitblt_readl,
2623 };
2624
2625 static CPUWriteMemoryFunc *cirrus_linear_bitblt_write[3] = {
2626 cirrus_linear_bitblt_writeb,
2627 cirrus_linear_bitblt_writew,
2628 cirrus_linear_bitblt_writel,
2629 };
2630
2631 void *set_vram_mapping(unsigned long begin, unsigned long end)
2632 {
2633 void *vram_pointer = NULL;
2634
2635 /* align begin and end address */
2636 begin = begin & TARGET_PAGE_MASK;
2637 end = begin + VGA_RAM_SIZE;
2638 end = (end + TARGET_PAGE_SIZE -1 ) & TARGET_PAGE_MASK;
2639
2640 if (kvm_enabled())
2641 vram_pointer = kvm_cpu_create_phys_mem(begin, end - begin, 1, 1);
2642
2643 if (vram_pointer == NULL) {
2644 printf("set_vram_mapping: cannot allocate memory: %m\n");
2645 return NULL;
2646 }
2647
2648 memset(vram_pointer, 0, end - begin);
2649
2650 return vram_pointer;
2651 }
2652
2653 int unset_vram_mapping(unsigned long begin, unsigned long end)
2654 {
2655 /* align begin and end address */
2656 end = begin + VGA_RAM_SIZE;
2657 begin = begin & TARGET_PAGE_MASK;
2658 end = (end + TARGET_PAGE_SIZE -1 ) & TARGET_PAGE_MASK;
2659
2660 if (kvm_enabled())
2661 kvm_cpu_destroy_phys_mem(begin, end - begin);
2662
2663 return 0;
2664 }
2665 #ifdef CONFIG_X86
2666 static void kvm_update_vga_alias(CirrusVGAState *s, int ok, int bank)
2667 {
2668 unsigned limit, base;
2669
2670 if (!ok && !s->aliases_enabled)
2671 return;
2672 limit = s->cirrus_bank_limit[bank];
2673 if (limit > 0x8000)
2674 limit = 0x8000;
2675 base = s->cirrus_lfb_addr + s->cirrus_bank_base[bank];
2676 if (ok) {
2677 if (!s->aliases_enabled
2678 || base != s->aliased_bank_base[bank]
2679 || limit != s->aliased_bank_limit[bank]) {
2680 kvm_create_memory_alias(kvm_context,
2681 0xa0000 + bank * 0x8000,
2682 limit, base);
2683 s->aliased_bank_base[bank] = base;
2684 s->aliased_bank_limit[bank] = limit;
2685 }
2686 } else {
2687 kvm_destroy_memory_alias(kvm_context, 0xa0000 + bank * 0x8000);
2688 }
2689 }
2690
2691 static void kvm_update_vga_aliases(CirrusVGAState *s, int ok)
2692 {
2693 if (kvm_enabled()) {
2694 kvm_update_vga_alias(s, ok, 0);
2695 kvm_update_vga_alias(s, ok, 1);
2696 }
2697 s->aliases_enabled = ok;
2698 }
2699 #endif
2700
2701 /* Compute the memory access functions */
2702 static void cirrus_update_memory_access(CirrusVGAState *s)
2703 {
2704 unsigned mode;
2705 #ifdef CONFIG_X86
2706 int want_vga_alias = 0;
2707 #endif
2708
2709 if ((s->sr[0x17] & 0x44) == 0x44) {
2710 goto generic_io;
2711 } else if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2712 goto generic_io;
2713 } else {
2714 if ((s->gr[0x0B] & 0x14) == 0x14) {
2715 goto generic_io;
2716 } else if (s->gr[0x0B] & 0x02) {
2717 goto generic_io;
2718 }
2719
2720 mode = s->gr[0x05] & 0x7;
2721 if (mode < 4 || mode > 5 || ((s->gr[0x0B] & 0x4) == 0)) {
2722 if (kvm_enabled() && s->cirrus_lfb_addr && s->cirrus_lfb_end &&
2723 !s->map_addr) {
2724 void *vram_pointer, *old_vram;
2725
2726 vram_pointer = set_vram_mapping(s->cirrus_lfb_addr,
2727 s->cirrus_lfb_end);
2728 if (!vram_pointer)
2729 fprintf(stderr, "NULL vram_pointer\n");
2730 else {
2731 old_vram = vga_update_vram((VGAState *)s, vram_pointer,
2732 VGA_RAM_SIZE);
2733 qemu_free(old_vram);
2734 }
2735 s->map_addr = s->cirrus_lfb_addr;
2736 s->map_end = s->cirrus_lfb_end;
2737 }
2738 #ifdef CONFIG_X86
2739 if (kvm_enabled()
2740 && !(s->cirrus_srcptr != s->cirrus_srcptr_end)
2741 && !((s->sr[0x07] & 0x01) == 0)
2742 && !((s->gr[0x0B] & 0x14) == 0x14)
2743 && !(s->gr[0x0B] & 0x02))
2744 want_vga_alias = 1;
2745 #endif
2746 s->cirrus_linear_write[0] = cirrus_linear_mem_writeb;
2747 s->cirrus_linear_write[1] = cirrus_linear_mem_writew;
2748 s->cirrus_linear_write[2] = cirrus_linear_mem_writel;
2749 } else {
2750 generic_io:
2751 if (kvm_enabled() && s->cirrus_lfb_addr && s->cirrus_lfb_end &&
2752 s->map_addr) {
2753 int error;
2754 void *old_vram = NULL;
2755
2756 error = unset_vram_mapping(s->cirrus_lfb_addr,
2757 s->cirrus_lfb_end);
2758 if (!error)
2759 old_vram = vga_update_vram((VGAState *)s, NULL,
2760 VGA_RAM_SIZE);
2761 if (old_vram)
2762 munmap(old_vram, s->map_end - s->map_addr);
2763 s->map_addr = s->map_end = 0;
2764 }
2765 s->cirrus_linear_write[0] = cirrus_linear_writeb;
2766 s->cirrus_linear_write[1] = cirrus_linear_writew;
2767 s->cirrus_linear_write[2] = cirrus_linear_writel;
2768 }
2769 }
2770 #if defined(CONFIG_X86)
2771 kvm_update_vga_aliases(s, want_vga_alias);
2772 #endif
2773
2774 }
2775
2776
2777 /* I/O ports */
2778
2779 static uint32_t vga_ioport_read(void *opaque, uint32_t addr)
2780 {
2781 CirrusVGAState *s = opaque;
2782 int val, index;
2783
2784 /* check port range access depending on color/monochrome mode */
2785 if ((addr >= 0x3b0 && addr <= 0x3bf && (s->msr & MSR_COLOR_EMULATION))
2786 || (addr >= 0x3d0 && addr <= 0x3df
2787 && !(s->msr & MSR_COLOR_EMULATION))) {
2788 val = 0xff;
2789 } else {
2790 switch (addr) {
2791 case 0x3c0:
2792 if (s->ar_flip_flop == 0) {
2793 val = s->ar_index;
2794 } else {
2795 val = 0;
2796 }
2797 break;
2798 case 0x3c1:
2799 index = s->ar_index & 0x1f;
2800 if (index < 21)
2801 val = s->ar[index];
2802 else
2803 val = 0;
2804 break;
2805 case 0x3c2:
2806 val = s->st00;
2807 break;
2808 case 0x3c4:
2809 val = s->sr_index;
2810 break;
2811 case 0x3c5:
2812 if (cirrus_hook_read_sr(s, s->sr_index, &val))
2813 break;
2814 val = s->sr[s->sr_index];
2815 #ifdef DEBUG_VGA_REG
2816 printf("vga: read SR%x = 0x%02x\n", s->sr_index, val);
2817 #endif
2818 break;
2819 case 0x3c6:
2820 cirrus_read_hidden_dac(s, &val);
2821 break;
2822 case 0x3c7:
2823 val = s->dac_state;
2824 break;
2825 case 0x3c8:
2826 val = s->dac_write_index;
2827 s->cirrus_hidden_dac_lockindex = 0;
2828 break;
2829 case 0x3c9:
2830 if (cirrus_hook_read_palette(s, &val))
2831 break;
2832 val = s->palette[s->dac_read_index * 3 + s->dac_sub_index];
2833 if (++s->dac_sub_index == 3) {
2834 s->dac_sub_index = 0;
2835 s->dac_read_index++;
2836 }
2837 break;
2838 case 0x3ca:
2839 val = s->fcr;
2840 break;
2841 case 0x3cc:
2842 val = s->msr;
2843 break;
2844 case 0x3ce:
2845 val = s->gr_index;
2846 break;
2847 case 0x3cf:
2848 if (cirrus_hook_read_gr(s, s->gr_index, &val))
2849 break;
2850 val = s->gr[s->gr_index];
2851 #ifdef DEBUG_VGA_REG
2852 printf("vga: read GR%x = 0x%02x\n", s->gr_index, val);
2853 #endif
2854 break;
2855 case 0x3b4:
2856 case 0x3d4:
2857 val = s->cr_index;
2858 break;
2859 case 0x3b5:
2860 case 0x3d5:
2861 if (cirrus_hook_read_cr(s, s->cr_index, &val))
2862 break;
2863 val = s->cr[s->cr_index];
2864 #ifdef DEBUG_VGA_REG
2865 printf("vga: read CR%x = 0x%02x\n", s->cr_index, val);
2866 #endif
2867 break;
2868 case 0x3ba:
2869 case 0x3da:
2870 /* just toggle to fool polling */
2871 s->st01 ^= ST01_V_RETRACE | ST01_DISP_ENABLE;
2872 val = s->st01;
2873 s->ar_flip_flop = 0;
2874 break;
2875 default:
2876 val = 0x00;
2877 break;
2878 }
2879 }
2880 #if defined(DEBUG_VGA)
2881 printf("VGA: read addr=0x%04x data=0x%02x\n", addr, val);
2882 #endif
2883 return val;
2884 }
2885
2886 static void vga_ioport_write(void *opaque, uint32_t addr, uint32_t val)
2887 {
2888 CirrusVGAState *s = opaque;
2889 int index;
2890
2891 /* check port range access depending on color/monochrome mode */
2892 if ((addr >= 0x3b0 && addr <= 0x3bf && (s->msr & MSR_COLOR_EMULATION))
2893 || (addr >= 0x3d0 && addr <= 0x3df
2894 && !(s->msr & MSR_COLOR_EMULATION)))
2895 return;
2896
2897 #ifdef DEBUG_VGA
2898 printf("VGA: write addr=0x%04x data=0x%02x\n", addr, val);
2899 #endif
2900
2901 switch (addr) {
2902 case 0x3c0:
2903 if (s->ar_flip_flop == 0) {
2904 val &= 0x3f;
2905 s->ar_index = val;
2906 } else {
2907 index = s->ar_index & 0x1f;
2908 switch (index) {
2909 case 0x00 ... 0x0f:
2910 s->ar[index] = val & 0x3f;
2911 break;
2912 case 0x10:
2913 s->ar[index] = val & ~0x10;
2914 break;
2915 case 0x11:
2916 s->ar[index] = val;
2917 break;
2918 case 0x12:
2919 s->ar[index] = val & ~0xc0;
2920 break;
2921 case 0x13:
2922 s->ar[index] = val & ~0xf0;
2923 break;
2924 case 0x14:
2925 s->ar[index] = val & ~0xf0;
2926 break;
2927 default:
2928 break;
2929 }
2930 }
2931 s->ar_flip_flop ^= 1;
2932 break;
2933 case 0x3c2:
2934 s->msr = val & ~0x10;
2935 break;
2936 case 0x3c4:
2937 s->sr_index = val;
2938 break;
2939 case 0x3c5:
2940 if (cirrus_hook_write_sr(s, s->sr_index, val))
2941 break;
2942 #ifdef DEBUG_VGA_REG
2943 printf("vga: write SR%x = 0x%02x\n", s->sr_index, val);
2944 #endif
2945 s->sr[s->sr_index] = val & sr_mask[s->sr_index];
2946 break;
2947 case 0x3c6:
2948 cirrus_write_hidden_dac(s, val);
2949 break;
2950 case 0x3c7:
2951 s->dac_read_index = val;
2952 s->dac_sub_index = 0;
2953 s->dac_state = 3;
2954 break;
2955 case 0x3c8:
2956 s->dac_write_index = val;
2957 s->dac_sub_index = 0;
2958 s->dac_state = 0;
2959 break;
2960 case 0x3c9:
2961 if (cirrus_hook_write_palette(s, val))
2962 break;
2963 s->dac_cache[s->dac_sub_index] = val;
2964 if (++s->dac_sub_index == 3) {
2965 memcpy(&s->palette[s->dac_write_index * 3], s->dac_cache, 3);
2966 s->dac_sub_index = 0;
2967 s->dac_write_index++;
2968 }
2969 break;
2970 case 0x3ce:
2971 s->gr_index = val;
2972 break;
2973 case 0x3cf:
2974 if (cirrus_hook_write_gr(s, s->gr_index, val))
2975 break;
2976 #ifdef DEBUG_VGA_REG
2977 printf("vga: write GR%x = 0x%02x\n", s->gr_index, val);
2978 #endif
2979 s->gr[s->gr_index] = val & gr_mask[s->gr_index];
2980 break;
2981 case 0x3b4:
2982 case 0x3d4:
2983 s->cr_index = val;
2984 break;
2985 case 0x3b5:
2986 case 0x3d5:
2987 if (cirrus_hook_write_cr(s, s->cr_index, val))
2988 break;
2989 #ifdef DEBUG_VGA_REG
2990 printf("vga: write CR%x = 0x%02x\n", s->cr_index, val);
2991 #endif
2992 /* handle CR0-7 protection */
2993 if ((s->cr[0x11] & 0x80) && s->cr_index <= 7) {
2994 /* can always write bit 4 of CR7 */
2995 if (s->cr_index == 7)
2996 s->cr[7] = (s->cr[7] & ~0x10) | (val & 0x10);
2997 return;
2998 }
2999 switch (s->cr_index) {
3000 case 0x01: /* horizontal display end */
3001 case 0x07:
3002 case 0x09:
3003 case 0x0c:
3004 case 0x0d:
3005 case 0x12: /* vertical display end */
3006 s->cr[s->cr_index] = val;
3007 break;
3008
3009 default:
3010 s->cr[s->cr_index] = val;
3011 break;
3012 }
3013 break;
3014 case 0x3ba:
3015 case 0x3da:
3016 s->fcr = val & 0x10;
3017 break;
3018 }
3019 }
3020
3021 /***************************************
3022 *
3023 * memory-mapped I/O access
3024 *
3025 ***************************************/
3026
3027 static uint32_t cirrus_mmio_readb(void *opaque, target_phys_addr_t addr)
3028 {
3029 CirrusVGAState *s = (CirrusVGAState *) opaque;
3030
3031 addr &= CIRRUS_PNPMMIO_SIZE - 1;
3032
3033 if (addr >= 0x100) {
3034 return cirrus_mmio_blt_read(s, addr - 0x100);
3035 } else {
3036 return vga_ioport_read(s, addr + 0x3c0);
3037 }
3038 }
3039
3040 static uint32_t cirrus_mmio_readw(void *opaque, target_phys_addr_t addr)
3041 {
3042 uint32_t v;
3043 #ifdef TARGET_WORDS_BIGENDIAN
3044 v = cirrus_mmio_readb(opaque, addr) << 8;
3045 v |= cirrus_mmio_readb(opaque, addr + 1);
3046 #else
3047 v = cirrus_mmio_readb(opaque, addr);
3048 v |= cirrus_mmio_readb(opaque, addr + 1) << 8;
3049 #endif
3050 return v;
3051 }
3052
3053 static uint32_t cirrus_mmio_readl(void *opaque, target_phys_addr_t addr)
3054 {
3055 uint32_t v;
3056 #ifdef TARGET_WORDS_BIGENDIAN
3057 v = cirrus_mmio_readb(opaque, addr) << 24;
3058 v |= cirrus_mmio_readb(opaque, addr + 1) << 16;
3059 v |= cirrus_mmio_readb(opaque, addr + 2) << 8;
3060 v |= cirrus_mmio_readb(opaque, addr + 3);
3061 #else
3062 v = cirrus_mmio_readb(opaque, addr);
3063 v |= cirrus_mmio_readb(opaque, addr + 1) << 8;
3064 v |= cirrus_mmio_readb(opaque, addr + 2) << 16;
3065 v |= cirrus_mmio_readb(opaque, addr + 3) << 24;
3066 #endif
3067 return v;
3068 }
3069
3070 static void cirrus_mmio_writeb(void *opaque, target_phys_addr_t addr,
3071 uint32_t val)
3072 {
3073 CirrusVGAState *s = (CirrusVGAState *) opaque;
3074
3075 addr &= CIRRUS_PNPMMIO_SIZE - 1;
3076
3077 if (addr >= 0x100) {
3078 cirrus_mmio_blt_write(s, addr - 0x100, val);
3079 } else {
3080 vga_ioport_write(s, addr + 0x3c0, val);
3081 }
3082 }
3083
3084 static void cirrus_mmio_writew(void *opaque, target_phys_addr_t addr,
3085 uint32_t val)
3086 {
3087 #ifdef TARGET_WORDS_BIGENDIAN
3088 cirrus_mmio_writeb(opaque, addr, (val >> 8) & 0xff);
3089 cirrus_mmio_writeb(opaque, addr + 1, val & 0xff);
3090 #else
3091 cirrus_mmio_writeb(opaque, addr, val & 0xff);
3092 cirrus_mmio_writeb(opaque, addr + 1, (val >> 8) & 0xff);
3093 #endif
3094 }
3095
3096 static void cirrus_mmio_writel(void *opaque, target_phys_addr_t addr,
3097 uint32_t val)
3098 {
3099 #ifdef TARGET_WORDS_BIGENDIAN
3100 cirrus_mmio_writeb(opaque, addr, (val >> 24) & 0xff);
3101 cirrus_mmio_writeb(opaque, addr + 1, (val >> 16) & 0xff);
3102 cirrus_mmio_writeb(opaque, addr + 2, (val >> 8) & 0xff);
3103 cirrus_mmio_writeb(opaque, addr + 3, val & 0xff);
3104 #else
3105 cirrus_mmio_writeb(opaque, addr, val & 0xff);
3106 cirrus_mmio_writeb(opaque, addr + 1, (val >> 8) & 0xff);
3107 cirrus_mmio_writeb(opaque, addr + 2, (val >> 16) & 0xff);
3108 cirrus_mmio_writeb(opaque, addr + 3, (val >> 24) & 0xff);
3109 #endif
3110 }
3111
3112
3113 static CPUReadMemoryFunc *cirrus_mmio_read[3] = {
3114 cirrus_mmio_readb,
3115 cirrus_mmio_readw,
3116 cirrus_mmio_readl,
3117 };
3118
3119 static CPUWriteMemoryFunc *cirrus_mmio_write[3] = {
3120 cirrus_mmio_writeb,
3121 cirrus_mmio_writew,
3122 cirrus_mmio_writel,
3123 };
3124
3125 /* load/save state */
3126
3127 static void cirrus_vga_save(QEMUFile *f, void *opaque)
3128 {
3129 CirrusVGAState *s = opaque;
3130
3131 if (s->pci_dev)
3132 pci_device_save(s->pci_dev, f);
3133
3134 qemu_put_be32s(f, &s->latch);
3135 qemu_put_8s(f, &s->sr_index);
3136 qemu_put_buffer(f, s->sr, 256);
3137 qemu_put_8s(f, &s->gr_index);
3138 qemu_put_8s(f, &s->cirrus_shadow_gr0);
3139 qemu_put_8s(f, &s->cirrus_shadow_gr1);
3140 qemu_put_buffer(f, s->gr + 2, 254);
3141 qemu_put_8s(f, &s->ar_index);
3142 qemu_put_buffer(f, s->ar, 21);
3143 qemu_put_be32(f, s->ar_flip_flop);
3144 qemu_put_8s(f, &s->cr_index);
3145 qemu_put_buffer(f, s->cr, 256);
3146 qemu_put_8s(f, &s->msr);
3147 qemu_put_8s(f, &s->fcr);
3148 qemu_put_8s(f, &s->st00);
3149 qemu_put_8s(f, &s->st01);
3150
3151 qemu_put_8s(f, &s->dac_state);
3152 qemu_put_8s(f, &s->dac_sub_index);
3153 qemu_put_8s(f, &s->dac_read_index);
3154 qemu_put_8s(f, &s->dac_write_index);
3155 qemu_put_buffer(f, s->dac_cache, 3);
3156 qemu_put_buffer(f, s->palette, 768);
3157
3158 qemu_put_be32(f, s->bank_offset);
3159
3160 qemu_put_8s(f, &s->cirrus_hidden_dac_lockindex);
3161 qemu_put_8s(f, &s->cirrus_hidden_dac_data);
3162
3163 qemu_put_be32s(f, &s->hw_cursor_x);
3164 qemu_put_be32s(f, &s->hw_cursor_y);
3165 /* XXX: we do not save the bitblt state - we assume we do not save
3166 the state when the blitter is active */
3167
3168 if (kvm_enabled()) { /* XXX: KVM images ought to be loadable in QEMU */
3169 qemu_put_be32s(f, &s->real_vram_size);
3170 qemu_put_buffer(f, s->vram_ptr, s->real_vram_size);
3171 }
3172 }
3173
3174 static int cirrus_vga_load(QEMUFile *f, void *opaque, int version_id)
3175 {
3176 CirrusVGAState *s = opaque;
3177 int ret;
3178
3179 if (version_id > 2)
3180 return -EINVAL;
3181
3182 if (s->pci_dev && version_id >= 2) {
3183 ret = pci_device_load(s->pci_dev, f);
3184 if (ret < 0)
3185 return ret;
3186 }
3187
3188 qemu_get_be32s(f, &s->latch);
3189 qemu_get_8s(f, &s->sr_index);
3190 qemu_get_buffer(f, s->sr, 256);
3191 qemu_get_8s(f, &s->gr_index);
3192 qemu_get_8s(f, &s->cirrus_shadow_gr0);
3193 qemu_get_8s(f, &s->cirrus_shadow_gr1);
3194 s->gr[0x00] = s->cirrus_shadow_gr0 & 0x0f;
3195 s->gr[0x01] = s->cirrus_shadow_gr1 & 0x0f;
3196 qemu_get_buffer(f, s->gr + 2, 254);
3197 qemu_get_8s(f, &s->ar_index);
3198 qemu_get_buffer(f, s->ar, 21);
3199 s->ar_flip_flop=qemu_get_be32(f);
3200 qemu_get_8s(f, &s->cr_index);
3201 qemu_get_buffer(f, s->cr, 256);
3202 qemu_get_8s(f, &s->msr);
3203 qemu_get_8s(f, &s->fcr);
3204 qemu_get_8s(f, &s->st00);
3205 qemu_get_8s(f, &s->st01);
3206
3207 qemu_get_8s(f, &s->dac_state);
3208 qemu_get_8s(f, &s->dac_sub_index);
3209 qemu_get_8s(f, &s->dac_read_index);
3210 qemu_get_8s(f, &s->dac_write_index);
3211 qemu_get_buffer(f, s->dac_cache, 3);
3212 qemu_get_buffer(f, s->palette, 768);
3213
3214 s->bank_offset=qemu_get_be32(f);
3215
3216 qemu_get_8s(f, &s->cirrus_hidden_dac_lockindex);
3217 qemu_get_8s(f, &s->cirrus_hidden_dac_data);
3218
3219 qemu_get_be32s(f, &s->hw_cursor_x);
3220 qemu_get_be32s(f, &s->hw_cursor_y);
3221
3222 if (kvm_enabled()) {
3223 int real_vram_size;
3224 qemu_get_be32s(f, &real_vram_size);
3225 if (real_vram_size != s->real_vram_size) {
3226 if (real_vram_size > s->real_vram_size)
3227 real_vram_size = s->real_vram_size;
3228 printf("%s: REAL_VRAM_SIZE MISMATCH !!!!!! SAVED=%d CURRENT=%d",
3229 __FUNCTION__, real_vram_size, s->real_vram_size);
3230 }
3231 qemu_get_buffer(f, s->vram_ptr, real_vram_size);
3232 cirrus_update_memory_access(s);
3233 }
3234
3235
3236 /* force refresh */
3237 s->graphic_mode = -1;
3238 cirrus_update_bank_ptr(s, 0);
3239 cirrus_update_bank_ptr(s, 1);
3240 return 0;
3241 }
3242
3243 /***************************************
3244 *
3245 * initialize
3246 *
3247 ***************************************/
3248
3249 static void cirrus_init_common(CirrusVGAState * s, int device_id, int is_pci)
3250 {
3251 int vga_io_memory, i;
3252 static int inited;
3253
3254 if (!inited) {
3255 inited = 1;
3256 for(i = 0;i < 256; i++)
3257 rop_to_index[i] = CIRRUS_ROP_NOP_INDEX; /* nop rop */
3258 rop_to_index[CIRRUS_ROP_0] = 0;
3259 rop_to_index[CIRRUS_ROP_SRC_AND_DST] = 1;
3260 rop_to_index[CIRRUS_ROP_NOP] = 2;
3261 rop_to_index[CIRRUS_ROP_SRC_AND_NOTDST] = 3;
3262 rop_to_index[CIRRUS_ROP_NOTDST] = 4;
3263 rop_to_index[CIRRUS_ROP_SRC] = 5;
3264 rop_to_index[CIRRUS_ROP_1] = 6;
3265 rop_to_index[CIRRUS_ROP_NOTSRC_AND_DST] = 7;
3266 rop_to_index[CIRRUS_ROP_SRC_XOR_DST] = 8;
3267 rop_to_index[CIRRUS_ROP_SRC_OR_DST] = 9;
3268 rop_to_index[CIRRUS_ROP_NOTSRC_OR_NOTDST] = 10;
3269 rop_to_index[CIRRUS_ROP_SRC_NOTXOR_DST] = 11;
3270 rop_to_index[CIRRUS_ROP_SRC_OR_NOTDST] = 12;
3271 rop_to_index[CIRRUS_ROP_NOTSRC] = 13;
3272 rop_to_index[CIRRUS_ROP_NOTSRC_OR_DST] = 14;
3273 rop_to_index[CIRRUS_ROP_NOTSRC_AND_NOTDST] = 15;
3274 }
3275
3276 register_ioport_write(0x3c0, 16, 1, vga_ioport_write, s);
3277
3278 register_ioport_write(0x3b4, 2, 1, vga_ioport_write, s);
3279 register_ioport_write(0x3d4, 2, 1, vga_ioport_write, s);
3280 register_ioport_write(0x3ba, 1, 1, vga_ioport_write, s);
3281 register_ioport_write(0x3da, 1, 1, vga_ioport_write, s);
3282
3283 register_ioport_read(0x3c0, 16, 1, vga_ioport_read, s);
3284
3285 register_ioport_read(0x3b4, 2, 1, vga_ioport_read, s);
3286 register_ioport_read(0x3d4, 2, 1, vga_ioport_read, s);
3287 register_ioport_read(0x3ba, 1, 1, vga_ioport_read, s);
3288 register_ioport_read(0x3da, 1, 1, vga_ioport_read, s);
3289
3290 vga_io_memory = cpu_register_io_memory(0, cirrus_vga_mem_read,
3291 cirrus_vga_mem_write, s);
3292 cpu_register_physical_memory(isa_mem_base + 0x000a0000, 0x20000,
3293 vga_io_memory);
3294 if (kvm_enabled())
3295 qemu_kvm_register_coalesced_mmio(isa_mem_base + 0x000a0000, 0x20000);
3296
3297 s->sr[0x06] = 0x0f;
3298 if (device_id == CIRRUS_ID_CLGD5446) {
3299 /* 4MB 64 bit memory config, always PCI */
3300 s->sr[0x1F] = 0x2d; // MemClock
3301 s->gr[0x18] = 0x0f; // fastest memory configuration
3302 #if 1
3303 s->sr[0x0f] = 0x98;
3304 s->sr[0x17] = 0x20;
3305 s->sr[0x15] = 0x04; /* memory size, 3=2MB, 4=4MB */
3306 s->real_vram_size = 4096 * 1024;
3307 #else
3308 s->sr[0x0f] = 0x18;
3309 s->sr[0x17] = 0x20;
3310 s->sr[0x15] = 0x03; /* memory size, 3=2MB, 4=4MB */
3311 s->real_vram_size = 2048 * 1024;
3312 #endif
3313 } else {
3314 s->sr[0x1F] = 0x22; // MemClock
3315 s->sr[0x0F] = CIRRUS_MEMSIZE_2M;
3316 if (is_pci)
3317 s->sr[0x17] = CIRRUS_BUSTYPE_PCI;
3318 else
3319 s->sr[0x17] = CIRRUS_BUSTYPE_ISA;
3320 s->real_vram_size = 2048 * 1024;
3321 s->sr[0x15] = 0x03; /* memory size, 3=2MB, 4=4MB */
3322 }
3323 s->cr[0x27] = device_id;
3324
3325 /* Win2K seems to assume that the pattern buffer is at 0xff
3326 initially ! */
3327 memset(s->vram_ptr, 0xff, s->real_vram_size);
3328
3329 s->cirrus_hidden_dac_lockindex = 5;
3330 s->cirrus_hidden_dac_data = 0;
3331
3332 /* I/O handler for LFB */
3333 s->cirrus_linear_io_addr =
3334 cpu_register_io_memory(0, cirrus_linear_read, cirrus_linear_write,
3335 s);
3336 s->cirrus_linear_write = cpu_get_io_memory_write(s->cirrus_linear_io_addr);
3337
3338 /* I/O handler for LFB */
3339 s->cirrus_linear_bitblt_io_addr =
3340 cpu_register_io_memory(0, cirrus_linear_bitblt_read, cirrus_linear_bitblt_write,
3341 s);
3342
3343 /* I/O handler for memory-mapped I/O */
3344 s->cirrus_mmio_io_addr =
3345 cpu_register_io_memory(0, cirrus_mmio_read, cirrus_mmio_write, s);
3346
3347 /* XXX: s->vram_size must be a power of two */
3348 s->cirrus_addr_mask = s->real_vram_size - 1;
3349 s->linear_mmio_mask = s->real_vram_size - 256;
3350
3351 s->get_bpp = cirrus_get_bpp;
3352 s->get_offsets = cirrus_get_offsets;
3353 s->get_resolution = cirrus_get_resolution;
3354 s->cursor_invalidate = cirrus_cursor_invalidate;
3355 s->cursor_draw_line = cirrus_cursor_draw_line;
3356
3357 register_savevm("cirrus_vga", 0, 2, cirrus_vga_save, cirrus_vga_load, s);
3358 }
3359
3360 /***************************************
3361 *
3362 * ISA bus support
3363 *
3364 ***************************************/
3365
3366 void isa_cirrus_vga_init(DisplayState *ds, uint8_t *vga_ram_base,
3367 unsigned long vga_ram_offset, int vga_ram_size)
3368 {
3369 CirrusVGAState *s;
3370
3371 s = qemu_mallocz(sizeof(CirrusVGAState));
3372
3373 vga_common_init((VGAState *)s,
3374 ds, vga_ram_base, vga_ram_offset, vga_ram_size);
3375 cirrus_init_common(s, CIRRUS_ID_CLGD5430, 0);
3376 /* XXX ISA-LFB support */
3377 }
3378
3379 /***************************************
3380 *
3381 * PCI bus support
3382 *
3383 ***************************************/
3384
3385 static void cirrus_pci_lfb_map(PCIDevice *d, int region_num,
3386 uint32_t addr, uint32_t size, int type)
3387 {
3388 CirrusVGAState *s = &((PCICirrusVGAState *)d)->cirrus_vga;
3389
3390 /* XXX: add byte swapping apertures */
3391 cpu_register_physical_memory(addr, s->vram_size,
3392 s->cirrus_linear_io_addr);
3393 if (kvm_enabled()) {
3394 s->cirrus_lfb_addr = addr;
3395 s->cirrus_lfb_end = addr + VGA_RAM_SIZE;
3396
3397 if (s->map_addr && (s->cirrus_lfb_addr != s->map_addr) &&
3398 (s->cirrus_lfb_end != s->map_end))
3399 printf("cirrus vga map change while on lfb mode\n");
3400 }
3401
3402 cpu_register_physical_memory(addr + 0x1000000, 0x400000,
3403 s->cirrus_linear_bitblt_io_addr);
3404 }
3405
3406 static void cirrus_pci_mmio_map(PCIDevice *d, int region_num,
3407 uint32_t addr, uint32_t size, int type)
3408 {
3409 CirrusVGAState *s = &((PCICirrusVGAState *)d)->cirrus_vga;
3410
3411 cpu_register_physical_memory(addr, CIRRUS_PNPMMIO_SIZE,
3412 s->cirrus_mmio_io_addr);
3413 }
3414
3415 void pci_cirrus_vga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
3416 unsigned long vga_ram_offset, int vga_ram_size)
3417 {
3418 PCICirrusVGAState *d;
3419 uint8_t *pci_conf;
3420 CirrusVGAState *s;
3421 int device_id;
3422
3423 device_id = CIRRUS_ID_CLGD5446;
3424
3425 /* setup PCI configuration registers */
3426 d = (PCICirrusVGAState *)pci_register_device(bus, "Cirrus VGA",
3427 sizeof(PCICirrusVGAState),
3428 -1, NULL, NULL);
3429 pci_conf = d->dev.config;
3430 pci_conf[0x00] = (uint8_t) (PCI_VENDOR_CIRRUS & 0xff);
3431 pci_conf[0x01] = (uint8_t) (PCI_VENDOR_CIRRUS >> 8);
3432 pci_conf[0x02] = (uint8_t) (device_id & 0xff);
3433 pci_conf[0x03] = (uint8_t) (device_id >> 8);
3434 pci_conf[0x04] = PCI_COMMAND_IOACCESS | PCI_COMMAND_MEMACCESS;
3435 pci_conf[0x0a] = PCI_CLASS_SUB_VGA;
3436 pci_conf[0x0b] = PCI_CLASS_BASE_DISPLAY;
3437 pci_conf[0x0e] = PCI_CLASS_HEADERTYPE_00h;
3438
3439 /* setup VGA */
3440 s = &d->cirrus_vga;
3441 vga_common_init((VGAState *)s,
3442 ds, vga_ram_base, vga_ram_offset, vga_ram_size);
3443 cirrus_init_common(s, device_id, 1);
3444
3445 s->console = graphic_console_init(s->ds, s->update, s->invalidate,
3446 s->screen_dump, s->text_update, s);
3447
3448 s->pci_dev = (PCIDevice *)d;
3449
3450 /* setup memory space */
3451 /* memory #0 LFB */
3452 /* memory #1 memory-mapped I/O */
3453 /* XXX: s->vram_size must be a power of two */
3454 pci_register_io_region((PCIDevice *)d, 0, 0x2000000,
3455 PCI_ADDRESS_SPACE_MEM_PREFETCH, cirrus_pci_lfb_map);
3456 if (device_id == CIRRUS_ID_CLGD5446) {
3457 pci_register_io_region((PCIDevice *)d, 1, CIRRUS_PNPMMIO_SIZE,
3458 PCI_ADDRESS_SPACE_MEM, cirrus_pci_mmio_map);
3459 }
3460 /* XXX: ROM BIOS */
3461 }
Patches shipped by Fedora