2 * defines common to all virtual CPUs
4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 #if defined(__arm__) || defined(__sparc__) || defined(__mips__) || defined(__hppa__)
27 /* some important defines:
29 * WORDS_ALIGNED : if defined, the host cpu can only make word aligned
32 * WORDS_BIGENDIAN : if defined, the host cpu is big endian and
33 * otherwise little endian.
35 * (TARGET_WORDS_ALIGNED : same for target cpu (not supported yet))
37 * TARGET_WORDS_BIGENDIAN : same for target cpu
41 #include "softfloat.h"
43 #if defined(WORDS_BIGENDIAN) != defined(TARGET_WORDS_BIGENDIAN)
49 static inline uint16_t tswap16(uint16_t s
)
54 static inline uint32_t tswap32(uint32_t s
)
59 static inline uint64_t tswap64(uint64_t s
)
64 static inline void tswap16s(uint16_t *s
)
69 static inline void tswap32s(uint32_t *s
)
74 static inline void tswap64s(uint64_t *s
)
81 static inline uint16_t tswap16(uint16_t s
)
86 static inline uint32_t tswap32(uint32_t s
)
91 static inline uint64_t tswap64(uint64_t s
)
96 static inline void tswap16s(uint16_t *s
)
100 static inline void tswap32s(uint32_t *s
)
104 static inline void tswap64s(uint64_t *s
)
110 #if TARGET_LONG_SIZE == 4
111 #define tswapl(s) tswap32(s)
112 #define tswapls(s) tswap32s((uint32_t *)(s))
113 #define bswaptls(s) bswap32s(s)
115 #define tswapl(s) tswap64(s)
116 #define tswapls(s) tswap64s((uint64_t *)(s))
117 #define bswaptls(s) bswap64s(s)
125 /* NOTE: arm FPA is horrible as double 32 bit words are stored in big
129 #if defined(WORDS_BIGENDIAN) \
130 || (defined(__arm__) && !defined(__VFP_FP__) && !defined(CONFIG_SOFTFLOAT))
147 #if defined(WORDS_BIGENDIAN) \
148 || (defined(__arm__) && !defined(__VFP_FP__) && !defined(CONFIG_SOFTFLOAT))
174 /* CPU memory access without any memory or io remapping */
177 * the generic syntax for the memory accesses is:
179 * load: ld{type}{sign}{size}{endian}_{access_type}(ptr)
181 * store: st{type}{size}{endian}_{access_type}(ptr, val)
184 * (empty): integer access
188 * (empty): for floats or 32 bit size
199 * (empty): target cpu endianness or 8 bit access
200 * r : reversed target cpu endianness (not implemented yet)
201 * be : big endian (not implemented yet)
202 * le : little endian (not implemented yet)
205 * raw : host memory access
206 * user : user mode access using soft MMU
207 * kernel : kernel mode access using soft MMU
209 static inline int ldub_p(void *ptr
)
211 return *(uint8_t *)ptr
;
214 static inline int ldsb_p(void *ptr
)
216 return *(int8_t *)ptr
;
219 static inline void stb_p(void *ptr
, int v
)
224 /* NOTE: on arm, putting 2 in /proc/sys/debug/alignment so that the
225 kernel handles unaligned load/stores may give better results, but
226 it is a system wide setting : bad */
227 #if defined(WORDS_BIGENDIAN) || defined(WORDS_ALIGNED)
229 /* conservative code for little endian unaligned accesses */
230 static inline int lduw_le_p(void *ptr
)
234 __asm__
__volatile__ ("lhbrx %0,0,%1" : "=r" (val
) : "r" (ptr
));
236 #elif defined(__sparc__)
237 #ifndef ASI_PRIMARY_LITTLE
238 #define ASI_PRIMARY_LITTLE 0x88
242 __asm__
__volatile__ ("lduha [%1] %2, %0" : "=r" (val
) : "r" (ptr
),
243 "i" (ASI_PRIMARY_LITTLE
));
247 return p
[0] | (p
[1] << 8);
251 static inline int ldsw_le_p(void *ptr
)
255 __asm__
__volatile__ ("lhbrx %0,0,%1" : "=r" (val
) : "r" (ptr
));
257 #elif defined(__sparc__)
259 __asm__
__volatile__ ("ldsha [%1] %2, %0" : "=r" (val
) : "r" (ptr
),
260 "i" (ASI_PRIMARY_LITTLE
));
264 return (int16_t)(p
[0] | (p
[1] << 8));
268 static inline int ldl_le_p(void *ptr
)
272 __asm__
__volatile__ ("lwbrx %0,0,%1" : "=r" (val
) : "r" (ptr
));
274 #elif defined(__sparc__)
276 __asm__
__volatile__ ("lduwa [%1] %2, %0" : "=r" (val
) : "r" (ptr
),
277 "i" (ASI_PRIMARY_LITTLE
));
281 return p
[0] | (p
[1] << 8) | (p
[2] << 16) | (p
[3] << 24);
285 static inline uint64_t ldq_le_p(void *ptr
)
287 #if defined(__sparc__)
289 __asm__
__volatile__ ("ldxa [%1] %2, %0" : "=r" (val
) : "r" (ptr
),
290 "i" (ASI_PRIMARY_LITTLE
));
296 v2
= ldl_le_p(p
+ 4);
297 return v1
| ((uint64_t)v2
<< 32);
301 static inline void stw_le_p(void *ptr
, int v
)
304 __asm__
__volatile__ ("sthbrx %1,0,%2" : "=m" (*(uint16_t *)ptr
) : "r" (v
), "r" (ptr
));
305 #elif defined(__sparc__)
306 __asm__
__volatile__ ("stha %1, [%2] %3" : "=m" (*(uint16_t *)ptr
) : "r" (v
),
307 "r" (ptr
), "i" (ASI_PRIMARY_LITTLE
));
315 static inline void stl_le_p(void *ptr
, int v
)
318 __asm__
__volatile__ ("stwbrx %1,0,%2" : "=m" (*(uint32_t *)ptr
) : "r" (v
), "r" (ptr
));
319 #elif defined(__sparc__)
320 __asm__
__volatile__ ("stwa %1, [%2] %3" : "=m" (*(uint32_t *)ptr
) : "r" (v
),
321 "r" (ptr
), "i" (ASI_PRIMARY_LITTLE
));
331 static inline void stq_le_p(void *ptr
, uint64_t v
)
333 #if defined(__sparc__)
334 __asm__
__volatile__ ("stxa %1, [%2] %3" : "=m" (*(uint64_t *)ptr
) : "r" (v
),
335 "r" (ptr
), "i" (ASI_PRIMARY_LITTLE
));
336 #undef ASI_PRIMARY_LITTLE
339 stl_le_p(p
, (uint32_t)v
);
340 stl_le_p(p
+ 4, v
>> 32);
346 static inline float32
ldfl_le_p(void *ptr
)
356 static inline void stfl_le_p(void *ptr
, float32 v
)
366 static inline float64
ldfq_le_p(void *ptr
)
369 u
.l
.lower
= ldl_le_p(ptr
);
370 u
.l
.upper
= ldl_le_p(ptr
+ 4);
374 static inline void stfq_le_p(void *ptr
, float64 v
)
378 stl_le_p(ptr
, u
.l
.lower
);
379 stl_le_p(ptr
+ 4, u
.l
.upper
);
384 static inline int lduw_le_p(void *ptr
)
386 return *(uint16_t *)ptr
;
389 static inline int ldsw_le_p(void *ptr
)
391 return *(int16_t *)ptr
;
394 static inline int ldl_le_p(void *ptr
)
396 return *(uint32_t *)ptr
;
399 static inline uint64_t ldq_le_p(void *ptr
)
401 return *(uint64_t *)ptr
;
404 static inline void stw_le_p(void *ptr
, int v
)
406 *(uint16_t *)ptr
= v
;
409 static inline void stl_le_p(void *ptr
, int v
)
411 *(uint32_t *)ptr
= v
;
414 static inline void stq_le_p(void *ptr
, uint64_t v
)
416 *(uint64_t *)ptr
= v
;
421 static inline float32
ldfl_le_p(void *ptr
)
423 return *(float32
*)ptr
;
426 static inline float64
ldfq_le_p(void *ptr
)
428 return *(float64
*)ptr
;
431 static inline void stfl_le_p(void *ptr
, float32 v
)
436 static inline void stfq_le_p(void *ptr
, float64 v
)
442 #if !defined(WORDS_BIGENDIAN) || defined(WORDS_ALIGNED)
444 static inline int lduw_be_p(void *ptr
)
446 #if defined(__i386__)
448 asm volatile ("movzwl %1, %0\n"
451 : "m" (*(uint16_t *)ptr
));
454 uint8_t *b
= (uint8_t *) ptr
;
455 return ((b
[0] << 8) | b
[1]);
459 static inline int ldsw_be_p(void *ptr
)
461 #if defined(__i386__)
463 asm volatile ("movzwl %1, %0\n"
466 : "m" (*(uint16_t *)ptr
));
469 uint8_t *b
= (uint8_t *) ptr
;
470 return (int16_t)((b
[0] << 8) | b
[1]);
474 static inline int ldl_be_p(void *ptr
)
476 #if defined(__i386__) || defined(__x86_64__)
478 asm volatile ("movl %1, %0\n"
481 : "m" (*(uint32_t *)ptr
));
484 uint8_t *b
= (uint8_t *) ptr
;
485 return (b
[0] << 24) | (b
[1] << 16) | (b
[2] << 8) | b
[3];
489 static inline uint64_t ldq_be_p(void *ptr
)
493 b
= ldl_be_p((uint8_t *)ptr
+ 4);
494 return (((uint64_t)a
<<32)|b
);
497 static inline void stw_be_p(void *ptr
, int v
)
499 #if defined(__i386__)
500 asm volatile ("xchgb %b0, %h0\n"
503 : "m" (*(uint16_t *)ptr
), "0" (v
));
505 uint8_t *d
= (uint8_t *) ptr
;
511 static inline void stl_be_p(void *ptr
, int v
)
513 #if defined(__i386__) || defined(__x86_64__)
514 asm volatile ("bswap %0\n"
517 : "m" (*(uint32_t *)ptr
), "0" (v
));
519 uint8_t *d
= (uint8_t *) ptr
;
527 static inline void stq_be_p(void *ptr
, uint64_t v
)
529 stl_be_p(ptr
, v
>> 32);
530 stl_be_p((uint8_t *)ptr
+ 4, v
);
535 static inline float32
ldfl_be_p(void *ptr
)
545 static inline void stfl_be_p(void *ptr
, float32 v
)
555 static inline float64
ldfq_be_p(void *ptr
)
558 u
.l
.upper
= ldl_be_p(ptr
);
559 u
.l
.lower
= ldl_be_p((uint8_t *)ptr
+ 4);
563 static inline void stfq_be_p(void *ptr
, float64 v
)
567 stl_be_p(ptr
, u
.l
.upper
);
568 stl_be_p((uint8_t *)ptr
+ 4, u
.l
.lower
);
573 static inline int lduw_be_p(void *ptr
)
575 return *(uint16_t *)ptr
;
578 static inline int ldsw_be_p(void *ptr
)
580 return *(int16_t *)ptr
;
583 static inline int ldl_be_p(void *ptr
)
585 return *(uint32_t *)ptr
;
588 static inline uint64_t ldq_be_p(void *ptr
)
590 return *(uint64_t *)ptr
;
593 static inline void stw_be_p(void *ptr
, int v
)
595 *(uint16_t *)ptr
= v
;
598 static inline void stl_be_p(void *ptr
, int v
)
600 *(uint32_t *)ptr
= v
;
603 static inline void stq_be_p(void *ptr
, uint64_t v
)
605 *(uint64_t *)ptr
= v
;
610 static inline float32
ldfl_be_p(void *ptr
)
612 return *(float32
*)ptr
;
615 static inline float64
ldfq_be_p(void *ptr
)
617 return *(float64
*)ptr
;
620 static inline void stfl_be_p(void *ptr
, float32 v
)
625 static inline void stfq_be_p(void *ptr
, float64 v
)
632 /* target CPU memory access functions */
633 #if defined(TARGET_WORDS_BIGENDIAN)
634 #define lduw_p(p) lduw_be_p(p)
635 #define ldsw_p(p) ldsw_be_p(p)
636 #define ldl_p(p) ldl_be_p(p)
637 #define ldq_p(p) ldq_be_p(p)
638 #define ldfl_p(p) ldfl_be_p(p)
639 #define ldfq_p(p) ldfq_be_p(p)
640 #define stw_p(p, v) stw_be_p(p, v)
641 #define stl_p(p, v) stl_be_p(p, v)
642 #define stq_p(p, v) stq_be_p(p, v)
643 #define stfl_p(p, v) stfl_be_p(p, v)
644 #define stfq_p(p, v) stfq_be_p(p, v)
646 #define lduw_p(p) lduw_le_p(p)
647 #define ldsw_p(p) ldsw_le_p(p)
648 #define ldl_p(p) ldl_le_p(p)
649 #define ldq_p(p) ldq_le_p(p)
650 #define ldfl_p(p) ldfl_le_p(p)
651 #define ldfq_p(p) ldfq_le_p(p)
652 #define stw_p(p, v) stw_le_p(p, v)
653 #define stl_p(p, v) stl_le_p(p, v)
654 #define stq_p(p, v) stq_le_p(p, v)
655 #define stfl_p(p, v) stfl_le_p(p, v)
656 #define stfq_p(p, v) stfq_le_p(p, v)
659 /* MMU memory access macros */
661 #if defined(CONFIG_USER_ONLY)
662 /* On some host systems the guest address space is reserved on the host.
663 * This allows the guest address space to be offset to a convenient location.
665 //#define GUEST_BASE 0x20000000
668 /* All direct uses of g2h and h2g need to go away for usermode softmmu. */
669 #define g2h(x) ((void *)((unsigned long)(x) + GUEST_BASE))
670 #define h2g(x) ((target_ulong)((unsigned long)(x) - GUEST_BASE))
672 #define saddr(x) g2h(x)
673 #define laddr(x) g2h(x)
675 #else /* !CONFIG_USER_ONLY */
676 /* NOTE: we use double casts if pointers and target_ulong have
678 #define saddr(x) (uint8_t *)(long)(x)
679 #define laddr(x) (uint8_t *)(long)(x)
682 #define ldub_raw(p) ldub_p(laddr((p)))
683 #define ldsb_raw(p) ldsb_p(laddr((p)))
684 #define lduw_raw(p) lduw_p(laddr((p)))
685 #define ldsw_raw(p) ldsw_p(laddr((p)))
686 #define ldl_raw(p) ldl_p(laddr((p)))
687 #define ldq_raw(p) ldq_p(laddr((p)))
688 #define ldfl_raw(p) ldfl_p(laddr((p)))
689 #define ldfq_raw(p) ldfq_p(laddr((p)))
690 #define stb_raw(p, v) stb_p(saddr((p)), v)
691 #define stw_raw(p, v) stw_p(saddr((p)), v)
692 #define stl_raw(p, v) stl_p(saddr((p)), v)
693 #define stq_raw(p, v) stq_p(saddr((p)), v)
694 #define stfl_raw(p, v) stfl_p(saddr((p)), v)
695 #define stfq_raw(p, v) stfq_p(saddr((p)), v)
698 #if defined(CONFIG_USER_ONLY)
700 /* if user mode, no other memory access functions */
701 #define ldub(p) ldub_raw(p)
702 #define ldsb(p) ldsb_raw(p)
703 #define lduw(p) lduw_raw(p)
704 #define ldsw(p) ldsw_raw(p)
705 #define ldl(p) ldl_raw(p)
706 #define ldq(p) ldq_raw(p)
707 #define ldfl(p) ldfl_raw(p)
708 #define ldfq(p) ldfq_raw(p)
709 #define stb(p, v) stb_raw(p, v)
710 #define stw(p, v) stw_raw(p, v)
711 #define stl(p, v) stl_raw(p, v)
712 #define stq(p, v) stq_raw(p, v)
713 #define stfl(p, v) stfl_raw(p, v)
714 #define stfq(p, v) stfq_raw(p, v)
716 #define ldub_code(p) ldub_raw(p)
717 #define ldsb_code(p) ldsb_raw(p)
718 #define lduw_code(p) lduw_raw(p)
719 #define ldsw_code(p) ldsw_raw(p)
720 #define ldl_code(p) ldl_raw(p)
721 #define ldq_code(p) ldq_raw(p)
723 #define ldub_kernel(p) ldub_raw(p)
724 #define ldsb_kernel(p) ldsb_raw(p)
725 #define lduw_kernel(p) lduw_raw(p)
726 #define ldsw_kernel(p) ldsw_raw(p)
727 #define ldl_kernel(p) ldl_raw(p)
728 #define ldq_kernel(p) ldq_raw(p)
729 #define ldfl_kernel(p) ldfl_raw(p)
730 #define ldfq_kernel(p) ldfq_raw(p)
731 #define stb_kernel(p, v) stb_raw(p, v)
732 #define stw_kernel(p, v) stw_raw(p, v)
733 #define stl_kernel(p, v) stl_raw(p, v)
734 #define stq_kernel(p, v) stq_raw(p, v)
735 #define stfl_kernel(p, v) stfl_raw(p, v)
736 #define stfq_kernel(p, vt) stfq_raw(p, v)
738 #endif /* defined(CONFIG_USER_ONLY) */
740 /* page related stuff */
742 #define TARGET_PAGE_SIZE (1ul << TARGET_PAGE_BITS)
743 #define TARGET_PAGE_MASK ~(TARGET_PAGE_SIZE - 1)
744 #define TARGET_PAGE_ALIGN(addr) (((addr) + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK)
746 /* ??? These should be the larger of unsigned long and target_ulong. */
747 extern unsigned long qemu_real_host_page_size
;
748 extern unsigned long qemu_host_page_bits
;
749 extern unsigned long qemu_host_page_size
;
750 extern unsigned long qemu_host_page_mask
;
752 #define HOST_PAGE_ALIGN(addr) (((addr) + qemu_host_page_size - 1) & qemu_host_page_mask)
754 /* same as PROT_xxx */
755 #define PAGE_READ 0x0001
756 #define PAGE_WRITE 0x0002
757 #define PAGE_EXEC 0x0004
758 #define PAGE_BITS (PAGE_READ | PAGE_WRITE | PAGE_EXEC)
759 #define PAGE_VALID 0x0008
760 /* original state of the write flag (used when tracking self-modifying
762 #define PAGE_WRITE_ORG 0x0010
763 #define PAGE_RESERVED 0x0020
765 void page_dump(FILE *f
);
766 int page_get_flags(target_ulong address
);
767 void page_set_flags(target_ulong start
, target_ulong end
, int flags
);
768 int page_check_range(target_ulong start
, target_ulong len
, int flags
);
770 void cpu_exec_init_all(unsigned long tb_size
);
771 CPUState
*cpu_copy(CPUState
*env
);
773 void cpu_dump_state(CPUState
*env
, FILE *f
,
774 int (*cpu_fprintf
)(FILE *f
, const char *fmt
, ...),
776 void cpu_dump_statistics (CPUState
*env
, FILE *f
,
777 int (*cpu_fprintf
)(FILE *f
, const char *fmt
, ...),
780 void cpu_abort(CPUState
*env
, const char *fmt
, ...)
781 __attribute__ ((__format__ (__printf__
, 2, 3)))
782 __attribute__ ((__noreturn__
));
783 extern CPUState
*first_cpu
;
784 extern CPUState
*cpu_single_env
;
785 extern int64_t qemu_icount
;
786 extern int use_icount
;
788 #define CPU_INTERRUPT_EXIT 0x01 /* wants exit from main loop */
789 #define CPU_INTERRUPT_HARD 0x02 /* hardware interrupt pending */
790 #define CPU_INTERRUPT_EXITTB 0x04 /* exit the current TB (use for x86 a20 case) */
791 #define CPU_INTERRUPT_TIMER 0x08 /* internal timer exception pending */
792 #define CPU_INTERRUPT_FIQ 0x10 /* Fast interrupt pending. */
793 #define CPU_INTERRUPT_HALT 0x20 /* CPU halt wanted */
794 #define CPU_INTERRUPT_SMI 0x40 /* (x86 only) SMI interrupt pending */
795 #define CPU_INTERRUPT_DEBUG 0x80 /* Debug event occured. */
796 #define CPU_INTERRUPT_VIRQ 0x100 /* virtual interrupt pending. */
797 #define CPU_INTERRUPT_NMI 0x200 /* NMI pending. */
799 void cpu_interrupt(CPUState
*s
, int mask
);
800 void cpu_reset_interrupt(CPUState
*env
, int mask
);
802 int cpu_watchpoint_insert(CPUState
*env
, target_ulong addr
, int type
);
803 int cpu_watchpoint_remove(CPUState
*env
, target_ulong addr
);
804 void cpu_watchpoint_remove_all(CPUState
*env
);
805 int cpu_breakpoint_insert(CPUState
*env
, target_ulong pc
);
806 int cpu_breakpoint_remove(CPUState
*env
, target_ulong pc
);
807 void cpu_breakpoint_remove_all(CPUState
*env
);
809 #define SSTEP_ENABLE 0x1 /* Enable simulated HW single stepping */
810 #define SSTEP_NOIRQ 0x2 /* Do not use IRQ while single stepping */
811 #define SSTEP_NOTIMER 0x4 /* Do not Timers while single stepping */
813 void cpu_single_step(CPUState
*env
, int enabled
);
814 void cpu_reset(CPUState
*s
);
816 /* Return the physical page corresponding to a virtual one. Use it
817 only for debugging because no protection checks are done. Return -1
819 target_phys_addr_t
cpu_get_phys_page_debug(CPUState
*env
, target_ulong addr
);
821 #define CPU_LOG_TB_OUT_ASM (1 << 0)
822 #define CPU_LOG_TB_IN_ASM (1 << 1)
823 #define CPU_LOG_TB_OP (1 << 2)
824 #define CPU_LOG_TB_OP_OPT (1 << 3)
825 #define CPU_LOG_INT (1 << 4)
826 #define CPU_LOG_EXEC (1 << 5)
827 #define CPU_LOG_PCALL (1 << 6)
828 #define CPU_LOG_IOPORT (1 << 7)
829 #define CPU_LOG_TB_CPU (1 << 8)
831 /* define log items */
832 typedef struct CPULogItem
{
838 extern CPULogItem cpu_log_items
[];
840 void cpu_set_log(int log_flags
);
841 void cpu_set_log_filename(const char *filename
);
842 int cpu_str_to_log_mask(const char *str
);
846 /* NOTE: as these functions may be even used when there is an isa
847 brige on non x86 targets, we always defined them */
848 #ifndef NO_CPU_IO_DEFS
849 void cpu_outb(CPUState
*env
, int addr
, int val
);
850 void cpu_outw(CPUState
*env
, int addr
, int val
);
851 void cpu_outl(CPUState
*env
, int addr
, int val
);
852 int cpu_inb(CPUState
*env
, int addr
);
853 int cpu_inw(CPUState
*env
, int addr
);
854 int cpu_inl(CPUState
*env
, int addr
);
857 /* address in the RAM (different from a physical address) */
859 typedef uint32_t ram_addr_t
;
861 typedef unsigned long ram_addr_t
;
866 extern ram_addr_t phys_ram_size
;
867 extern int phys_ram_fd
;
868 extern uint8_t *phys_ram_base
;
869 extern uint8_t *phys_ram_dirty
;
870 extern ram_addr_t ram_size
;
871 extern uint8_t *bios_mem
;
873 /* physical memory access */
875 /* MMIO pages are identified by a combination of an IO device index and
876 3 flags. The ROMD code stores the page ram offset in iotlb entry,
877 so only a limited number of ids are avaiable. */
879 #define IO_MEM_SHIFT 3
880 #define IO_MEM_NB_ENTRIES (1 << (TARGET_PAGE_BITS - IO_MEM_SHIFT))
882 #define IO_MEM_RAM (0 << IO_MEM_SHIFT) /* hardcoded offset */
883 #define IO_MEM_ROM (1 << IO_MEM_SHIFT) /* hardcoded offset */
884 #define IO_MEM_UNASSIGNED (2 << IO_MEM_SHIFT)
885 #define IO_MEM_NOTDIRTY (3 << IO_MEM_SHIFT)
887 /* Acts like a ROM when read and like a device when written. */
888 #define IO_MEM_ROMD (1)
889 #define IO_MEM_SUBPAGE (2)
890 #define IO_MEM_SUBWIDTH (4)
892 /* Flags stored in the low bits of the TLB virtual address. These are
893 defined so that fast path ram access is all zeros. */
894 /* Zero if TLB entry is valid. */
895 #define TLB_INVALID_MASK (1 << 3)
896 /* Set if TLB entry references a clean RAM page. The iotlb entry will
897 contain the page physical address. */
898 #define TLB_NOTDIRTY (1 << 4)
899 /* Set if TLB entry is an IO callback. */
900 #define TLB_MMIO (1 << 5)
902 typedef void CPUWriteMemoryFunc(void *opaque
, target_phys_addr_t addr
, uint32_t value
);
903 typedef uint32_t CPUReadMemoryFunc(void *opaque
, target_phys_addr_t addr
);
905 void cpu_register_physical_memory(target_phys_addr_t start_addr
,
907 ram_addr_t phys_offset
);
908 ram_addr_t
cpu_get_physical_page_desc(target_phys_addr_t addr
);
909 ram_addr_t
qemu_ram_alloc(ram_addr_t
);
910 void qemu_ram_free(ram_addr_t addr
);
911 int cpu_register_io_memory(int io_index
,
912 CPUReadMemoryFunc
**mem_read
,
913 CPUWriteMemoryFunc
**mem_write
,
915 void cpu_unregister_io_memory(int table_address
);
916 CPUWriteMemoryFunc
**cpu_get_io_memory_write(int io_index
);
917 CPUReadMemoryFunc
**cpu_get_io_memory_read(int io_index
);
919 void cpu_physical_memory_rw(target_phys_addr_t addr
, uint8_t *buf
,
920 int len
, int is_write
);
921 static inline void cpu_physical_memory_read(target_phys_addr_t addr
,
922 uint8_t *buf
, int len
)
924 cpu_physical_memory_rw(addr
, buf
, len
, 0);
926 static inline void cpu_physical_memory_write(target_phys_addr_t addr
,
927 const uint8_t *buf
, int len
)
929 cpu_physical_memory_rw(addr
, (uint8_t *)buf
, len
, 1);
931 uint32_t ldub_phys(target_phys_addr_t addr
);
932 uint32_t lduw_phys(target_phys_addr_t addr
);
933 uint32_t ldl_phys(target_phys_addr_t addr
);
934 uint64_t ldq_phys(target_phys_addr_t addr
);
935 void stl_phys_notdirty(target_phys_addr_t addr
, uint32_t val
);
936 void stq_phys_notdirty(target_phys_addr_t addr
, uint64_t val
);
937 void stb_phys(target_phys_addr_t addr
, uint32_t val
);
938 void stw_phys(target_phys_addr_t addr
, uint32_t val
);
939 void stl_phys(target_phys_addr_t addr
, uint32_t val
);
940 void stq_phys(target_phys_addr_t addr
, uint64_t val
);
942 void cpu_physical_memory_write_rom(target_phys_addr_t addr
,
943 const uint8_t *buf
, int len
);
944 int cpu_memory_rw_debug(CPUState
*env
, target_ulong addr
,
945 uint8_t *buf
, int len
, int is_write
);
947 #define VGA_DIRTY_FLAG 0x01
948 #define CODE_DIRTY_FLAG 0x02
949 #define MIGRATION_DIRTY_FLAG 0x08
951 /* read dirty bit (return 0 or 1) */
952 static inline int cpu_physical_memory_is_dirty(ram_addr_t addr
)
954 return phys_ram_dirty
[addr
>> TARGET_PAGE_BITS
] == 0xff;
957 static inline int cpu_physical_memory_get_dirty(ram_addr_t addr
,
960 return phys_ram_dirty
[addr
>> TARGET_PAGE_BITS
] & dirty_flags
;
963 static inline void cpu_physical_memory_set_dirty(ram_addr_t addr
)
965 phys_ram_dirty
[addr
>> TARGET_PAGE_BITS
] = 0xff;
968 void cpu_physical_memory_reset_dirty(ram_addr_t start
, ram_addr_t end
,
970 void cpu_tlb_update_dirty(CPUState
*env
);
972 int cpu_physical_memory_set_dirty_tracking(int enable
);
974 int cpu_physical_memory_get_dirty_tracking(void);
976 void dump_exec_info(FILE *f
,
977 int (*cpu_fprintf
)(FILE *f
, const char *fmt
, ...));
979 /*******************************************/
980 /* host CPU ticks (if available) */
982 #if defined(__powerpc__)
984 static inline uint32_t get_tbl(void)
987 asm volatile("mftb %0" : "=r" (tbl
));
991 static inline uint32_t get_tbu(void)
994 asm volatile("mftbu %0" : "=r" (tbl
));
998 static inline int64_t cpu_get_real_ticks(void)
1001 /* NOTE: we test if wrapping has occurred */
1007 return ((int64_t)h
<< 32) | l
;
1010 #elif defined(__i386__)
1012 static inline int64_t cpu_get_real_ticks(void)
1015 asm volatile ("rdtsc" : "=A" (val
));
1019 #elif defined(__x86_64__)
1021 static inline int64_t cpu_get_real_ticks(void)
1025 asm volatile("rdtsc" : "=a" (low
), "=d" (high
));
1032 #elif defined(__hppa__)
1034 static inline int64_t cpu_get_real_ticks(void)
1037 asm volatile ("mfctl %%cr16, %0" : "=r"(val
));
1041 #elif defined(__ia64)
1043 static inline int64_t cpu_get_real_ticks(void)
1046 asm volatile ("mov %0 = ar.itc" : "=r"(val
) :: "memory");
1050 #elif defined(__s390__)
1052 static inline int64_t cpu_get_real_ticks(void)
1055 asm volatile("stck 0(%1)" : "=m" (val
) : "a" (&val
) : "cc");
1059 #elif defined(__sparc_v8plus__) || defined(__sparc_v8plusa__) || defined(__sparc_v9__)
1061 static inline int64_t cpu_get_real_ticks (void)
1065 asm volatile("rd %%tick,%0" : "=r"(rval
));
1075 asm volatile("rd %%tick,%1; srlx %1,32,%0"
1076 : "=r"(rval
.i32
.high
), "=r"(rval
.i32
.low
));
1081 #elif defined(__mips__)
1083 static inline int64_t cpu_get_real_ticks(void)
1085 #if __mips_isa_rev >= 2
1087 static uint32_t cyc_per_count
= 0;
1090 __asm__
__volatile__("rdhwr %0, $3" : "=r" (cyc_per_count
));
1092 __asm__
__volatile__("rdhwr %1, $2" : "=r" (count
));
1093 return (int64_t)(count
* cyc_per_count
);
1096 static int64_t ticks
= 0;
1102 /* The host CPU doesn't have an easily accessible cycle counter.
1103 Just return a monotonically increasing value. This will be
1104 totally wrong, but hopefully better than nothing. */
1105 static inline int64_t cpu_get_real_ticks (void)
1107 static int64_t ticks
= 0;
1113 #ifdef CONFIG_PROFILER
1114 static inline int64_t profile_getclock(void)
1116 return cpu_get_real_ticks();
1119 extern int64_t kqemu_time
, kqemu_time_start
;
1120 extern int64_t qemu_time
, qemu_time_start
;
1121 extern int64_t tlb_flush_time
;
1122 extern int64_t kqemu_exec_count
;
1123 extern int64_t dev_time
;
1124 extern int64_t kqemu_ret_int_count
;
1125 extern int64_t kqemu_ret_excp_count
;
1126 extern int64_t kqemu_ret_intr_count
;
1129 #endif /* CPU_ALL_H */