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Set default audio timer period to a sane value (otherwise qemu becomes unusable if...
[qemu-kvm/fedora.git] / tcg / x86_64 / tcg-target.c
blob551ca78bb972922f566c3cb6b6e53fa2dfa012ce
1 /*
2 * Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2008 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #ifndef NDEBUG
26 static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
27 "%rax",
28 "%rcx",
29 "%rdx",
30 "%rbx",
31 "%rsp",
32 "%rbp",
33 "%rsi",
34 "%rdi",
35 "%r8",
36 "%r9",
37 "%r10",
38 "%r11",
39 "%r12",
40 "%r13",
41 "%r14",
42 "%r15",
43 };
44 #endif
45
46 static const int tcg_target_reg_alloc_order[] = {
47 TCG_REG_RDI,
48 TCG_REG_RSI,
49 TCG_REG_RDX,
50 TCG_REG_RCX,
51 TCG_REG_R8,
52 TCG_REG_R9,
53 TCG_REG_RAX,
54 TCG_REG_R10,
55 TCG_REG_R11,
56
57 TCG_REG_RBP,
58 TCG_REG_RBX,
59 TCG_REG_R12,
60 TCG_REG_R13,
61 TCG_REG_R14,
62 TCG_REG_R15,
63 };
64
65 static const int tcg_target_call_iarg_regs[6] = {
66 TCG_REG_RDI,
67 TCG_REG_RSI,
68 TCG_REG_RDX,
69 TCG_REG_RCX,
70 TCG_REG_R8,
71 TCG_REG_R9,
72 };
73
74 static const int tcg_target_call_oarg_regs[2] = {
75 TCG_REG_RAX,
76 TCG_REG_RDX
77 };
78
79 static uint8_t *tb_ret_addr;
80
81 static void patch_reloc(uint8_t *code_ptr, int type,
82 tcg_target_long value, tcg_target_long addend)
83 {
84 value += addend;
85 switch(type) {
86 case R_X86_64_32:
87 if (value != (uint32_t)value)
88 tcg_abort();
89 *(uint32_t *)code_ptr = value;
90 break;
91 case R_X86_64_32S:
92 if (value != (int32_t)value)
93 tcg_abort();
94 *(uint32_t *)code_ptr = value;
95 break;
96 case R_386_PC32:
97 value -= (long)code_ptr;
98 if (value != (int32_t)value)
99 tcg_abort();
100 *(uint32_t *)code_ptr = value;
101 break;
102 default:
103 tcg_abort();
104 }
105 }
106
107 /* maximum number of register used for input function arguments */
108 static inline int tcg_target_get_call_iarg_regs_count(int flags)
109 {
110 return 6;
111 }
112
113 /* parse target specific constraints */
114 static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
115 {
116 const char *ct_str;
117
118 ct_str = *pct_str;
119 switch(ct_str[0]) {
120 case 'a':
121 ct->ct |= TCG_CT_REG;
122 tcg_regset_set_reg(ct->u.regs, TCG_REG_RAX);
123 break;
124 case 'b':
125 ct->ct |= TCG_CT_REG;
126 tcg_regset_set_reg(ct->u.regs, TCG_REG_RBX);
127 break;
128 case 'c':
129 ct->ct |= TCG_CT_REG;
130 tcg_regset_set_reg(ct->u.regs, TCG_REG_RCX);
131 break;
132 case 'd':
133 ct->ct |= TCG_CT_REG;
134 tcg_regset_set_reg(ct->u.regs, TCG_REG_RDX);
135 break;
136 case 'S':
137 ct->ct |= TCG_CT_REG;
138 tcg_regset_set_reg(ct->u.regs, TCG_REG_RSI);
139 break;
140 case 'D':
141 ct->ct |= TCG_CT_REG;
142 tcg_regset_set_reg(ct->u.regs, TCG_REG_RDI);
143 break;
144 case 'q':
145 ct->ct |= TCG_CT_REG;
146 tcg_regset_set32(ct->u.regs, 0, 0xf);
147 break;
148 case 'r':
149 ct->ct |= TCG_CT_REG;
150 tcg_regset_set32(ct->u.regs, 0, 0xffff);
151 break;
152 case 'L': /* qemu_ld/st constraint */
153 ct->ct |= TCG_CT_REG;
154 tcg_regset_set32(ct->u.regs, 0, 0xffff);
155 tcg_regset_reset_reg(ct->u.regs, TCG_REG_RSI);
156 tcg_regset_reset_reg(ct->u.regs, TCG_REG_RDI);
157 break;
158 case 'e':
159 ct->ct |= TCG_CT_CONST_S32;
160 break;
161 case 'Z':
162 ct->ct |= TCG_CT_CONST_U32;
163 break;
164 default:
165 return -1;
166 }
167 ct_str++;
168 *pct_str = ct_str;
169 return 0;
170 }
171
172 /* test if a constant matches the constraint */
173 static inline int tcg_target_const_match(tcg_target_long val,
174 const TCGArgConstraint *arg_ct)
175 {
176 int ct;
177 ct = arg_ct->ct;
178 if (ct & TCG_CT_CONST)
179 return 1;
180 else if ((ct & TCG_CT_CONST_S32) && val == (int32_t)val)
181 return 1;
182 else if ((ct & TCG_CT_CONST_U32) && val == (uint32_t)val)
183 return 1;
184 else
185 return 0;
186 }
187
188 #define ARITH_ADD 0
189 #define ARITH_OR 1
190 #define ARITH_ADC 2
191 #define ARITH_SBB 3
192 #define ARITH_AND 4
193 #define ARITH_SUB 5
194 #define ARITH_XOR 6
195 #define ARITH_CMP 7
196
197 #define SHIFT_SHL 4
198 #define SHIFT_SHR 5
199 #define SHIFT_SAR 7
200
201 #define JCC_JMP (-1)
202 #define JCC_JO 0x0
203 #define JCC_JNO 0x1
204 #define JCC_JB 0x2
205 #define JCC_JAE 0x3
206 #define JCC_JE 0x4
207 #define JCC_JNE 0x5
208 #define JCC_JBE 0x6
209 #define JCC_JA 0x7
210 #define JCC_JS 0x8
211 #define JCC_JNS 0x9
212 #define JCC_JP 0xa
213 #define JCC_JNP 0xb
214 #define JCC_JL 0xc
215 #define JCC_JGE 0xd
216 #define JCC_JLE 0xe
217 #define JCC_JG 0xf
218
219 #define P_EXT 0x100 /* 0x0f opcode prefix */
220 #define P_REXW 0x200 /* set rex.w = 1 */
221 #define P_REXB 0x400 /* force rex use for byte registers */
222
223 static const uint8_t tcg_cond_to_jcc[10] = {
224 [TCG_COND_EQ] = JCC_JE,
225 [TCG_COND_NE] = JCC_JNE,
226 [TCG_COND_LT] = JCC_JL,
227 [TCG_COND_GE] = JCC_JGE,
228 [TCG_COND_LE] = JCC_JLE,
229 [TCG_COND_GT] = JCC_JG,
230 [TCG_COND_LTU] = JCC_JB,
231 [TCG_COND_GEU] = JCC_JAE,
232 [TCG_COND_LEU] = JCC_JBE,
233 [TCG_COND_GTU] = JCC_JA,
234 };
235
236 static inline void tcg_out_opc(TCGContext *s, int opc, int r, int rm, int x)
237 {
238 int rex;
239 rex = ((opc >> 6) & 0x8) | ((r >> 1) & 0x4) |
240 ((x >> 2) & 2) | ((rm >> 3) & 1);
241 if (rex || (opc & P_REXB)) {
242 tcg_out8(s, rex | 0x40);
243 }
244 if (opc & P_EXT)
245 tcg_out8(s, 0x0f);
246 tcg_out8(s, opc);
247 }
248
249 static inline void tcg_out_modrm(TCGContext *s, int opc, int r, int rm)
250 {
251 tcg_out_opc(s, opc, r, rm, 0);
252 tcg_out8(s, 0xc0 | ((r & 7) << 3) | (rm & 7));
253 }
254
255 /* rm < 0 means no register index plus (-rm - 1 immediate bytes) */
256 static inline void tcg_out_modrm_offset(TCGContext *s, int opc, int r, int rm,
257 tcg_target_long offset)
258 {
259 if (rm < 0) {
260 tcg_target_long val;
261 tcg_out_opc(s, opc, r, 0, 0);
262 val = offset - ((tcg_target_long)s->code_ptr + 5 + (-rm - 1));
263 if (val == (int32_t)val) {
264 /* eip relative */
265 tcg_out8(s, 0x05 | ((r & 7) << 3));
266 tcg_out32(s, val);
267 } else if (offset == (int32_t)offset) {
268 tcg_out8(s, 0x04 | ((r & 7) << 3));
269 tcg_out8(s, 0x25); /* sib */
270 tcg_out32(s, offset);
271 } else {
272 tcg_abort();
273 }
274 } else if (offset == 0 && (rm & 7) != TCG_REG_RBP) {
275 tcg_out_opc(s, opc, r, rm, 0);
276 if ((rm & 7) == TCG_REG_RSP) {
277 tcg_out8(s, 0x04 | ((r & 7) << 3));
278 tcg_out8(s, 0x24);
279 } else {
280 tcg_out8(s, 0x00 | ((r & 7) << 3) | (rm & 7));
281 }
282 } else if ((int8_t)offset == offset) {
283 tcg_out_opc(s, opc, r, rm, 0);
284 if ((rm & 7) == TCG_REG_RSP) {
285 tcg_out8(s, 0x44 | ((r & 7) << 3));
286 tcg_out8(s, 0x24);
287 } else {
288 tcg_out8(s, 0x40 | ((r & 7) << 3) | (rm & 7));
289 }
290 tcg_out8(s, offset);
291 } else {
292 tcg_out_opc(s, opc, r, rm, 0);
293 if ((rm & 7) == TCG_REG_RSP) {
294 tcg_out8(s, 0x84 | ((r & 7) << 3));
295 tcg_out8(s, 0x24);
296 } else {
297 tcg_out8(s, 0x80 | ((r & 7) << 3) | (rm & 7));
298 }
299 tcg_out32(s, offset);
300 }
301 }
302
303 #if defined(CONFIG_SOFTMMU)
304 /* XXX: incomplete. index must be different from ESP */
305 static void tcg_out_modrm_offset2(TCGContext *s, int opc, int r, int rm,
306 int index, int shift,
307 tcg_target_long offset)
308 {
309 int mod;
310 if (rm == -1)
311 tcg_abort();
312 if (offset == 0 && (rm & 7) != TCG_REG_RBP) {
313 mod = 0;
314 } else if (offset == (int8_t)offset) {
315 mod = 0x40;
316 } else if (offset == (int32_t)offset) {
317 mod = 0x80;
318 } else {
319 tcg_abort();
320 }
321 if (index == -1) {
322 tcg_out_opc(s, opc, r, rm, 0);
323 if ((rm & 7) == TCG_REG_RSP) {
324 tcg_out8(s, mod | ((r & 7) << 3) | 0x04);
325 tcg_out8(s, 0x04 | (rm & 7));
326 } else {
327 tcg_out8(s, mod | ((r & 7) << 3) | (rm & 7));
328 }
329 } else {
330 tcg_out_opc(s, opc, r, rm, index);
331 tcg_out8(s, mod | ((r & 7) << 3) | 0x04);
332 tcg_out8(s, (shift << 6) | ((index & 7) << 3) | (rm & 7));
333 }
334 if (mod == 0x40) {
335 tcg_out8(s, offset);
336 } else if (mod == 0x80) {
337 tcg_out32(s, offset);
338 }
339 }
340 #endif
341
342 static inline void tcg_out_mov(TCGContext *s, int ret, int arg)
343 {
344 tcg_out_modrm(s, 0x8b | P_REXW, ret, arg);
345 }
346
347 static inline void tcg_out_movi(TCGContext *s, TCGType type,
348 int ret, tcg_target_long arg)
349 {
350 if (arg == 0) {
351 tcg_out_modrm(s, 0x01 | (ARITH_XOR << 3), ret, ret); /* xor r0,r0 */
352 } else if (arg == (uint32_t)arg || type == TCG_TYPE_I32) {
353 tcg_out_opc(s, 0xb8 + (ret & 7), 0, ret, 0);
354 tcg_out32(s, arg);
355 } else if (arg == (int32_t)arg) {
356 tcg_out_modrm(s, 0xc7 | P_REXW, 0, ret);
357 tcg_out32(s, arg);
358 } else {
359 tcg_out_opc(s, (0xb8 + (ret & 7)) | P_REXW, 0, ret, 0);
360 tcg_out32(s, arg);
361 tcg_out32(s, arg >> 32);
362 }
363 }
364
365 static inline void tcg_out_ld(TCGContext *s, TCGType type, int ret,
366 int arg1, tcg_target_long arg2)
367 {
368 if (type == TCG_TYPE_I32)
369 tcg_out_modrm_offset(s, 0x8b, ret, arg1, arg2); /* movl */
370 else
371 tcg_out_modrm_offset(s, 0x8b | P_REXW, ret, arg1, arg2); /* movq */
372 }
373
374 static inline void tcg_out_st(TCGContext *s, TCGType type, int arg,
375 int arg1, tcg_target_long arg2)
376 {
377 if (type == TCG_TYPE_I32)
378 tcg_out_modrm_offset(s, 0x89, arg, arg1, arg2); /* movl */
379 else
380 tcg_out_modrm_offset(s, 0x89 | P_REXW, arg, arg1, arg2); /* movq */
381 }
382
383 static inline void tgen_arithi32(TCGContext *s, int c, int r0, int32_t val)
384 {
385 if (val == (int8_t)val) {
386 tcg_out_modrm(s, 0x83, c, r0);
387 tcg_out8(s, val);
388 } else if (c == ARITH_AND && val == 0xffu) {
389 /* movzbl */
390 tcg_out_modrm(s, 0xb6 | P_EXT | P_REXB, r0, r0);
391 } else if (c == ARITH_AND && val == 0xffffu) {
392 /* movzwl */
393 tcg_out_modrm(s, 0xb7 | P_EXT, r0, r0);
394 } else {
395 tcg_out_modrm(s, 0x81, c, r0);
396 tcg_out32(s, val);
397 }
398 }
399
400 static inline void tgen_arithi64(TCGContext *s, int c, int r0, int64_t val)
401 {
402 if (val == (int8_t)val) {
403 tcg_out_modrm(s, 0x83 | P_REXW, c, r0);
404 tcg_out8(s, val);
405 } else if (c == ARITH_AND && val == 0xffu) {
406 /* movzbl */
407 tcg_out_modrm(s, 0xb6 | P_EXT | P_REXW, r0, r0);
408 } else if (c == ARITH_AND && val == 0xffffu) {
409 /* movzwl */
410 tcg_out_modrm(s, 0xb7 | P_EXT | P_REXW, r0, r0);
411 } else if (c == ARITH_AND && val == 0xffffffffu) {
412 /* 32-bit mov zero extends */
413 tcg_out_modrm(s, 0x8b, r0, r0);
414 } else if (val == (int32_t)val) {
415 tcg_out_modrm(s, 0x81 | P_REXW, c, r0);
416 tcg_out32(s, val);
417 } else if (c == ARITH_AND && val == (uint32_t)val) {
418 tcg_out_modrm(s, 0x81, c, r0);
419 tcg_out32(s, val);
420 } else {
421 tcg_abort();
422 }
423 }
424
425 static void tcg_out_addi(TCGContext *s, int reg, tcg_target_long val)
426 {
427 if (val != 0)
428 tgen_arithi64(s, ARITH_ADD, reg, val);
429 }
430
431 static void tcg_out_jxx(TCGContext *s, int opc, int label_index)
432 {
433 int32_t val, val1;
434 TCGLabel *l = &s->labels[label_index];
435
436 if (l->has_value) {
437 val = l->u.value - (tcg_target_long)s->code_ptr;
438 val1 = val - 2;
439 if ((int8_t)val1 == val1) {
440 if (opc == -1)
441 tcg_out8(s, 0xeb);
442 else
443 tcg_out8(s, 0x70 + opc);
444 tcg_out8(s, val1);
445 } else {
446 if (opc == -1) {
447 tcg_out8(s, 0xe9);
448 tcg_out32(s, val - 5);
449 } else {
450 tcg_out8(s, 0x0f);
451 tcg_out8(s, 0x80 + opc);
452 tcg_out32(s, val - 6);
453 }
454 }
455 } else {
456 if (opc == -1) {
457 tcg_out8(s, 0xe9);
458 } else {
459 tcg_out8(s, 0x0f);
460 tcg_out8(s, 0x80 + opc);
461 }
462 tcg_out_reloc(s, s->code_ptr, R_386_PC32, label_index, -4);
463 s->code_ptr += 4;
464 }
465 }
466
467 static void tcg_out_brcond(TCGContext *s, int cond,
468 TCGArg arg1, TCGArg arg2, int const_arg2,
469 int label_index, int rexw)
470 {
471 if (const_arg2) {
472 if (arg2 == 0) {
473 /* test r, r */
474 tcg_out_modrm(s, 0x85 | rexw, arg1, arg1);
475 } else {
476 if (rexw)
477 tgen_arithi64(s, ARITH_CMP, arg1, arg2);
478 else
479 tgen_arithi32(s, ARITH_CMP, arg1, arg2);
480 }
481 } else {
482 tcg_out_modrm(s, 0x01 | (ARITH_CMP << 3) | rexw, arg2, arg1);
483 }
484 tcg_out_jxx(s, tcg_cond_to_jcc[cond], label_index);
485 }
486
487 #if defined(CONFIG_SOFTMMU)
488
489 #include "../../softmmu_defs.h"
490
491 static void *qemu_ld_helpers[4] = {
492 __ldb_mmu,
493 __ldw_mmu,
494 __ldl_mmu,
495 __ldq_mmu,
496 };
497
498 static void *qemu_st_helpers[4] = {
499 __stb_mmu,
500 __stw_mmu,
501 __stl_mmu,
502 __stq_mmu,
503 };
504 #endif
505
506 static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args,
507 int opc)
508 {
509 int addr_reg, data_reg, r0, r1, mem_index, s_bits, bswap, rexw;
510 #if defined(CONFIG_SOFTMMU)
511 uint8_t *label1_ptr, *label2_ptr;
512 #endif
513
514 data_reg = *args++;
515 addr_reg = *args++;
516 mem_index = *args;
517 s_bits = opc & 3;
518
519 r0 = TCG_REG_RDI;
520 r1 = TCG_REG_RSI;
521
522 #if TARGET_LONG_BITS == 32
523 rexw = 0;
524 #else
525 rexw = P_REXW;
526 #endif
527 #if defined(CONFIG_SOFTMMU)
528 /* mov */
529 tcg_out_modrm(s, 0x8b | rexw, r1, addr_reg);
530
531 /* mov */
532 tcg_out_modrm(s, 0x8b | rexw, r0, addr_reg);
533
534 tcg_out_modrm(s, 0xc1 | rexw, 5, r1); /* shr $x, r1 */
535 tcg_out8(s, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS);
536
537 tcg_out_modrm(s, 0x81 | rexw, 4, r0); /* andl $x, r0 */
538 tcg_out32(s, TARGET_PAGE_MASK | ((1 << s_bits) - 1));
539
540 tcg_out_modrm(s, 0x81, 4, r1); /* andl $x, r1 */
541 tcg_out32(s, (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS);
542
543 /* lea offset(r1, env), r1 */
544 tcg_out_modrm_offset2(s, 0x8d | P_REXW, r1, r1, TCG_AREG0, 0,
545 offsetof(CPUState, tlb_table[mem_index][0].addr_read));
546
547 /* cmp 0(r1), r0 */
548 tcg_out_modrm_offset(s, 0x3b | rexw, r0, r1, 0);
549
550 /* mov */
551 tcg_out_modrm(s, 0x8b | rexw, r0, addr_reg);
552
553 /* je label1 */
554 tcg_out8(s, 0x70 + JCC_JE);
555 label1_ptr = s->code_ptr;
556 s->code_ptr++;
557
558 /* XXX: move that code at the end of the TB */
559 tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_RSI, mem_index);
560 tcg_out8(s, 0xe8);
561 tcg_out32(s, (tcg_target_long)qemu_ld_helpers[s_bits] -
562 (tcg_target_long)s->code_ptr - 4);
563
564 switch(opc) {
565 case 0 | 4:
566 /* movsbq */
567 tcg_out_modrm(s, 0xbe | P_EXT | P_REXW, data_reg, TCG_REG_RAX);
568 break;
569 case 1 | 4:
570 /* movswq */
571 tcg_out_modrm(s, 0xbf | P_EXT | P_REXW, data_reg, TCG_REG_RAX);
572 break;
573 case 2 | 4:
574 /* movslq */
575 tcg_out_modrm(s, 0x63 | P_REXW, data_reg, TCG_REG_RAX);
576 break;
577 case 0:
578 case 1:
579 case 2:
580 default:
581 /* movl */
582 tcg_out_modrm(s, 0x8b, data_reg, TCG_REG_RAX);
583 break;
584 case 3:
585 tcg_out_mov(s, data_reg, TCG_REG_RAX);
586 break;
587 }
588
589 /* jmp label2 */
590 tcg_out8(s, 0xeb);
591 label2_ptr = s->code_ptr;
592 s->code_ptr++;
593
594 /* label1: */
595 *label1_ptr = s->code_ptr - label1_ptr - 1;
596
597 /* add x(r1), r0 */
598 tcg_out_modrm_offset(s, 0x03 | P_REXW, r0, r1, offsetof(CPUTLBEntry, addend) -
599 offsetof(CPUTLBEntry, addr_read));
600 #else
601 r0 = addr_reg;
602 #endif
603
604 #ifdef TARGET_WORDS_BIGENDIAN
605 bswap = 1;
606 #else
607 bswap = 0;
608 #endif
609 switch(opc) {
610 case 0:
611 /* movzbl */
612 tcg_out_modrm_offset(s, 0xb6 | P_EXT, data_reg, r0, 0);
613 break;
614 case 0 | 4:
615 /* movsbX */
616 tcg_out_modrm_offset(s, 0xbe | P_EXT | rexw, data_reg, r0, 0);
617 break;
618 case 1:
619 /* movzwl */
620 tcg_out_modrm_offset(s, 0xb7 | P_EXT, data_reg, r0, 0);
621 if (bswap) {
622 /* rolw $8, data_reg */
623 tcg_out8(s, 0x66);
624 tcg_out_modrm(s, 0xc1, 0, data_reg);
625 tcg_out8(s, 8);
626 }
627 break;
628 case 1 | 4:
629 if (bswap) {
630 /* movzwl */
631 tcg_out_modrm_offset(s, 0xb7 | P_EXT, data_reg, r0, 0);
632 /* rolw $8, data_reg */
633 tcg_out8(s, 0x66);
634 tcg_out_modrm(s, 0xc1, 0, data_reg);
635 tcg_out8(s, 8);
636
637 /* movswX data_reg, data_reg */
638 tcg_out_modrm(s, 0xbf | P_EXT | rexw, data_reg, data_reg);
639 } else {
640 /* movswX */
641 tcg_out_modrm_offset(s, 0xbf | P_EXT | rexw, data_reg, r0, 0);
642 }
643 break;
644 case 2:
645 /* movl (r0), data_reg */
646 tcg_out_modrm_offset(s, 0x8b, data_reg, r0, 0);
647 if (bswap) {
648 /* bswap */
649 tcg_out_opc(s, (0xc8 + (data_reg & 7)) | P_EXT, 0, data_reg, 0);
650 }
651 break;
652 case 2 | 4:
653 if (bswap) {
654 /* movl (r0), data_reg */
655 tcg_out_modrm_offset(s, 0x8b, data_reg, r0, 0);
656 /* bswap */
657 tcg_out_opc(s, (0xc8 + (data_reg & 7)) | P_EXT, 0, data_reg, 0);
658 /* movslq */
659 tcg_out_modrm(s, 0x63 | P_REXW, data_reg, data_reg);
660 } else {
661 /* movslq */
662 tcg_out_modrm_offset(s, 0x63 | P_REXW, data_reg, r0, 0);
663 }
664 break;
665 case 3:
666 /* movq (r0), data_reg */
667 tcg_out_modrm_offset(s, 0x8b | P_REXW, data_reg, r0, 0);
668 if (bswap) {
669 /* bswap */
670 tcg_out_opc(s, (0xc8 + (data_reg & 7)) | P_EXT | P_REXW, 0, data_reg, 0);
671 }
672 break;
673 default:
674 tcg_abort();
675 }
676
677 #if defined(CONFIG_SOFTMMU)
678 /* label2: */
679 *label2_ptr = s->code_ptr - label2_ptr - 1;
680 #endif
681 }
682
683 static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args,
684 int opc)
685 {
686 int addr_reg, data_reg, r0, r1, mem_index, s_bits, bswap, rexw;
687 #if defined(CONFIG_SOFTMMU)
688 uint8_t *label1_ptr, *label2_ptr;
689 #endif
690
691 data_reg = *args++;
692 addr_reg = *args++;
693 mem_index = *args;
694
695 s_bits = opc;
696
697 r0 = TCG_REG_RDI;
698 r1 = TCG_REG_RSI;
699
700 #if TARGET_LONG_BITS == 32
701 rexw = 0;
702 #else
703 rexw = P_REXW;
704 #endif
705 #if defined(CONFIG_SOFTMMU)
706 /* mov */
707 tcg_out_modrm(s, 0x8b | rexw, r1, addr_reg);
708
709 /* mov */
710 tcg_out_modrm(s, 0x8b | rexw, r0, addr_reg);
711
712 tcg_out_modrm(s, 0xc1 | rexw, 5, r1); /* shr $x, r1 */
713 tcg_out8(s, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS);
714
715 tcg_out_modrm(s, 0x81 | rexw, 4, r0); /* andl $x, r0 */
716 tcg_out32(s, TARGET_PAGE_MASK | ((1 << s_bits) - 1));
717
718 tcg_out_modrm(s, 0x81, 4, r1); /* andl $x, r1 */
719 tcg_out32(s, (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS);
720
721 /* lea offset(r1, env), r1 */
722 tcg_out_modrm_offset2(s, 0x8d | P_REXW, r1, r1, TCG_AREG0, 0,
723 offsetof(CPUState, tlb_table[mem_index][0].addr_write));
724
725 /* cmp 0(r1), r0 */
726 tcg_out_modrm_offset(s, 0x3b | rexw, r0, r1, 0);
727
728 /* mov */
729 tcg_out_modrm(s, 0x8b | rexw, r0, addr_reg);
730
731 /* je label1 */
732 tcg_out8(s, 0x70 + JCC_JE);
733 label1_ptr = s->code_ptr;
734 s->code_ptr++;
735
736 /* XXX: move that code at the end of the TB */
737 switch(opc) {
738 case 0:
739 /* movzbl */
740 tcg_out_modrm(s, 0xb6 | P_EXT | P_REXB, TCG_REG_RSI, data_reg);
741 break;
742 case 1:
743 /* movzwl */
744 tcg_out_modrm(s, 0xb7 | P_EXT, TCG_REG_RSI, data_reg);
745 break;
746 case 2:
747 /* movl */
748 tcg_out_modrm(s, 0x8b, TCG_REG_RSI, data_reg);
749 break;
750 default:
751 case 3:
752 tcg_out_mov(s, TCG_REG_RSI, data_reg);
753 break;
754 }
755 tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_RDX, mem_index);
756 tcg_out8(s, 0xe8);
757 tcg_out32(s, (tcg_target_long)qemu_st_helpers[s_bits] -
758 (tcg_target_long)s->code_ptr - 4);
759
760 /* jmp label2 */
761 tcg_out8(s, 0xeb);
762 label2_ptr = s->code_ptr;
763 s->code_ptr++;
764
765 /* label1: */
766 *label1_ptr = s->code_ptr - label1_ptr - 1;
767
768 /* add x(r1), r0 */
769 tcg_out_modrm_offset(s, 0x03 | P_REXW, r0, r1, offsetof(CPUTLBEntry, addend) -
770 offsetof(CPUTLBEntry, addr_write));
771 #else
772 r0 = addr_reg;
773 #endif
774
775 #ifdef TARGET_WORDS_BIGENDIAN
776 bswap = 1;
777 #else
778 bswap = 0;
779 #endif
780 switch(opc) {
781 case 0:
782 /* movb */
783 tcg_out_modrm_offset(s, 0x88 | P_REXB, data_reg, r0, 0);
784 break;
785 case 1:
786 if (bswap) {
787 tcg_out_modrm(s, 0x8b, r1, data_reg); /* movl */
788 tcg_out8(s, 0x66); /* rolw $8, %ecx */
789 tcg_out_modrm(s, 0xc1, 0, r1);
790 tcg_out8(s, 8);
791 data_reg = r1;
792 }
793 /* movw */
794 tcg_out8(s, 0x66);
795 tcg_out_modrm_offset(s, 0x89, data_reg, r0, 0);
796 break;
797 case 2:
798 if (bswap) {
799 tcg_out_modrm(s, 0x8b, r1, data_reg); /* movl */
800 /* bswap data_reg */
801 tcg_out_opc(s, (0xc8 + r1) | P_EXT, 0, r1, 0);
802 data_reg = r1;
803 }
804 /* movl */
805 tcg_out_modrm_offset(s, 0x89, data_reg, r0, 0);
806 break;
807 case 3:
808 if (bswap) {
809 tcg_out_mov(s, r1, data_reg);
810 /* bswap data_reg */
811 tcg_out_opc(s, (0xc8 + r1) | P_EXT | P_REXW, 0, r1, 0);
812 data_reg = r1;
813 }
814 /* movq */
815 tcg_out_modrm_offset(s, 0x89 | P_REXW, data_reg, r0, 0);
816 break;
817 default:
818 tcg_abort();
819 }
820
821 #if defined(CONFIG_SOFTMMU)
822 /* label2: */
823 *label2_ptr = s->code_ptr - label2_ptr - 1;
824 #endif
825 }
826
827 static inline void tcg_out_op(TCGContext *s, int opc, const TCGArg *args,
828 const int *const_args)
829 {
830 int c;
831
832 switch(opc) {
833 case INDEX_op_exit_tb:
834 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_RAX, args[0]);
835 tcg_out8(s, 0xe9); /* jmp tb_ret_addr */
836 tcg_out32(s, tb_ret_addr - s->code_ptr - 4);
837 break;
838 case INDEX_op_goto_tb:
839 if (s->tb_jmp_offset) {
840 /* direct jump method */
841 tcg_out8(s, 0xe9); /* jmp im */
842 s->tb_jmp_offset[args[0]] = s->code_ptr - s->code_buf;
843 tcg_out32(s, 0);
844 } else {
845 /* indirect jump method */
846 /* jmp Ev */
847 tcg_out_modrm_offset(s, 0xff, 4, -1,
848 (tcg_target_long)(s->tb_next +
849 args[0]));
850 }
851 s->tb_next_offset[args[0]] = s->code_ptr - s->code_buf;
852 break;
853 case INDEX_op_call:
854 if (const_args[0]) {
855 tcg_out8(s, 0xe8);
856 tcg_out32(s, args[0] - (tcg_target_long)s->code_ptr - 4);
857 } else {
858 tcg_out_modrm(s, 0xff, 2, args[0]);
859 }
860 break;
861 case INDEX_op_jmp:
862 if (const_args[0]) {
863 tcg_out8(s, 0xe9);
864 tcg_out32(s, args[0] - (tcg_target_long)s->code_ptr - 4);
865 } else {
866 tcg_out_modrm(s, 0xff, 4, args[0]);
867 }
868 break;
869 case INDEX_op_br:
870 tcg_out_jxx(s, JCC_JMP, args[0]);
871 break;
872 case INDEX_op_movi_i32:
873 tcg_out_movi(s, TCG_TYPE_I32, args[0], (uint32_t)args[1]);
874 break;
875 case INDEX_op_movi_i64:
876 tcg_out_movi(s, TCG_TYPE_I64, args[0], args[1]);
877 break;
878 case INDEX_op_ld8u_i32:
879 case INDEX_op_ld8u_i64:
880 /* movzbl */
881 tcg_out_modrm_offset(s, 0xb6 | P_EXT, args[0], args[1], args[2]);
882 break;
883 case INDEX_op_ld8s_i32:
884 /* movsbl */
885 tcg_out_modrm_offset(s, 0xbe | P_EXT, args[0], args[1], args[2]);
886 break;
887 case INDEX_op_ld8s_i64:
888 /* movsbq */
889 tcg_out_modrm_offset(s, 0xbe | P_EXT | P_REXW, args[0], args[1], args[2]);
890 break;
891 case INDEX_op_ld16u_i32:
892 case INDEX_op_ld16u_i64:
893 /* movzwl */
894 tcg_out_modrm_offset(s, 0xb7 | P_EXT, args[0], args[1], args[2]);
895 break;
896 case INDEX_op_ld16s_i32:
897 /* movswl */
898 tcg_out_modrm_offset(s, 0xbf | P_EXT, args[0], args[1], args[2]);
899 break;
900 case INDEX_op_ld16s_i64:
901 /* movswq */
902 tcg_out_modrm_offset(s, 0xbf | P_EXT | P_REXW, args[0], args[1], args[2]);
903 break;
904 case INDEX_op_ld_i32:
905 case INDEX_op_ld32u_i64:
906 /* movl */
907 tcg_out_modrm_offset(s, 0x8b, args[0], args[1], args[2]);
908 break;
909 case INDEX_op_ld32s_i64:
910 /* movslq */
911 tcg_out_modrm_offset(s, 0x63 | P_REXW, args[0], args[1], args[2]);
912 break;
913 case INDEX_op_ld_i64:
914 /* movq */
915 tcg_out_modrm_offset(s, 0x8b | P_REXW, args[0], args[1], args[2]);
916 break;
917
918 case INDEX_op_st8_i32:
919 case INDEX_op_st8_i64:
920 /* movb */
921 tcg_out_modrm_offset(s, 0x88 | P_REXB, args[0], args[1], args[2]);
922 break;
923 case INDEX_op_st16_i32:
924 case INDEX_op_st16_i64:
925 /* movw */
926 tcg_out8(s, 0x66);
927 tcg_out_modrm_offset(s, 0x89, args[0], args[1], args[2]);
928 break;
929 case INDEX_op_st_i32:
930 case INDEX_op_st32_i64:
931 /* movl */
932 tcg_out_modrm_offset(s, 0x89, args[0], args[1], args[2]);
933 break;
934 case INDEX_op_st_i64:
935 /* movq */
936 tcg_out_modrm_offset(s, 0x89 | P_REXW, args[0], args[1], args[2]);
937 break;
938
939 case INDEX_op_sub_i32:
940 c = ARITH_SUB;
941 goto gen_arith32;
942 case INDEX_op_and_i32:
943 c = ARITH_AND;
944 goto gen_arith32;
945 case INDEX_op_or_i32:
946 c = ARITH_OR;
947 goto gen_arith32;
948 case INDEX_op_xor_i32:
949 c = ARITH_XOR;
950 goto gen_arith32;
951 case INDEX_op_add_i32:
952 c = ARITH_ADD;
953 gen_arith32:
954 if (const_args[2]) {
955 tgen_arithi32(s, c, args[0], args[2]);
956 } else {
957 tcg_out_modrm(s, 0x01 | (c << 3), args[2], args[0]);
958 }
959 break;
960
961 case INDEX_op_sub_i64:
962 c = ARITH_SUB;
963 goto gen_arith64;
964 case INDEX_op_and_i64:
965 c = ARITH_AND;
966 goto gen_arith64;
967 case INDEX_op_or_i64:
968 c = ARITH_OR;
969 goto gen_arith64;
970 case INDEX_op_xor_i64:
971 c = ARITH_XOR;
972 goto gen_arith64;
973 case INDEX_op_add_i64:
974 c = ARITH_ADD;
975 gen_arith64:
976 if (const_args[2]) {
977 tgen_arithi64(s, c, args[0], args[2]);
978 } else {
979 tcg_out_modrm(s, 0x01 | (c << 3) | P_REXW, args[2], args[0]);
980 }
981 break;
982
983 case INDEX_op_mul_i32:
984 if (const_args[2]) {
985 int32_t val;
986 val = args[2];
987 if (val == (int8_t)val) {
988 tcg_out_modrm(s, 0x6b, args[0], args[0]);
989 tcg_out8(s, val);
990 } else {
991 tcg_out_modrm(s, 0x69, args[0], args[0]);
992 tcg_out32(s, val);
993 }
994 } else {
995 tcg_out_modrm(s, 0xaf | P_EXT, args[0], args[2]);
996 }
997 break;
998 case INDEX_op_mul_i64:
999 if (const_args[2]) {
1000 int32_t val;
1001 val = args[2];
1002 if (val == (int8_t)val) {
1003 tcg_out_modrm(s, 0x6b | P_REXW, args[0], args[0]);
1004 tcg_out8(s, val);
1005 } else {
1006 tcg_out_modrm(s, 0x69 | P_REXW, args[0], args[0]);
1007 tcg_out32(s, val);
1008 }
1009 } else {
1010 tcg_out_modrm(s, 0xaf | P_EXT | P_REXW, args[0], args[2]);
1011 }
1012 break;
1013 case INDEX_op_div2_i32:
1014 tcg_out_modrm(s, 0xf7, 7, args[4]);
1015 break;
1016 case INDEX_op_divu2_i32:
1017 tcg_out_modrm(s, 0xf7, 6, args[4]);
1018 break;
1019 case INDEX_op_div2_i64:
1020 tcg_out_modrm(s, 0xf7 | P_REXW, 7, args[4]);
1021 break;
1022 case INDEX_op_divu2_i64:
1023 tcg_out_modrm(s, 0xf7 | P_REXW, 6, args[4]);
1024 break;
1025
1026 case INDEX_op_shl_i32:
1027 c = SHIFT_SHL;
1028 gen_shift32:
1029 if (const_args[2]) {
1030 if (args[2] == 1) {
1031 tcg_out_modrm(s, 0xd1, c, args[0]);
1032 } else {
1033 tcg_out_modrm(s, 0xc1, c, args[0]);
1034 tcg_out8(s, args[2]);
1035 }
1036 } else {
1037 tcg_out_modrm(s, 0xd3, c, args[0]);
1038 }
1039 break;
1040 case INDEX_op_shr_i32:
1041 c = SHIFT_SHR;
1042 goto gen_shift32;
1043 case INDEX_op_sar_i32:
1044 c = SHIFT_SAR;
1045 goto gen_shift32;
1046
1047 case INDEX_op_shl_i64:
1048 c = SHIFT_SHL;
1049 gen_shift64:
1050 if (const_args[2]) {
1051 if (args[2] == 1) {
1052 tcg_out_modrm(s, 0xd1 | P_REXW, c, args[0]);
1053 } else {
1054 tcg_out_modrm(s, 0xc1 | P_REXW, c, args[0]);
1055 tcg_out8(s, args[2]);
1056 }
1057 } else {
1058 tcg_out_modrm(s, 0xd3 | P_REXW, c, args[0]);
1059 }
1060 break;
1061 case INDEX_op_shr_i64:
1062 c = SHIFT_SHR;
1063 goto gen_shift64;
1064 case INDEX_op_sar_i64:
1065 c = SHIFT_SAR;
1066 goto gen_shift64;
1067
1068 case INDEX_op_brcond_i32:
1069 tcg_out_brcond(s, args[2], args[0], args[1], const_args[1],
1070 args[3], 0);
1071 break;
1072 case INDEX_op_brcond_i64:
1073 tcg_out_brcond(s, args[2], args[0], args[1], const_args[1],
1074 args[3], P_REXW);
1075 break;
1076
1077 case INDEX_op_bswap_i32:
1078 tcg_out_opc(s, (0xc8 + (args[0] & 7)) | P_EXT, 0, args[0], 0);
1079 break;
1080 case INDEX_op_bswap_i64:
1081 tcg_out_opc(s, (0xc8 + (args[0] & 7)) | P_EXT | P_REXW, 0, args[0], 0);
1082 break;
1083
1084 case INDEX_op_neg_i32:
1085 tcg_out_modrm(s, 0xf7, 3, args[0]);
1086 break;
1087 case INDEX_op_neg_i64:
1088 tcg_out_modrm(s, 0xf7 | P_REXW, 3, args[0]);
1089 break;
1090
1091 case INDEX_op_ext8s_i32:
1092 tcg_out_modrm(s, 0xbe | P_EXT | P_REXB, args[0], args[1]);
1093 break;
1094 case INDEX_op_ext16s_i32:
1095 tcg_out_modrm(s, 0xbf | P_EXT, args[0], args[1]);
1096 break;
1097 case INDEX_op_ext8s_i64:
1098 tcg_out_modrm(s, 0xbe | P_EXT | P_REXW, args[0], args[1]);
1099 break;
1100 case INDEX_op_ext16s_i64:
1101 tcg_out_modrm(s, 0xbf | P_EXT | P_REXW, args[0], args[1]);
1102 break;
1103 case INDEX_op_ext32s_i64:
1104 tcg_out_modrm(s, 0x63 | P_REXW, args[0], args[1]);
1105 break;
1106
1107 case INDEX_op_qemu_ld8u:
1108 tcg_out_qemu_ld(s, args, 0);
1109 break;
1110 case INDEX_op_qemu_ld8s:
1111 tcg_out_qemu_ld(s, args, 0 | 4);
1112 break;
1113 case INDEX_op_qemu_ld16u:
1114 tcg_out_qemu_ld(s, args, 1);
1115 break;
1116 case INDEX_op_qemu_ld16s:
1117 tcg_out_qemu_ld(s, args, 1 | 4);
1118 break;
1119 case INDEX_op_qemu_ld32u:
1120 tcg_out_qemu_ld(s, args, 2);
1121 break;
1122 case INDEX_op_qemu_ld32s:
1123 tcg_out_qemu_ld(s, args, 2 | 4);
1124 break;
1125 case INDEX_op_qemu_ld64:
1126 tcg_out_qemu_ld(s, args, 3);
1127 break;
1128
1129 case INDEX_op_qemu_st8:
1130 tcg_out_qemu_st(s, args, 0);
1131 break;
1132 case INDEX_op_qemu_st16:
1133 tcg_out_qemu_st(s, args, 1);
1134 break;
1135 case INDEX_op_qemu_st32:
1136 tcg_out_qemu_st(s, args, 2);
1137 break;
1138 case INDEX_op_qemu_st64:
1139 tcg_out_qemu_st(s, args, 3);
1140 break;
1141
1142 default:
1143 tcg_abort();
1144 }
1145 }
1146
1147 static int tcg_target_callee_save_regs[] = {
1148 TCG_REG_RBP,
1149 TCG_REG_RBX,
1150 TCG_REG_R12,
1151 TCG_REG_R13,
1152 /* TCG_REG_R14, */ /* currently used for the global env, so no
1153 need to save */
1154 TCG_REG_R15,
1155 };
1156
1157 static inline void tcg_out_push(TCGContext *s, int reg)
1158 {
1159 tcg_out_opc(s, (0x50 + (reg & 7)), 0, reg, 0);
1160 }
1161
1162 static inline void tcg_out_pop(TCGContext *s, int reg)
1163 {
1164 tcg_out_opc(s, (0x58 + (reg & 7)), 0, reg, 0);
1165 }
1166
1167 /* Generate global QEMU prologue and epilogue code */
1168 void tcg_target_qemu_prologue(TCGContext *s)
1169 {
1170 int i, frame_size, push_size, stack_addend;
1171
1172 /* TB prologue */
1173 /* save all callee saved registers */
1174 for(i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) {
1175 tcg_out_push(s, tcg_target_callee_save_regs[i]);
1176
1177 }
1178 /* reserve some stack space */
1179 push_size = 8 + ARRAY_SIZE(tcg_target_callee_save_regs) * 8;
1180 frame_size = push_size + TCG_STATIC_CALL_ARGS_SIZE;
1181 frame_size = (frame_size + TCG_TARGET_STACK_ALIGN - 1) &
1182 ~(TCG_TARGET_STACK_ALIGN - 1);
1183 stack_addend = frame_size - push_size;
1184 tcg_out_addi(s, TCG_REG_RSP, -stack_addend);
1185
1186 tcg_out_modrm(s, 0xff, 4, TCG_REG_RDI); /* jmp *%rdi */
1187
1188 /* TB epilogue */
1189 tb_ret_addr = s->code_ptr;
1190 tcg_out_addi(s, TCG_REG_RSP, stack_addend);
1191 for(i = ARRAY_SIZE(tcg_target_callee_save_regs) - 1; i >= 0; i--) {
1192 tcg_out_pop(s, tcg_target_callee_save_regs[i]);
1193 }
1194 tcg_out8(s, 0xc3); /* ret */
1195 }
1196
1197 static const TCGTargetOpDef x86_64_op_defs[] = {
1198 { INDEX_op_exit_tb, { } },
1199 { INDEX_op_goto_tb, { } },
1200 { INDEX_op_call, { "ri" } }, /* XXX: might need a specific constant constraint */
1201 { INDEX_op_jmp, { "ri" } }, /* XXX: might need a specific constant constraint */
1202 { INDEX_op_br, { } },
1203
1204 { INDEX_op_mov_i32, { "r", "r" } },
1205 { INDEX_op_movi_i32, { "r" } },
1206 { INDEX_op_ld8u_i32, { "r", "r" } },
1207 { INDEX_op_ld8s_i32, { "r", "r" } },
1208 { INDEX_op_ld16u_i32, { "r", "r" } },
1209 { INDEX_op_ld16s_i32, { "r", "r" } },
1210 { INDEX_op_ld_i32, { "r", "r" } },
1211 { INDEX_op_st8_i32, { "r", "r" } },
1212 { INDEX_op_st16_i32, { "r", "r" } },
1213 { INDEX_op_st_i32, { "r", "r" } },
1214
1215 { INDEX_op_add_i32, { "r", "0", "ri" } },
1216 { INDEX_op_mul_i32, { "r", "0", "ri" } },
1217 { INDEX_op_div2_i32, { "a", "d", "0", "1", "r" } },
1218 { INDEX_op_divu2_i32, { "a", "d", "0", "1", "r" } },
1219 { INDEX_op_sub_i32, { "r", "0", "ri" } },
1220 { INDEX_op_and_i32, { "r", "0", "ri" } },
1221 { INDEX_op_or_i32, { "r", "0", "ri" } },
1222 { INDEX_op_xor_i32, { "r", "0", "ri" } },
1223
1224 { INDEX_op_shl_i32, { "r", "0", "ci" } },
1225 { INDEX_op_shr_i32, { "r", "0", "ci" } },
1226 { INDEX_op_sar_i32, { "r", "0", "ci" } },
1227
1228 { INDEX_op_brcond_i32, { "r", "ri" } },
1229
1230 { INDEX_op_mov_i64, { "r", "r" } },
1231 { INDEX_op_movi_i64, { "r" } },
1232 { INDEX_op_ld8u_i64, { "r", "r" } },
1233 { INDEX_op_ld8s_i64, { "r", "r" } },
1234 { INDEX_op_ld16u_i64, { "r", "r" } },
1235 { INDEX_op_ld16s_i64, { "r", "r" } },
1236 { INDEX_op_ld32u_i64, { "r", "r" } },
1237 { INDEX_op_ld32s_i64, { "r", "r" } },
1238 { INDEX_op_ld_i64, { "r", "r" } },
1239 { INDEX_op_st8_i64, { "r", "r" } },
1240 { INDEX_op_st16_i64, { "r", "r" } },
1241 { INDEX_op_st32_i64, { "r", "r" } },
1242 { INDEX_op_st_i64, { "r", "r" } },
1243
1244 { INDEX_op_add_i64, { "r", "0", "re" } },
1245 { INDEX_op_mul_i64, { "r", "0", "re" } },
1246 { INDEX_op_div2_i64, { "a", "d", "0", "1", "r" } },
1247 { INDEX_op_divu2_i64, { "a", "d", "0", "1", "r" } },
1248 { INDEX_op_sub_i64, { "r", "0", "re" } },
1249 { INDEX_op_and_i64, { "r", "0", "reZ" } },
1250 { INDEX_op_or_i64, { "r", "0", "re" } },
1251 { INDEX_op_xor_i64, { "r", "0", "re" } },
1252
1253 { INDEX_op_shl_i64, { "r", "0", "ci" } },
1254 { INDEX_op_shr_i64, { "r", "0", "ci" } },
1255 { INDEX_op_sar_i64, { "r", "0", "ci" } },
1256
1257 { INDEX_op_brcond_i64, { "r", "re" } },
1258
1259 { INDEX_op_bswap_i32, { "r", "0" } },
1260 { INDEX_op_bswap_i64, { "r", "0" } },
1261
1262 { INDEX_op_neg_i32, { "r", "0" } },
1263 { INDEX_op_neg_i64, { "r", "0" } },
1264
1265 { INDEX_op_ext8s_i32, { "r", "r"} },
1266 { INDEX_op_ext16s_i32, { "r", "r"} },
1267 { INDEX_op_ext8s_i64, { "r", "r"} },
1268 { INDEX_op_ext16s_i64, { "r", "r"} },
1269 { INDEX_op_ext32s_i64, { "r", "r"} },
1270
1271 { INDEX_op_qemu_ld8u, { "r", "L" } },
1272 { INDEX_op_qemu_ld8s, { "r", "L" } },
1273 { INDEX_op_qemu_ld16u, { "r", "L" } },
1274 { INDEX_op_qemu_ld16s, { "r", "L" } },
1275 { INDEX_op_qemu_ld32u, { "r", "L" } },
1276 { INDEX_op_qemu_ld32s, { "r", "L" } },
1277 { INDEX_op_qemu_ld64, { "r", "L" } },
1278
1279 { INDEX_op_qemu_st8, { "L", "L" } },
1280 { INDEX_op_qemu_st16, { "L", "L" } },
1281 { INDEX_op_qemu_st32, { "L", "L" } },
1282 { INDEX_op_qemu_st64, { "L", "L", "L" } },
1283
1284 { -1 },
1285 };
1286
1287 void tcg_target_init(TCGContext *s)
1288 {
1289 /* fail safe */
1290 if ((1 << CPU_TLB_ENTRY_BITS) != sizeof(CPUTLBEntry))
1291 tcg_abort();
1292
1293 tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffff);
1294 tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I64], 0, 0xffff);
1295 tcg_regset_set32(tcg_target_call_clobber_regs, 0,
1296 (1 << TCG_REG_RDI) |
1297 (1 << TCG_REG_RSI) |
1298 (1 << TCG_REG_RDX) |
1299 (1 << TCG_REG_RCX) |
1300 (1 << TCG_REG_R8) |
1301 (1 << TCG_REG_R9) |
1302 (1 << TCG_REG_RAX) |
1303 (1 << TCG_REG_R10) |
1304 (1 << TCG_REG_R11));
1305
1306 tcg_regset_clear(s->reserved_regs);
1307 tcg_regset_set_reg(s->reserved_regs, TCG_REG_RSP);
1308
1309 tcg_add_target_add_op_defs(x86_64_op_defs);
1310 }
Patches shipped by Fedora