hw/r2d.c

   1 /*
   2  * Renesas SH7751R R2D-PLUS emulation
   3  *
   4  * Copyright (c) 2007 Magnus Damm
   5  * Copyright (c) 2008 Paul Mundt
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  */
  25
  26 #include "hw.h"
  27 #include "sh.h"
  28 #include "sysemu.h"
  29 #include "boards.h"
  30
  31 #define SDRAM_BASE 0x0c000000 /* Physical location of SDRAM: Area 3 */
  32 #define SDRAM_SIZE 0x04000000
  33
  34 #define PA_POWOFF       0x30
  35 #define PA_VERREG       0x32
  36 #define PA_OUTPORT      0x36
  37
  38 typedef struct {
  39     target_phys_addr_t base;
  40
  41     uint16_t bcr;
  42     uint16_t irlmon;
  43     uint16_t cfctl;
  44     uint16_t cfpow;
  45     uint16_t dispctl;
  46     uint16_t sdmpow;
  47     uint16_t rtcce;
  48     uint16_t pcicd;
  49     uint16_t voyagerrts;
  50     uint16_t cfrst;
  51     uint16_t admrts;
  52     uint16_t extrst;
  53     uint16_t cfcdintclr;
  54     uint16_t keyctlclr;
  55     uint16_t pad0;
  56     uint16_t pad1;
  57     uint16_t powoff;
  58     uint16_t verreg;
  59     uint16_t inport;
  60     uint16_t outport;
  61     uint16_t bverreg;
  62 } r2d_fpga_t;
  63
  64 static uint32_t r2d_fpga_read(void *opaque, target_phys_addr_t addr)
  65 {
  66     r2d_fpga_t *s = opaque;
  67
  68     addr -= s->base;
  69
  70     switch (addr) {
  71     case PA_OUTPORT:
  72         return s->outport;
  73     case PA_POWOFF:
  74         return s->powoff;
  75     case PA_VERREG:
  76         return 0x10;
  77     }
  78
  79     return 0;
  80 }
  81
  82 static void
  83 r2d_fpga_write(void *opaque, target_phys_addr_t addr, uint32_t value)
  84 {
  85     r2d_fpga_t *s = opaque;
  86
  87     addr -= s->base;
  88
  89     switch (addr) {
  90     case PA_OUTPORT:
  91         s->outport = value;
  92         break;
  93     case PA_POWOFF:
  94         s->powoff = value;
  95         break;
  96     case PA_VERREG:
  97         /* Discard writes */
  98         break;
  99     }
 100 }
 101
 102 static CPUReadMemoryFunc *r2d_fpga_readfn[] = {
 103     r2d_fpga_read,
 104     r2d_fpga_read,
 105     NULL,
 106 };
 107
 108 static CPUWriteMemoryFunc *r2d_fpga_writefn[] = {
 109     r2d_fpga_write,
 110     r2d_fpga_write,
 111     NULL,
 112 };
 113
 114 static void r2d_fpga_init(target_phys_addr_t base)
 115 {
 116     int iomemtype;
 117     r2d_fpga_t *s;
 118
 119     s = qemu_mallocz(sizeof(r2d_fpga_t));
 120     if (!s)
 121         return;
 122
 123     s->base = base;
 124     iomemtype = cpu_register_io_memory(0, r2d_fpga_readfn,
 125                                        r2d_fpga_writefn, s);
 126     cpu_register_physical_memory(base, 0x40, iomemtype);
 127 }
 128
 129 static void r2d_init(ram_addr_t ram_size, int vga_ram_size,
 130               const char *boot_device, DisplayState * ds,
 131               const char *kernel_filename, const char *kernel_cmdline,
 132               const char *initrd_filename, const char *cpu_model)
 133 {
 134     CPUState *env;
 135     struct SH7750State *s;
 136
 137     if (!cpu_model)
 138         cpu_model = "SH7751R";
 139
 140     env = cpu_init(cpu_model);
 141     if (!env) {
 142         fprintf(stderr, "Unable to find CPU definition\n");
 143         exit(1);
 144     }
 145
 146     /* Allocate memory space */
 147     cpu_register_physical_memory(SDRAM_BASE, SDRAM_SIZE, 0);
 148     /* Register peripherals */
 149     r2d_fpga_init(0x04000000);
 150     s = sh7750_init(env);
 151     /* Todo: register on board registers */
 152     {
 153       int kernel_size;
 154
 155       kernel_size = load_image(kernel_filename, phys_ram_base);
 156
 157       if (kernel_size < 0) {
 158         fprintf(stderr, "qemu: could not load kernel '%s'\n", kernel_filename);
 159         exit(1);
 160       }
 161
 162       env->pc = SDRAM_BASE | 0xa0000000; /* Start from P2 area */
 163     }
 164 }
 165
 166 QEMUMachine r2d_machine = {
 167     .name = "r2d",
 168     .desc = "r2d-plus board",
 169     .init = r2d_init,
 170     .ram_require = SDRAM_SIZE | RAMSIZE_FIXED,
 171     .max_cpus = 1,
 172 };