hw/musicpal.c

   1 /*
   2  * Marvell MV88W8618 / Freecom MusicPal emulation.
   3  *
   4  * Copyright (c) 2008 Jan Kiszka
   5  *
   6  * This code is licenced under the GNU GPL v2.
   7  */
   8
   9 #include "sysbus.h"
  10 #include "arm-misc.h"
  11 #include "devices.h"
  12 #include "net.h"
  13 #include "sysemu.h"
  14 #include "boards.h"
  15 #include "pc.h"
  16 #include "qemu-timer.h"
  17 #include "block.h"
  18 #include "flash.h"
  19 #include "console.h"
  20 #include "audio/audio.h"
  21 #include "i2c.h"
  22
  23 #define MP_MISC_BASE            0x80002000
  24 #define MP_MISC_SIZE            0x00001000
  25
  26 #define MP_ETH_BASE             0x80008000
  27 #define MP_ETH_SIZE             0x00001000
  28
  29 #define MP_WLAN_BASE            0x8000C000
  30 #define MP_WLAN_SIZE            0x00000800
  31
  32 #define MP_UART1_BASE           0x8000C840
  33 #define MP_UART2_BASE           0x8000C940
  34
  35 #define MP_GPIO_BASE            0x8000D000
  36 #define MP_GPIO_SIZE            0x00001000
  37
  38 #define MP_FLASHCFG_BASE        0x90006000
  39 #define MP_FLASHCFG_SIZE        0x00001000
  40
  41 #define MP_AUDIO_BASE           0x90007000
  42 #define MP_AUDIO_SIZE           0x00001000
  43
  44 #define MP_PIC_BASE             0x90008000
  45 #define MP_PIC_SIZE             0x00001000
  46
  47 #define MP_PIT_BASE             0x90009000
  48 #define MP_PIT_SIZE             0x00001000
  49
  50 #define MP_LCD_BASE             0x9000c000
  51 #define MP_LCD_SIZE             0x00001000
  52
  53 #define MP_SRAM_BASE            0xC0000000
  54 #define MP_SRAM_SIZE            0x00020000
  55
  56 #define MP_RAM_DEFAULT_SIZE     32*1024*1024
  57 #define MP_FLASH_SIZE_MAX       32*1024*1024
  58
  59 #define MP_TIMER1_IRQ           4
  60 #define MP_TIMER2_IRQ           5
  61 #define MP_TIMER3_IRQ           6
  62 #define MP_TIMER4_IRQ           7
  63 #define MP_EHCI_IRQ             8
  64 #define MP_ETH_IRQ              9
  65 #define MP_UART1_IRQ            11
  66 #define MP_UART2_IRQ            11
  67 #define MP_GPIO_IRQ             12
  68 #define MP_RTC_IRQ              28
  69 #define MP_AUDIO_IRQ            30
  70
  71 static uint32_t gpio_in_state = 0xffffffff;
  72 static uint32_t gpio_isr;
  73 static uint32_t gpio_out_state;
  74 static ram_addr_t sram_off;
  75
  76 typedef enum i2c_state {
  77     STOPPED = 0,
  78     INITIALIZING,
  79     SENDING_BIT7,
  80     SENDING_BIT6,
  81     SENDING_BIT5,
  82     SENDING_BIT4,
  83     SENDING_BIT3,
  84     SENDING_BIT2,
  85     SENDING_BIT1,
  86     SENDING_BIT0,
  87     WAITING_FOR_ACK,
  88     RECEIVING_BIT7,
  89     RECEIVING_BIT6,
  90     RECEIVING_BIT5,
  91     RECEIVING_BIT4,
  92     RECEIVING_BIT3,
  93     RECEIVING_BIT2,
  94     RECEIVING_BIT1,
  95     RECEIVING_BIT0,
  96     SENDING_ACK
  97 } i2c_state;
  98
  99 typedef struct i2c_interface {
 100     i2c_bus *bus;
 101     i2c_state state;
 102     int last_data;
 103     int last_clock;
 104     uint8_t buffer;
 105     int current_addr;
 106 } i2c_interface;
 107
 108 static void i2c_enter_stop(i2c_interface *i2c)
 109 {
 110     if (i2c->current_addr >= 0)
 111         i2c_end_transfer(i2c->bus);
 112     i2c->current_addr = -1;
 113     i2c->state = STOPPED;
 114 }
 115
 116 static void i2c_state_update(i2c_interface *i2c, int data, int clock)
 117 {
 118     if (!i2c)
 119         return;
 120
 121     switch (i2c->state) {
 122     case STOPPED:
 123         if (data == 0 && i2c->last_data == 1 && clock == 1)
 124             i2c->state = INITIALIZING;
 125         break;
 126
 127     case INITIALIZING:
 128         if (clock == 0 && i2c->last_clock == 1 && data == 0)
 129             i2c->state = SENDING_BIT7;
 130         else
 131             i2c_enter_stop(i2c);
 132         break;
 133
 134     case SENDING_BIT7 ... SENDING_BIT0:
 135         if (clock == 0 && i2c->last_clock == 1) {
 136             i2c->buffer = (i2c->buffer << 1) | data;
 137             i2c->state++; /* will end up in WAITING_FOR_ACK */
 138         } else if (data == 1 && i2c->last_data == 0 && clock == 1)
 139             i2c_enter_stop(i2c);
 140         break;
 141
 142     case WAITING_FOR_ACK:
 143         if (clock == 0 && i2c->last_clock == 1) {
 144             if (i2c->current_addr < 0) {
 145                 i2c->current_addr = i2c->buffer;
 146                 i2c_start_transfer(i2c->bus, i2c->current_addr & 0xfe,
 147                                    i2c->buffer & 1);
 148             } else
 149                 i2c_send(i2c->bus, i2c->buffer);
 150             if (i2c->current_addr & 1) {
 151                 i2c->state = RECEIVING_BIT7;
 152                 i2c->buffer = i2c_recv(i2c->bus);
 153             } else
 154                 i2c->state = SENDING_BIT7;
 155         } else if (data == 1 && i2c->last_data == 0 && clock == 1)
 156             i2c_enter_stop(i2c);
 157         break;
 158
 159     case RECEIVING_BIT7 ... RECEIVING_BIT0:
 160         if (clock == 0 && i2c->last_clock == 1) {
 161             i2c->state++; /* will end up in SENDING_ACK */
 162             i2c->buffer <<= 1;
 163         } else if (data == 1 && i2c->last_data == 0 && clock == 1)
 164             i2c_enter_stop(i2c);
 165         break;
 166
 167     case SENDING_ACK:
 168         if (clock == 0 && i2c->last_clock == 1) {
 169             i2c->state = RECEIVING_BIT7;
 170             if (data == 0)
 171                 i2c->buffer = i2c_recv(i2c->bus);
 172             else
 173                 i2c_nack(i2c->bus);
 174         } else if (data == 1 && i2c->last_data == 0 && clock == 1)
 175             i2c_enter_stop(i2c);
 176         break;
 177     }
 178
 179     i2c->last_data = data;
 180     i2c->last_clock = clock;
 181 }
 182
 183 static int i2c_get_data(i2c_interface *i2c)
 184 {
 185     if (!i2c)
 186         return 0;
 187
 188     switch (i2c->state) {
 189     case RECEIVING_BIT7 ... RECEIVING_BIT0:
 190         return (i2c->buffer >> 7);
 191
 192     case WAITING_FOR_ACK:
 193     default:
 194         return 0;
 195     }
 196 }
 197
 198 static i2c_interface *mixer_i2c;
 199
 200 #ifdef HAS_AUDIO
 201
 202 /* Audio register offsets */
 203 #define MP_AUDIO_PLAYBACK_MODE  0x00
 204 #define MP_AUDIO_CLOCK_DIV      0x18
 205 #define MP_AUDIO_IRQ_STATUS     0x20
 206 #define MP_AUDIO_IRQ_ENABLE     0x24
 207 #define MP_AUDIO_TX_START_LO    0x28
 208 #define MP_AUDIO_TX_THRESHOLD   0x2C
 209 #define MP_AUDIO_TX_STATUS      0x38
 210 #define MP_AUDIO_TX_START_HI    0x40
 211
 212 /* Status register and IRQ enable bits */
 213 #define MP_AUDIO_TX_HALF        (1 << 6)
 214 #define MP_AUDIO_TX_FULL        (1 << 7)
 215
 216 /* Playback mode bits */
 217 #define MP_AUDIO_16BIT_SAMPLE   (1 << 0)
 218 #define MP_AUDIO_PLAYBACK_EN    (1 << 7)
 219 #define MP_AUDIO_CLOCK_24MHZ    (1 << 9)
 220 #define MP_AUDIO_MONO           (1 << 14)
 221
 222 /* Wolfson 8750 I2C address */
 223 #define MP_WM_ADDR              0x34
 224
 225 static const char audio_name[] = "mv88w8618";
 226
 227 typedef struct musicpal_audio_state {
 228     qemu_irq irq;
 229     uint32_t playback_mode;
 230     uint32_t status;
 231     uint32_t irq_enable;
 232     unsigned long phys_buf;
 233     uint32_t target_buffer;
 234     unsigned int threshold;
 235     unsigned int play_pos;
 236     unsigned int last_free;
 237     uint32_t clock_div;
 238     DeviceState *wm;
 239 } musicpal_audio_state;
 240
 241 static void audio_callback(void *opaque, int free_out, int free_in)
 242 {
 243     musicpal_audio_state *s = opaque;
 244     int16_t *codec_buffer;
 245     int8_t buf[4096];
 246     int8_t *mem_buffer;
 247     int pos, block_size;
 248
 249     if (!(s->playback_mode & MP_AUDIO_PLAYBACK_EN))
 250         return;
 251
 252     if (s->playback_mode & MP_AUDIO_16BIT_SAMPLE)
 253         free_out <<= 1;
 254
 255     if (!(s->playback_mode & MP_AUDIO_MONO))
 256         free_out <<= 1;
 257
 258     block_size = s->threshold/2;
 259     if (free_out - s->last_free < block_size)
 260         return;
 261
 262     if (block_size > 4096)
 263         return;
 264
 265     cpu_physical_memory_read(s->target_buffer + s->play_pos, (void *)buf,
 266                              block_size);
 267     mem_buffer = buf;
 268     if (s->playback_mode & MP_AUDIO_16BIT_SAMPLE) {
 269         if (s->playback_mode & MP_AUDIO_MONO) {
 270             codec_buffer = wm8750_dac_buffer(s->wm, block_size >> 1);
 271             for (pos = 0; pos < block_size; pos += 2) {
 272                 *codec_buffer++ = *(int16_t *)mem_buffer;
 273                 *codec_buffer++ = *(int16_t *)mem_buffer;
 274                 mem_buffer += 2;
 275             }
 276         } else
 277             memcpy(wm8750_dac_buffer(s->wm, block_size >> 2),
 278                    (uint32_t *)mem_buffer, block_size);
 279     } else {
 280         if (s->playback_mode & MP_AUDIO_MONO) {
 281             codec_buffer = wm8750_dac_buffer(s->wm, block_size);
 282             for (pos = 0; pos < block_size; pos++) {
 283                 *codec_buffer++ = cpu_to_le16(256 * *mem_buffer);
 284                 *codec_buffer++ = cpu_to_le16(256 * *mem_buffer++);
 285             }
 286         } else {
 287             codec_buffer = wm8750_dac_buffer(s->wm, block_size >> 1);
 288             for (pos = 0; pos < block_size; pos += 2) {
 289                 *codec_buffer++ = cpu_to_le16(256 * *mem_buffer++);
 290                 *codec_buffer++ = cpu_to_le16(256 * *mem_buffer++);
 291             }
 292         }
 293     }
 294     wm8750_dac_commit(s->wm);
 295
 296     s->last_free = free_out - block_size;
 297
 298     if (s->play_pos == 0) {
 299         s->status |= MP_AUDIO_TX_HALF;
 300         s->play_pos = block_size;
 301     } else {
 302         s->status |= MP_AUDIO_TX_FULL;
 303         s->play_pos = 0;
 304     }
 305
 306     if (s->status & s->irq_enable)
 307         qemu_irq_raise(s->irq);
 308 }
 309
 310 static void musicpal_audio_clock_update(musicpal_audio_state *s)
 311 {
 312     int rate;
 313
 314     if (s->playback_mode & MP_AUDIO_CLOCK_24MHZ)
 315         rate = 24576000 / 64; /* 24.576MHz */
 316     else
 317         rate = 11289600 / 64; /* 11.2896MHz */
 318
 319     rate /= ((s->clock_div >> 8) & 0xff) + 1;
 320
 321     wm8750_set_bclk_in(s->wm, rate);
 322 }
 323
 324 static uint32_t musicpal_audio_read(void *opaque, target_phys_addr_t offset)
 325 {
 326     musicpal_audio_state *s = opaque;
 327
 328     switch (offset) {
 329     case MP_AUDIO_PLAYBACK_MODE:
 330         return s->playback_mode;
 331
 332     case MP_AUDIO_CLOCK_DIV:
 333         return s->clock_div;
 334
 335     case MP_AUDIO_IRQ_STATUS:
 336         return s->status;
 337
 338     case MP_AUDIO_IRQ_ENABLE:
 339         return s->irq_enable;
 340
 341     case MP_AUDIO_TX_STATUS:
 342         return s->play_pos >> 2;
 343
 344     default:
 345         return 0;
 346     }
 347 }
 348
 349 static void musicpal_audio_write(void *opaque, target_phys_addr_t offset,
 350                                  uint32_t value)
 351 {
 352     musicpal_audio_state *s = opaque;
 353
 354     switch (offset) {
 355     case MP_AUDIO_PLAYBACK_MODE:
 356         if (value & MP_AUDIO_PLAYBACK_EN &&
 357             !(s->playback_mode & MP_AUDIO_PLAYBACK_EN)) {
 358             s->status = 0;
 359             s->last_free = 0;
 360             s->play_pos = 0;
 361         }
 362         s->playback_mode = value;
 363         musicpal_audio_clock_update(s);
 364         break;
 365
 366     case MP_AUDIO_CLOCK_DIV:
 367         s->clock_div = value;
 368         s->last_free = 0;
 369         s->play_pos = 0;
 370         musicpal_audio_clock_update(s);
 371         break;
 372
 373     case MP_AUDIO_IRQ_STATUS:
 374         s->status &= ~value;
 375         break;
 376
 377     case MP_AUDIO_IRQ_ENABLE:
 378         s->irq_enable = value;
 379         if (s->status & s->irq_enable)
 380             qemu_irq_raise(s->irq);
 381         break;
 382
 383     case MP_AUDIO_TX_START_LO:
 384         s->phys_buf = (s->phys_buf & 0xFFFF0000) | (value & 0xFFFF);
 385         s->target_buffer = s->phys_buf;
 386         s->play_pos = 0;
 387         s->last_free = 0;
 388         break;
 389
 390     case MP_AUDIO_TX_THRESHOLD:
 391         s->threshold = (value + 1) * 4;
 392         break;
 393
 394     case MP_AUDIO_TX_START_HI:
 395         s->phys_buf = (s->phys_buf & 0xFFFF) | (value << 16);
 396         s->target_buffer = s->phys_buf;
 397         s->play_pos = 0;
 398         s->last_free = 0;
 399         break;
 400     }
 401 }
 402
 403 static void musicpal_audio_reset(void *opaque)
 404 {
 405     musicpal_audio_state *s = opaque;
 406
 407     s->playback_mode = 0;
 408     s->status = 0;
 409     s->irq_enable = 0;
 410 }
 411
 412 static CPUReadMemoryFunc *musicpal_audio_readfn[] = {
 413     musicpal_audio_read,
 414     musicpal_audio_read,
 415     musicpal_audio_read
 416 };
 417
 418 static CPUWriteMemoryFunc *musicpal_audio_writefn[] = {
 419     musicpal_audio_write,
 420     musicpal_audio_write,
 421     musicpal_audio_write
 422 };
 423
 424 static i2c_interface *musicpal_audio_init(qemu_irq irq)
 425 {
 426     musicpal_audio_state *s;
 427     i2c_interface *i2c;
 428     int iomemtype;
 429
 430     s = qemu_mallocz(sizeof(musicpal_audio_state));
 431     s->irq = irq;
 432
 433     i2c = qemu_mallocz(sizeof(i2c_interface));
 434     i2c->bus = i2c_init_bus(NULL, "i2c");
 435     i2c->current_addr = -1;
 436
 437     s->wm = i2c_create_slave(i2c->bus, "wm8750", MP_WM_ADDR);
 438     wm8750_data_req_set(s->wm, audio_callback, s);
 439
 440     iomemtype = cpu_register_io_memory(musicpal_audio_readfn,
 441                        musicpal_audio_writefn, s);
 442     cpu_register_physical_memory(MP_AUDIO_BASE, MP_AUDIO_SIZE, iomemtype);
 443
 444     qemu_register_reset(musicpal_audio_reset, 0, s);
 445
 446     return i2c;
 447 }
 448 #else  /* !HAS_AUDIO */
 449 static i2c_interface *musicpal_audio_init(qemu_irq irq)
 450 {
 451     return NULL;
 452 }
 453 #endif /* !HAS_AUDIO */
 454
 455 /* Ethernet register offsets */
 456 #define MP_ETH_SMIR             0x010
 457 #define MP_ETH_PCXR             0x408
 458 #define MP_ETH_SDCMR            0x448
 459 #define MP_ETH_ICR              0x450
 460 #define MP_ETH_IMR              0x458
 461 #define MP_ETH_FRDP0            0x480
 462 #define MP_ETH_FRDP1            0x484
 463 #define MP_ETH_FRDP2            0x488
 464 #define MP_ETH_FRDP3            0x48C
 465 #define MP_ETH_CRDP0            0x4A0
 466 #define MP_ETH_CRDP1            0x4A4
 467 #define MP_ETH_CRDP2            0x4A8
 468 #define MP_ETH_CRDP3            0x4AC
 469 #define MP_ETH_CTDP0            0x4E0
 470 #define MP_ETH_CTDP1            0x4E4
 471 #define MP_ETH_CTDP2            0x4E8
 472 #define MP_ETH_CTDP3            0x4EC
 473
 474 /* MII PHY access */
 475 #define MP_ETH_SMIR_DATA        0x0000FFFF
 476 #define MP_ETH_SMIR_ADDR        0x03FF0000
 477 #define MP_ETH_SMIR_OPCODE      (1 << 26) /* Read value */
 478 #define MP_ETH_SMIR_RDVALID     (1 << 27)
 479
 480 /* PHY registers */
 481 #define MP_ETH_PHY1_BMSR        0x00210000
 482 #define MP_ETH_PHY1_PHYSID1     0x00410000
 483 #define MP_ETH_PHY1_PHYSID2     0x00610000
 484
 485 #define MP_PHY_BMSR_LINK        0x0004
 486 #define MP_PHY_BMSR_AUTONEG     0x0008
 487
 488 #define MP_PHY_88E3015          0x01410E20
 489
 490 /* TX descriptor status */
 491 #define MP_ETH_TX_OWN           (1 << 31)
 492
 493 /* RX descriptor status */
 494 #define MP_ETH_RX_OWN           (1 << 31)
 495
 496 /* Interrupt cause/mask bits */
 497 #define MP_ETH_IRQ_RX_BIT       0
 498 #define MP_ETH_IRQ_RX           (1 << MP_ETH_IRQ_RX_BIT)
 499 #define MP_ETH_IRQ_TXHI_BIT     2
 500 #define MP_ETH_IRQ_TXLO_BIT     3
 501
 502 /* Port config bits */
 503 #define MP_ETH_PCXR_2BSM_BIT    28 /* 2-byte incoming suffix */
 504
 505 /* SDMA command bits */
 506 #define MP_ETH_CMD_TXHI         (1 << 23)
 507 #define MP_ETH_CMD_TXLO         (1 << 22)
 508
 509 typedef struct mv88w8618_tx_desc {
 510     uint32_t cmdstat;
 511     uint16_t res;
 512     uint16_t bytes;
 513     uint32_t buffer;
 514     uint32_t next;
 515 } mv88w8618_tx_desc;
 516
 517 typedef struct mv88w8618_rx_desc {
 518     uint32_t cmdstat;
 519     uint16_t bytes;
 520     uint16_t buffer_size;
 521     uint32_t buffer;
 522     uint32_t next;
 523 } mv88w8618_rx_desc;
 524
 525 typedef struct mv88w8618_eth_state {
 526     SysBusDevice busdev;
 527     qemu_irq irq;
 528     uint32_t smir;
 529     uint32_t icr;
 530     uint32_t imr;
 531     int mmio_index;
 532     int vlan_header;
 533     uint32_t tx_queue[2];
 534     uint32_t rx_queue[4];
 535     uint32_t frx_queue[4];
 536     uint32_t cur_rx[4];
 537     VLANClientState *vc;
 538 } mv88w8618_eth_state;
 539
 540 static void eth_rx_desc_put(uint32_t addr, mv88w8618_rx_desc *desc)
 541 {
 542     cpu_to_le32s(&desc->cmdstat);
 543     cpu_to_le16s(&desc->bytes);
 544     cpu_to_le16s(&desc->buffer_size);
 545     cpu_to_le32s(&desc->buffer);
 546     cpu_to_le32s(&desc->next);
 547     cpu_physical_memory_write(addr, (void *)desc, sizeof(*desc));
 548 }
 549
 550 static void eth_rx_desc_get(uint32_t addr, mv88w8618_rx_desc *desc)
 551 {
 552     cpu_physical_memory_read(addr, (void *)desc, sizeof(*desc));
 553     le32_to_cpus(&desc->cmdstat);
 554     le16_to_cpus(&desc->bytes);
 555     le16_to_cpus(&desc->buffer_size);
 556     le32_to_cpus(&desc->buffer);
 557     le32_to_cpus(&desc->next);
 558 }
 559
 560 static int eth_can_receive(VLANClientState *vc)
 561 {
 562     return 1;
 563 }
 564
 565 static ssize_t eth_receive(VLANClientState *vc, const uint8_t *buf, size_t size)
 566 {
 567     mv88w8618_eth_state *s = vc->opaque;
 568     uint32_t desc_addr;
 569     mv88w8618_rx_desc desc;
 570     int i;
 571
 572     for (i = 0; i < 4; i++) {
 573         desc_addr = s->cur_rx[i];
 574         if (!desc_addr)
 575             continue;
 576         do {
 577             eth_rx_desc_get(desc_addr, &desc);
 578             if ((desc.cmdstat & MP_ETH_RX_OWN) && desc.buffer_size >= size) {
 579                 cpu_physical_memory_write(desc.buffer + s->vlan_header,
 580                                           buf, size);
 581                 desc.bytes = size + s->vlan_header;
 582                 desc.cmdstat &= ~MP_ETH_RX_OWN;
 583                 s->cur_rx[i] = desc.next;
 584
 585                 s->icr |= MP_ETH_IRQ_RX;
 586                 if (s->icr & s->imr)
 587                     qemu_irq_raise(s->irq);
 588                 eth_rx_desc_put(desc_addr, &desc);
 589                 return size;
 590             }
 591             desc_addr = desc.next;
 592         } while (desc_addr != s->rx_queue[i]);
 593     }
 594     return size;
 595 }
 596
 597 static void eth_tx_desc_put(uint32_t addr, mv88w8618_tx_desc *desc)
 598 {
 599     cpu_to_le32s(&desc->cmdstat);
 600     cpu_to_le16s(&desc->res);
 601     cpu_to_le16s(&desc->bytes);
 602     cpu_to_le32s(&desc->buffer);
 603     cpu_to_le32s(&desc->next);
 604     cpu_physical_memory_write(addr, (void *)desc, sizeof(*desc));
 605 }
 606
 607 static void eth_tx_desc_get(uint32_t addr, mv88w8618_tx_desc *desc)
 608 {
 609     cpu_physical_memory_read(addr, (void *)desc, sizeof(*desc));
 610     le32_to_cpus(&desc->cmdstat);
 611     le16_to_cpus(&desc->res);
 612     le16_to_cpus(&desc->bytes);
 613     le32_to_cpus(&desc->buffer);
 614     le32_to_cpus(&desc->next);
 615 }
 616
 617 static void eth_send(mv88w8618_eth_state *s, int queue_index)
 618 {
 619     uint32_t desc_addr = s->tx_queue[queue_index];
 620     mv88w8618_tx_desc desc;
 621     uint8_t buf[2048];
 622     int len;
 623
 624
 625     do {
 626         eth_tx_desc_get(desc_addr, &desc);
 627         if (desc.cmdstat & MP_ETH_TX_OWN) {
 628             len = desc.bytes;
 629             if (len < 2048) {
 630                 cpu_physical_memory_read(desc.buffer, buf, len);
 631                 qemu_send_packet(s->vc, buf, len);
 632             }
 633             desc.cmdstat &= ~MP_ETH_TX_OWN;
 634             s->icr |= 1 << (MP_ETH_IRQ_TXLO_BIT - queue_index);
 635             eth_tx_desc_put(desc_addr, &desc);
 636         }
 637         desc_addr = desc.next;
 638     } while (desc_addr != s->tx_queue[queue_index]);
 639 }
 640
 641 static uint32_t mv88w8618_eth_read(void *opaque, target_phys_addr_t offset)
 642 {
 643     mv88w8618_eth_state *s = opaque;
 644
 645     switch (offset) {
 646     case MP_ETH_SMIR:
 647         if (s->smir & MP_ETH_SMIR_OPCODE) {
 648             switch (s->smir & MP_ETH_SMIR_ADDR) {
 649             case MP_ETH_PHY1_BMSR:
 650                 return MP_PHY_BMSR_LINK | MP_PHY_BMSR_AUTONEG |
 651                        MP_ETH_SMIR_RDVALID;
 652             case MP_ETH_PHY1_PHYSID1:
 653                 return (MP_PHY_88E3015 >> 16) | MP_ETH_SMIR_RDVALID;
 654             case MP_ETH_PHY1_PHYSID2:
 655                 return (MP_PHY_88E3015 & 0xFFFF) | MP_ETH_SMIR_RDVALID;
 656             default:
 657                 return MP_ETH_SMIR_RDVALID;
 658             }
 659         }
 660         return 0;
 661
 662     case MP_ETH_ICR:
 663         return s->icr;
 664
 665     case MP_ETH_IMR:
 666         return s->imr;
 667
 668     case MP_ETH_FRDP0 ... MP_ETH_FRDP3:
 669         return s->frx_queue[(offset - MP_ETH_FRDP0)/4];
 670
 671     case MP_ETH_CRDP0 ... MP_ETH_CRDP3:
 672         return s->rx_queue[(offset - MP_ETH_CRDP0)/4];
 673
 674     case MP_ETH_CTDP0 ... MP_ETH_CTDP3:
 675         return s->tx_queue[(offset - MP_ETH_CTDP0)/4];
 676
 677     default:
 678         return 0;
 679     }
 680 }
 681
 682 static void mv88w8618_eth_write(void *opaque, target_phys_addr_t offset,
 683                                 uint32_t value)
 684 {
 685     mv88w8618_eth_state *s = opaque;
 686
 687     switch (offset) {
 688     case MP_ETH_SMIR:
 689         s->smir = value;
 690         break;
 691
 692     case MP_ETH_PCXR:
 693         s->vlan_header = ((value >> MP_ETH_PCXR_2BSM_BIT) & 1) * 2;
 694         break;
 695
 696     case MP_ETH_SDCMR:
 697         if (value & MP_ETH_CMD_TXHI)
 698             eth_send(s, 1);
 699         if (value & MP_ETH_CMD_TXLO)
 700             eth_send(s, 0);
 701         if (value & (MP_ETH_CMD_TXHI | MP_ETH_CMD_TXLO) && s->icr & s->imr)
 702             qemu_irq_raise(s->irq);
 703         break;
 704
 705     case MP_ETH_ICR:
 706         s->icr &= value;
 707         break;
 708
 709     case MP_ETH_IMR:
 710         s->imr = value;
 711         if (s->icr & s->imr)
 712             qemu_irq_raise(s->irq);
 713         break;
 714
 715     case MP_ETH_FRDP0 ... MP_ETH_FRDP3:
 716         s->frx_queue[(offset - MP_ETH_FRDP0)/4] = value;
 717         break;
 718
 719     case MP_ETH_CRDP0 ... MP_ETH_CRDP3:
 720         s->rx_queue[(offset - MP_ETH_CRDP0)/4] =
 721             s->cur_rx[(offset - MP_ETH_CRDP0)/4] = value;
 722         break;
 723
 724     case MP_ETH_CTDP0 ... MP_ETH_CTDP3:
 725         s->tx_queue[(offset - MP_ETH_CTDP0)/4] = value;
 726         break;
 727     }
 728 }
 729
 730 static CPUReadMemoryFunc *mv88w8618_eth_readfn[] = {
 731     mv88w8618_eth_read,
 732     mv88w8618_eth_read,
 733     mv88w8618_eth_read
 734 };
 735
 736 static CPUWriteMemoryFunc *mv88w8618_eth_writefn[] = {
 737     mv88w8618_eth_write,
 738     mv88w8618_eth_write,
 739     mv88w8618_eth_write
 740 };
 741
 742 static void eth_cleanup(VLANClientState *vc)
 743 {
 744     mv88w8618_eth_state *s = vc->opaque;
 745
 746     cpu_unregister_io_memory(s->mmio_index);
 747
 748     qemu_free(s);
 749 }
 750
 751 static void mv88w8618_eth_init(SysBusDevice *dev)
 752 {
 753     mv88w8618_eth_state *s = FROM_SYSBUS(mv88w8618_eth_state, dev);
 754
 755     sysbus_init_irq(dev, &s->irq);
 756     s->vc = qdev_get_vlan_client(&dev->qdev,
 757                                  eth_can_receive, eth_receive, NULL,
 758                                  eth_cleanup, s);
 759     s->mmio_index = cpu_register_io_memory(mv88w8618_eth_readfn,
 760                                            mv88w8618_eth_writefn, s);
 761     sysbus_init_mmio(dev, MP_ETH_SIZE, s->mmio_index);
 762 }
 763
 764 /* LCD register offsets */
 765 #define MP_LCD_IRQCTRL          0x180
 766 #define MP_LCD_IRQSTAT          0x184
 767 #define MP_LCD_SPICTRL          0x1ac
 768 #define MP_LCD_INST             0x1bc
 769 #define MP_LCD_DATA             0x1c0
 770
 771 /* Mode magics */
 772 #define MP_LCD_SPI_DATA         0x00100011
 773 #define MP_LCD_SPI_CMD          0x00104011
 774 #define MP_LCD_SPI_INVALID      0x00000000
 775
 776 /* Commmands */
 777 #define MP_LCD_INST_SETPAGE0    0xB0
 778 /* ... */
 779 #define MP_LCD_INST_SETPAGE7    0xB7
 780
 781 #define MP_LCD_TEXTCOLOR        0xe0e0ff /* RRGGBB */
 782
 783 typedef struct musicpal_lcd_state {
 784     SysBusDevice busdev;
 785     uint32_t mode;
 786     uint32_t irqctrl;
 787     int page;
 788     int page_off;
 789     DisplayState *ds;
 790     uint8_t video_ram[128*64/8];
 791 } musicpal_lcd_state;
 792
 793 static uint32_t lcd_brightness;
 794
 795 static uint8_t scale_lcd_color(uint8_t col)
 796 {
 797     int tmp = col;
 798
 799     switch (lcd_brightness) {
 800     case 0x00000007: /* 0 */
 801         return 0;
 802
 803     case 0x00020000: /* 1 */
 804         return (tmp * 1) / 7;
 805
 806     case 0x00020001: /* 2 */
 807         return (tmp * 2) / 7;
 808
 809     case 0x00040000: /* 3 */
 810         return (tmp * 3) / 7;
 811
 812     case 0x00010006: /* 4 */
 813         return (tmp * 4) / 7;
 814
 815     case 0x00020005: /* 5 */
 816         return (tmp * 5) / 7;
 817
 818     case 0x00040003: /* 6 */
 819         return (tmp * 6) / 7;
 820
 821     case 0x00030004: /* 7 */
 822     default:
 823         return col;
 824     }
 825 }
 826
 827 #define SET_LCD_PIXEL(depth, type) \
 828 static inline void glue(set_lcd_pixel, depth) \
 829         (musicpal_lcd_state *s, int x, int y, type col) \
 830 { \
 831     int dx, dy; \
 832     type *pixel = &((type *) ds_get_data(s->ds))[(y * 128 * 3 + x) * 3]; \
 833 \
 834     for (dy = 0; dy < 3; dy++, pixel += 127 * 3) \
 835         for (dx = 0; dx < 3; dx++, pixel++) \
 836             *pixel = col; \
 837 }
 838 SET_LCD_PIXEL(8, uint8_t)
 839 SET_LCD_PIXEL(16, uint16_t)
 840 SET_LCD_PIXEL(32, uint32_t)
 841
 842 #include "pixel_ops.h"
 843
 844 static void lcd_refresh(void *opaque)
 845 {
 846     musicpal_lcd_state *s = opaque;
 847     int x, y, col;
 848
 849     switch (ds_get_bits_per_pixel(s->ds)) {
 850     case 0:
 851         return;
 852 #define LCD_REFRESH(depth, func) \
 853     case depth: \
 854         col = func(scale_lcd_color((MP_LCD_TEXTCOLOR >> 16) & 0xff), \
 855                    scale_lcd_color((MP_LCD_TEXTCOLOR >> 8) & 0xff), \
 856                    scale_lcd_color(MP_LCD_TEXTCOLOR & 0xff)); \
 857         for (x = 0; x < 128; x++) \
 858             for (y = 0; y < 64; y++) \
 859                 if (s->video_ram[x + (y/8)*128] & (1 << (y % 8))) \
 860                     glue(set_lcd_pixel, depth)(s, x, y, col); \
 861                 else \
 862                     glue(set_lcd_pixel, depth)(s, x, y, 0); \
 863         break;
 864     LCD_REFRESH(8, rgb_to_pixel8)
 865     LCD_REFRESH(16, rgb_to_pixel16)
 866     LCD_REFRESH(32, (is_surface_bgr(s->ds->surface) ?
 867                      rgb_to_pixel32bgr : rgb_to_pixel32))
 868     default:
 869         hw_error("unsupported colour depth %i\n",
 870                   ds_get_bits_per_pixel(s->ds));
 871     }
 872
 873     dpy_update(s->ds, 0, 0, 128*3, 64*3);
 874 }
 875
 876 static void lcd_invalidate(void *opaque)
 877 {
 878 }
 879
 880 static uint32_t musicpal_lcd_read(void *opaque, target_phys_addr_t offset)
 881 {
 882     musicpal_lcd_state *s = opaque;
 883
 884     switch (offset) {
 885     case MP_LCD_IRQCTRL:
 886         return s->irqctrl;
 887
 888     default:
 889         return 0;
 890     }
 891 }
 892
 893 static void musicpal_lcd_write(void *opaque, target_phys_addr_t offset,
 894                                uint32_t value)
 895 {
 896     musicpal_lcd_state *s = opaque;
 897
 898     switch (offset) {
 899     case MP_LCD_IRQCTRL:
 900         s->irqctrl = value;
 901         break;
 902
 903     case MP_LCD_SPICTRL:
 904         if (value == MP_LCD_SPI_DATA || value == MP_LCD_SPI_CMD)
 905             s->mode = value;
 906         else
 907             s->mode = MP_LCD_SPI_INVALID;
 908         break;
 909
 910     case MP_LCD_INST:
 911         if (value >= MP_LCD_INST_SETPAGE0 && value <= MP_LCD_INST_SETPAGE7) {
 912             s->page = value - MP_LCD_INST_SETPAGE0;
 913             s->page_off = 0;
 914         }
 915         break;
 916
 917     case MP_LCD_DATA:
 918         if (s->mode == MP_LCD_SPI_CMD) {
 919             if (value >= MP_LCD_INST_SETPAGE0 &&
 920                 value <= MP_LCD_INST_SETPAGE7) {
 921                 s->page = value - MP_LCD_INST_SETPAGE0;
 922                 s->page_off = 0;
 923             }
 924         } else if (s->mode == MP_LCD_SPI_DATA) {
 925             s->video_ram[s->page*128 + s->page_off] = value;
 926             s->page_off = (s->page_off + 1) & 127;
 927         }
 928         break;
 929     }
 930 }
 931
 932 static CPUReadMemoryFunc *musicpal_lcd_readfn[] = {
 933     musicpal_lcd_read,
 934     musicpal_lcd_read,
 935     musicpal_lcd_read
 936 };
 937
 938 static CPUWriteMemoryFunc *musicpal_lcd_writefn[] = {
 939     musicpal_lcd_write,
 940     musicpal_lcd_write,
 941     musicpal_lcd_write
 942 };
 943
 944 static void musicpal_lcd_init(SysBusDevice *dev)
 945 {
 946     musicpal_lcd_state *s = FROM_SYSBUS(musicpal_lcd_state, dev);
 947     int iomemtype;
 948
 949     iomemtype = cpu_register_io_memory(musicpal_lcd_readfn,
 950                                        musicpal_lcd_writefn, s);
 951     sysbus_init_mmio(dev, MP_LCD_SIZE, iomemtype);
 952     cpu_register_physical_memory(MP_LCD_BASE, MP_LCD_SIZE, iomemtype);
 953
 954     s->ds = graphic_console_init(lcd_refresh, lcd_invalidate,
 955                                  NULL, NULL, s);
 956     qemu_console_resize(s->ds, 128*3, 64*3);
 957 }
 958
 959 /* PIC register offsets */
 960 #define MP_PIC_STATUS           0x00
 961 #define MP_PIC_ENABLE_SET       0x08
 962 #define MP_PIC_ENABLE_CLR       0x0C
 963
 964 typedef struct mv88w8618_pic_state
 965 {
 966     SysBusDevice busdev;
 967     uint32_t level;
 968     uint32_t enabled;
 969     qemu_irq parent_irq;
 970 } mv88w8618_pic_state;
 971
 972 static void mv88w8618_pic_update(mv88w8618_pic_state *s)
 973 {
 974     qemu_set_irq(s->parent_irq, (s->level & s->enabled));
 975 }
 976
 977 static void mv88w8618_pic_set_irq(void *opaque, int irq, int level)
 978 {
 979     mv88w8618_pic_state *s = opaque;
 980
 981     if (level)
 982         s->level |= 1 << irq;
 983     else
 984         s->level &= ~(1 << irq);
 985     mv88w8618_pic_update(s);
 986 }
 987
 988 static uint32_t mv88w8618_pic_read(void *opaque, target_phys_addr_t offset)
 989 {
 990     mv88w8618_pic_state *s = opaque;
 991
 992     switch (offset) {
 993     case MP_PIC_STATUS:
 994         return s->level & s->enabled;
 995
 996     default:
 997         return 0;
 998     }
 999 }
1000
1001 static void mv88w8618_pic_write(void *opaque, target_phys_addr_t offset,
1002                                 uint32_t value)
1003 {
1004     mv88w8618_pic_state *s = opaque;
1005
1006     switch (offset) {
1007     case MP_PIC_ENABLE_SET:
1008         s->enabled |= value;
1009         break;
1010
1011     case MP_PIC_ENABLE_CLR:
1012         s->enabled &= ~value;
1013         s->level &= ~value;
1014         break;
1015     }
1016     mv88w8618_pic_update(s);
1017 }
1018
1019 static void mv88w8618_pic_reset(void *opaque)
1020 {
1021     mv88w8618_pic_state *s = opaque;
1022
1023     s->level = 0;
1024     s->enabled = 0;
1025 }
1026
1027 static CPUReadMemoryFunc *mv88w8618_pic_readfn[] = {
1028     mv88w8618_pic_read,
1029     mv88w8618_pic_read,
1030     mv88w8618_pic_read
1031 };
1032
1033 static CPUWriteMemoryFunc *mv88w8618_pic_writefn[] = {
1034     mv88w8618_pic_write,
1035     mv88w8618_pic_write,
1036     mv88w8618_pic_write
1037 };
1038
1039 static void mv88w8618_pic_init(SysBusDevice *dev)
1040 {
1041     mv88w8618_pic_state *s = FROM_SYSBUS(mv88w8618_pic_state, dev);
1042     int iomemtype;
1043
1044     qdev_init_gpio_in(&dev->qdev, mv88w8618_pic_set_irq, 32);
1045     sysbus_init_irq(dev, &s->parent_irq);
1046     iomemtype = cpu_register_io_memory(mv88w8618_pic_readfn,
1047                                        mv88w8618_pic_writefn, s);
1048     sysbus_init_mmio(dev, MP_PIC_SIZE, iomemtype);
1049
1050     qemu_register_reset(mv88w8618_pic_reset, 0, s);
1051 }
1052
1053 /* PIT register offsets */
1054 #define MP_PIT_TIMER1_LENGTH    0x00
1055 /* ... */
1056 #define MP_PIT_TIMER4_LENGTH    0x0C
1057 #define MP_PIT_CONTROL          0x10
1058 #define MP_PIT_TIMER1_VALUE     0x14
1059 /* ... */
1060 #define MP_PIT_TIMER4_VALUE     0x20
1061 #define MP_BOARD_RESET          0x34
1062
1063 /* Magic board reset value (probably some watchdog behind it) */
1064 #define MP_BOARD_RESET_MAGIC    0x10000
1065
1066 typedef struct mv88w8618_timer_state {
1067     ptimer_state *ptimer;
1068     uint32_t limit;
1069     int freq;
1070     qemu_irq irq;
1071 } mv88w8618_timer_state;
1072
1073 typedef struct mv88w8618_pit_state {
1074     SysBusDevice busdev;
1075     mv88w8618_timer_state timer[4];
1076     uint32_t control;
1077 } mv88w8618_pit_state;
1078
1079 static void mv88w8618_timer_tick(void *opaque)
1080 {
1081     mv88w8618_timer_state *s = opaque;
1082
1083     qemu_irq_raise(s->irq);
1084 }
1085
1086 static void mv88w8618_timer_init(SysBusDevice *dev, mv88w8618_timer_state *s,
1087                                  uint32_t freq)
1088 {
1089     QEMUBH *bh;
1090
1091     sysbus_init_irq(dev, &s->irq);
1092     s->freq = freq;
1093
1094     bh = qemu_bh_new(mv88w8618_timer_tick, s);
1095     s->ptimer = ptimer_init(bh);
1096 }
1097
1098 static uint32_t mv88w8618_pit_read(void *opaque, target_phys_addr_t offset)
1099 {
1100     mv88w8618_pit_state *s = opaque;
1101     mv88w8618_timer_state *t;
1102
1103     switch (offset) {
1104     case MP_PIT_TIMER1_VALUE ... MP_PIT_TIMER4_VALUE:
1105         t = &s->timer[(offset-MP_PIT_TIMER1_VALUE) >> 2];
1106         return ptimer_get_count(t->ptimer);
1107
1108     default:
1109         return 0;
1110     }
1111 }
1112
1113 static void mv88w8618_pit_write(void *opaque, target_phys_addr_t offset,
1114                                 uint32_t value)
1115 {
1116     mv88w8618_pit_state *s = opaque;
1117     mv88w8618_timer_state *t;
1118     int i;
1119
1120     switch (offset) {
1121     case MP_PIT_TIMER1_LENGTH ... MP_PIT_TIMER4_LENGTH:
1122         t = &s->timer[offset >> 2];
1123         t->limit = value;
1124         ptimer_set_limit(t->ptimer, t->limit, 1);
1125         break;
1126
1127     case MP_PIT_CONTROL:
1128         for (i = 0; i < 4; i++) {
1129             if (value & 0xf) {
1130                 t = &s->timer[i];
1131                 ptimer_set_limit(t->ptimer, t->limit, 0);
1132                 ptimer_set_freq(t->ptimer, t->freq);
1133                 ptimer_run(t->ptimer, 0);
1134             }
1135             value >>= 4;
1136         }
1137         break;
1138
1139     case MP_BOARD_RESET:
1140         if (value == MP_BOARD_RESET_MAGIC)
1141             qemu_system_reset_request();
1142         break;
1143     }
1144 }
1145
1146 static CPUReadMemoryFunc *mv88w8618_pit_readfn[] = {
1147     mv88w8618_pit_read,
1148     mv88w8618_pit_read,
1149     mv88w8618_pit_read
1150 };
1151
1152 static CPUWriteMemoryFunc *mv88w8618_pit_writefn[] = {
1153     mv88w8618_pit_write,
1154     mv88w8618_pit_write,
1155     mv88w8618_pit_write
1156 };
1157
1158 static void mv88w8618_pit_init(SysBusDevice *dev)
1159 {
1160     int iomemtype;
1161     mv88w8618_pit_state *s = FROM_SYSBUS(mv88w8618_pit_state, dev);
1162     int i;
1163
1164     /* Letting them all run at 1 MHz is likely just a pragmatic
1165      * simplification. */
1166     for (i = 0; i < 4; i++) {
1167         mv88w8618_timer_init(dev, &s->timer[i], 1000000);
1168     }
1169
1170     iomemtype = cpu_register_io_memory(mv88w8618_pit_readfn,
1171                                        mv88w8618_pit_writefn, s);
1172     sysbus_init_mmio(dev, MP_PIT_SIZE, iomemtype);
1173 }
1174
1175 /* Flash config register offsets */
1176 #define MP_FLASHCFG_CFGR0    0x04
1177
1178 typedef struct mv88w8618_flashcfg_state {
1179     SysBusDevice busdev;
1180     uint32_t cfgr0;
1181 } mv88w8618_flashcfg_state;
1182
1183 static uint32_t mv88w8618_flashcfg_read(void *opaque,
1184                                         target_phys_addr_t offset)
1185 {
1186     mv88w8618_flashcfg_state *s = opaque;
1187
1188     switch (offset) {
1189     case MP_FLASHCFG_CFGR0:
1190         return s->cfgr0;
1191
1192     default:
1193         return 0;
1194     }
1195 }
1196
1197 static void mv88w8618_flashcfg_write(void *opaque, target_phys_addr_t offset,
1198                                      uint32_t value)
1199 {
1200     mv88w8618_flashcfg_state *s = opaque;
1201
1202     switch (offset) {
1203     case MP_FLASHCFG_CFGR0:
1204         s->cfgr0 = value;
1205         break;
1206     }
1207 }
1208
1209 static CPUReadMemoryFunc *mv88w8618_flashcfg_readfn[] = {
1210     mv88w8618_flashcfg_read,
1211     mv88w8618_flashcfg_read,
1212     mv88w8618_flashcfg_read
1213 };
1214
1215 static CPUWriteMemoryFunc *mv88w8618_flashcfg_writefn[] = {
1216     mv88w8618_flashcfg_write,
1217     mv88w8618_flashcfg_write,
1218     mv88w8618_flashcfg_write
1219 };
1220
1221 static void mv88w8618_flashcfg_init(SysBusDevice *dev)
1222 {
1223     int iomemtype;
1224     mv88w8618_flashcfg_state *s = FROM_SYSBUS(mv88w8618_flashcfg_state, dev);
1225
1226     s->cfgr0 = 0xfffe4285; /* Default as set by U-Boot for 8 MB flash */
1227     iomemtype = cpu_register_io_memory(mv88w8618_flashcfg_readfn,
1228                        mv88w8618_flashcfg_writefn, s);
1229     sysbus_init_mmio(dev, MP_FLASHCFG_SIZE, iomemtype);
1230 }
1231
1232 /* Misc register offsets */
1233 #define MP_MISC_BOARD_REVISION  0x18
1234
1235 #define MP_BOARD_REVISION       0x31
1236
1237 static uint32_t musicpal_misc_read(void *opaque, target_phys_addr_t offset)
1238 {
1239     switch (offset) {
1240     case MP_MISC_BOARD_REVISION:
1241         return MP_BOARD_REVISION;
1242
1243     default:
1244         return 0;
1245     }
1246 }
1247
1248 static void musicpal_misc_write(void *opaque, target_phys_addr_t offset,
1249                                 uint32_t value)
1250 {
1251 }
1252
1253 static CPUReadMemoryFunc *musicpal_misc_readfn[] = {
1254     musicpal_misc_read,
1255     musicpal_misc_read,
1256     musicpal_misc_read,
1257 };
1258
1259 static CPUWriteMemoryFunc *musicpal_misc_writefn[] = {
1260     musicpal_misc_write,
1261     musicpal_misc_write,
1262     musicpal_misc_write,
1263 };
1264
1265 static void musicpal_misc_init(void)
1266 {
1267     int iomemtype;
1268
1269     iomemtype = cpu_register_io_memory(musicpal_misc_readfn,
1270                                        musicpal_misc_writefn, NULL);
1271     cpu_register_physical_memory(MP_MISC_BASE, MP_MISC_SIZE, iomemtype);
1272 }
1273
1274 /* WLAN register offsets */
1275 #define MP_WLAN_MAGIC1          0x11c
1276 #define MP_WLAN_MAGIC2          0x124
1277
1278 static uint32_t mv88w8618_wlan_read(void *opaque, target_phys_addr_t offset)
1279 {
1280     switch (offset) {
1281     /* Workaround to allow loading the binary-only wlandrv.ko crap
1282      * from the original Freecom firmware. */
1283     case MP_WLAN_MAGIC1:
1284         return ~3;
1285     case MP_WLAN_MAGIC2:
1286         return -1;
1287
1288     default:
1289         return 0;
1290     }
1291 }
1292
1293 static void mv88w8618_wlan_write(void *opaque, target_phys_addr_t offset,
1294                                  uint32_t value)
1295 {
1296 }
1297
1298 static CPUReadMemoryFunc *mv88w8618_wlan_readfn[] = {
1299     mv88w8618_wlan_read,
1300     mv88w8618_wlan_read,
1301     mv88w8618_wlan_read,
1302 };
1303
1304 static CPUWriteMemoryFunc *mv88w8618_wlan_writefn[] = {
1305     mv88w8618_wlan_write,
1306     mv88w8618_wlan_write,
1307     mv88w8618_wlan_write,
1308 };
1309
1310 static void mv88w8618_wlan_init(SysBusDevice *dev)
1311 {
1312     int iomemtype;
1313
1314     iomemtype = cpu_register_io_memory(mv88w8618_wlan_readfn,
1315                                        mv88w8618_wlan_writefn, NULL);
1316     sysbus_init_mmio(dev, MP_WLAN_SIZE, iomemtype);
1317 }
1318
1319 /* GPIO register offsets */
1320 #define MP_GPIO_OE_LO           0x008
1321 #define MP_GPIO_OUT_LO          0x00c
1322 #define MP_GPIO_IN_LO           0x010
1323 #define MP_GPIO_ISR_LO          0x020
1324 #define MP_GPIO_OE_HI           0x508
1325 #define MP_GPIO_OUT_HI          0x50c
1326 #define MP_GPIO_IN_HI           0x510
1327 #define MP_GPIO_ISR_HI          0x520
1328
1329 /* GPIO bits & masks */
1330 #define MP_GPIO_WHEEL_VOL       (1 << 8)
1331 #define MP_GPIO_WHEEL_VOL_INV   (1 << 9)
1332 #define MP_GPIO_WHEEL_NAV       (1 << 10)
1333 #define MP_GPIO_WHEEL_NAV_INV   (1 << 11)
1334 #define MP_GPIO_LCD_BRIGHTNESS  0x00070000
1335 #define MP_GPIO_BTN_FAVORITS    (1 << 19)
1336 #define MP_GPIO_BTN_MENU        (1 << 20)
1337 #define MP_GPIO_BTN_VOLUME      (1 << 21)
1338 #define MP_GPIO_BTN_NAVIGATION  (1 << 22)
1339 #define MP_GPIO_I2C_DATA_BIT    29
1340 #define MP_GPIO_I2C_DATA        (1 << MP_GPIO_I2C_DATA_BIT)
1341 #define MP_GPIO_I2C_CLOCK_BIT   30
1342
1343 /* LCD brightness bits in GPIO_OE_HI */
1344 #define MP_OE_LCD_BRIGHTNESS    0x0007
1345
1346 static uint32_t musicpal_gpio_read(void *opaque, target_phys_addr_t offset)
1347 {
1348     switch (offset) {
1349     case MP_GPIO_OE_HI: /* used for LCD brightness control */
1350         return lcd_brightness & MP_OE_LCD_BRIGHTNESS;
1351
1352     case MP_GPIO_OUT_LO:
1353         return gpio_out_state & 0xFFFF;
1354     case MP_GPIO_OUT_HI:
1355         return gpio_out_state >> 16;
1356
1357     case MP_GPIO_IN_LO:
1358         return gpio_in_state & 0xFFFF;
1359     case MP_GPIO_IN_HI:
1360         /* Update received I2C data */
1361         gpio_in_state = (gpio_in_state & ~MP_GPIO_I2C_DATA) |
1362                         (i2c_get_data(mixer_i2c) << MP_GPIO_I2C_DATA_BIT);
1363         return gpio_in_state >> 16;
1364
1365     case MP_GPIO_ISR_LO:
1366         return gpio_isr & 0xFFFF;
1367     case MP_GPIO_ISR_HI:
1368         return gpio_isr >> 16;
1369
1370     default:
1371         return 0;
1372     }
1373 }
1374
1375 static void musicpal_gpio_write(void *opaque, target_phys_addr_t offset,
1376                                 uint32_t value)
1377 {
1378     switch (offset) {
1379     case MP_GPIO_OE_HI: /* used for LCD brightness control */
1380         lcd_brightness = (lcd_brightness & MP_GPIO_LCD_BRIGHTNESS) |
1381                          (value & MP_OE_LCD_BRIGHTNESS);
1382         break;
1383
1384     case MP_GPIO_OUT_LO:
1385         gpio_out_state = (gpio_out_state & 0xFFFF0000) | (value & 0xFFFF);
1386         break;
1387     case MP_GPIO_OUT_HI:
1388         gpio_out_state = (gpio_out_state & 0xFFFF) | (value << 16);
1389         lcd_brightness = (lcd_brightness & 0xFFFF) |
1390                          (gpio_out_state & MP_GPIO_LCD_BRIGHTNESS);
1391         i2c_state_update(mixer_i2c,
1392                          (gpio_out_state >> MP_GPIO_I2C_DATA_BIT) & 1,
1393                          (gpio_out_state >> MP_GPIO_I2C_CLOCK_BIT) & 1);
1394         break;
1395
1396     }
1397 }
1398
1399 static CPUReadMemoryFunc *musicpal_gpio_readfn[] = {
1400     musicpal_gpio_read,
1401     musicpal_gpio_read,
1402     musicpal_gpio_read,
1403 };
1404
1405 static CPUWriteMemoryFunc *musicpal_gpio_writefn[] = {
1406     musicpal_gpio_write,
1407     musicpal_gpio_write,
1408     musicpal_gpio_write,
1409 };
1410
1411 static void musicpal_gpio_init(void)
1412 {
1413     int iomemtype;
1414
1415     iomemtype = cpu_register_io_memory(musicpal_gpio_readfn,
1416                                        musicpal_gpio_writefn, NULL);
1417     cpu_register_physical_memory(MP_GPIO_BASE, MP_GPIO_SIZE, iomemtype);
1418 }
1419
1420 /* Keyboard codes & masks */
1421 #define KEY_RELEASED            0x80
1422 #define KEY_CODE                0x7f
1423
1424 #define KEYCODE_TAB             0x0f
1425 #define KEYCODE_ENTER           0x1c
1426 #define KEYCODE_F               0x21
1427 #define KEYCODE_M               0x32
1428
1429 #define KEYCODE_EXTENDED        0xe0
1430 #define KEYCODE_UP              0x48
1431 #define KEYCODE_DOWN            0x50
1432 #define KEYCODE_LEFT            0x4b
1433 #define KEYCODE_RIGHT           0x4d
1434
1435 static void musicpal_key_event(void *opaque, int keycode)
1436 {
1437     qemu_irq irq = opaque;
1438     uint32_t event = 0;
1439     static int kbd_extended;
1440
1441     if (keycode == KEYCODE_EXTENDED) {
1442         kbd_extended = 1;
1443         return;
1444     }
1445
1446     if (kbd_extended)
1447         switch (keycode & KEY_CODE) {
1448         case KEYCODE_UP:
1449             event = MP_GPIO_WHEEL_NAV | MP_GPIO_WHEEL_NAV_INV;
1450             break;
1451
1452         case KEYCODE_DOWN:
1453             event = MP_GPIO_WHEEL_NAV;
1454             break;
1455
1456         case KEYCODE_LEFT:
1457             event = MP_GPIO_WHEEL_VOL | MP_GPIO_WHEEL_VOL_INV;
1458             break;
1459
1460         case KEYCODE_RIGHT:
1461             event = MP_GPIO_WHEEL_VOL;
1462             break;
1463         }
1464     else {
1465         switch (keycode & KEY_CODE) {
1466         case KEYCODE_F:
1467             event = MP_GPIO_BTN_FAVORITS;
1468             break;
1469
1470         case KEYCODE_TAB:
1471             event = MP_GPIO_BTN_VOLUME;
1472             break;
1473
1474         case KEYCODE_ENTER:
1475             event = MP_GPIO_BTN_NAVIGATION;
1476             break;
1477
1478         case KEYCODE_M:
1479             event = MP_GPIO_BTN_MENU;
1480             break;
1481         }
1482         /* Do not repeat already pressed buttons */
1483         if (!(keycode & KEY_RELEASED) && !(gpio_in_state & event))
1484             event = 0;
1485     }
1486
1487     if (event) {
1488         if (keycode & KEY_RELEASED) {
1489             gpio_in_state |= event;
1490         } else {
1491             gpio_in_state &= ~event;
1492             gpio_isr = event;
1493             qemu_irq_raise(irq);
1494         }
1495     }
1496
1497     kbd_extended = 0;
1498 }
1499
1500 static struct arm_boot_info musicpal_binfo = {
1501     .loader_start = 0x0,
1502     .board_id = 0x20e,
1503 };
1504
1505 static void musicpal_init(ram_addr_t ram_size,
1506                const char *boot_device,
1507                const char *kernel_filename, const char *kernel_cmdline,
1508                const char *initrd_filename, const char *cpu_model)
1509 {
1510     CPUState *env;
1511     qemu_irq *cpu_pic;
1512     qemu_irq pic[32];
1513     DeviceState *dev;
1514     int i;
1515     int index;
1516     unsigned long flash_size;
1517
1518     if (!cpu_model)
1519         cpu_model = "arm926";
1520
1521     env = cpu_init(cpu_model);
1522     if (!env) {
1523         fprintf(stderr, "Unable to find CPU definition\n");
1524         exit(1);
1525     }
1526     cpu_pic = arm_pic_init_cpu(env);
1527
1528     /* For now we use a fixed - the original - RAM size */
1529     cpu_register_physical_memory(0, MP_RAM_DEFAULT_SIZE,
1530                                  qemu_ram_alloc(MP_RAM_DEFAULT_SIZE));
1531
1532     sram_off = qemu_ram_alloc(MP_SRAM_SIZE);
1533     cpu_register_physical_memory(MP_SRAM_BASE, MP_SRAM_SIZE, sram_off);
1534
1535     dev = sysbus_create_simple("mv88w8618_pic", MP_PIC_BASE,
1536                                cpu_pic[ARM_PIC_CPU_IRQ]);
1537     for (i = 0; i < 32; i++) {
1538         pic[i] = qdev_get_gpio_in(dev, i);
1539     }
1540     sysbus_create_varargs("mv88w8618_pit", MP_PIT_BASE, pic[MP_TIMER1_IRQ],
1541                           pic[MP_TIMER2_IRQ], pic[MP_TIMER3_IRQ],
1542                           pic[MP_TIMER4_IRQ], NULL);
1543
1544     if (serial_hds[0])
1545         serial_mm_init(MP_UART1_BASE, 2, pic[MP_UART1_IRQ], 1825000,
1546                    serial_hds[0], 1);
1547     if (serial_hds[1])
1548         serial_mm_init(MP_UART2_BASE, 2, pic[MP_UART2_IRQ], 1825000,
1549                    serial_hds[1], 1);
1550
1551     /* Register flash */
1552     index = drive_get_index(IF_PFLASH, 0, 0);
1553     if (index != -1) {
1554         flash_size = bdrv_getlength(drives_table[index].bdrv);
1555         if (flash_size != 8*1024*1024 && flash_size != 16*1024*1024 &&
1556             flash_size != 32*1024*1024) {
1557             fprintf(stderr, "Invalid flash image size\n");
1558             exit(1);
1559         }
1560
1561         /*
1562          * The original U-Boot accesses the flash at 0xFE000000 instead of
1563          * 0xFF800000 (if there is 8 MB flash). So remap flash access if the
1564          * image is smaller than 32 MB.
1565          */
1566         pflash_cfi02_register(0-MP_FLASH_SIZE_MAX, qemu_ram_alloc(flash_size),
1567                               drives_table[index].bdrv, 0x10000,
1568                               (flash_size + 0xffff) >> 16,
1569                               MP_FLASH_SIZE_MAX / flash_size,
1570                               2, 0x00BF, 0x236D, 0x0000, 0x0000,
1571                               0x5555, 0x2AAA);
1572     }
1573     sysbus_create_simple("mv88w8618_flashcfg", MP_FLASHCFG_BASE, NULL);
1574
1575     sysbus_create_simple("musicpal_lcd", MP_LCD_BASE, NULL);
1576
1577     qemu_add_kbd_event_handler(musicpal_key_event, pic[MP_GPIO_IRQ]);
1578
1579     qemu_check_nic_model(&nd_table[0], "mv88w8618");
1580     dev = qdev_create(NULL, "mv88w8618_eth");
1581     qdev_set_netdev(dev, &nd_table[0]);
1582     qdev_init(dev);
1583     sysbus_mmio_map(sysbus_from_qdev(dev), 0, MP_ETH_BASE);
1584     sysbus_connect_irq(sysbus_from_qdev(dev), 0, pic[MP_ETH_IRQ]);
1585
1586     mixer_i2c = musicpal_audio_init(pic[MP_AUDIO_IRQ]);
1587
1588     sysbus_create_simple("mv88w8618_wlan", MP_WLAN_BASE, NULL);
1589
1590     musicpal_misc_init();
1591     musicpal_gpio_init();
1592
1593     musicpal_binfo.ram_size = MP_RAM_DEFAULT_SIZE;
1594     musicpal_binfo.kernel_filename = kernel_filename;
1595     musicpal_binfo.kernel_cmdline = kernel_cmdline;
1596     musicpal_binfo.initrd_filename = initrd_filename;
1597     arm_load_kernel(env, &musicpal_binfo);
1598 }
1599
1600 static QEMUMachine musicpal_machine = {
1601     .name = "musicpal",
1602     .desc = "Marvell 88w8618 / MusicPal (ARM926EJ-S)",
1603     .init = musicpal_init,
1604 };
1605
1606 static void musicpal_machine_init(void)
1607 {
1608     qemu_register_machine(&musicpal_machine);
1609 }
1610
1611 machine_init(musicpal_machine_init);
1612
1613 static void musicpal_register_devices(void)
1614 {
1615     sysbus_register_dev("mv88w8618_pic", sizeof(mv88w8618_pic_state),
1616                         mv88w8618_pic_init);
1617     sysbus_register_dev("mv88w8618_pit", sizeof(mv88w8618_pit_state),
1618                         mv88w8618_pit_init);
1619     sysbus_register_dev("mv88w8618_flashcfg", sizeof(mv88w8618_flashcfg_state),
1620                         mv88w8618_flashcfg_init);
1621     sysbus_register_dev("mv88w8618_eth", sizeof(mv88w8618_eth_state),
1622                         mv88w8618_eth_init);
1623     sysbus_register_dev("mv88w8618_wlan", sizeof(SysBusDevice),
1624                         mv88w8618_wlan_init);
1625     sysbus_register_dev("musicpal_lcd", sizeof(musicpal_lcd_state),
1626                         musicpal_lcd_init);
1627 }
1628
1629 device_init(musicpal_register_devices)