hw/ppc4xx_devs.c

   1 /*
   2  * QEMU PowerPC 4xx embedded processors shared devices emulation
   3  *
   4  * Copyright (c) 2007 Jocelyn Mayer
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "ppc.h"
  26 #include "ppc4xx.h"
  27 #include "sysemu.h"
  28 #include "qemu-log.h"
  29
  30 //#define DEBUG_MMIO
  31 //#define DEBUG_UNASSIGNED
  32 #define DEBUG_UIC
  33
  34
  35 #ifdef DEBUG_UIC
  36 #  define LOG_UIC(...) do {              \
  37      if (loglevel & CPU_LOG_INT)         \
  38        fprintf(logfile, ## __VA_ARGS__); \
  39    } while (0)
  40 #else
  41 #  define LOG_UIC(...) do { } while (0)
  42 #endif
  43
  44 /*****************************************************************************/
  45 /* Generic PowerPC 4xx processor instanciation */
  46 CPUState *ppc4xx_init (const char *cpu_model,
  47                        clk_setup_t *cpu_clk, clk_setup_t *tb_clk,
  48                        uint32_t sysclk)
  49 {
  50     CPUState *env;
  51
  52     /* init CPUs */
  53     env = cpu_init(cpu_model);
  54     if (!env) {
  55         fprintf(stderr, "Unable to find PowerPC %s CPU definition\n",
  56                 cpu_model);
  57         exit(1);
  58     }
  59     cpu_clk->cb = NULL; /* We don't care about CPU clock frequency changes */
  60     cpu_clk->opaque = env;
  61     /* Set time-base frequency to sysclk */
  62     tb_clk->cb = ppc_emb_timers_init(env, sysclk);
  63     tb_clk->opaque = env;
  64     ppc_dcr_init(env, NULL, NULL);
  65     /* Register qemu callbacks */
  66     qemu_register_reset(&cpu_ppc_reset, env);
  67
  68     return env;
  69 }
  70
  71 /*****************************************************************************/
  72 /* Fake device used to map multiple devices in a single memory page */
  73 #define MMIO_AREA_BITS 8
  74 #define MMIO_AREA_LEN (1 << MMIO_AREA_BITS)
  75 #define MMIO_AREA_NB (1 << (TARGET_PAGE_BITS - MMIO_AREA_BITS))
  76 #define MMIO_IDX(addr) (((addr) >> MMIO_AREA_BITS) & (MMIO_AREA_NB - 1))
  77 struct ppc4xx_mmio_t {
  78     target_phys_addr_t base;
  79     CPUReadMemoryFunc **mem_read[MMIO_AREA_NB];
  80     CPUWriteMemoryFunc **mem_write[MMIO_AREA_NB];
  81     void *opaque[MMIO_AREA_NB];
  82 };
  83
  84 static uint32_t unassigned_mmio_readb (void *opaque, target_phys_addr_t addr)
  85 {
  86 #ifdef DEBUG_UNASSIGNED
  87     ppc4xx_mmio_t *mmio;
  88
  89     mmio = opaque;
  90     printf("Unassigned mmio read 0x" PADDRX " base " PADDRX "\n",
  91            addr, mmio->base);
  92 #endif
  93
  94     return 0;
  95 }
  96
  97 static void unassigned_mmio_writeb (void *opaque,
  98                                     target_phys_addr_t addr, uint32_t val)
  99 {
 100 #ifdef DEBUG_UNASSIGNED
 101     ppc4xx_mmio_t *mmio;
 102
 103     mmio = opaque;
 104     printf("Unassigned mmio write 0x" PADDRX " = 0x%x base " PADDRX "\n",
 105            addr, val, mmio->base);
 106 #endif
 107 }
 108
 109 static CPUReadMemoryFunc *unassigned_mmio_read[3] = {
 110     unassigned_mmio_readb,
 111     unassigned_mmio_readb,
 112     unassigned_mmio_readb,
 113 };
 114
 115 static CPUWriteMemoryFunc *unassigned_mmio_write[3] = {
 116     unassigned_mmio_writeb,
 117     unassigned_mmio_writeb,
 118     unassigned_mmio_writeb,
 119 };
 120
 121 static uint32_t mmio_readlen (ppc4xx_mmio_t *mmio,
 122                               target_phys_addr_t addr, int len)
 123 {
 124     CPUReadMemoryFunc **mem_read;
 125     uint32_t ret;
 126     int idx;
 127
 128     idx = MMIO_IDX(addr);
 129 #if defined(DEBUG_MMIO)
 130     printf("%s: mmio %p len %d addr " PADDRX " idx %d\n", __func__,
 131            mmio, len, addr, idx);
 132 #endif
 133     mem_read = mmio->mem_read[idx];
 134     ret = (*mem_read[len])(mmio->opaque[idx], addr);
 135
 136     return ret;
 137 }
 138
 139 static void mmio_writelen (ppc4xx_mmio_t *mmio,
 140                            target_phys_addr_t addr, uint32_t value, int len)
 141 {
 142     CPUWriteMemoryFunc **mem_write;
 143     int idx;
 144
 145     idx = MMIO_IDX(addr);
 146 #if defined(DEBUG_MMIO)
 147     printf("%s: mmio %p len %d addr " PADDRX " idx %d value %08" PRIx32 "\n",
 148            __func__, mmio, len, addr, idx, value);
 149 #endif
 150     mem_write = mmio->mem_write[idx];
 151     (*mem_write[len])(mmio->opaque[idx], addr, value);
 152 }
 153
 154 static uint32_t mmio_readb (void *opaque, target_phys_addr_t addr)
 155 {
 156 #if defined(DEBUG_MMIO)
 157     printf("%s: addr " PADDRX "\n", __func__, addr);
 158 #endif
 159
 160     return mmio_readlen(opaque, addr, 0);
 161 }
 162
 163 static void mmio_writeb (void *opaque,
 164                          target_phys_addr_t addr, uint32_t value)
 165 {
 166 #if defined(DEBUG_MMIO)
 167     printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
 168 #endif
 169     mmio_writelen(opaque, addr, value, 0);
 170 }
 171
 172 static uint32_t mmio_readw (void *opaque, target_phys_addr_t addr)
 173 {
 174 #if defined(DEBUG_MMIO)
 175     printf("%s: addr " PADDRX "\n", __func__, addr);
 176 #endif
 177
 178     return mmio_readlen(opaque, addr, 1);
 179 }
 180
 181 static void mmio_writew (void *opaque,
 182                          target_phys_addr_t addr, uint32_t value)
 183 {
 184 #if defined(DEBUG_MMIO)
 185     printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
 186 #endif
 187     mmio_writelen(opaque, addr, value, 1);
 188 }
 189
 190 static uint32_t mmio_readl (void *opaque, target_phys_addr_t addr)
 191 {
 192 #if defined(DEBUG_MMIO)
 193     printf("%s: addr " PADDRX "\n", __func__, addr);
 194 #endif
 195
 196     return mmio_readlen(opaque, addr, 2);
 197 }
 198
 199 static void mmio_writel (void *opaque,
 200                          target_phys_addr_t addr, uint32_t value)
 201 {
 202 #if defined(DEBUG_MMIO)
 203     printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
 204 #endif
 205     mmio_writelen(opaque, addr, value, 2);
 206 }
 207
 208 static CPUReadMemoryFunc *mmio_read[] = {
 209     &mmio_readb,
 210     &mmio_readw,
 211     &mmio_readl,
 212 };
 213
 214 static CPUWriteMemoryFunc *mmio_write[] = {
 215     &mmio_writeb,
 216     &mmio_writew,
 217     &mmio_writel,
 218 };
 219
 220 int ppc4xx_mmio_register (CPUState *env, ppc4xx_mmio_t *mmio,
 221                           target_phys_addr_t offset, uint32_t len,
 222                           CPUReadMemoryFunc **mem_read,
 223                           CPUWriteMemoryFunc **mem_write, void *opaque)
 224 {
 225     target_phys_addr_t end;
 226     int idx, eidx;
 227
 228     if ((offset + len) > TARGET_PAGE_SIZE)
 229         return -1;
 230     idx = MMIO_IDX(offset);
 231     end = offset + len - 1;
 232     eidx = MMIO_IDX(end);
 233 #if defined(DEBUG_MMIO)
 234     printf("%s: offset " PADDRX " len %08" PRIx32 " " PADDRX " %d %d\n",
 235            __func__, offset, len, end, idx, eidx);
 236 #endif
 237     for (; idx <= eidx; idx++) {
 238         mmio->mem_read[idx] = mem_read;
 239         mmio->mem_write[idx] = mem_write;
 240         mmio->opaque[idx] = opaque;
 241     }
 242
 243     return 0;
 244 }
 245
 246 ppc4xx_mmio_t *ppc4xx_mmio_init (CPUState *env, target_phys_addr_t base)
 247 {
 248     ppc4xx_mmio_t *mmio;
 249     int mmio_memory;
 250
 251     mmio = qemu_mallocz(sizeof(ppc4xx_mmio_t));
 252     if (mmio != NULL) {
 253         mmio->base = base;
 254         mmio_memory = cpu_register_io_memory(0, mmio_read, mmio_write, mmio);
 255 #if defined(DEBUG_MMIO)
 256         printf("%s: base " PADDRX " len %08x %d\n", __func__,
 257                base, TARGET_PAGE_SIZE, mmio_memory);
 258 #endif
 259         cpu_register_physical_memory(base, TARGET_PAGE_SIZE, mmio_memory);
 260         ppc4xx_mmio_register(env, mmio, 0, TARGET_PAGE_SIZE,
 261                              unassigned_mmio_read, unassigned_mmio_write,
 262                              mmio);
 263     }
 264
 265     return mmio;
 266 }
 267
 268 /*****************************************************************************/
 269 /* "Universal" Interrupt controller */
 270 enum {
 271     DCR_UICSR  = 0x000,
 272     DCR_UICSRS = 0x001,
 273     DCR_UICER  = 0x002,
 274     DCR_UICCR  = 0x003,
 275     DCR_UICPR  = 0x004,
 276     DCR_UICTR  = 0x005,
 277     DCR_UICMSR = 0x006,
 278     DCR_UICVR  = 0x007,
 279     DCR_UICVCR = 0x008,
 280     DCR_UICMAX = 0x009,
 281 };
 282
 283 #define UIC_MAX_IRQ 32
 284 typedef struct ppcuic_t ppcuic_t;
 285 struct ppcuic_t {
 286     uint32_t dcr_base;
 287     int use_vectors;
 288     uint32_t level;  /* Remembers the state of level-triggered interrupts. */
 289     uint32_t uicsr;  /* Status register */
 290     uint32_t uicer;  /* Enable register */
 291     uint32_t uiccr;  /* Critical register */
 292     uint32_t uicpr;  /* Polarity register */
 293     uint32_t uictr;  /* Triggering register */
 294     uint32_t uicvcr; /* Vector configuration register */
 295     uint32_t uicvr;
 296     qemu_irq *irqs;
 297 };
 298
 299 static void ppcuic_trigger_irq (ppcuic_t *uic)
 300 {
 301     uint32_t ir, cr;
 302     int start, end, inc, i;
 303
 304     /* Trigger interrupt if any is pending */
 305     ir = uic->uicsr & uic->uicer & (~uic->uiccr);
 306     cr = uic->uicsr & uic->uicer & uic->uiccr;
 307     LOG_UIC("%s: uicsr %08" PRIx32 " uicer %08" PRIx32
 308                 " uiccr %08" PRIx32 "\n"
 309                 "   %08" PRIx32 " ir %08" PRIx32 " cr %08" PRIx32 "\n",
 310                 __func__, uic->uicsr, uic->uicer, uic->uiccr,
 311                 uic->uicsr & uic->uicer, ir, cr);
 312     if (ir != 0x0000000) {
 313         LOG_UIC("Raise UIC interrupt\n");
 314         qemu_irq_raise(uic->irqs[PPCUIC_OUTPUT_INT]);
 315     } else {
 316         LOG_UIC("Lower UIC interrupt\n");
 317         qemu_irq_lower(uic->irqs[PPCUIC_OUTPUT_INT]);
 318     }
 319     /* Trigger critical interrupt if any is pending and update vector */
 320     if (cr != 0x0000000) {
 321         qemu_irq_raise(uic->irqs[PPCUIC_OUTPUT_CINT]);
 322         if (uic->use_vectors) {
 323             /* Compute critical IRQ vector */
 324             if (uic->uicvcr & 1) {
 325                 start = 31;
 326                 end = 0;
 327                 inc = -1;
 328             } else {
 329                 start = 0;
 330                 end = 31;
 331                 inc = 1;
 332             }
 333             uic->uicvr = uic->uicvcr & 0xFFFFFFFC;
 334             for (i = start; i <= end; i += inc) {
 335                 if (cr & (1 << i)) {
 336                     uic->uicvr += (i - start) * 512 * inc;
 337                     break;
 338                 }
 339             }
 340         }
 341         LOG_UIC("Raise UIC critical interrupt - "
 342                     "vector %08" PRIx32 "\n", uic->uicvr);
 343     } else {
 344         LOG_UIC("Lower UIC critical interrupt\n");
 345         qemu_irq_lower(uic->irqs[PPCUIC_OUTPUT_CINT]);
 346         uic->uicvr = 0x00000000;
 347     }
 348 }
 349
 350 static void ppcuic_set_irq (void *opaque, int irq_num, int level)
 351 {
 352     ppcuic_t *uic;
 353     uint32_t mask, sr;
 354
 355     uic = opaque;
 356     mask = 1 << (31-irq_num);
 357     LOG_UIC("%s: irq %d level %d uicsr %08" PRIx32
 358                 " mask %08" PRIx32 " => %08" PRIx32 " %08" PRIx32 "\n",
 359                 __func__, irq_num, level,
 360                 uic->uicsr, mask, uic->uicsr & mask, level << irq_num);
 361     if (irq_num < 0 || irq_num > 31)
 362         return;
 363     sr = uic->uicsr;
 364
 365     /* Update status register */
 366     if (uic->uictr & mask) {
 367         /* Edge sensitive interrupt */
 368         if (level == 1)
 369             uic->uicsr |= mask;
 370     } else {
 371         /* Level sensitive interrupt */
 372         if (level == 1) {
 373             uic->uicsr |= mask;
 374             uic->level |= mask;
 375         } else {
 376             uic->uicsr &= ~mask;
 377             uic->level &= ~mask;
 378         }
 379     }
 380     LOG_UIC("%s: irq %d level %d sr %" PRIx32 " => "
 381                 "%08" PRIx32 "\n", __func__, irq_num, level, uic->uicsr, sr);
 382     if (sr != uic->uicsr)
 383         ppcuic_trigger_irq(uic);
 384 }
 385
 386 static target_ulong dcr_read_uic (void *opaque, int dcrn)
 387 {
 388     ppcuic_t *uic;
 389     target_ulong ret;
 390
 391     uic = opaque;
 392     dcrn -= uic->dcr_base;
 393     switch (dcrn) {
 394     case DCR_UICSR:
 395     case DCR_UICSRS:
 396         ret = uic->uicsr;
 397         break;
 398     case DCR_UICER:
 399         ret = uic->uicer;
 400         break;
 401     case DCR_UICCR:
 402         ret = uic->uiccr;
 403         break;
 404     case DCR_UICPR:
 405         ret = uic->uicpr;
 406         break;
 407     case DCR_UICTR:
 408         ret = uic->uictr;
 409         break;
 410     case DCR_UICMSR:
 411         ret = uic->uicsr & uic->uicer;
 412         break;
 413     case DCR_UICVR:
 414         if (!uic->use_vectors)
 415             goto no_read;
 416         ret = uic->uicvr;
 417         break;
 418     case DCR_UICVCR:
 419         if (!uic->use_vectors)
 420             goto no_read;
 421         ret = uic->uicvcr;
 422         break;
 423     default:
 424     no_read:
 425         ret = 0x00000000;
 426         break;
 427     }
 428
 429     return ret;
 430 }
 431
 432 static void dcr_write_uic (void *opaque, int dcrn, target_ulong val)
 433 {
 434     ppcuic_t *uic;
 435
 436     uic = opaque;
 437     dcrn -= uic->dcr_base;
 438     LOG_UIC("%s: dcr %d val " ADDRX "\n", __func__, dcrn, val);
 439     switch (dcrn) {
 440     case DCR_UICSR:
 441         uic->uicsr &= ~val;
 442         uic->uicsr |= uic->level;
 443         ppcuic_trigger_irq(uic);
 444         break;
 445     case DCR_UICSRS:
 446         uic->uicsr |= val;
 447         ppcuic_trigger_irq(uic);
 448         break;
 449     case DCR_UICER:
 450         uic->uicer = val;
 451         ppcuic_trigger_irq(uic);
 452         break;
 453     case DCR_UICCR:
 454         uic->uiccr = val;
 455         ppcuic_trigger_irq(uic);
 456         break;
 457     case DCR_UICPR:
 458         uic->uicpr = val;
 459         break;
 460     case DCR_UICTR:
 461         uic->uictr = val;
 462         ppcuic_trigger_irq(uic);
 463         break;
 464     case DCR_UICMSR:
 465         break;
 466     case DCR_UICVR:
 467         break;
 468     case DCR_UICVCR:
 469         uic->uicvcr = val & 0xFFFFFFFD;
 470         ppcuic_trigger_irq(uic);
 471         break;
 472     }
 473 }
 474
 475 static void ppcuic_reset (void *opaque)
 476 {
 477     ppcuic_t *uic;
 478
 479     uic = opaque;
 480     uic->uiccr = 0x00000000;
 481     uic->uicer = 0x00000000;
 482     uic->uicpr = 0x00000000;
 483     uic->uicsr = 0x00000000;
 484     uic->uictr = 0x00000000;
 485     if (uic->use_vectors) {
 486         uic->uicvcr = 0x00000000;
 487         uic->uicvr = 0x0000000;
 488     }
 489 }
 490
 491 qemu_irq *ppcuic_init (CPUState *env, qemu_irq *irqs,
 492                        uint32_t dcr_base, int has_ssr, int has_vr)
 493 {
 494     ppcuic_t *uic;
 495     int i;
 496
 497     uic = qemu_mallocz(sizeof(ppcuic_t));
 498     if (uic != NULL) {
 499         uic->dcr_base = dcr_base;
 500         uic->irqs = irqs;
 501         if (has_vr)
 502             uic->use_vectors = 1;
 503         for (i = 0; i < DCR_UICMAX; i++) {
 504             ppc_dcr_register(env, dcr_base + i, uic,
 505                              &dcr_read_uic, &dcr_write_uic);
 506         }
 507         qemu_register_reset(ppcuic_reset, uic);
 508         ppcuic_reset(uic);
 509     }
 510
 511     return qemu_allocate_irqs(&ppcuic_set_irq, uic, UIC_MAX_IRQ);
 512 }
 513
 514 /*****************************************************************************/
 515 /* SDRAM controller */
 516 typedef struct ppc4xx_sdram_t ppc4xx_sdram_t;
 517 struct ppc4xx_sdram_t {
 518     uint32_t addr;
 519     int nbanks;
 520     target_phys_addr_t ram_bases[4];
 521     target_phys_addr_t ram_sizes[4];
 522     uint32_t besr0;
 523     uint32_t besr1;
 524     uint32_t bear;
 525     uint32_t cfg;
 526     uint32_t status;
 527     uint32_t rtr;
 528     uint32_t pmit;
 529     uint32_t bcr[4];
 530     uint32_t tr;
 531     uint32_t ecccfg;
 532     uint32_t eccesr;
 533     qemu_irq irq;
 534 };
 535
 536 enum {
 537     SDRAM0_CFGADDR = 0x010,
 538     SDRAM0_CFGDATA = 0x011,
 539 };
 540
 541 /* XXX: TOFIX: some patches have made this code become inconsistent:
 542  *      there are type inconsistencies, mixing target_phys_addr_t, target_ulong
 543  *      and uint32_t
 544  */
 545 static uint32_t sdram_bcr (target_phys_addr_t ram_base,
 546                            target_phys_addr_t ram_size)
 547 {
 548     uint32_t bcr;
 549
 550     switch (ram_size) {
 551     case (4 * 1024 * 1024):
 552         bcr = 0x00000000;
 553         break;
 554     case (8 * 1024 * 1024):
 555         bcr = 0x00020000;
 556         break;
 557     case (16 * 1024 * 1024):
 558         bcr = 0x00040000;
 559         break;
 560     case (32 * 1024 * 1024):
 561         bcr = 0x00060000;
 562         break;
 563     case (64 * 1024 * 1024):
 564         bcr = 0x00080000;
 565         break;
 566     case (128 * 1024 * 1024):
 567         bcr = 0x000A0000;
 568         break;
 569     case (256 * 1024 * 1024):
 570         bcr = 0x000C0000;
 571         break;
 572     default:
 573         printf("%s: invalid RAM size " PADDRX "\n", __func__, ram_size);
 574         return 0x00000000;
 575     }
 576     bcr |= ram_base & 0xFF800000;
 577     bcr |= 1;
 578
 579     return bcr;
 580 }
 581
 582 static always_inline target_phys_addr_t sdram_base (uint32_t bcr)
 583 {
 584     return bcr & 0xFF800000;
 585 }
 586
 587 static target_ulong sdram_size (uint32_t bcr)
 588 {
 589     target_ulong size;
 590     int sh;
 591
 592     sh = (bcr >> 17) & 0x7;
 593     if (sh == 7)
 594         size = -1;
 595     else
 596         size = (4 * 1024 * 1024) << sh;
 597
 598     return size;
 599 }
 600
 601 static void sdram_set_bcr (uint32_t *bcrp, uint32_t bcr, int enabled)
 602 {
 603     if (*bcrp & 0x00000001) {
 604         /* Unmap RAM */
 605 #ifdef DEBUG_SDRAM
 606         printf("%s: unmap RAM area " PADDRX " " ADDRX "\n",
 607                __func__, sdram_base(*bcrp), sdram_size(*bcrp));
 608 #endif
 609         cpu_register_physical_memory(sdram_base(*bcrp), sdram_size(*bcrp),
 610                                      IO_MEM_UNASSIGNED);
 611     }
 612     *bcrp = bcr & 0xFFDEE001;
 613     if (enabled && (bcr & 0x00000001)) {
 614 #ifdef DEBUG_SDRAM
 615         printf("%s: Map RAM area " PADDRX " " ADDRX "\n",
 616                __func__, sdram_base(bcr), sdram_size(bcr));
 617 #endif
 618         cpu_register_physical_memory(sdram_base(bcr), sdram_size(bcr),
 619                                      sdram_base(bcr) | IO_MEM_RAM);
 620     }
 621 }
 622
 623 static void sdram_map_bcr (ppc4xx_sdram_t *sdram)
 624 {
 625     int i;
 626
 627     for (i = 0; i < sdram->nbanks; i++) {
 628         if (sdram->ram_sizes[i] != 0) {
 629             sdram_set_bcr(&sdram->bcr[i],
 630                           sdram_bcr(sdram->ram_bases[i], sdram->ram_sizes[i]),
 631                           1);
 632         } else {
 633             sdram_set_bcr(&sdram->bcr[i], 0x00000000, 0);
 634         }
 635     }
 636 }
 637
 638 static void sdram_unmap_bcr (ppc4xx_sdram_t *sdram)
 639 {
 640     int i;
 641
 642     for (i = 0; i < sdram->nbanks; i++) {
 643 #ifdef DEBUG_SDRAM
 644         printf("%s: Unmap RAM area " PADDRX " " ADDRX "\n",
 645                __func__, sdram_base(sdram->bcr[i]), sdram_size(sdram->bcr[i]));
 646 #endif
 647         cpu_register_physical_memory(sdram_base(sdram->bcr[i]),
 648                                      sdram_size(sdram->bcr[i]),
 649                                      IO_MEM_UNASSIGNED);
 650     }
 651 }
 652
 653 static target_ulong dcr_read_sdram (void *opaque, int dcrn)
 654 {
 655     ppc4xx_sdram_t *sdram;
 656     target_ulong ret;
 657
 658     sdram = opaque;
 659     switch (dcrn) {
 660     case SDRAM0_CFGADDR:
 661         ret = sdram->addr;
 662         break;
 663     case SDRAM0_CFGDATA:
 664         switch (sdram->addr) {
 665         case 0x00: /* SDRAM_BESR0 */
 666             ret = sdram->besr0;
 667             break;
 668         case 0x08: /* SDRAM_BESR1 */
 669             ret = sdram->besr1;
 670             break;
 671         case 0x10: /* SDRAM_BEAR */
 672             ret = sdram->bear;
 673             break;
 674         case 0x20: /* SDRAM_CFG */
 675             ret = sdram->cfg;
 676             break;
 677         case 0x24: /* SDRAM_STATUS */
 678             ret = sdram->status;
 679             break;
 680         case 0x30: /* SDRAM_RTR */
 681             ret = sdram->rtr;
 682             break;
 683         case 0x34: /* SDRAM_PMIT */
 684             ret = sdram->pmit;
 685             break;
 686         case 0x40: /* SDRAM_B0CR */
 687             ret = sdram->bcr[0];
 688             break;
 689         case 0x44: /* SDRAM_B1CR */
 690             ret = sdram->bcr[1];
 691             break;
 692         case 0x48: /* SDRAM_B2CR */
 693             ret = sdram->bcr[2];
 694             break;
 695         case 0x4C: /* SDRAM_B3CR */
 696             ret = sdram->bcr[3];
 697             break;
 698         case 0x80: /* SDRAM_TR */
 699             ret = -1; /* ? */
 700             break;
 701         case 0x94: /* SDRAM_ECCCFG */
 702             ret = sdram->ecccfg;
 703             break;
 704         case 0x98: /* SDRAM_ECCESR */
 705             ret = sdram->eccesr;
 706             break;
 707         default: /* Error */
 708             ret = -1;
 709             break;
 710         }
 711         break;
 712     default:
 713         /* Avoid gcc warning */
 714         ret = 0x00000000;
 715         break;
 716     }
 717
 718     return ret;
 719 }
 720
 721 static void dcr_write_sdram (void *opaque, int dcrn, target_ulong val)
 722 {
 723     ppc4xx_sdram_t *sdram;
 724
 725     sdram = opaque;
 726     switch (dcrn) {
 727     case SDRAM0_CFGADDR:
 728         sdram->addr = val;
 729         break;
 730     case SDRAM0_CFGDATA:
 731         switch (sdram->addr) {
 732         case 0x00: /* SDRAM_BESR0 */
 733             sdram->besr0 &= ~val;
 734             break;
 735         case 0x08: /* SDRAM_BESR1 */
 736             sdram->besr1 &= ~val;
 737             break;
 738         case 0x10: /* SDRAM_BEAR */
 739             sdram->bear = val;
 740             break;
 741         case 0x20: /* SDRAM_CFG */
 742             val &= 0xFFE00000;
 743             if (!(sdram->cfg & 0x80000000) && (val & 0x80000000)) {
 744 #ifdef DEBUG_SDRAM
 745                 printf("%s: enable SDRAM controller\n", __func__);
 746 #endif
 747                 /* validate all RAM mappings */
 748                 sdram_map_bcr(sdram);
 749                 sdram->status &= ~0x80000000;
 750             } else if ((sdram->cfg & 0x80000000) && !(val & 0x80000000)) {
 751 #ifdef DEBUG_SDRAM
 752                 printf("%s: disable SDRAM controller\n", __func__);
 753 #endif
 754                 /* invalidate all RAM mappings */
 755                 sdram_unmap_bcr(sdram);
 756                 sdram->status |= 0x80000000;
 757             }
 758             if (!(sdram->cfg & 0x40000000) && (val & 0x40000000))
 759                 sdram->status |= 0x40000000;
 760             else if ((sdram->cfg & 0x40000000) && !(val & 0x40000000))
 761                 sdram->status &= ~0x40000000;
 762             sdram->cfg = val;
 763             break;
 764         case 0x24: /* SDRAM_STATUS */
 765             /* Read-only register */
 766             break;
 767         case 0x30: /* SDRAM_RTR */
 768             sdram->rtr = val & 0x3FF80000;
 769             break;
 770         case 0x34: /* SDRAM_PMIT */
 771             sdram->pmit = (val & 0xF8000000) | 0x07C00000;
 772             break;
 773         case 0x40: /* SDRAM_B0CR */
 774             sdram_set_bcr(&sdram->bcr[0], val, sdram->cfg & 0x80000000);
 775             break;
 776         case 0x44: /* SDRAM_B1CR */
 777             sdram_set_bcr(&sdram->bcr[1], val, sdram->cfg & 0x80000000);
 778             break;
 779         case 0x48: /* SDRAM_B2CR */
 780             sdram_set_bcr(&sdram->bcr[2], val, sdram->cfg & 0x80000000);
 781             break;
 782         case 0x4C: /* SDRAM_B3CR */
 783             sdram_set_bcr(&sdram->bcr[3], val, sdram->cfg & 0x80000000);
 784             break;
 785         case 0x80: /* SDRAM_TR */
 786             sdram->tr = val & 0x018FC01F;
 787             break;
 788         case 0x94: /* SDRAM_ECCCFG */
 789             sdram->ecccfg = val & 0x00F00000;
 790             break;
 791         case 0x98: /* SDRAM_ECCESR */
 792             val &= 0xFFF0F000;
 793             if (sdram->eccesr == 0 && val != 0)
 794                 qemu_irq_raise(sdram->irq);
 795             else if (sdram->eccesr != 0 && val == 0)
 796                 qemu_irq_lower(sdram->irq);
 797             sdram->eccesr = val;
 798             break;
 799         default: /* Error */
 800             break;
 801         }
 802         break;
 803     }
 804 }
 805
 806 static void sdram_reset (void *opaque)
 807 {
 808     ppc4xx_sdram_t *sdram;
 809
 810     sdram = opaque;
 811     sdram->addr = 0x00000000;
 812     sdram->bear = 0x00000000;
 813     sdram->besr0 = 0x00000000; /* No error */
 814     sdram->besr1 = 0x00000000; /* No error */
 815     sdram->cfg = 0x00000000;
 816     sdram->ecccfg = 0x00000000; /* No ECC */
 817     sdram->eccesr = 0x00000000; /* No error */
 818     sdram->pmit = 0x07C00000;
 819     sdram->rtr = 0x05F00000;
 820     sdram->tr = 0x00854009;
 821     /* We pre-initialize RAM banks */
 822     sdram->status = 0x00000000;
 823     sdram->cfg = 0x00800000;
 824     sdram_unmap_bcr(sdram);
 825 }
 826
 827 void ppc4xx_sdram_init (CPUState *env, qemu_irq irq, int nbanks,
 828                         target_phys_addr_t *ram_bases,
 829                         target_phys_addr_t *ram_sizes,
 830                         int do_init)
 831 {
 832     ppc4xx_sdram_t *sdram;
 833
 834     sdram = qemu_mallocz(sizeof(ppc4xx_sdram_t));
 835     if (sdram != NULL) {
 836         sdram->irq = irq;
 837         sdram->nbanks = nbanks;
 838         memset(sdram->ram_bases, 0, 4 * sizeof(target_phys_addr_t));
 839         memcpy(sdram->ram_bases, ram_bases,
 840                nbanks * sizeof(target_phys_addr_t));
 841         memset(sdram->ram_sizes, 0, 4 * sizeof(target_phys_addr_t));
 842         memcpy(sdram->ram_sizes, ram_sizes,
 843                nbanks * sizeof(target_phys_addr_t));
 844         sdram_reset(sdram);
 845         qemu_register_reset(&sdram_reset, sdram);
 846         ppc_dcr_register(env, SDRAM0_CFGADDR,
 847                          sdram, &dcr_read_sdram, &dcr_write_sdram);
 848         ppc_dcr_register(env, SDRAM0_CFGDATA,
 849                          sdram, &dcr_read_sdram, &dcr_write_sdram);
 850         if (do_init)
 851             sdram_map_bcr(sdram);
 852     }
 853 }
 854
 855 /* Fill in consecutive SDRAM banks with 'ram_size' bytes of memory.
 856  *
 857  * sdram_bank_sizes[] must be 0-terminated.
 858  *
 859  * The 4xx SDRAM controller supports a small number of banks, and each bank
 860  * must be one of a small set of sizes. The number of banks and the supported
 861  * sizes varies by SoC. */
 862 ram_addr_t ppc4xx_sdram_adjust(ram_addr_t ram_size, int nr_banks,
 863                                target_phys_addr_t ram_bases[],
 864                                target_phys_addr_t ram_sizes[],
 865                                const unsigned int sdram_bank_sizes[])
 866 {
 867     ram_addr_t ram_end = 0;
 868     int i;
 869     int j;
 870
 871     for (i = 0; i < nr_banks; i++) {
 872         for (j = 0; sdram_bank_sizes[j] != 0; j++) {
 873             unsigned int bank_size = sdram_bank_sizes[j];
 874
 875             if (bank_size <= ram_size) {
 876                 ram_bases[i] = ram_end;
 877                 ram_sizes[i] = bank_size;
 878                 ram_end += bank_size;
 879                 ram_size -= bank_size;
 880                 break;
 881             }
 882         }
 883
 884         if (!ram_size) {
 885             /* No need to use the remaining banks. */
 886             break;
 887         }
 888     }
 889
 890     if (ram_size)
 891         printf("Truncating memory to %d MiB to fit SDRAM controller limits.\n",
 892                (int)(ram_end >> 20));
 893
 894     return ram_end;
 895 }