target-ppc/cpu.h

   1 /*
   2  *  PowerPC emulation cpu definitions for qemu.
   3  *
   4  *  Copyright (c) 2003-2007 Jocelyn Mayer
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  19  */
  20 #if !defined (__CPU_PPC_H__)
  21 #define __CPU_PPC_H__
  22
  23 #include "config.h"
  24 #include <inttypes.h>
  25
  26 //#define PPC_EMULATE_32BITS_HYPV
  27
  28 #if defined (TARGET_PPC64)
  29 /* PowerPC 64 definitions */
  30 typedef uint64_t ppc_gpr_t;
  31 #define TARGET_LONG_BITS 64
  32 #define TARGET_PAGE_BITS 12
  33
  34 #else /* defined (TARGET_PPC64) */
  35 /* PowerPC 32 definitions */
  36 #if (HOST_LONG_BITS >= 64)
  37 /* When using 64 bits temporary registers,
  38  * we can use 64 bits GPR with no extra cost
  39  * It's even an optimization as this will prevent
  40  * the compiler to do unuseful masking in the micro-ops.
  41  */
  42 typedef uint64_t ppc_gpr_t;
  43 #else /* (HOST_LONG_BITS >= 64) */
  44 typedef uint32_t ppc_gpr_t;
  45 #endif /* (HOST_LONG_BITS >= 64) */
  46
  47 #define TARGET_LONG_BITS 32
  48
  49 #if defined(TARGET_PPCEMB)
  50 /* Specific definitions for PowerPC embedded */
  51 /* BookE have 36 bits physical address space */
  52 #define TARGET_PHYS_ADDR_BITS 64
  53 #if defined(CONFIG_USER_ONLY) || defined(USE_KVM)
  54 /* It looks like a lot of Linux programs assume page size
  55  * is 4kB long. This is evil, but we have to deal with it...
  56  * Also kvm for embedded powerpc needs (atm) 4kB aligned pages
  57  */
  58 #define TARGET_PAGE_BITS 12
  59 #else /* defined(CONFIG_USER_ONLY) */
  60 /* Pages can be 1 kB small */
  61 #define TARGET_PAGE_BITS 10
  62 #endif /* defined(CONFIG_USER_ONLY) */
  63 #else /* defined(TARGET_PPCEMB) */
  64 /* "standard" PowerPC 32 definitions */
  65 #define TARGET_PAGE_BITS 12
  66 #endif /* defined(TARGET_PPCEMB) */
  67
  68 #endif /* defined (TARGET_PPC64) */
  69
  70 #include "cpu-defs.h"
  71
  72 #define REGX "%016" PRIx64
  73 #define ADDRX TARGET_FMT_lx
  74 #define PADDRX TARGET_FMT_plx
  75
  76 #include <setjmp.h>
  77
  78 #include "softfloat.h"
  79
  80 #define TARGET_HAS_ICE 1
  81
  82 #if defined (TARGET_PPC64)
  83 #define ELF_MACHINE     EM_PPC64
  84 #else
  85 #define ELF_MACHINE     EM_PPC
  86 #endif
  87
  88 /*****************************************************************************/
  89 /* MMU model                                                                 */
  90 typedef enum powerpc_mmu_t powerpc_mmu_t;
  91 enum powerpc_mmu_t {
  92     POWERPC_MMU_UNKNOWN    = 0x00000000,
  93     /* Standard 32 bits PowerPC MMU                            */
  94     POWERPC_MMU_32B        = 0x00000001,
  95     /* PowerPC 6xx MMU with software TLB                       */
  96     POWERPC_MMU_SOFT_6xx   = 0x00000002,
  97     /* PowerPC 74xx MMU with software TLB                      */
  98     POWERPC_MMU_SOFT_74xx  = 0x00000003,
  99     /* PowerPC 4xx MMU with software TLB                       */
 100     POWERPC_MMU_SOFT_4xx   = 0x00000004,
 101     /* PowerPC 4xx MMU with software TLB and zones protections */
 102     POWERPC_MMU_SOFT_4xx_Z = 0x00000005,
 103     /* PowerPC MMU in real mode only                           */
 104     POWERPC_MMU_REAL       = 0x00000006,
 105     /* Freescale MPC8xx MMU model                              */
 106     POWERPC_MMU_MPC8xx     = 0x00000007,
 107     /* BookE MMU model                                         */
 108     POWERPC_MMU_BOOKE      = 0x00000008,
 109     /* BookE FSL MMU model                                     */
 110     POWERPC_MMU_BOOKE_FSL  = 0x00000009,
 111     /* PowerPC 601 MMU model (specific BATs format)            */
 112     POWERPC_MMU_601        = 0x0000000A,
 113 #if defined(TARGET_PPC64)
 114 #define POWERPC_MMU_64       0x00010000
 115     /* 64 bits PowerPC MMU                                     */
 116     POWERPC_MMU_64B        = POWERPC_MMU_64 | 0x00000001,
 117     /* 620 variant (no segment exceptions)                     */
 118     POWERPC_MMU_620        = POWERPC_MMU_64 | 0x00000002,
 119 #endif /* defined(TARGET_PPC64) */
 120 };
 121
 122 /*****************************************************************************/
 123 /* Exception model                                                           */
 124 typedef enum powerpc_excp_t powerpc_excp_t;
 125 enum powerpc_excp_t {
 126     POWERPC_EXCP_UNKNOWN   = 0,
 127     /* Standard PowerPC exception model */
 128     POWERPC_EXCP_STD,
 129     /* PowerPC 40x exception model      */
 130     POWERPC_EXCP_40x,
 131     /* PowerPC 601 exception model      */
 132     POWERPC_EXCP_601,
 133     /* PowerPC 602 exception model      */
 134     POWERPC_EXCP_602,
 135     /* PowerPC 603 exception model      */
 136     POWERPC_EXCP_603,
 137     /* PowerPC 603e exception model     */
 138     POWERPC_EXCP_603E,
 139     /* PowerPC G2 exception model       */
 140     POWERPC_EXCP_G2,
 141     /* PowerPC 604 exception model      */
 142     POWERPC_EXCP_604,
 143     /* PowerPC 7x0 exception model      */
 144     POWERPC_EXCP_7x0,
 145     /* PowerPC 7x5 exception model      */
 146     POWERPC_EXCP_7x5,
 147     /* PowerPC 74xx exception model     */
 148     POWERPC_EXCP_74xx,
 149     /* BookE exception model            */
 150     POWERPC_EXCP_BOOKE,
 151 #if defined(TARGET_PPC64)
 152     /* PowerPC 970 exception model      */
 153     POWERPC_EXCP_970,
 154 #endif /* defined(TARGET_PPC64) */
 155 };
 156
 157 /*****************************************************************************/
 158 /* Exception vectors definitions                                             */
 159 enum {
 160     POWERPC_EXCP_NONE    = -1,
 161     /* The 64 first entries are used by the PowerPC embedded specification   */
 162     POWERPC_EXCP_CRITICAL = 0,  /* Critical input                            */
 163     POWERPC_EXCP_MCHECK   = 1,  /* Machine check exception                   */
 164     POWERPC_EXCP_DSI      = 2,  /* Data storage exception                    */
 165     POWERPC_EXCP_ISI      = 3,  /* Instruction storage exception             */
 166     POWERPC_EXCP_EXTERNAL = 4,  /* External input                            */
 167     POWERPC_EXCP_ALIGN    = 5,  /* Alignment exception                       */
 168     POWERPC_EXCP_PROGRAM  = 6,  /* Program exception                         */
 169     POWERPC_EXCP_FPU      = 7,  /* Floating-point unavailable exception      */
 170     POWERPC_EXCP_SYSCALL  = 8,  /* System call exception                     */
 171     POWERPC_EXCP_APU      = 9,  /* Auxiliary processor unavailable           */
 172     POWERPC_EXCP_DECR     = 10, /* Decrementer exception                     */
 173     POWERPC_EXCP_FIT      = 11, /* Fixed-interval timer interrupt            */
 174     POWERPC_EXCP_WDT      = 12, /* Watchdog timer interrupt                  */
 175     POWERPC_EXCP_DTLB     = 13, /* Data TLB miss                             */
 176     POWERPC_EXCP_ITLB     = 14, /* Instruction TLB miss                      */
 177     POWERPC_EXCP_DEBUG    = 15, /* Debug interrupt                           */
 178     /* Vectors 16 to 31 are reserved                                         */
 179     POWERPC_EXCP_SPEU     = 32, /* SPE/embedded floating-point unavailable   */
 180     POWERPC_EXCP_EFPDI    = 33, /* Embedded floating-point data interrupt    */
 181     POWERPC_EXCP_EFPRI    = 34, /* Embedded floating-point round interrupt   */
 182     POWERPC_EXCP_EPERFM   = 35, /* Embedded performance monitor interrupt    */
 183     POWERPC_EXCP_DOORI    = 36, /* Embedded doorbell interrupt               */
 184     POWERPC_EXCP_DOORCI   = 37, /* Embedded doorbell critical interrupt      */
 185     /* Vectors 38 to 63 are reserved                                         */
 186     /* Exceptions defined in the PowerPC server specification                */
 187     POWERPC_EXCP_RESET    = 64, /* System reset exception                    */
 188     POWERPC_EXCP_DSEG     = 65, /* Data segment exception                    */
 189     POWERPC_EXCP_ISEG     = 66, /* Instruction segment exception             */
 190     POWERPC_EXCP_HDECR    = 67, /* Hypervisor decrementer exception          */
 191     POWERPC_EXCP_TRACE    = 68, /* Trace exception                           */
 192     POWERPC_EXCP_HDSI     = 69, /* Hypervisor data storage exception         */
 193     POWERPC_EXCP_HISI     = 70, /* Hypervisor instruction storage exception  */
 194     POWERPC_EXCP_HDSEG    = 71, /* Hypervisor data segment exception         */
 195     POWERPC_EXCP_HISEG    = 72, /* Hypervisor instruction segment exception  */
 196     POWERPC_EXCP_VPU      = 73, /* Vector unavailable exception              */
 197     /* 40x specific exceptions                                               */
 198     POWERPC_EXCP_PIT      = 74, /* Programmable interval timer interrupt     */
 199     /* 601 specific exceptions                                               */
 200     POWERPC_EXCP_IO       = 75, /* IO error exception                        */
 201     POWERPC_EXCP_RUNM     = 76, /* Run mode exception                        */
 202     /* 602 specific exceptions                                               */
 203     POWERPC_EXCP_EMUL     = 77, /* Emulation trap exception                  */
 204     /* 602/603 specific exceptions                                           */
 205     POWERPC_EXCP_IFTLB    = 78, /* Instruction fetch TLB miss                */
 206     POWERPC_EXCP_DLTLB    = 79, /* Data load TLB miss                        */
 207     POWERPC_EXCP_DSTLB    = 80, /* Data store TLB miss                       */
 208     /* Exceptions available on most PowerPC                                  */
 209     POWERPC_EXCP_FPA      = 81, /* Floating-point assist exception           */
 210     POWERPC_EXCP_DABR     = 82, /* Data address breakpoint                   */
 211     POWERPC_EXCP_IABR     = 83, /* Instruction address breakpoint            */
 212     POWERPC_EXCP_SMI      = 84, /* System management interrupt               */
 213     POWERPC_EXCP_PERFM    = 85, /* Embedded performance monitor interrupt    */
 214     /* 7xx/74xx specific exceptions                                          */
 215     POWERPC_EXCP_THERM    = 86, /* Thermal interrupt                         */
 216     /* 74xx specific exceptions                                              */
 217     POWERPC_EXCP_VPUA     = 87, /* Vector assist exception                   */
 218     /* 970FX specific exceptions                                             */
 219     POWERPC_EXCP_SOFTP    = 88, /* Soft patch exception                      */
 220     POWERPC_EXCP_MAINT    = 89, /* Maintenance exception                     */
 221     /* Freescale embeded cores specific exceptions                           */
 222     POWERPC_EXCP_MEXTBR   = 90, /* Maskable external breakpoint              */
 223     POWERPC_EXCP_NMEXTBR  = 91, /* Non maskable external breakpoint          */
 224     POWERPC_EXCP_ITLBE    = 92, /* Instruction TLB error                     */
 225     POWERPC_EXCP_DTLBE    = 93, /* Data TLB error                            */
 226     /* EOL                                                                   */
 227     POWERPC_EXCP_NB       = 96,
 228     /* Qemu exceptions: used internally during code translation              */
 229     POWERPC_EXCP_STOP         = 0x200, /* stop translation                   */
 230     POWERPC_EXCP_BRANCH       = 0x201, /* branch instruction                 */
 231     /* Qemu exceptions: special cases we want to stop translation            */
 232     POWERPC_EXCP_SYNC         = 0x202, /* context synchronizing instruction  */
 233     POWERPC_EXCP_SYSCALL_USER = 0x203, /* System call in user mode only      */
 234 };
 235
 236 /* Exceptions error codes                                                    */
 237 enum {
 238     /* Exception subtypes for POWERPC_EXCP_ALIGN                             */
 239     POWERPC_EXCP_ALIGN_FP      = 0x01,  /* FP alignment exception            */
 240     POWERPC_EXCP_ALIGN_LST     = 0x02,  /* Unaligned mult/extern load/store  */
 241     POWERPC_EXCP_ALIGN_LE      = 0x03,  /* Multiple little-endian access     */
 242     POWERPC_EXCP_ALIGN_PROT    = 0x04,  /* Access cross protection boundary  */
 243     POWERPC_EXCP_ALIGN_BAT     = 0x05,  /* Access cross a BAT/seg boundary   */
 244     POWERPC_EXCP_ALIGN_CACHE   = 0x06,  /* Impossible dcbz access            */
 245     /* Exception subtypes for POWERPC_EXCP_PROGRAM                           */
 246     /* FP exceptions                                                         */
 247     POWERPC_EXCP_FP            = 0x10,
 248     POWERPC_EXCP_FP_OX         = 0x01,  /* FP overflow                       */
 249     POWERPC_EXCP_FP_UX         = 0x02,  /* FP underflow                      */
 250     POWERPC_EXCP_FP_ZX         = 0x03,  /* FP divide by zero                 */
 251     POWERPC_EXCP_FP_XX         = 0x04,  /* FP inexact                        */
 252     POWERPC_EXCP_FP_VXSNAN     = 0x05,  /* FP invalid SNaN op                */
 253     POWERPC_EXCP_FP_VXISI      = 0x06,  /* FP invalid infinite subtraction   */
 254     POWERPC_EXCP_FP_VXIDI      = 0x07,  /* FP invalid infinite divide        */
 255     POWERPC_EXCP_FP_VXZDZ      = 0x08,  /* FP invalid zero divide            */
 256     POWERPC_EXCP_FP_VXIMZ      = 0x09,  /* FP invalid infinite * zero        */
 257     POWERPC_EXCP_FP_VXVC       = 0x0A,  /* FP invalid compare                */
 258     POWERPC_EXCP_FP_VXSOFT     = 0x0B,  /* FP invalid operation              */
 259     POWERPC_EXCP_FP_VXSQRT     = 0x0C,  /* FP invalid square root            */
 260     POWERPC_EXCP_FP_VXCVI      = 0x0D,  /* FP invalid integer conversion     */
 261     /* Invalid instruction                                                   */
 262     POWERPC_EXCP_INVAL         = 0x20,
 263     POWERPC_EXCP_INVAL_INVAL   = 0x01,  /* Invalid instruction               */
 264     POWERPC_EXCP_INVAL_LSWX    = 0x02,  /* Invalid lswx instruction          */
 265     POWERPC_EXCP_INVAL_SPR     = 0x03,  /* Invalid SPR access                */
 266     POWERPC_EXCP_INVAL_FP      = 0x04,  /* Unimplemented mandatory fp instr  */
 267     /* Privileged instruction                                                */
 268     POWERPC_EXCP_PRIV          = 0x30,
 269     POWERPC_EXCP_PRIV_OPC      = 0x01,  /* Privileged operation exception    */
 270     POWERPC_EXCP_PRIV_REG      = 0x02,  /* Privileged register exception     */
 271     /* Trap                                                                  */
 272     POWERPC_EXCP_TRAP          = 0x40,
 273 };
 274
 275 /*****************************************************************************/
 276 /* Input pins model                                                          */
 277 typedef enum powerpc_input_t powerpc_input_t;
 278 enum powerpc_input_t {
 279     PPC_FLAGS_INPUT_UNKNOWN = 0,
 280     /* PowerPC 6xx bus                  */
 281     PPC_FLAGS_INPUT_6xx,
 282     /* BookE bus                        */
 283     PPC_FLAGS_INPUT_BookE,
 284     /* PowerPC 405 bus                  */
 285     PPC_FLAGS_INPUT_405,
 286     /* PowerPC 970 bus                  */
 287     PPC_FLAGS_INPUT_970,
 288     /* PowerPC 401 bus                  */
 289     PPC_FLAGS_INPUT_401,
 290     /* Freescale RCPU bus               */
 291     PPC_FLAGS_INPUT_RCPU,
 292 };
 293
 294 #define PPC_INPUT(env) (env->bus_model)
 295
 296 /*****************************************************************************/
 297 typedef struct ppc_def_t ppc_def_t;
 298 typedef struct opc_handler_t opc_handler_t;
 299
 300 /*****************************************************************************/
 301 /* Types used to describe some PowerPC registers */
 302 typedef struct CPUPPCState CPUPPCState;
 303 typedef struct ppc_tb_t ppc_tb_t;
 304 typedef struct ppc_spr_t ppc_spr_t;
 305 typedef struct ppc_dcr_t ppc_dcr_t;
 306 typedef union ppc_avr_t ppc_avr_t;
 307 typedef union ppc_tlb_t ppc_tlb_t;
 308
 309 /* SPR access micro-ops generations callbacks */
 310 struct ppc_spr_t {
 311     void (*uea_read)(void *opaque, int spr_num);
 312     void (*uea_write)(void *opaque, int spr_num);
 313 #if !defined(CONFIG_USER_ONLY)
 314     void (*oea_read)(void *opaque, int spr_num);
 315     void (*oea_write)(void *opaque, int spr_num);
 316     void (*hea_read)(void *opaque, int spr_num);
 317     void (*hea_write)(void *opaque, int spr_num);
 318 #endif
 319     const unsigned char *name;
 320 };
 321
 322 /* Altivec registers (128 bits) */
 323 union ppc_avr_t {
 324     uint8_t u8[16];
 325     uint16_t u16[8];
 326     uint32_t u32[4];
 327     uint64_t u64[2];
 328 };
 329
 330 /* Software TLB cache */
 331 typedef struct ppc6xx_tlb_t ppc6xx_tlb_t;
 332 struct ppc6xx_tlb_t {
 333     target_ulong pte0;
 334     target_ulong pte1;
 335     target_ulong EPN;
 336 };
 337
 338 typedef struct ppcemb_tlb_t ppcemb_tlb_t;
 339 struct ppcemb_tlb_t {
 340     target_phys_addr_t RPN;
 341     target_ulong EPN;
 342     target_ulong PID;
 343     target_ulong size;
 344     uint32_t prot;
 345     uint32_t attr; /* Storage attributes */
 346 };
 347
 348 union ppc_tlb_t {
 349     ppc6xx_tlb_t tlb6;
 350     ppcemb_tlb_t tlbe;
 351 };
 352
 353 /*****************************************************************************/
 354 /* Machine state register bits definition                                    */
 355 #define MSR_SF   63 /* Sixty-four-bit mode                            hflags */
 356 #define MSR_TAG  62 /* Tag-active mode (POWERx ?)                            */
 357 #define MSR_ISF  61 /* Sixty-four-bit interrupt mode on 630                  */
 358 #define MSR_SHV  60 /* hypervisor state                               hflags */
 359 #define MSR_CM   31 /* Computation mode for BookE                     hflags */
 360 #define MSR_ICM  30 /* Interrupt computation mode for BookE                  */
 361 #define MSR_THV  29 /* hypervisor state for 32 bits PowerPC           hflags */
 362 #define MSR_UCLE 26 /* User-mode cache lock enable for BookE                 */
 363 #define MSR_VR   25 /* altivec available                            x hflags */
 364 #define MSR_SPE  25 /* SPE enable for BookE                         x hflags */
 365 #define MSR_AP   23 /* Access privilege state on 602                  hflags */
 366 #define MSR_SA   22 /* Supervisor access mode on 602                  hflags */
 367 #define MSR_KEY  19 /* key bit on 603e                                       */
 368 #define MSR_POW  18 /* Power management                                      */
 369 #define MSR_TGPR 17 /* TGPR usage on 602/603                        x        */
 370 #define MSR_CE   17 /* Critical interrupt enable on embedded PowerPC x       */
 371 #define MSR_ILE  16 /* Interrupt little-endian mode                          */
 372 #define MSR_EE   15 /* External interrupt enable                             */
 373 #define MSR_PR   14 /* Problem state                                  hflags */
 374 #define MSR_FP   13 /* Floating point available                       hflags */
 375 #define MSR_ME   12 /* Machine check interrupt enable                        */
 376 #define MSR_FE0  11 /* Floating point exception mode 0                hflags */
 377 #define MSR_SE   10 /* Single-step trace enable                     x hflags */
 378 #define MSR_DWE  10 /* Debug wait enable on 405                     x        */
 379 #define MSR_UBLE 10 /* User BTB lock enable on e500                 x        */
 380 #define MSR_BE   9  /* Branch trace enable                          x hflags */
 381 #define MSR_DE   9  /* Debug interrupts enable on embedded PowerPC  x        */
 382 #define MSR_FE1  8  /* Floating point exception mode 1                hflags */
 383 #define MSR_AL   7  /* AL bit on POWER                                       */
 384 #define MSR_EP   6  /* Exception prefix on 601                               */
 385 #define MSR_IR   5  /* Instruction relocate                                  */
 386 #define MSR_DR   4  /* Data relocate                                         */
 387 #define MSR_PE   3  /* Protection enable on 403                              */
 388 #define MSR_PX   2  /* Protection exclusive on 403                  x        */
 389 #define MSR_PMM  2  /* Performance monitor mark on POWER            x        */
 390 #define MSR_RI   1  /* Recoverable interrupt                        1        */
 391 #define MSR_LE   0  /* Little-endian mode                           1 hflags */
 392
 393 #define msr_sf   ((env->msr >> MSR_SF)   & 1)
 394 #define msr_isf  ((env->msr >> MSR_ISF)  & 1)
 395 #define msr_shv  ((env->msr >> MSR_SHV)  & 1)
 396 #define msr_cm   ((env->msr >> MSR_CM)   & 1)
 397 #define msr_icm  ((env->msr >> MSR_ICM)  & 1)
 398 #define msr_thv  ((env->msr >> MSR_THV)  & 1)
 399 #define msr_ucle ((env->msr >> MSR_UCLE) & 1)
 400 #define msr_vr   ((env->msr >> MSR_VR)   & 1)
 401 #define msr_spe  ((env->msr >> MSR_SPE)  & 1)
 402 #define msr_ap   ((env->msr >> MSR_AP)   & 1)
 403 #define msr_sa   ((env->msr >> MSR_SA)   & 1)
 404 #define msr_key  ((env->msr >> MSR_KEY)  & 1)
 405 #define msr_pow  ((env->msr >> MSR_POW)  & 1)
 406 #define msr_tgpr ((env->msr >> MSR_TGPR) & 1)
 407 #define msr_ce   ((env->msr >> MSR_CE)   & 1)
 408 #define msr_ile  ((env->msr >> MSR_ILE)  & 1)
 409 #define msr_ee   ((env->msr >> MSR_EE)   & 1)
 410 #define msr_pr   ((env->msr >> MSR_PR)   & 1)
 411 #define msr_fp   ((env->msr >> MSR_FP)   & 1)
 412 #define msr_me   ((env->msr >> MSR_ME)   & 1)
 413 #define msr_fe0  ((env->msr >> MSR_FE0)  & 1)
 414 #define msr_se   ((env->msr >> MSR_SE)   & 1)
 415 #define msr_dwe  ((env->msr >> MSR_DWE)  & 1)
 416 #define msr_uble ((env->msr >> MSR_UBLE) & 1)
 417 #define msr_be   ((env->msr >> MSR_BE)   & 1)
 418 #define msr_de   ((env->msr >> MSR_DE)   & 1)
 419 #define msr_fe1  ((env->msr >> MSR_FE1)  & 1)
 420 #define msr_al   ((env->msr >> MSR_AL)   & 1)
 421 #define msr_ep   ((env->msr >> MSR_EP)   & 1)
 422 #define msr_ir   ((env->msr >> MSR_IR)   & 1)
 423 #define msr_dr   ((env->msr >> MSR_DR)   & 1)
 424 #define msr_pe   ((env->msr >> MSR_PE)   & 1)
 425 #define msr_px   ((env->msr >> MSR_PX)   & 1)
 426 #define msr_pmm  ((env->msr >> MSR_PMM)  & 1)
 427 #define msr_ri   ((env->msr >> MSR_RI)   & 1)
 428 #define msr_le   ((env->msr >> MSR_LE)   & 1)
 429 /* Hypervisor bit is more specific */
 430 #if defined(TARGET_PPC64)
 431 #define MSR_HVB (1ULL << MSR_SHV)
 432 #define msr_hv  msr_shv
 433 #else
 434 #if defined(PPC_EMULATE_32BITS_HYPV)
 435 #define MSR_HVB (1ULL << MSR_THV)
 436 #define msr_hv  msr_thv
 437 #else
 438 #define MSR_HVB (0ULL)
 439 #define msr_hv  (0)
 440 #endif
 441 #endif
 442
 443 enum {
 444     POWERPC_FLAG_NONE     = 0x00000000,
 445     /* Flag for MSR bit 25 signification (VRE/SPE)                           */
 446     POWERPC_FLAG_SPE      = 0x00000001,
 447     POWERPC_FLAG_VRE      = 0x00000002,
 448     /* Flag for MSR bit 17 signification (TGPR/CE)                           */
 449     POWERPC_FLAG_TGPR     = 0x00000004,
 450     POWERPC_FLAG_CE       = 0x00000008,
 451     /* Flag for MSR bit 10 signification (SE/DWE/UBLE)                       */
 452     POWERPC_FLAG_SE       = 0x00000010,
 453     POWERPC_FLAG_DWE      = 0x00000020,
 454     POWERPC_FLAG_UBLE     = 0x00000040,
 455     /* Flag for MSR bit 9 signification (BE/DE)                              */
 456     POWERPC_FLAG_BE       = 0x00000080,
 457     POWERPC_FLAG_DE       = 0x00000100,
 458     /* Flag for MSR bit 2 signification (PX/PMM)                             */
 459     POWERPC_FLAG_PX       = 0x00000200,
 460     POWERPC_FLAG_PMM      = 0x00000400,
 461     /* Flag for special features                                             */
 462     /* Decrementer clock: RTC clock (POWER, 601) or bus clock                */
 463     POWERPC_FLAG_RTC_CLK  = 0x00010000,
 464     POWERPC_FLAG_BUS_CLK  = 0x00020000,
 465 };
 466
 467 /*****************************************************************************/
 468 /* Floating point status and control register                                */
 469 #define FPSCR_FX     31 /* Floating-point exception summary                  */
 470 #define FPSCR_FEX    30 /* Floating-point enabled exception summary          */
 471 #define FPSCR_VX     29 /* Floating-point invalid operation exception summ.  */
 472 #define FPSCR_OX     28 /* Floating-point overflow exception                 */
 473 #define FPSCR_UX     27 /* Floating-point underflow exception                */
 474 #define FPSCR_ZX     26 /* Floating-point zero divide exception              */
 475 #define FPSCR_XX     25 /* Floating-point inexact exception                  */
 476 #define FPSCR_VXSNAN 24 /* Floating-point invalid operation exception (sNan) */
 477 #define FPSCR_VXISI  23 /* Floating-point invalid operation exception (inf)  */
 478 #define FPSCR_VXIDI  22 /* Floating-point invalid operation exception (inf)  */
 479 #define FPSCR_VXZDZ  21 /* Floating-point invalid operation exception (zero) */
 480 #define FPSCR_VXIMZ  20 /* Floating-point invalid operation exception (inf)  */
 481 #define FPSCR_VXVC   19 /* Floating-point invalid operation exception (comp) */
 482 #define FPSCR_FR     18 /* Floating-point fraction rounded                   */
 483 #define FPSCR_FI     17 /* Floating-point fraction inexact                   */
 484 #define FPSCR_C      16 /* Floating-point result class descriptor            */
 485 #define FPSCR_FL     15 /* Floating-point less than or negative              */
 486 #define FPSCR_FG     14 /* Floating-point greater than or negative           */
 487 #define FPSCR_FE     13 /* Floating-point equal or zero                      */
 488 #define FPSCR_FU     12 /* Floating-point unordered or NaN                   */
 489 #define FPSCR_FPCC   12 /* Floating-point condition code                     */
 490 #define FPSCR_FPRF   12 /* Floating-point result flags                       */
 491 #define FPSCR_VXSOFT 10 /* Floating-point invalid operation exception (soft) */
 492 #define FPSCR_VXSQRT 9  /* Floating-point invalid operation exception (sqrt) */
 493 #define FPSCR_VXCVI  8  /* Floating-point invalid operation exception (int)  */
 494 #define FPSCR_VE     7  /* Floating-point invalid operation exception enable */
 495 #define FPSCR_OE     6  /* Floating-point overflow exception enable          */
 496 #define FPSCR_UE     5  /* Floating-point undeflow exception enable          */
 497 #define FPSCR_ZE     4  /* Floating-point zero divide exception enable       */
 498 #define FPSCR_XE     3  /* Floating-point inexact exception enable           */
 499 #define FPSCR_NI     2  /* Floating-point non-IEEE mode                      */
 500 #define FPSCR_RN1    1
 501 #define FPSCR_RN     0  /* Floating-point rounding control                   */
 502 #define fpscr_fex    (((env->fpscr) >> FPSCR_FEX)    & 0x1)
 503 #define fpscr_vx     (((env->fpscr) >> FPSCR_VX)     & 0x1)
 504 #define fpscr_ox     (((env->fpscr) >> FPSCR_OX)     & 0x1)
 505 #define fpscr_ux     (((env->fpscr) >> FPSCR_UX)     & 0x1)
 506 #define fpscr_zx     (((env->fpscr) >> FPSCR_ZX)     & 0x1)
 507 #define fpscr_xx     (((env->fpscr) >> FPSCR_XX)     & 0x1)
 508 #define fpscr_vxsnan (((env->fpscr) >> FPSCR_VXSNAN) & 0x1)
 509 #define fpscr_vxisi  (((env->fpscr) >> FPSCR_VXISI)  & 0x1)
 510 #define fpscr_vxidi  (((env->fpscr) >> FPSCR_VXIDI)  & 0x1)
 511 #define fpscr_vxzdz  (((env->fpscr) >> FPSCR_VXZDZ)  & 0x1)
 512 #define fpscr_vximz  (((env->fpscr) >> FPSCR_VXIMZ)  & 0x1)
 513 #define fpscr_vxvc   (((env->fpscr) >> FPSCR_VXVC)   & 0x1)
 514 #define fpscr_fpcc   (((env->fpscr) >> FPSCR_FPCC)   & 0xF)
 515 #define fpscr_vxsoft (((env->fpscr) >> FPSCR_VXSOFT) & 0x1)
 516 #define fpscr_vxsqrt (((env->fpscr) >> FPSCR_VXSQRT) & 0x1)
 517 #define fpscr_vxcvi  (((env->fpscr) >> FPSCR_VXCVI)  & 0x1)
 518 #define fpscr_ve     (((env->fpscr) >> FPSCR_VE)     & 0x1)
 519 #define fpscr_oe     (((env->fpscr) >> FPSCR_OE)     & 0x1)
 520 #define fpscr_ue     (((env->fpscr) >> FPSCR_UE)     & 0x1)
 521 #define fpscr_ze     (((env->fpscr) >> FPSCR_ZE)     & 0x1)
 522 #define fpscr_xe     (((env->fpscr) >> FPSCR_XE)     & 0x1)
 523 #define fpscr_ni     (((env->fpscr) >> FPSCR_NI)     & 0x1)
 524 #define fpscr_rn     (((env->fpscr) >> FPSCR_RN)     & 0x3)
 525 /* Invalid operation exception summary */
 526 #define fpscr_ix ((env->fpscr) & ((1 << FPSCR_VXSNAN) | (1 << FPSCR_VXISI)  | \
 527                                   (1 << FPSCR_VXIDI)  | (1 << FPSCR_VXZDZ)  | \
 528                                   (1 << FPSCR_VXIMZ)  | (1 << FPSCR_VXVC)   | \
 529                                   (1 << FPSCR_VXSOFT) | (1 << FPSCR_VXSQRT) | \
 530                                   (1 << FPSCR_VXCVI)))
 531 /* exception summary */
 532 #define fpscr_ex  (((env->fpscr) >> FPSCR_XX) & 0x1F)
 533 /* enabled exception summary */
 534 #define fpscr_eex (((env->fpscr) >> FPSCR_XX) & ((env->fpscr) >> FPSCR_XE) &  \
 535                    0x1F)
 536
 537 /*****************************************************************************/
 538 /* The whole PowerPC CPU context */
 539 #define NB_MMU_MODES 3
 540
 541 struct CPUPPCState {
 542     /* First are the most commonly used resources
 543      * during translated code execution
 544      */
 545 #if (HOST_LONG_BITS == 32)
 546     /* temporary fixed-point registers
 547      * used to emulate 64 bits registers on 32 bits hosts
 548      */
 549     uint64_t t0, t1, t2;
 550 #endif
 551     ppc_avr_t avr0, avr1, avr2;
 552
 553     /* general purpose registers */
 554     ppc_gpr_t gpr[32];
 555 #if !defined(TARGET_PPC64)
 556     /* Storage for GPR MSB, used by the SPE extension */
 557     ppc_gpr_t gprh[32];
 558 #endif
 559     /* LR */
 560     target_ulong lr;
 561     /* CTR */
 562     target_ulong ctr;
 563     /* condition register */
 564     uint8_t crf[8];
 565     /* XER */
 566     /* XXX: We use only 5 fields, but we want to keep the structure aligned */
 567     uint8_t xer[8];
 568     /* Reservation address */
 569     target_ulong reserve;
 570
 571     /* Those ones are used in supervisor mode only */
 572     /* machine state register */
 573     target_ulong msr;
 574     /* temporary general purpose registers */
 575     ppc_gpr_t tgpr[4]; /* Used to speed-up TLB assist handlers */
 576
 577     /* Floating point execution context */
 578     /* temporary float registers */
 579     float64 ft0;
 580     float64 ft1;
 581     float64 ft2;
 582     float_status fp_status;
 583     /* floating point registers */
 584     float64 fpr[32];
 585     /* floating point status and control register */
 586     uint32_t fpscr;
 587
 588     CPU_COMMON
 589
 590     int access_type; /* when a memory exception occurs, the access
 591                         type is stored here */
 592
 593     /* MMU context - only relevant for full system emulation */
 594 #if !defined(CONFIG_USER_ONLY)
 595 #if defined(TARGET_PPC64)
 596     /* Address space register */
 597     target_ulong asr;
 598     /* PowerPC 64 SLB area */
 599     int slb_nr;
 600 #endif
 601     /* segment registers */
 602     target_ulong sdr1;
 603     target_ulong sr[16];
 604     /* BATs */
 605     int nb_BATs;
 606     target_ulong DBAT[2][8];
 607     target_ulong IBAT[2][8];
 608     /* PowerPC TLB registers (for 4xx and 60x software driven TLBs) */
 609     int nb_tlb;      /* Total number of TLB                                  */
 610     int tlb_per_way; /* Speed-up helper: used to avoid divisions at run time */
 611     int nb_ways;     /* Number of ways in the TLB set                        */
 612     int last_way;    /* Last used way used to allocate TLB in a LRU way      */
 613     int id_tlbs;     /* If 1, MMU has separated TLBs for instructions & data */
 614     int nb_pids;     /* Number of available PID registers                    */
 615     ppc_tlb_t *tlb;  /* TLB is optional. Allocate them only if needed        */
 616     /* 403 dedicated access protection registers */
 617     target_ulong pb[4];
 618 #endif
 619
 620     /* Other registers */
 621     /* Special purpose registers */
 622     target_ulong spr[1024];
 623     ppc_spr_t spr_cb[1024];
 624     /* Altivec registers */
 625     ppc_avr_t avr[32];
 626     uint32_t vscr;
 627     /* SPE registers */
 628     ppc_gpr_t spe_acc;
 629     float_status spe_status;
 630     uint32_t spe_fscr;
 631
 632     /* Internal devices resources */
 633     /* Time base and decrementer */
 634     ppc_tb_t *tb_env;
 635     /* Device control registers */
 636     ppc_dcr_t *dcr_env;
 637
 638     int dcache_line_size;
 639     int icache_line_size;
 640
 641     /* Those resources are used during exception processing */
 642     /* CPU model definition */
 643     target_ulong msr_mask;
 644     powerpc_mmu_t mmu_model;
 645     powerpc_excp_t excp_model;
 646     powerpc_input_t bus_model;
 647     int bfd_mach;
 648     uint32_t flags;
 649
 650     int error_code;
 651     uint32_t pending_interrupts;
 652 #if !defined(CONFIG_USER_ONLY)
 653     /* This is the IRQ controller, which is implementation dependant
 654      * and only relevant when emulating a complete machine.
 655      */
 656     uint32_t irq_input_state;
 657     void **irq_inputs;
 658     /* Exception vectors */
 659     target_ulong excp_vectors[POWERPC_EXCP_NB];
 660     target_ulong excp_prefix;
 661     target_ulong ivor_mask;
 662     target_ulong ivpr_mask;
 663     target_ulong hreset_vector;
 664 #endif
 665
 666     /* Those resources are used only during code translation */
 667     /* Next instruction pointer */
 668     target_ulong nip;
 669
 670     /* opcode handlers */
 671     opc_handler_t *opcodes[0x40];
 672
 673     /* Those resources are used only in Qemu core */
 674     target_ulong hflags;      /* hflags is a MSR & HFLAGS_MASK         */
 675     target_ulong hflags_nmsr; /* specific hflags, not comming from MSR */
 676     int mmu_idx;         /* precomputed MMU index to speed up mem accesses */
 677
 678     /* Power management */
 679     int power_mode;
 680     int (*check_pow)(CPUPPCState *env);
 681
 682     /* temporary hack to handle OSI calls (only used if non NULL) */
 683     int (*osi_call)(struct CPUPPCState *env);
 684 };
 685
 686 /* Context used internally during MMU translations */
 687 typedef struct mmu_ctx_t mmu_ctx_t;
 688 struct mmu_ctx_t {
 689     target_phys_addr_t raddr;      /* Real address              */
 690     int prot;                      /* Protection bits           */
 691     target_phys_addr_t pg_addr[2]; /* PTE tables base addresses */
 692     target_ulong ptem;             /* Virtual segment ID | API  */
 693     int key;                       /* Access key                */
 694     int nx;                        /* Non-execute area          */
 695 };
 696
 697 /*****************************************************************************/
 698 CPUPPCState *cpu_ppc_init (const char *cpu_model);
 699 void ppc_translate_init(void);
 700 int cpu_ppc_exec (CPUPPCState *s);
 701 void cpu_ppc_close (CPUPPCState *s);
 702 /* you can call this signal handler from your SIGBUS and SIGSEGV
 703    signal handlers to inform the virtual CPU of exceptions. non zero
 704    is returned if the signal was handled by the virtual CPU.  */
 705 int cpu_ppc_signal_handler (int host_signum, void *pinfo,
 706                             void *puc);
 707
 708 void do_interrupt (CPUPPCState *env);
 709 void ppc_hw_interrupt (CPUPPCState *env);
 710 void cpu_loop_exit (void);
 711
 712 void dump_stack (CPUPPCState *env);
 713
 714 #if !defined(CONFIG_USER_ONLY)
 715 target_ulong do_load_ibatu (CPUPPCState *env, int nr);
 716 target_ulong do_load_ibatl (CPUPPCState *env, int nr);
 717 void do_store_ibatu (CPUPPCState *env, int nr, target_ulong value);
 718 void do_store_ibatl (CPUPPCState *env, int nr, target_ulong value);
 719 target_ulong do_load_dbatu (CPUPPCState *env, int nr);
 720 target_ulong do_load_dbatl (CPUPPCState *env, int nr);
 721 void do_store_dbatu (CPUPPCState *env, int nr, target_ulong value);
 722 void do_store_dbatl (CPUPPCState *env, int nr, target_ulong value);
 723 void do_store_ibatu_601 (CPUPPCState *env, int nr, target_ulong value);
 724 void do_store_ibatl_601 (CPUPPCState *env, int nr, target_ulong value);
 725 target_ulong do_load_sdr1 (CPUPPCState *env);
 726 void do_store_sdr1 (CPUPPCState *env, target_ulong value);
 727 #if defined(TARGET_PPC64)
 728 target_ulong ppc_load_asr (CPUPPCState *env);
 729 void ppc_store_asr (CPUPPCState *env, target_ulong value);
 730 target_ulong ppc_load_slb (CPUPPCState *env, int slb_nr);
 731 void ppc_store_slb (CPUPPCState *env, int slb_nr, target_ulong rs);
 732 #endif /* defined(TARGET_PPC64) */
 733 #if 0 // Unused
 734 target_ulong do_load_sr (CPUPPCState *env, int srnum);
 735 #endif
 736 void do_store_sr (CPUPPCState *env, int srnum, target_ulong value);
 737 #endif /* !defined(CONFIG_USER_ONLY) */
 738 target_ulong ppc_load_xer (CPUPPCState *env);
 739 void ppc_store_xer (CPUPPCState *env, target_ulong value);
 740 void ppc_store_msr (CPUPPCState *env, target_ulong value);
 741
 742 void cpu_ppc_reset (void *opaque);
 743
 744 void ppc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...));
 745
 746 const ppc_def_t *cpu_ppc_find_by_name (const unsigned char *name);
 747 int cpu_ppc_register_internal (CPUPPCState *env, const ppc_def_t *def);
 748
 749 /* Time-base and decrementer management */
 750 #ifndef NO_CPU_IO_DEFS
 751 uint32_t cpu_ppc_load_tbl (CPUPPCState *env);
 752 uint32_t cpu_ppc_load_tbu (CPUPPCState *env);
 753 void cpu_ppc_store_tbu (CPUPPCState *env, uint32_t value);
 754 void cpu_ppc_store_tbl (CPUPPCState *env, uint32_t value);
 755 uint32_t cpu_ppc_load_atbl (CPUPPCState *env);
 756 uint32_t cpu_ppc_load_atbu (CPUPPCState *env);
 757 void cpu_ppc_store_atbl (CPUPPCState *env, uint32_t value);
 758 void cpu_ppc_store_atbu (CPUPPCState *env, uint32_t value);
 759 uint32_t cpu_ppc_load_decr (CPUPPCState *env);
 760 void cpu_ppc_store_decr (CPUPPCState *env, uint32_t value);
 761 uint32_t cpu_ppc_load_hdecr (CPUPPCState *env);
 762 void cpu_ppc_store_hdecr (CPUPPCState *env, uint32_t value);
 763 uint64_t cpu_ppc_load_purr (CPUPPCState *env);
 764 void cpu_ppc_store_purr (CPUPPCState *env, uint64_t value);
 765 uint32_t cpu_ppc601_load_rtcl (CPUPPCState *env);
 766 uint32_t cpu_ppc601_load_rtcu (CPUPPCState *env);
 767 #if !defined(CONFIG_USER_ONLY)
 768 void cpu_ppc601_store_rtcl (CPUPPCState *env, uint32_t value);
 769 void cpu_ppc601_store_rtcu (CPUPPCState *env, uint32_t value);
 770 target_ulong load_40x_pit (CPUPPCState *env);
 771 void store_40x_pit (CPUPPCState *env, target_ulong val);
 772 void store_40x_dbcr0 (CPUPPCState *env, uint32_t val);
 773 void store_40x_sler (CPUPPCState *env, uint32_t val);
 774 void store_booke_tcr (CPUPPCState *env, target_ulong val);
 775 void store_booke_tsr (CPUPPCState *env, target_ulong val);
 776 void ppc_tlb_invalidate_all (CPUPPCState *env);
 777 void ppc_tlb_invalidate_one (CPUPPCState *env, target_ulong addr);
 778 #if defined(TARGET_PPC64)
 779 void ppc_slb_invalidate_all (CPUPPCState *env);
 780 void ppc_slb_invalidate_one (CPUPPCState *env, uint64_t T0);
 781 #endif
 782 int ppcemb_tlb_search (CPUPPCState *env, target_ulong address, uint32_t pid);
 783 #endif
 784 #endif
 785
 786 static always_inline uint64_t ppc_dump_gpr (CPUPPCState *env, int gprn)
 787 {
 788     uint64_t gprv;
 789
 790     gprv = env->gpr[gprn];
 791 #if !defined(TARGET_PPC64)
 792     if (env->flags & POWERPC_FLAG_SPE) {
 793         /* If the CPU implements the SPE extension, we have to get the
 794          * high bits of the GPR from the gprh storage area
 795          */
 796         gprv &= 0xFFFFFFFFULL;
 797         gprv |= (uint64_t)env->gprh[gprn] << 32;
 798     }
 799 #endif
 800
 801     return gprv;
 802 }
 803
 804 /* Device control registers */
 805 int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, target_ulong *valp);
 806 int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, target_ulong val);
 807
 808 #define CPUState CPUPPCState
 809 #define cpu_init cpu_ppc_init
 810 #define cpu_exec cpu_ppc_exec
 811 #define cpu_gen_code cpu_ppc_gen_code
 812 #define cpu_signal_handler cpu_ppc_signal_handler
 813 #define cpu_list ppc_cpu_list
 814
 815 #define CPU_SAVE_VERSION 3
 816
 817 /* MMU modes definitions */
 818 #define MMU_MODE0_SUFFIX _user
 819 #define MMU_MODE1_SUFFIX _kernel
 820 #define MMU_MODE2_SUFFIX _hypv
 821 #define MMU_USER_IDX 0
 822 static inline int cpu_mmu_index (CPUState *env)
 823 {
 824     return env->mmu_idx;
 825 }
 826
 827 #if defined(CONFIG_USER_ONLY)
 828 static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
 829 {
 830     int i;
 831     if (newsp)
 832         env->gpr[1] = newsp;
 833     for (i = 7; i < 32; i++)
 834         env->gpr[i] = 0;
 835 }
 836 #endif
 837
 838 #define CPU_PC_FROM_TB(env, tb) env->nip = tb->pc
 839
 840 #include "cpu-all.h"
 841
 842 /*****************************************************************************/
 843 /* Registers definitions */
 844 #define XER_SO 31
 845 #define XER_OV 30
 846 #define XER_CA 29
 847 #define XER_CMP 8
 848 #define XER_BC  0
 849 #define xer_so  env->xer[4]
 850 #define xer_ov  env->xer[6]
 851 #define xer_ca  env->xer[2]
 852 #define xer_cmp env->xer[1]
 853 #define xer_bc  env->xer[0]
 854
 855 /* SPR definitions */
 856 #define SPR_MQ                (0x000)
 857 #define SPR_XER               (0x001)
 858 #define SPR_601_VRTCU         (0x004)
 859 #define SPR_601_VRTCL         (0x005)
 860 #define SPR_601_UDECR         (0x006)
 861 #define SPR_LR                (0x008)
 862 #define SPR_CTR               (0x009)
 863 #define SPR_DSISR             (0x012)
 864 #define SPR_DAR               (0x013) /* DAE for PowerPC 601 */
 865 #define SPR_601_RTCU          (0x014)
 866 #define SPR_601_RTCL          (0x015)
 867 #define SPR_DECR              (0x016)
 868 #define SPR_SDR1              (0x019)
 869 #define SPR_SRR0              (0x01A)
 870 #define SPR_SRR1              (0x01B)
 871 #define SPR_AMR               (0x01D)
 872 #define SPR_BOOKE_PID         (0x030)
 873 #define SPR_BOOKE_DECAR       (0x036)
 874 #define SPR_BOOKE_CSRR0       (0x03A)
 875 #define SPR_BOOKE_CSRR1       (0x03B)
 876 #define SPR_BOOKE_DEAR        (0x03D)
 877 #define SPR_BOOKE_ESR         (0x03E)
 878 #define SPR_BOOKE_IVPR        (0x03F)
 879 #define SPR_MPC_EIE           (0x050)
 880 #define SPR_MPC_EID           (0x051)
 881 #define SPR_MPC_NRI           (0x052)
 882 #define SPR_CTRL              (0x088)
 883 #define SPR_MPC_CMPA          (0x090)
 884 #define SPR_MPC_CMPB          (0x091)
 885 #define SPR_MPC_CMPC          (0x092)
 886 #define SPR_MPC_CMPD          (0x093)
 887 #define SPR_MPC_ECR           (0x094)
 888 #define SPR_MPC_DER           (0x095)
 889 #define SPR_MPC_COUNTA        (0x096)
 890 #define SPR_MPC_COUNTB        (0x097)
 891 #define SPR_UCTRL             (0x098)
 892 #define SPR_MPC_CMPE          (0x098)
 893 #define SPR_MPC_CMPF          (0x099)
 894 #define SPR_MPC_CMPG          (0x09A)
 895 #define SPR_MPC_CMPH          (0x09B)
 896 #define SPR_MPC_LCTRL1        (0x09C)
 897 #define SPR_MPC_LCTRL2        (0x09D)
 898 #define SPR_MPC_ICTRL         (0x09E)
 899 #define SPR_MPC_BAR           (0x09F)
 900 #define SPR_VRSAVE            (0x100)
 901 #define SPR_USPRG0            (0x100)
 902 #define SPR_USPRG1            (0x101)
 903 #define SPR_USPRG2            (0x102)
 904 #define SPR_USPRG3            (0x103)
 905 #define SPR_USPRG4            (0x104)
 906 #define SPR_USPRG5            (0x105)
 907 #define SPR_USPRG6            (0x106)
 908 #define SPR_USPRG7            (0x107)
 909 #define SPR_VTBL              (0x10C)
 910 #define SPR_VTBU              (0x10D)
 911 #define SPR_SPRG0             (0x110)
 912 #define SPR_SPRG1             (0x111)
 913 #define SPR_SPRG2             (0x112)
 914 #define SPR_SPRG3             (0x113)
 915 #define SPR_SPRG4             (0x114)
 916 #define SPR_SCOMC             (0x114)
 917 #define SPR_SPRG5             (0x115)
 918 #define SPR_SCOMD             (0x115)
 919 #define SPR_SPRG6             (0x116)
 920 #define SPR_SPRG7             (0x117)
 921 #define SPR_ASR               (0x118)
 922 #define SPR_EAR               (0x11A)
 923 #define SPR_TBL               (0x11C)
 924 #define SPR_TBU               (0x11D)
 925 #define SPR_TBU40             (0x11E)
 926 #define SPR_SVR               (0x11E)
 927 #define SPR_BOOKE_PIR         (0x11E)
 928 #define SPR_PVR               (0x11F)
 929 #define SPR_HSPRG0            (0x130)
 930 #define SPR_BOOKE_DBSR        (0x130)
 931 #define SPR_HSPRG1            (0x131)
 932 #define SPR_HDSISR            (0x132)
 933 #define SPR_HDAR              (0x133)
 934 #define SPR_BOOKE_DBCR0       (0x134)
 935 #define SPR_IBCR              (0x135)
 936 #define SPR_PURR              (0x135)
 937 #define SPR_BOOKE_DBCR1       (0x135)
 938 #define SPR_DBCR              (0x136)
 939 #define SPR_HDEC              (0x136)
 940 #define SPR_BOOKE_DBCR2       (0x136)
 941 #define SPR_HIOR              (0x137)
 942 #define SPR_MBAR              (0x137)
 943 #define SPR_RMOR              (0x138)
 944 #define SPR_BOOKE_IAC1        (0x138)
 945 #define SPR_HRMOR             (0x139)
 946 #define SPR_BOOKE_IAC2        (0x139)
 947 #define SPR_HSRR0             (0x13A)
 948 #define SPR_BOOKE_IAC3        (0x13A)
 949 #define SPR_HSRR1             (0x13B)
 950 #define SPR_BOOKE_IAC4        (0x13B)
 951 #define SPR_LPCR              (0x13C)
 952 #define SPR_BOOKE_DAC1        (0x13C)
 953 #define SPR_LPIDR             (0x13D)
 954 #define SPR_DABR2             (0x13D)
 955 #define SPR_BOOKE_DAC2        (0x13D)
 956 #define SPR_BOOKE_DVC1        (0x13E)
 957 #define SPR_BOOKE_DVC2        (0x13F)
 958 #define SPR_BOOKE_TSR         (0x150)
 959 #define SPR_BOOKE_TCR         (0x154)
 960 #define SPR_BOOKE_IVOR0       (0x190)
 961 #define SPR_BOOKE_IVOR1       (0x191)
 962 #define SPR_BOOKE_IVOR2       (0x192)
 963 #define SPR_BOOKE_IVOR3       (0x193)
 964 #define SPR_BOOKE_IVOR4       (0x194)
 965 #define SPR_BOOKE_IVOR5       (0x195)
 966 #define SPR_BOOKE_IVOR6       (0x196)
 967 #define SPR_BOOKE_IVOR7       (0x197)
 968 #define SPR_BOOKE_IVOR8       (0x198)
 969 #define SPR_BOOKE_IVOR9       (0x199)
 970 #define SPR_BOOKE_IVOR10      (0x19A)
 971 #define SPR_BOOKE_IVOR11      (0x19B)
 972 #define SPR_BOOKE_IVOR12      (0x19C)
 973 #define SPR_BOOKE_IVOR13      (0x19D)
 974 #define SPR_BOOKE_IVOR14      (0x19E)
 975 #define SPR_BOOKE_IVOR15      (0x19F)
 976 #define SPR_BOOKE_SPEFSCR     (0x200)
 977 #define SPR_Exxx_BBEAR        (0x201)
 978 #define SPR_Exxx_BBTAR        (0x202)
 979 #define SPR_Exxx_L1CFG0       (0x203)
 980 #define SPR_Exxx_NPIDR        (0x205)
 981 #define SPR_ATBL              (0x20E)
 982 #define SPR_ATBU              (0x20F)
 983 #define SPR_IBAT0U            (0x210)
 984 #define SPR_BOOKE_IVOR32      (0x210)
 985 #define SPR_RCPU_MI_GRA       (0x210)
 986 #define SPR_IBAT0L            (0x211)
 987 #define SPR_BOOKE_IVOR33      (0x211)
 988 #define SPR_IBAT1U            (0x212)
 989 #define SPR_BOOKE_IVOR34      (0x212)
 990 #define SPR_IBAT1L            (0x213)
 991 #define SPR_BOOKE_IVOR35      (0x213)
 992 #define SPR_IBAT2U            (0x214)
 993 #define SPR_BOOKE_IVOR36      (0x214)
 994 #define SPR_IBAT2L            (0x215)
 995 #define SPR_BOOKE_IVOR37      (0x215)
 996 #define SPR_IBAT3U            (0x216)
 997 #define SPR_IBAT3L            (0x217)
 998 #define SPR_DBAT0U            (0x218)
 999 #define SPR_RCPU_L2U_GRA      (0x218)
1000 #define SPR_DBAT0L            (0x219)
1001 #define SPR_DBAT1U            (0x21A)
1002 #define SPR_DBAT1L            (0x21B)
1003 #define SPR_DBAT2U            (0x21C)
1004 #define SPR_DBAT2L            (0x21D)
1005 #define SPR_DBAT3U            (0x21E)
1006 #define SPR_DBAT3L            (0x21F)
1007 #define SPR_IBAT4U            (0x230)
1008 #define SPR_RPCU_BBCMCR       (0x230)
1009 #define SPR_MPC_IC_CST        (0x230)
1010 #define SPR_Exxx_CTXCR        (0x230)
1011 #define SPR_IBAT4L            (0x231)
1012 #define SPR_MPC_IC_ADR        (0x231)
1013 #define SPR_Exxx_DBCR3        (0x231)
1014 #define SPR_IBAT5U            (0x232)
1015 #define SPR_MPC_IC_DAT        (0x232)
1016 #define SPR_Exxx_DBCNT        (0x232)
1017 #define SPR_IBAT5L            (0x233)
1018 #define SPR_IBAT6U            (0x234)
1019 #define SPR_IBAT6L            (0x235)
1020 #define SPR_IBAT7U            (0x236)
1021 #define SPR_IBAT7L            (0x237)
1022 #define SPR_DBAT4U            (0x238)
1023 #define SPR_RCPU_L2U_MCR      (0x238)
1024 #define SPR_MPC_DC_CST        (0x238)
1025 #define SPR_Exxx_ALTCTXCR     (0x238)
1026 #define SPR_DBAT4L            (0x239)
1027 #define SPR_MPC_DC_ADR        (0x239)
1028 #define SPR_DBAT5U            (0x23A)
1029 #define SPR_BOOKE_MCSRR0      (0x23A)
1030 #define SPR_MPC_DC_DAT        (0x23A)
1031 #define SPR_DBAT5L            (0x23B)
1032 #define SPR_BOOKE_MCSRR1      (0x23B)
1033 #define SPR_DBAT6U            (0x23C)
1034 #define SPR_BOOKE_MCSR        (0x23C)
1035 #define SPR_DBAT6L            (0x23D)
1036 #define SPR_Exxx_MCAR         (0x23D)
1037 #define SPR_DBAT7U            (0x23E)
1038 #define SPR_BOOKE_DSRR0       (0x23E)
1039 #define SPR_DBAT7L            (0x23F)
1040 #define SPR_BOOKE_DSRR1       (0x23F)
1041 #define SPR_BOOKE_SPRG8       (0x25C)
1042 #define SPR_BOOKE_SPRG9       (0x25D)
1043 #define SPR_BOOKE_MAS0        (0x270)
1044 #define SPR_BOOKE_MAS1        (0x271)
1045 #define SPR_BOOKE_MAS2        (0x272)
1046 #define SPR_BOOKE_MAS3        (0x273)
1047 #define SPR_BOOKE_MAS4        (0x274)
1048 #define SPR_BOOKE_MAS5        (0x275)
1049 #define SPR_BOOKE_MAS6        (0x276)
1050 #define SPR_BOOKE_PID1        (0x279)
1051 #define SPR_BOOKE_PID2        (0x27A)
1052 #define SPR_MPC_DPDR          (0x280)
1053 #define SPR_MPC_IMMR          (0x288)
1054 #define SPR_BOOKE_TLB0CFG     (0x2B0)
1055 #define SPR_BOOKE_TLB1CFG     (0x2B1)
1056 #define SPR_BOOKE_TLB2CFG     (0x2B2)
1057 #define SPR_BOOKE_TLB3CFG     (0x2B3)
1058 #define SPR_BOOKE_EPR         (0x2BE)
1059 #define SPR_PERF0             (0x300)
1060 #define SPR_RCPU_MI_RBA0      (0x300)
1061 #define SPR_MPC_MI_CTR        (0x300)
1062 #define SPR_PERF1             (0x301)
1063 #define SPR_RCPU_MI_RBA1      (0x301)
1064 #define SPR_PERF2             (0x302)
1065 #define SPR_RCPU_MI_RBA2      (0x302)
1066 #define SPR_MPC_MI_AP         (0x302)
1067 #define SPR_PERF3             (0x303)
1068 #define SPR_620_PMC1R         (0x303)
1069 #define SPR_RCPU_MI_RBA3      (0x303)
1070 #define SPR_MPC_MI_EPN        (0x303)
1071 #define SPR_PERF4             (0x304)
1072 #define SPR_620_PMC2R         (0x304)
1073 #define SPR_PERF5             (0x305)
1074 #define SPR_MPC_MI_TWC        (0x305)
1075 #define SPR_PERF6             (0x306)
1076 #define SPR_MPC_MI_RPN        (0x306)
1077 #define SPR_PERF7             (0x307)
1078 #define SPR_PERF8             (0x308)
1079 #define SPR_RCPU_L2U_RBA0     (0x308)
1080 #define SPR_MPC_MD_CTR        (0x308)
1081 #define SPR_PERF9             (0x309)
1082 #define SPR_RCPU_L2U_RBA1     (0x309)
1083 #define SPR_MPC_MD_CASID      (0x309)
1084 #define SPR_PERFA             (0x30A)
1085 #define SPR_RCPU_L2U_RBA2     (0x30A)
1086 #define SPR_MPC_MD_AP         (0x30A)
1087 #define SPR_PERFB             (0x30B)
1088 #define SPR_620_MMCR0R        (0x30B)
1089 #define SPR_RCPU_L2U_RBA3     (0x30B)
1090 #define SPR_MPC_MD_EPN        (0x30B)
1091 #define SPR_PERFC             (0x30C)
1092 #define SPR_MPC_MD_TWB        (0x30C)
1093 #define SPR_PERFD             (0x30D)
1094 #define SPR_MPC_MD_TWC        (0x30D)
1095 #define SPR_PERFE             (0x30E)
1096 #define SPR_MPC_MD_RPN        (0x30E)
1097 #define SPR_PERFF             (0x30F)
1098 #define SPR_MPC_MD_TW         (0x30F)
1099 #define SPR_UPERF0            (0x310)
1100 #define SPR_UPERF1            (0x311)
1101 #define SPR_UPERF2            (0x312)
1102 #define SPR_UPERF3            (0x313)
1103 #define SPR_620_PMC1W         (0x313)
1104 #define SPR_UPERF4            (0x314)
1105 #define SPR_620_PMC2W         (0x314)
1106 #define SPR_UPERF5            (0x315)
1107 #define SPR_UPERF6            (0x316)
1108 #define SPR_UPERF7            (0x317)
1109 #define SPR_UPERF8            (0x318)
1110 #define SPR_UPERF9            (0x319)
1111 #define SPR_UPERFA            (0x31A)
1112 #define SPR_UPERFB            (0x31B)
1113 #define SPR_620_MMCR0W        (0x31B)
1114 #define SPR_UPERFC            (0x31C)
1115 #define SPR_UPERFD            (0x31D)
1116 #define SPR_UPERFE            (0x31E)
1117 #define SPR_UPERFF            (0x31F)
1118 #define SPR_RCPU_MI_RA0       (0x320)
1119 #define SPR_MPC_MI_DBCAM      (0x320)
1120 #define SPR_RCPU_MI_RA1       (0x321)
1121 #define SPR_MPC_MI_DBRAM0     (0x321)
1122 #define SPR_RCPU_MI_RA2       (0x322)
1123 #define SPR_MPC_MI_DBRAM1     (0x322)
1124 #define SPR_RCPU_MI_RA3       (0x323)
1125 #define SPR_RCPU_L2U_RA0      (0x328)
1126 #define SPR_MPC_MD_DBCAM      (0x328)
1127 #define SPR_RCPU_L2U_RA1      (0x329)
1128 #define SPR_MPC_MD_DBRAM0     (0x329)
1129 #define SPR_RCPU_L2U_RA2      (0x32A)
1130 #define SPR_MPC_MD_DBRAM1     (0x32A)
1131 #define SPR_RCPU_L2U_RA3      (0x32B)
1132 #define SPR_440_INV0          (0x370)
1133 #define SPR_440_INV1          (0x371)
1134 #define SPR_440_INV2          (0x372)
1135 #define SPR_440_INV3          (0x373)
1136 #define SPR_440_ITV0          (0x374)
1137 #define SPR_440_ITV1          (0x375)
1138 #define SPR_440_ITV2          (0x376)
1139 #define SPR_440_ITV3          (0x377)
1140 #define SPR_440_CCR1          (0x378)
1141 #define SPR_DCRIPR            (0x37B)
1142 #define SPR_PPR               (0x380)
1143 #define SPR_750_GQR0          (0x390)
1144 #define SPR_440_DNV0          (0x390)
1145 #define SPR_750_GQR1          (0x391)
1146 #define SPR_440_DNV1          (0x391)
1147 #define SPR_750_GQR2          (0x392)
1148 #define SPR_440_DNV2          (0x392)
1149 #define SPR_750_GQR3          (0x393)
1150 #define SPR_440_DNV3          (0x393)
1151 #define SPR_750_GQR4          (0x394)
1152 #define SPR_440_DTV0          (0x394)
1153 #define SPR_750_GQR5          (0x395)
1154 #define SPR_440_DTV1          (0x395)
1155 #define SPR_750_GQR6          (0x396)
1156 #define SPR_440_DTV2          (0x396)
1157 #define SPR_750_GQR7          (0x397)
1158 #define SPR_440_DTV3          (0x397)
1159 #define SPR_750_THRM4         (0x398)
1160 #define SPR_750CL_HID2        (0x398)
1161 #define SPR_440_DVLIM         (0x398)
1162 #define SPR_750_WPAR          (0x399)
1163 #define SPR_440_IVLIM         (0x399)
1164 #define SPR_750_DMAU          (0x39A)
1165 #define SPR_750_DMAL          (0x39B)
1166 #define SPR_440_RSTCFG        (0x39B)
1167 #define SPR_BOOKE_DCDBTRL     (0x39C)
1168 #define SPR_BOOKE_DCDBTRH     (0x39D)
1169 #define SPR_BOOKE_ICDBTRL     (0x39E)
1170 #define SPR_BOOKE_ICDBTRH     (0x39F)
1171 #define SPR_UMMCR2            (0x3A0)
1172 #define SPR_UPMC5             (0x3A1)
1173 #define SPR_UPMC6             (0x3A2)
1174 #define SPR_UBAMR             (0x3A7)
1175 #define SPR_UMMCR0            (0x3A8)
1176 #define SPR_UPMC1             (0x3A9)
1177 #define SPR_UPMC2             (0x3AA)
1178 #define SPR_USIAR             (0x3AB)
1179 #define SPR_UMMCR1            (0x3AC)
1180 #define SPR_UPMC3             (0x3AD)
1181 #define SPR_UPMC4             (0x3AE)
1182 #define SPR_USDA              (0x3AF)
1183 #define SPR_40x_ZPR           (0x3B0)
1184 #define SPR_BOOKE_MAS7        (0x3B0)
1185 #define SPR_620_PMR0          (0x3B0)
1186 #define SPR_MMCR2             (0x3B0)
1187 #define SPR_PMC5              (0x3B1)
1188 #define SPR_40x_PID           (0x3B1)
1189 #define SPR_620_PMR1          (0x3B1)
1190 #define SPR_PMC6              (0x3B2)
1191 #define SPR_440_MMUCR         (0x3B2)
1192 #define SPR_620_PMR2          (0x3B2)
1193 #define SPR_4xx_CCR0          (0x3B3)
1194 #define SPR_BOOKE_EPLC        (0x3B3)
1195 #define SPR_620_PMR3          (0x3B3)
1196 #define SPR_405_IAC3          (0x3B4)
1197 #define SPR_BOOKE_EPSC        (0x3B4)
1198 #define SPR_620_PMR4          (0x3B4)
1199 #define SPR_405_IAC4          (0x3B5)
1200 #define SPR_620_PMR5          (0x3B5)
1201 #define SPR_405_DVC1          (0x3B6)
1202 #define SPR_620_PMR6          (0x3B6)
1203 #define SPR_405_DVC2          (0x3B7)
1204 #define SPR_620_PMR7          (0x3B7)
1205 #define SPR_BAMR              (0x3B7)
1206 #define SPR_MMCR0             (0x3B8)
1207 #define SPR_620_PMR8          (0x3B8)
1208 #define SPR_PMC1              (0x3B9)
1209 #define SPR_40x_SGR           (0x3B9)
1210 #define SPR_620_PMR9          (0x3B9)
1211 #define SPR_PMC2              (0x3BA)
1212 #define SPR_40x_DCWR          (0x3BA)
1213 #define SPR_620_PMRA          (0x3BA)
1214 #define SPR_SIAR              (0x3BB)
1215 #define SPR_405_SLER          (0x3BB)
1216 #define SPR_620_PMRB          (0x3BB)
1217 #define SPR_MMCR1             (0x3BC)
1218 #define SPR_405_SU0R          (0x3BC)
1219 #define SPR_620_PMRC          (0x3BC)
1220 #define SPR_401_SKR           (0x3BC)
1221 #define SPR_PMC3              (0x3BD)
1222 #define SPR_405_DBCR1         (0x3BD)
1223 #define SPR_620_PMRD          (0x3BD)
1224 #define SPR_PMC4              (0x3BE)
1225 #define SPR_620_PMRE          (0x3BE)
1226 #define SPR_SDA               (0x3BF)
1227 #define SPR_620_PMRF          (0x3BF)
1228 #define SPR_403_VTBL          (0x3CC)
1229 #define SPR_403_VTBU          (0x3CD)
1230 #define SPR_DMISS             (0x3D0)
1231 #define SPR_DCMP              (0x3D1)
1232 #define SPR_HASH1             (0x3D2)
1233 #define SPR_HASH2             (0x3D3)
1234 #define SPR_BOOKE_ICDBDR      (0x3D3)
1235 #define SPR_TLBMISS           (0x3D4)
1236 #define SPR_IMISS             (0x3D4)
1237 #define SPR_40x_ESR           (0x3D4)
1238 #define SPR_PTEHI             (0x3D5)
1239 #define SPR_ICMP              (0x3D5)
1240 #define SPR_40x_DEAR          (0x3D5)
1241 #define SPR_PTELO             (0x3D6)
1242 #define SPR_RPA               (0x3D6)
1243 #define SPR_40x_EVPR          (0x3D6)
1244 #define SPR_L3PM              (0x3D7)
1245 #define SPR_403_CDBCR         (0x3D7)
1246 #define SPR_L3ITCR0           (0x3D8)
1247 #define SPR_TCR               (0x3D8)
1248 #define SPR_40x_TSR           (0x3D8)
1249 #define SPR_IBR               (0x3DA)
1250 #define SPR_40x_TCR           (0x3DA)
1251 #define SPR_ESASRR            (0x3DB)
1252 #define SPR_40x_PIT           (0x3DB)
1253 #define SPR_403_TBL           (0x3DC)
1254 #define SPR_403_TBU           (0x3DD)
1255 #define SPR_SEBR              (0x3DE)
1256 #define SPR_40x_SRR2          (0x3DE)
1257 #define SPR_SER               (0x3DF)
1258 #define SPR_40x_SRR3          (0x3DF)
1259 #define SPR_L3OHCR            (0x3E8)
1260 #define SPR_L3ITCR1           (0x3E9)
1261 #define SPR_L3ITCR2           (0x3EA)
1262 #define SPR_L3ITCR3           (0x3EB)
1263 #define SPR_HID0              (0x3F0)
1264 #define SPR_40x_DBSR          (0x3F0)
1265 #define SPR_HID1              (0x3F1)
1266 #define SPR_IABR              (0x3F2)
1267 #define SPR_40x_DBCR0         (0x3F2)
1268 #define SPR_601_HID2          (0x3F2)
1269 #define SPR_Exxx_L1CSR0       (0x3F2)
1270 #define SPR_ICTRL             (0x3F3)
1271 #define SPR_HID2              (0x3F3)
1272 #define SPR_750CL_HID4        (0x3F3)
1273 #define SPR_Exxx_L1CSR1       (0x3F3)
1274 #define SPR_440_DBDR          (0x3F3)
1275 #define SPR_LDSTDB            (0x3F4)
1276 #define SPR_750_TDCL          (0x3F4)
1277 #define SPR_40x_IAC1          (0x3F4)
1278 #define SPR_MMUCSR0           (0x3F4)
1279 #define SPR_DABR              (0x3F5)
1280 #define DABR_MASK (~(target_ulong)0x7)
1281 #define SPR_Exxx_BUCSR        (0x3F5)
1282 #define SPR_40x_IAC2          (0x3F5)
1283 #define SPR_601_HID5          (0x3F5)
1284 #define SPR_40x_DAC1          (0x3F6)
1285 #define SPR_MSSCR0            (0x3F6)
1286 #define SPR_970_HID5          (0x3F6)
1287 #define SPR_MSSSR0            (0x3F7)
1288 #define SPR_MSSCR1            (0x3F7)
1289 #define SPR_DABRX             (0x3F7)
1290 #define SPR_40x_DAC2          (0x3F7)
1291 #define SPR_MMUCFG            (0x3F7)
1292 #define SPR_LDSTCR            (0x3F8)
1293 #define SPR_L2PMCR            (0x3F8)
1294 #define SPR_750FX_HID2        (0x3F8)
1295 #define SPR_620_BUSCSR        (0x3F8)
1296 #define SPR_Exxx_L1FINV0      (0x3F8)
1297 #define SPR_L2CR              (0x3F9)
1298 #define SPR_620_L2CR          (0x3F9)
1299 #define SPR_L3CR              (0x3FA)
1300 #define SPR_750_TDCH          (0x3FA)
1301 #define SPR_IABR2             (0x3FA)
1302 #define SPR_40x_DCCR          (0x3FA)
1303 #define SPR_620_L2SR          (0x3FA)
1304 #define SPR_ICTC              (0x3FB)
1305 #define SPR_40x_ICCR          (0x3FB)
1306 #define SPR_THRM1             (0x3FC)
1307 #define SPR_403_PBL1          (0x3FC)
1308 #define SPR_SP                (0x3FD)
1309 #define SPR_THRM2             (0x3FD)
1310 #define SPR_403_PBU1          (0x3FD)
1311 #define SPR_604_HID13         (0x3FD)
1312 #define SPR_LT                (0x3FE)
1313 #define SPR_THRM3             (0x3FE)
1314 #define SPR_RCPU_FPECR        (0x3FE)
1315 #define SPR_403_PBL2          (0x3FE)
1316 #define SPR_PIR               (0x3FF)
1317 #define SPR_403_PBU2          (0x3FF)
1318 #define SPR_601_HID15         (0x3FF)
1319 #define SPR_604_HID15         (0x3FF)
1320 #define SPR_E500_SVR          (0x3FF)
1321
1322 /*****************************************************************************/
1323 /* Memory access type :
1324  * may be needed for precise access rights control and precise exceptions.
1325  */
1326 enum {
1327     /* 1 bit to define user level / supervisor access */
1328     ACCESS_USER  = 0x00,
1329     ACCESS_SUPER = 0x01,
1330     /* Type of instruction that generated the access */
1331     ACCESS_CODE  = 0x10, /* Code fetch access                */
1332     ACCESS_INT   = 0x20, /* Integer load/store access        */
1333     ACCESS_FLOAT = 0x30, /* floating point load/store access */
1334     ACCESS_RES   = 0x40, /* load/store with reservation      */
1335     ACCESS_EXT   = 0x50, /* external access                  */
1336     ACCESS_CACHE = 0x60, /* Cache manipulation               */
1337 };
1338
1339 /* Hardware interruption sources:
1340  * all those exception can be raised simulteaneously
1341  */
1342 /* Input pins definitions */
1343 enum {
1344     /* 6xx bus input pins */
1345     PPC6xx_INPUT_HRESET     = 0,
1346     PPC6xx_INPUT_SRESET     = 1,
1347     PPC6xx_INPUT_CKSTP_IN   = 2,
1348     PPC6xx_INPUT_MCP        = 3,
1349     PPC6xx_INPUT_SMI        = 4,
1350     PPC6xx_INPUT_INT        = 5,
1351     PPC6xx_INPUT_TBEN       = 6,
1352     PPC6xx_INPUT_WAKEUP     = 7,
1353     PPC6xx_INPUT_NB,
1354 };
1355
1356 enum {
1357     /* Embedded PowerPC input pins */
1358     PPCBookE_INPUT_HRESET     = 0,
1359     PPCBookE_INPUT_SRESET     = 1,
1360     PPCBookE_INPUT_CKSTP_IN   = 2,
1361     PPCBookE_INPUT_MCP        = 3,
1362     PPCBookE_INPUT_SMI        = 4,
1363     PPCBookE_INPUT_INT        = 5,
1364     PPCBookE_INPUT_CINT       = 6,
1365     PPCBookE_INPUT_NB,
1366 };
1367
1368 enum {
1369     /* PowerPC 40x input pins */
1370     PPC40x_INPUT_RESET_CORE = 0,
1371     PPC40x_INPUT_RESET_CHIP = 1,
1372     PPC40x_INPUT_RESET_SYS  = 2,
1373     PPC40x_INPUT_CINT       = 3,
1374     PPC40x_INPUT_INT        = 4,
1375     PPC40x_INPUT_HALT       = 5,
1376     PPC40x_INPUT_DEBUG      = 6,
1377     PPC40x_INPUT_NB,
1378 };
1379
1380 enum {
1381     /* RCPU input pins */
1382     PPCRCPU_INPUT_PORESET   = 0,
1383     PPCRCPU_INPUT_HRESET    = 1,
1384     PPCRCPU_INPUT_SRESET    = 2,
1385     PPCRCPU_INPUT_IRQ0      = 3,
1386     PPCRCPU_INPUT_IRQ1      = 4,
1387     PPCRCPU_INPUT_IRQ2      = 5,
1388     PPCRCPU_INPUT_IRQ3      = 6,
1389     PPCRCPU_INPUT_IRQ4      = 7,
1390     PPCRCPU_INPUT_IRQ5      = 8,
1391     PPCRCPU_INPUT_IRQ6      = 9,
1392     PPCRCPU_INPUT_IRQ7      = 10,
1393     PPCRCPU_INPUT_NB,
1394 };
1395
1396 #if defined(TARGET_PPC64)
1397 enum {
1398     /* PowerPC 970 input pins */
1399     PPC970_INPUT_HRESET     = 0,
1400     PPC970_INPUT_SRESET     = 1,
1401     PPC970_INPUT_CKSTP      = 2,
1402     PPC970_INPUT_TBEN       = 3,
1403     PPC970_INPUT_MCP        = 4,
1404     PPC970_INPUT_INT        = 5,
1405     PPC970_INPUT_THINT      = 6,
1406     PPC970_INPUT_NB,
1407 };
1408 #endif
1409
1410 /* Hardware exceptions definitions */
1411 enum {
1412     /* External hardware exception sources */
1413     PPC_INTERRUPT_RESET     = 0,  /* Reset exception                      */
1414     PPC_INTERRUPT_WAKEUP,         /* Wakeup exception                     */
1415     PPC_INTERRUPT_MCK,            /* Machine check exception              */
1416     PPC_INTERRUPT_EXT,            /* External interrupt                   */
1417     PPC_INTERRUPT_SMI,            /* System management interrupt          */
1418     PPC_INTERRUPT_CEXT,           /* Critical external interrupt          */
1419     PPC_INTERRUPT_DEBUG,          /* External debug exception             */
1420     PPC_INTERRUPT_THERM,          /* Thermal exception                    */
1421     /* Internal hardware exception sources */
1422     PPC_INTERRUPT_DECR,           /* Decrementer exception                */
1423     PPC_INTERRUPT_HDECR,          /* Hypervisor decrementer exception     */
1424     PPC_INTERRUPT_PIT,            /* Programmable inteval timer interrupt */
1425     PPC_INTERRUPT_FIT,            /* Fixed interval timer interrupt       */
1426     PPC_INTERRUPT_WDT,            /* Watchdog timer interrupt             */
1427     PPC_INTERRUPT_CDOORBELL,      /* Critical doorbell interrupt          */
1428     PPC_INTERRUPT_DOORBELL,       /* Doorbell interrupt                   */
1429     PPC_INTERRUPT_PERFM,          /* Performance monitor interrupt        */
1430 };
1431
1432 /*****************************************************************************/
1433
1434 /* hidden flags (hflags) - used internally by qemu to represent additional
1435  * cpu states.
1436  */
1437 #define HF_HALTED_SHIFT 1
1438
1439 #define HF_HALTED_MASK 1<<HF_HALTED_SHIFT
1440
1441 #endif /* !defined (__CPU_PPC_H__) */