kvm/include/x86/asm/vmx.h

   1 #ifndef KVM_UNIFDEF_H
   2 #define KVM_UNIFDEF_H
   3
   4 #ifdef __i386__
   5 #ifndef CONFIG_X86_32
   6 #define CONFIG_X86_32 1
   7 #endif
   8 #endif
   9
  10 #ifdef __x86_64__
  11 #ifndef CONFIG_X86_64
  12 #define CONFIG_X86_64 1
  13 #endif
  14 #endif
  15
  16 #if defined(__i386__) || defined (__x86_64__)
  17 #ifndef CONFIG_X86
  18 #define CONFIG_X86 1
  19 #endif
  20 #endif
  21
  22 #ifdef __ia64__
  23 #ifndef CONFIG_IA64
  24 #define CONFIG_IA64 1
  25 #endif
  26 #endif
  27
  28 #ifdef __PPC__
  29 #ifndef CONFIG_PPC
  30 #define CONFIG_PPC 1
  31 #endif
  32 #endif
  33
  34 #ifdef __s390__
  35 #ifndef CONFIG_S390
  36 #define CONFIG_S390 1
  37 #endif
  38 #endif
  39
  40 #endif
  41 #ifndef VMX_H
  42 #define VMX_H
  43
  44 /*
  45  * vmx.h: VMX Architecture related definitions
  46  * Copyright (c) 2004, Intel Corporation.
  47  *
  48  * This program is free software; you can redistribute it and/or modify it
  49  * under the terms and conditions of the GNU General Public License,
  50  * version 2, as published by the Free Software Foundation.
  51  *
  52  * This program is distributed in the hope it will be useful, but WITHOUT
  53  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  54  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  55  * more details.
  56  *
  57  * You should have received a copy of the GNU General Public License along with
  58  * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
  59  * Place - Suite 330, Boston, MA 02111-1307 USA.
  60  *
  61  * A few random additions are:
  62  * Copyright (C) 2006 Qumranet
  63  *    Avi Kivity <avi@qumranet.com>
  64  *    Yaniv Kamay <yaniv@qumranet.com>
  65  *
  66  */
  67
  68 /*
  69  * Definitions of Primary Processor-Based VM-Execution Controls.
  70  */
  71 #define CPU_BASED_VIRTUAL_INTR_PENDING          0x00000004
  72 #define CPU_BASED_USE_TSC_OFFSETING             0x00000008
  73 #define CPU_BASED_HLT_EXITING                   0x00000080
  74 #define CPU_BASED_INVLPG_EXITING                0x00000200
  75 #define CPU_BASED_MWAIT_EXITING                 0x00000400
  76 #define CPU_BASED_RDPMC_EXITING                 0x00000800
  77 #define CPU_BASED_RDTSC_EXITING                 0x00001000
  78 #define CPU_BASED_CR3_LOAD_EXITING              0x00008000
  79 #define CPU_BASED_CR3_STORE_EXITING             0x00010000
  80 #define CPU_BASED_CR8_LOAD_EXITING              0x00080000
  81 #define CPU_BASED_CR8_STORE_EXITING             0x00100000
  82 #define CPU_BASED_TPR_SHADOW                    0x00200000
  83 #define CPU_BASED_VIRTUAL_NMI_PENDING           0x00400000
  84 #define CPU_BASED_MOV_DR_EXITING                0x00800000
  85 #define CPU_BASED_UNCOND_IO_EXITING             0x01000000
  86 #define CPU_BASED_USE_IO_BITMAPS                0x02000000
  87 #define CPU_BASED_USE_MSR_BITMAPS               0x10000000
  88 #define CPU_BASED_MONITOR_EXITING               0x20000000
  89 #define CPU_BASED_PAUSE_EXITING                 0x40000000
  90 #define CPU_BASED_ACTIVATE_SECONDARY_CONTROLS   0x80000000
  91 /*
  92  * Definitions of Secondary Processor-Based VM-Execution Controls.
  93  */
  94 #define SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES 0x00000001
  95 #define SECONDARY_EXEC_ENABLE_EPT               0x00000002
  96 #define SECONDARY_EXEC_ENABLE_VPID              0x00000020
  97 #define SECONDARY_EXEC_WBINVD_EXITING           0x00000040
  98
  99
 100 #define PIN_BASED_EXT_INTR_MASK                 0x00000001
 101 #define PIN_BASED_NMI_EXITING                   0x00000008
 102 #define PIN_BASED_VIRTUAL_NMIS                  0x00000020
 103
 104 #define VM_EXIT_HOST_ADDR_SPACE_SIZE            0x00000200
 105 #define VM_EXIT_ACK_INTR_ON_EXIT                0x00008000
 106 #define VM_EXIT_SAVE_IA32_PAT                   0x00040000
 107 #define VM_EXIT_LOAD_IA32_PAT                   0x00080000
 108
 109 #define VM_ENTRY_IA32E_MODE                     0x00000200
 110 #define VM_ENTRY_SMM                            0x00000400
 111 #define VM_ENTRY_DEACT_DUAL_MONITOR             0x00000800
 112 #define VM_ENTRY_LOAD_IA32_PAT                  0x00004000
 113
 114 /* VMCS Encodings */
 115 enum vmcs_field {
 116         VIRTUAL_PROCESSOR_ID            = 0x00000000,
 117         GUEST_ES_SELECTOR               = 0x00000800,
 118         GUEST_CS_SELECTOR               = 0x00000802,
 119         GUEST_SS_SELECTOR               = 0x00000804,
 120         GUEST_DS_SELECTOR               = 0x00000806,
 121         GUEST_FS_SELECTOR               = 0x00000808,
 122         GUEST_GS_SELECTOR               = 0x0000080a,
 123         GUEST_LDTR_SELECTOR             = 0x0000080c,
 124         GUEST_TR_SELECTOR               = 0x0000080e,
 125         HOST_ES_SELECTOR                = 0x00000c00,
 126         HOST_CS_SELECTOR                = 0x00000c02,
 127         HOST_SS_SELECTOR                = 0x00000c04,
 128         HOST_DS_SELECTOR                = 0x00000c06,
 129         HOST_FS_SELECTOR                = 0x00000c08,
 130         HOST_GS_SELECTOR                = 0x00000c0a,
 131         HOST_TR_SELECTOR                = 0x00000c0c,
 132         IO_BITMAP_A                     = 0x00002000,
 133         IO_BITMAP_A_HIGH                = 0x00002001,
 134         IO_BITMAP_B                     = 0x00002002,
 135         IO_BITMAP_B_HIGH                = 0x00002003,
 136         MSR_BITMAP                      = 0x00002004,
 137         MSR_BITMAP_HIGH                 = 0x00002005,
 138         VM_EXIT_MSR_STORE_ADDR          = 0x00002006,
 139         VM_EXIT_MSR_STORE_ADDR_HIGH     = 0x00002007,
 140         VM_EXIT_MSR_LOAD_ADDR           = 0x00002008,
 141         VM_EXIT_MSR_LOAD_ADDR_HIGH      = 0x00002009,
 142         VM_ENTRY_MSR_LOAD_ADDR          = 0x0000200a,
 143         VM_ENTRY_MSR_LOAD_ADDR_HIGH     = 0x0000200b,
 144         TSC_OFFSET                      = 0x00002010,
 145         TSC_OFFSET_HIGH                 = 0x00002011,
 146         VIRTUAL_APIC_PAGE_ADDR          = 0x00002012,
 147         VIRTUAL_APIC_PAGE_ADDR_HIGH     = 0x00002013,
 148         APIC_ACCESS_ADDR                = 0x00002014,
 149         APIC_ACCESS_ADDR_HIGH           = 0x00002015,
 150         EPT_POINTER                     = 0x0000201a,
 151         EPT_POINTER_HIGH                = 0x0000201b,
 152         GUEST_PHYSICAL_ADDRESS          = 0x00002400,
 153         GUEST_PHYSICAL_ADDRESS_HIGH     = 0x00002401,
 154         VMCS_LINK_POINTER               = 0x00002800,
 155         VMCS_LINK_POINTER_HIGH          = 0x00002801,
 156         GUEST_IA32_DEBUGCTL             = 0x00002802,
 157         GUEST_IA32_DEBUGCTL_HIGH        = 0x00002803,
 158         GUEST_IA32_PAT                  = 0x00002804,
 159         GUEST_IA32_PAT_HIGH             = 0x00002805,
 160         GUEST_PDPTR0                    = 0x0000280a,
 161         GUEST_PDPTR0_HIGH               = 0x0000280b,
 162         GUEST_PDPTR1                    = 0x0000280c,
 163         GUEST_PDPTR1_HIGH               = 0x0000280d,
 164         GUEST_PDPTR2                    = 0x0000280e,
 165         GUEST_PDPTR2_HIGH               = 0x0000280f,
 166         GUEST_PDPTR3                    = 0x00002810,
 167         GUEST_PDPTR3_HIGH               = 0x00002811,
 168         HOST_IA32_PAT                   = 0x00002c00,
 169         HOST_IA32_PAT_HIGH              = 0x00002c01,
 170         PIN_BASED_VM_EXEC_CONTROL       = 0x00004000,
 171         CPU_BASED_VM_EXEC_CONTROL       = 0x00004002,
 172         EXCEPTION_BITMAP                = 0x00004004,
 173         PAGE_FAULT_ERROR_CODE_MASK      = 0x00004006,
 174         PAGE_FAULT_ERROR_CODE_MATCH     = 0x00004008,
 175         CR3_TARGET_COUNT                = 0x0000400a,
 176         VM_EXIT_CONTROLS                = 0x0000400c,
 177         VM_EXIT_MSR_STORE_COUNT         = 0x0000400e,
 178         VM_EXIT_MSR_LOAD_COUNT          = 0x00004010,
 179         VM_ENTRY_CONTROLS               = 0x00004012,
 180         VM_ENTRY_MSR_LOAD_COUNT         = 0x00004014,
 181         VM_ENTRY_INTR_INFO_FIELD        = 0x00004016,
 182         VM_ENTRY_EXCEPTION_ERROR_CODE   = 0x00004018,
 183         VM_ENTRY_INSTRUCTION_LEN        = 0x0000401a,
 184         TPR_THRESHOLD                   = 0x0000401c,
 185         SECONDARY_VM_EXEC_CONTROL       = 0x0000401e,
 186         VM_INSTRUCTION_ERROR            = 0x00004400,
 187         VM_EXIT_REASON                  = 0x00004402,
 188         VM_EXIT_INTR_INFO               = 0x00004404,
 189         VM_EXIT_INTR_ERROR_CODE         = 0x00004406,
 190         IDT_VECTORING_INFO_FIELD        = 0x00004408,
 191         IDT_VECTORING_ERROR_CODE        = 0x0000440a,
 192         VM_EXIT_INSTRUCTION_LEN         = 0x0000440c,
 193         VMX_INSTRUCTION_INFO            = 0x0000440e,
 194         GUEST_ES_LIMIT                  = 0x00004800,
 195         GUEST_CS_LIMIT                  = 0x00004802,
 196         GUEST_SS_LIMIT                  = 0x00004804,
 197         GUEST_DS_LIMIT                  = 0x00004806,
 198         GUEST_FS_LIMIT                  = 0x00004808,
 199         GUEST_GS_LIMIT                  = 0x0000480a,
 200         GUEST_LDTR_LIMIT                = 0x0000480c,
 201         GUEST_TR_LIMIT                  = 0x0000480e,
 202         GUEST_GDTR_LIMIT                = 0x00004810,
 203         GUEST_IDTR_LIMIT                = 0x00004812,
 204         GUEST_ES_AR_BYTES               = 0x00004814,
 205         GUEST_CS_AR_BYTES               = 0x00004816,
 206         GUEST_SS_AR_BYTES               = 0x00004818,
 207         GUEST_DS_AR_BYTES               = 0x0000481a,
 208         GUEST_FS_AR_BYTES               = 0x0000481c,
 209         GUEST_GS_AR_BYTES               = 0x0000481e,
 210         GUEST_LDTR_AR_BYTES             = 0x00004820,
 211         GUEST_TR_AR_BYTES               = 0x00004822,
 212         GUEST_INTERRUPTIBILITY_INFO     = 0x00004824,
 213         GUEST_ACTIVITY_STATE            = 0X00004826,
 214         GUEST_SYSENTER_CS               = 0x0000482A,
 215         HOST_IA32_SYSENTER_CS           = 0x00004c00,
 216         CR0_GUEST_HOST_MASK             = 0x00006000,
 217         CR4_GUEST_HOST_MASK             = 0x00006002,
 218         CR0_READ_SHADOW                 = 0x00006004,
 219         CR4_READ_SHADOW                 = 0x00006006,
 220         CR3_TARGET_VALUE0               = 0x00006008,
 221         CR3_TARGET_VALUE1               = 0x0000600a,
 222         CR3_TARGET_VALUE2               = 0x0000600c,
 223         CR3_TARGET_VALUE3               = 0x0000600e,
 224         EXIT_QUALIFICATION              = 0x00006400,
 225         GUEST_LINEAR_ADDRESS            = 0x0000640a,
 226         GUEST_CR0                       = 0x00006800,
 227         GUEST_CR3                       = 0x00006802,
 228         GUEST_CR4                       = 0x00006804,
 229         GUEST_ES_BASE                   = 0x00006806,
 230         GUEST_CS_BASE                   = 0x00006808,
 231         GUEST_SS_BASE                   = 0x0000680a,
 232         GUEST_DS_BASE                   = 0x0000680c,
 233         GUEST_FS_BASE                   = 0x0000680e,
 234         GUEST_GS_BASE                   = 0x00006810,
 235         GUEST_LDTR_BASE                 = 0x00006812,
 236         GUEST_TR_BASE                   = 0x00006814,
 237         GUEST_GDTR_BASE                 = 0x00006816,
 238         GUEST_IDTR_BASE                 = 0x00006818,
 239         GUEST_DR7                       = 0x0000681a,
 240         GUEST_RSP                       = 0x0000681c,
 241         GUEST_RIP                       = 0x0000681e,
 242         GUEST_RFLAGS                    = 0x00006820,
 243         GUEST_PENDING_DBG_EXCEPTIONS    = 0x00006822,
 244         GUEST_SYSENTER_ESP              = 0x00006824,
 245         GUEST_SYSENTER_EIP              = 0x00006826,
 246         HOST_CR0                        = 0x00006c00,
 247         HOST_CR3                        = 0x00006c02,
 248         HOST_CR4                        = 0x00006c04,
 249         HOST_FS_BASE                    = 0x00006c06,
 250         HOST_GS_BASE                    = 0x00006c08,
 251         HOST_TR_BASE                    = 0x00006c0a,
 252         HOST_GDTR_BASE                  = 0x00006c0c,
 253         HOST_IDTR_BASE                  = 0x00006c0e,
 254         HOST_IA32_SYSENTER_ESP          = 0x00006c10,
 255         HOST_IA32_SYSENTER_EIP          = 0x00006c12,
 256         HOST_RSP                        = 0x00006c14,
 257         HOST_RIP                        = 0x00006c16,
 258 };
 259
 260 #define VMX_EXIT_REASONS_FAILED_VMENTRY         0x80000000
 261
 262 #define EXIT_REASON_EXCEPTION_NMI       0
 263 #define EXIT_REASON_EXTERNAL_INTERRUPT  1
 264 #define EXIT_REASON_TRIPLE_FAULT        2
 265
 266 #define EXIT_REASON_PENDING_INTERRUPT   7
 267 #define EXIT_REASON_NMI_WINDOW          8
 268 #define EXIT_REASON_TASK_SWITCH         9
 269 #define EXIT_REASON_CPUID               10
 270 #define EXIT_REASON_HLT                 12
 271 #define EXIT_REASON_INVLPG              14
 272 #define EXIT_REASON_RDPMC               15
 273 #define EXIT_REASON_RDTSC               16
 274 #define EXIT_REASON_VMCALL              18
 275 #define EXIT_REASON_VMCLEAR             19
 276 #define EXIT_REASON_VMLAUNCH            20
 277 #define EXIT_REASON_VMPTRLD             21
 278 #define EXIT_REASON_VMPTRST             22
 279 #define EXIT_REASON_VMREAD              23
 280 #define EXIT_REASON_VMRESUME            24
 281 #define EXIT_REASON_VMWRITE             25
 282 #define EXIT_REASON_VMOFF               26
 283 #define EXIT_REASON_VMON                27
 284 #define EXIT_REASON_CR_ACCESS           28
 285 #define EXIT_REASON_DR_ACCESS           29
 286 #define EXIT_REASON_IO_INSTRUCTION      30
 287 #define EXIT_REASON_MSR_READ            31
 288 #define EXIT_REASON_MSR_WRITE           32
 289 #define EXIT_REASON_MWAIT_INSTRUCTION   36
 290 #define EXIT_REASON_TPR_BELOW_THRESHOLD 43
 291 #define EXIT_REASON_APIC_ACCESS         44
 292 #define EXIT_REASON_EPT_VIOLATION       48
 293 #define EXIT_REASON_EPT_MISCONFIG       49
 294 #define EXIT_REASON_WBINVD              54
 295
 296 /*
 297  * Interruption-information format
 298  */
 299 #define INTR_INFO_VECTOR_MASK           0xff            /* 7:0 */
 300 #define INTR_INFO_INTR_TYPE_MASK        0x700           /* 10:8 */
 301 #define INTR_INFO_DELIVER_CODE_MASK     0x800           /* 11 */
 302 #define INTR_INFO_UNBLOCK_NMI           0x1000          /* 12 */
 303 #define INTR_INFO_VALID_MASK            0x80000000      /* 31 */
 304 #define INTR_INFO_RESVD_BITS_MASK       0x7ffff000
 305
 306 #define VECTORING_INFO_VECTOR_MASK              INTR_INFO_VECTOR_MASK
 307 #define VECTORING_INFO_TYPE_MASK                INTR_INFO_INTR_TYPE_MASK
 308 #define VECTORING_INFO_DELIVER_CODE_MASK        INTR_INFO_DELIVER_CODE_MASK
 309 #define VECTORING_INFO_VALID_MASK               INTR_INFO_VALID_MASK
 310
 311 #define INTR_TYPE_EXT_INTR              (0 << 8) /* external interrupt */
 312 #define INTR_TYPE_NMI_INTR              (2 << 8) /* NMI */
 313 #define INTR_TYPE_HARD_EXCEPTION        (3 << 8) /* processor exception */
 314 #define INTR_TYPE_SOFT_INTR             (4 << 8) /* software interrupt */
 315 #define INTR_TYPE_SOFT_EXCEPTION        (6 << 8) /* software exception */
 316
 317 /* GUEST_INTERRUPTIBILITY_INFO flags. */
 318 #define GUEST_INTR_STATE_STI            0x00000001
 319 #define GUEST_INTR_STATE_MOV_SS         0x00000002
 320 #define GUEST_INTR_STATE_SMI            0x00000004
 321 #define GUEST_INTR_STATE_NMI            0x00000008
 322
 323 /*
 324  * Exit Qualifications for MOV for Control Register Access
 325  */
 326 #define CONTROL_REG_ACCESS_NUM          0x7     /* 2:0, number of control reg.*/
 327 #define CONTROL_REG_ACCESS_TYPE         0x30    /* 5:4, access type */
 328 #define CONTROL_REG_ACCESS_REG          0xf00   /* 10:8, general purpose reg. */
 329 #define LMSW_SOURCE_DATA_SHIFT 16
 330 #define LMSW_SOURCE_DATA  (0xFFFF << LMSW_SOURCE_DATA_SHIFT) /* 16:31 lmsw source */
 331 #define REG_EAX                         (0 << 8)
 332 #define REG_ECX                         (1 << 8)
 333 #define REG_EDX                         (2 << 8)
 334 #define REG_EBX                         (3 << 8)
 335 #define REG_ESP                         (4 << 8)
 336 #define REG_EBP                         (5 << 8)
 337 #define REG_ESI                         (6 << 8)
 338 #define REG_EDI                         (7 << 8)
 339 #define REG_R8                         (8 << 8)
 340 #define REG_R9                         (9 << 8)
 341 #define REG_R10                        (10 << 8)
 342 #define REG_R11                        (11 << 8)
 343 #define REG_R12                        (12 << 8)
 344 #define REG_R13                        (13 << 8)
 345 #define REG_R14                        (14 << 8)
 346 #define REG_R15                        (15 << 8)
 347
 348 /*
 349  * Exit Qualifications for MOV for Debug Register Access
 350  */
 351 #define DEBUG_REG_ACCESS_NUM            0x7     /* 2:0, number of debug reg. */
 352 #define DEBUG_REG_ACCESS_TYPE           0x10    /* 4, direction of access */
 353 #define TYPE_MOV_TO_DR                  (0 << 4)
 354 #define TYPE_MOV_FROM_DR                (1 << 4)
 355 #define DEBUG_REG_ACCESS_REG(eq)        (((eq) >> 8) & 0xf) /* 11:8, general purpose reg. */
 356
 357
 358 /* segment AR */
 359 #define SEGMENT_AR_L_MASK (1 << 13)
 360
 361 #define AR_TYPE_ACCESSES_MASK 1
 362 #define AR_TYPE_READABLE_MASK (1 << 1)
 363 #define AR_TYPE_WRITEABLE_MASK (1 << 2)
 364 #define AR_TYPE_CODE_MASK (1 << 3)
 365 #define AR_TYPE_MASK 0x0f
 366 #define AR_TYPE_BUSY_64_TSS 11
 367 #define AR_TYPE_BUSY_32_TSS 11
 368 #define AR_TYPE_BUSY_16_TSS 3
 369 #define AR_TYPE_LDT 2
 370
 371 #define AR_UNUSABLE_MASK (1 << 16)
 372 #define AR_S_MASK (1 << 4)
 373 #define AR_P_MASK (1 << 7)
 374 #define AR_L_MASK (1 << 13)
 375 #define AR_DB_MASK (1 << 14)
 376 #define AR_G_MASK (1 << 15)
 377 #define AR_DPL_SHIFT 5
 378 #define AR_DPL(ar) (((ar) >> AR_DPL_SHIFT) & 3)
 379
 380 #define AR_RESERVD_MASK 0xfffe0f00
 381
 382 #define TSS_PRIVATE_MEMSLOT                     (KVM_MEMORY_SLOTS + 0)
 383 #define APIC_ACCESS_PAGE_PRIVATE_MEMSLOT        (KVM_MEMORY_SLOTS + 1)
 384 #define IDENTITY_PAGETABLE_PRIVATE_MEMSLOT      (KVM_MEMORY_SLOTS + 2)
 385
 386 #define VMX_NR_VPIDS                            (1 << 16)
 387 #define VMX_VPID_EXTENT_SINGLE_CONTEXT          1
 388 #define VMX_VPID_EXTENT_ALL_CONTEXT             2
 389
 390 #define VMX_EPT_EXTENT_INDIVIDUAL_ADDR          0
 391 #define VMX_EPT_EXTENT_CONTEXT                  1
 392 #define VMX_EPT_EXTENT_GLOBAL                   2
 393 #define VMX_EPT_EXTENT_INDIVIDUAL_BIT           (1ull << 24)
 394 #define VMX_EPT_EXTENT_CONTEXT_BIT              (1ull << 25)
 395 #define VMX_EPT_EXTENT_GLOBAL_BIT               (1ull << 26)
 396 #define VMX_EPT_DEFAULT_GAW                     3
 397 #define VMX_EPT_MAX_GAW                         0x4
 398 #define VMX_EPT_MT_EPTE_SHIFT                   3
 399 #define VMX_EPT_GAW_EPTP_SHIFT                  3
 400 #define VMX_EPT_DEFAULT_MT                      0x6ull
 401 #define VMX_EPT_READABLE_MASK                   0x1ull
 402 #define VMX_EPT_WRITABLE_MASK                   0x2ull
 403 #define VMX_EPT_EXECUTABLE_MASK                 0x4ull
 404 #define VMX_EPT_IGMT_BIT                        (1ull << 6)
 405
 406 #define VMX_EPT_IDENTITY_PAGETABLE_ADDR         0xfffbc000ul
 407
 408
 409 #define ASM_VMX_VMCLEAR_RAX       ".byte 0x66, 0x0f, 0xc7, 0x30"
 410 #define ASM_VMX_VMLAUNCH          ".byte 0x0f, 0x01, 0xc2"
 411 #define ASM_VMX_VMRESUME          ".byte 0x0f, 0x01, 0xc3"
 412 #define ASM_VMX_VMPTRLD_RAX       ".byte 0x0f, 0xc7, 0x30"
 413 #define ASM_VMX_VMREAD_RDX_RAX    ".byte 0x0f, 0x78, 0xd0"
 414 #define ASM_VMX_VMWRITE_RAX_RDX   ".byte 0x0f, 0x79, 0xd0"
 415 #define ASM_VMX_VMWRITE_RSP_RDX   ".byte 0x0f, 0x79, 0xd4"
 416 #define ASM_VMX_VMXOFF            ".byte 0x0f, 0x01, 0xc4"
 417 #define ASM_VMX_VMXON_RAX         ".byte 0xf3, 0x0f, 0xc7, 0x30"
 418 #define ASM_VMX_INVEPT            ".byte 0x66, 0x0f, 0x38, 0x80, 0x08"
 419 #define ASM_VMX_INVVPID           ".byte 0x66, 0x0f, 0x38, 0x81, 0x08"
 420
 421
 422
 423 #endif