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fold libkvm-all into standard qemu header
[qemu-kvm/fedora.git] / qemu-kvm-x86.c
blobb531ca46abdbb9fdf1933fd2fdb5ebdfe57c8ff3
1 /*
2 * qemu/kvm integration, x86 specific code
3 *
4 * Copyright (C) 2006-2008 Qumranet Technologies
5 *
6 * Licensed under the terms of the GNU GPL version 2 or higher.
7 */
8
9 #include "config.h"
10 #include "config-host.h"
11
12 #include <string.h>
13 #include "hw/hw.h"
14 #include "gdbstub.h"
15 #include <sys/io.h>
16
17 #include "qemu-kvm.h"
18 #include "libkvm.h"
19 #include <pthread.h>
20 #include <sys/utsname.h>
21 #include <linux/kvm_para.h>
22 #include <sys/ioctl.h>
23
24 #include "kvm.h"
25 #include "hw/pc.h"
26
27 #define MSR_IA32_TSC 0x10
28
29 static struct kvm_msr_list *kvm_msr_list;
30 extern unsigned int kvm_shadow_memory;
31 static int kvm_has_msr_star;
32 static int kvm_has_vm_hsave_pa;
33
34 static int lm_capable_kernel;
35
36 int kvm_set_tss_addr(kvm_context_t kvm, unsigned long addr)
37 {
38 #ifdef KVM_CAP_SET_TSS_ADDR
39 int r;
40
41 r = ioctl(kvm->fd, KVM_CHECK_EXTENSION, KVM_CAP_SET_TSS_ADDR);
42 if (r > 0) {
43 r = ioctl(kvm->vm_fd, KVM_SET_TSS_ADDR, addr);
44 if (r == -1) {
45 fprintf(stderr, "kvm_set_tss_addr: %m\n");
46 return -errno;
47 }
48 return 0;
49 }
50 #endif
51 return -ENOSYS;
52 }
53
54 static int kvm_init_tss(kvm_context_t kvm)
55 {
56 #ifdef KVM_CAP_SET_TSS_ADDR
57 int r;
58
59 r = ioctl(kvm->fd, KVM_CHECK_EXTENSION, KVM_CAP_SET_TSS_ADDR);
60 if (r > 0) {
61 /*
62 * this address is 3 pages before the bios, and the bios should present
63 * as unavaible memory
64 */
65 r = kvm_set_tss_addr(kvm, 0xfffbd000);
66 if (r < 0) {
67 fprintf(stderr, "kvm_init_tss: unable to set tss addr\n");
68 return r;
69 }
70
71 }
72 #endif
73 return 0;
74 }
75
76 static int kvm_create_pit(kvm_context_t kvm)
77 {
78 #ifdef KVM_CAP_PIT
79 int r;
80
81 kvm->pit_in_kernel = 0;
82 if (!kvm->no_pit_creation) {
83 r = ioctl(kvm->fd, KVM_CHECK_EXTENSION, KVM_CAP_PIT);
84 if (r > 0) {
85 r = ioctl(kvm->vm_fd, KVM_CREATE_PIT);
86 if (r >= 0)
87 kvm->pit_in_kernel = 1;
88 else {
89 fprintf(stderr, "Create kernel PIC irqchip failed\n");
90 return r;
91 }
92 }
93 }
94 #endif
95 return 0;
96 }
97
98 int kvm_arch_create(kvm_context_t kvm, unsigned long phys_mem_bytes,
99 void **vm_mem)
100 {
101 int r = 0;
102
103 r = kvm_init_tss(kvm);
104 if (r < 0)
105 return r;
106
107 r = kvm_create_pit(kvm);
108 if (r < 0)
109 return r;
110
111 r = kvm_init_coalesced_mmio(kvm);
112 if (r < 0)
113 return r;
114
115 return 0;
116 }
117
118 #ifdef KVM_EXIT_TPR_ACCESS
119
120 static int kvm_handle_tpr_access(kvm_vcpu_context_t vcpu)
121 {
122 struct kvm_run *run = vcpu->run;
123 kvm_tpr_access_report(cpu_single_env,
124 run->tpr_access.rip,
125 run->tpr_access.is_write);
126 return 0;
127 }
128
129
130 int kvm_enable_vapic(kvm_vcpu_context_t vcpu, uint64_t vapic)
131 {
132 int r;
133 struct kvm_vapic_addr va = {
134 .vapic_addr = vapic,
135 };
136
137 r = ioctl(vcpu->fd, KVM_SET_VAPIC_ADDR, &va);
138 if (r == -1) {
139 r = -errno;
140 perror("kvm_enable_vapic");
141 return r;
142 }
143 return 0;
144 }
145
146 #endif
147
148 int kvm_arch_run(kvm_vcpu_context_t vcpu)
149 {
150 int r = 0;
151 struct kvm_run *run = vcpu->run;
152
153
154 switch (run->exit_reason) {
155 #ifdef KVM_EXIT_SET_TPR
156 case KVM_EXIT_SET_TPR:
157 break;
158 #endif
159 #ifdef KVM_EXIT_TPR_ACCESS
160 case KVM_EXIT_TPR_ACCESS:
161 r = kvm_handle_tpr_access(vcpu);
162 break;
163 #endif
164 default:
165 r = 1;
166 break;
167 }
168
169 return r;
170 }
171
172 #define MAX_ALIAS_SLOTS 4
173 static struct {
174 uint64_t start;
175 uint64_t len;
176 } kvm_aliases[MAX_ALIAS_SLOTS];
177
178 static int get_alias_slot(uint64_t start)
179 {
180 int i;
181
182 for (i=0; i<MAX_ALIAS_SLOTS; i++)
183 if (kvm_aliases[i].start == start)
184 return i;
185 return -1;
186 }
187 static int get_free_alias_slot(void)
188 {
189 int i;
190
191 for (i=0; i<MAX_ALIAS_SLOTS; i++)
192 if (kvm_aliases[i].len == 0)
193 return i;
194 return -1;
195 }
196
197 static void register_alias(int slot, uint64_t start, uint64_t len)
198 {
199 kvm_aliases[slot].start = start;
200 kvm_aliases[slot].len = len;
201 }
202
203 int kvm_create_memory_alias(kvm_context_t kvm,
204 uint64_t phys_start,
205 uint64_t len,
206 uint64_t target_phys)
207 {
208 struct kvm_memory_alias alias = {
209 .flags = 0,
210 .guest_phys_addr = phys_start,
211 .memory_size = len,
212 .target_phys_addr = target_phys,
213 };
214 int fd = kvm->vm_fd;
215 int r;
216 int slot;
217
218 slot = get_alias_slot(phys_start);
219 if (slot < 0)
220 slot = get_free_alias_slot();
221 if (slot < 0)
222 return -EBUSY;
223 alias.slot = slot;
224
225 r = ioctl(fd, KVM_SET_MEMORY_ALIAS, &alias);
226 if (r == -1)
227 return -errno;
228
229 register_alias(slot, phys_start, len);
230 return 0;
231 }
232
233 int kvm_destroy_memory_alias(kvm_context_t kvm, uint64_t phys_start)
234 {
235 return kvm_create_memory_alias(kvm, phys_start, 0, 0);
236 }
237
238 #ifdef KVM_CAP_IRQCHIP
239
240 int kvm_get_lapic(kvm_vcpu_context_t vcpu, struct kvm_lapic_state *s)
241 {
242 int r;
243 if (!kvm_irqchip_in_kernel(vcpu->kvm))
244 return 0;
245 r = ioctl(vcpu->fd, KVM_GET_LAPIC, s);
246 if (r == -1) {
247 r = -errno;
248 perror("kvm_get_lapic");
249 }
250 return r;
251 }
252
253 int kvm_set_lapic(kvm_vcpu_context_t vcpu, struct kvm_lapic_state *s)
254 {
255 int r;
256 if (!kvm_irqchip_in_kernel(vcpu->kvm))
257 return 0;
258 r = ioctl(vcpu->fd, KVM_SET_LAPIC, s);
259 if (r == -1) {
260 r = -errno;
261 perror("kvm_set_lapic");
262 }
263 return r;
264 }
265
266 #endif
267
268 #ifdef KVM_CAP_PIT
269
270 int kvm_get_pit(kvm_context_t kvm, struct kvm_pit_state *s)
271 {
272 int r;
273 if (!kvm->pit_in_kernel)
274 return 0;
275 r = ioctl(kvm->vm_fd, KVM_GET_PIT, s);
276 if (r == -1) {
277 r = -errno;
278 perror("kvm_get_pit");
279 }
280 return r;
281 }
282
283 int kvm_set_pit(kvm_context_t kvm, struct kvm_pit_state *s)
284 {
285 int r;
286 if (!kvm->pit_in_kernel)
287 return 0;
288 r = ioctl(kvm->vm_fd, KVM_SET_PIT, s);
289 if (r == -1) {
290 r = -errno;
291 perror("kvm_set_pit");
292 }
293 return r;
294 }
295
296 #ifdef KVM_CAP_PIT_STATE2
297 int kvm_get_pit2(kvm_context_t kvm, struct kvm_pit_state2 *ps2)
298 {
299 int r;
300 if (!kvm->pit_in_kernel)
301 return 0;
302 r = ioctl(kvm->vm_fd, KVM_GET_PIT2, ps2);
303 if (r == -1) {
304 r = -errno;
305 perror("kvm_get_pit2");
306 }
307 return r;
308 }
309
310 int kvm_set_pit2(kvm_context_t kvm, struct kvm_pit_state2 *ps2)
311 {
312 int r;
313 if (!kvm->pit_in_kernel)
314 return 0;
315 r = ioctl(kvm->vm_fd, KVM_SET_PIT2, ps2);
316 if (r == -1) {
317 r = -errno;
318 perror("kvm_set_pit2");
319 }
320 return r;
321 }
322
323 #endif
324 #endif
325
326 int kvm_has_pit_state2(kvm_context_t kvm)
327 {
328 int r = 0;
329
330 #ifdef KVM_CAP_PIT_STATE2
331 r = kvm_check_extension(kvm, KVM_CAP_PIT_STATE2);
332 #endif
333 return r;
334 }
335
336 void kvm_show_code(kvm_vcpu_context_t vcpu)
337 {
338 #define SHOW_CODE_LEN 50
339 int fd = vcpu->fd;
340 struct kvm_regs regs;
341 struct kvm_sregs sregs;
342 int r, n;
343 int back_offset;
344 unsigned char code;
345 char code_str[SHOW_CODE_LEN * 3 + 1];
346 unsigned long rip;
347 kvm_context_t kvm = vcpu->kvm;
348
349 r = ioctl(fd, KVM_GET_SREGS, &sregs);
350 if (r == -1) {
351 perror("KVM_GET_SREGS");
352 return;
353 }
354 r = ioctl(fd, KVM_GET_REGS, &regs);
355 if (r == -1) {
356 perror("KVM_GET_REGS");
357 return;
358 }
359 rip = sregs.cs.base + regs.rip;
360 back_offset = regs.rip;
361 if (back_offset > 20)
362 back_offset = 20;
363 *code_str = 0;
364 for (n = -back_offset; n < SHOW_CODE_LEN-back_offset; ++n) {
365 if (n == 0)
366 strcat(code_str, " -->");
367 r = kvm_mmio_read(kvm->opaque, rip + n, &code, 1);
368 if (r < 0) {
369 strcat(code_str, " xx");
370 continue;
371 }
372 sprintf(code_str + strlen(code_str), " %02x", code);
373 }
374 fprintf(stderr, "code:%s\n", code_str);
375 }
376
377
378 /*
379 * Returns available msr list. User must free.
380 */
381 struct kvm_msr_list *kvm_get_msr_list(kvm_context_t kvm)
382 {
383 struct kvm_msr_list sizer, *msrs;
384 int r, e;
385
386 sizer.nmsrs = 0;
387 r = ioctl(kvm->fd, KVM_GET_MSR_INDEX_LIST, &sizer);
388 if (r == -1 && errno != E2BIG)
389 return NULL;
390 /* Old kernel modules had a bug and could write beyond the provided
391 memory. Allocate at least a safe amount of 1K. */
392 msrs = qemu_malloc(MAX(1024, sizeof(*msrs) +
393 sizer.nmsrs * sizeof(*msrs->indices)));
394
395 msrs->nmsrs = sizer.nmsrs;
396 r = ioctl(kvm->fd, KVM_GET_MSR_INDEX_LIST, msrs);
397 if (r == -1) {
398 e = errno;
399 free(msrs);
400 errno = e;
401 return NULL;
402 }
403 return msrs;
404 }
405
406 int kvm_get_msrs(kvm_vcpu_context_t vcpu, struct kvm_msr_entry *msrs, int n)
407 {
408 struct kvm_msrs *kmsrs = qemu_malloc(sizeof *kmsrs + n * sizeof *msrs);
409 int r, e;
410
411 kmsrs->nmsrs = n;
412 memcpy(kmsrs->entries, msrs, n * sizeof *msrs);
413 r = ioctl(vcpu->fd, KVM_GET_MSRS, kmsrs);
414 e = errno;
415 memcpy(msrs, kmsrs->entries, n * sizeof *msrs);
416 free(kmsrs);
417 errno = e;
418 return r;
419 }
420
421 int kvm_set_msrs(kvm_vcpu_context_t vcpu, struct kvm_msr_entry *msrs, int n)
422 {
423 struct kvm_msrs *kmsrs = qemu_malloc(sizeof *kmsrs + n * sizeof *msrs);
424 int r, e;
425
426 kmsrs->nmsrs = n;
427 memcpy(kmsrs->entries, msrs, n * sizeof *msrs);
428 r = ioctl(vcpu->fd, KVM_SET_MSRS, kmsrs);
429 e = errno;
430 free(kmsrs);
431 errno = e;
432 return r;
433 }
434
435 static void print_seg(FILE *file, const char *name, struct kvm_segment *seg)
436 {
437 fprintf(stderr,
438 "%s %04x (%08llx/%08x p %d dpl %d db %d s %d type %x l %d"
439 " g %d avl %d)\n",
440 name, seg->selector, seg->base, seg->limit, seg->present,
441 seg->dpl, seg->db, seg->s, seg->type, seg->l, seg->g,
442 seg->avl);
443 }
444
445 static void print_dt(FILE *file, const char *name, struct kvm_dtable *dt)
446 {
447 fprintf(stderr, "%s %llx/%x\n", name, dt->base, dt->limit);
448 }
449
450 void kvm_show_regs(kvm_vcpu_context_t vcpu)
451 {
452 int fd = vcpu->fd;
453 struct kvm_regs regs;
454 struct kvm_sregs sregs;
455 int r;
456
457 r = ioctl(fd, KVM_GET_REGS, &regs);
458 if (r == -1) {
459 perror("KVM_GET_REGS");
460 return;
461 }
462 fprintf(stderr,
463 "rax %016llx rbx %016llx rcx %016llx rdx %016llx\n"
464 "rsi %016llx rdi %016llx rsp %016llx rbp %016llx\n"
465 "r8 %016llx r9 %016llx r10 %016llx r11 %016llx\n"
466 "r12 %016llx r13 %016llx r14 %016llx r15 %016llx\n"
467 "rip %016llx rflags %08llx\n",
468 regs.rax, regs.rbx, regs.rcx, regs.rdx,
469 regs.rsi, regs.rdi, regs.rsp, regs.rbp,
470 regs.r8, regs.r9, regs.r10, regs.r11,
471 regs.r12, regs.r13, regs.r14, regs.r15,
472 regs.rip, regs.rflags);
473 r = ioctl(fd, KVM_GET_SREGS, &sregs);
474 if (r == -1) {
475 perror("KVM_GET_SREGS");
476 return;
477 }
478 print_seg(stderr, "cs", &sregs.cs);
479 print_seg(stderr, "ds", &sregs.ds);
480 print_seg(stderr, "es", &sregs.es);
481 print_seg(stderr, "ss", &sregs.ss);
482 print_seg(stderr, "fs", &sregs.fs);
483 print_seg(stderr, "gs", &sregs.gs);
484 print_seg(stderr, "tr", &sregs.tr);
485 print_seg(stderr, "ldt", &sregs.ldt);
486 print_dt(stderr, "gdt", &sregs.gdt);
487 print_dt(stderr, "idt", &sregs.idt);
488 fprintf(stderr, "cr0 %llx cr2 %llx cr3 %llx cr4 %llx cr8 %llx"
489 " efer %llx\n",
490 sregs.cr0, sregs.cr2, sregs.cr3, sregs.cr4, sregs.cr8,
491 sregs.efer);
492 }
493
494 uint64_t kvm_get_apic_base(kvm_vcpu_context_t vcpu)
495 {
496 return vcpu->run->apic_base;
497 }
498
499 void kvm_set_cr8(kvm_vcpu_context_t vcpu, uint64_t cr8)
500 {
501 vcpu->run->cr8 = cr8;
502 }
503
504 __u64 kvm_get_cr8(kvm_vcpu_context_t vcpu)
505 {
506 return vcpu->run->cr8;
507 }
508
509 int kvm_setup_cpuid(kvm_vcpu_context_t vcpu, int nent,
510 struct kvm_cpuid_entry *entries)
511 {
512 struct kvm_cpuid *cpuid;
513 int r;
514
515 cpuid = qemu_malloc(sizeof(*cpuid) + nent * sizeof(*entries));
516
517 cpuid->nent = nent;
518 memcpy(cpuid->entries, entries, nent * sizeof(*entries));
519 r = ioctl(vcpu->fd, KVM_SET_CPUID, cpuid);
520
521 free(cpuid);
522 return r;
523 }
524
525 int kvm_setup_cpuid2(kvm_vcpu_context_t vcpu, int nent,
526 struct kvm_cpuid_entry2 *entries)
527 {
528 struct kvm_cpuid2 *cpuid;
529 int r;
530
531 cpuid = qemu_malloc(sizeof(*cpuid) + nent * sizeof(*entries));
532
533 cpuid->nent = nent;
534 memcpy(cpuid->entries, entries, nent * sizeof(*entries));
535 r = ioctl(vcpu->fd, KVM_SET_CPUID2, cpuid);
536 if (r == -1) {
537 fprintf(stderr, "kvm_setup_cpuid2: %m\n");
538 return -errno;
539 }
540 free(cpuid);
541 return r;
542 }
543
544 int kvm_set_shadow_pages(kvm_context_t kvm, unsigned int nrshadow_pages)
545 {
546 #ifdef KVM_CAP_MMU_SHADOW_CACHE_CONTROL
547 int r;
548
549 r = ioctl(kvm->fd, KVM_CHECK_EXTENSION,
550 KVM_CAP_MMU_SHADOW_CACHE_CONTROL);
551 if (r > 0) {
552 r = ioctl(kvm->vm_fd, KVM_SET_NR_MMU_PAGES, nrshadow_pages);
553 if (r == -1) {
554 fprintf(stderr, "kvm_set_shadow_pages: %m\n");
555 return -errno;
556 }
557 return 0;
558 }
559 #endif
560 return -1;
561 }
562
563 int kvm_get_shadow_pages(kvm_context_t kvm, unsigned int *nrshadow_pages)
564 {
565 #ifdef KVM_CAP_MMU_SHADOW_CACHE_CONTROL
566 int r;
567
568 r = ioctl(kvm->fd, KVM_CHECK_EXTENSION,
569 KVM_CAP_MMU_SHADOW_CACHE_CONTROL);
570 if (r > 0) {
571 *nrshadow_pages = ioctl(kvm->vm_fd, KVM_GET_NR_MMU_PAGES);
572 return 0;
573 }
574 #endif
575 return -1;
576 }
577
578 #ifdef KVM_CAP_VAPIC
579
580 static int tpr_access_reporting(kvm_vcpu_context_t vcpu, int enabled)
581 {
582 int r;
583 struct kvm_tpr_access_ctl tac = {
584 .enabled = enabled,
585 };
586
587 r = ioctl(vcpu->kvm->fd, KVM_CHECK_EXTENSION, KVM_CAP_VAPIC);
588 if (r == -1 || r == 0)
589 return -ENOSYS;
590 r = ioctl(vcpu->fd, KVM_TPR_ACCESS_REPORTING, &tac);
591 if (r == -1) {
592 r = -errno;
593 perror("KVM_TPR_ACCESS_REPORTING");
594 return r;
595 }
596 return 0;
597 }
598
599 int kvm_enable_tpr_access_reporting(kvm_vcpu_context_t vcpu)
600 {
601 return tpr_access_reporting(vcpu, 1);
602 }
603
604 int kvm_disable_tpr_access_reporting(kvm_vcpu_context_t vcpu)
605 {
606 return tpr_access_reporting(vcpu, 0);
607 }
608
609 #endif
610
611 #ifdef KVM_CAP_EXT_CPUID
612
613 static struct kvm_cpuid2 *try_get_cpuid(kvm_context_t kvm, int max)
614 {
615 struct kvm_cpuid2 *cpuid;
616 int r, size;
617
618 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
619 cpuid = qemu_malloc(size);
620 cpuid->nent = max;
621 r = ioctl(kvm->fd, KVM_GET_SUPPORTED_CPUID, cpuid);
622 if (r == -1)
623 r = -errno;
624 else if (r == 0 && cpuid->nent >= max)
625 r = -E2BIG;
626 if (r < 0) {
627 if (r == -E2BIG) {
628 free(cpuid);
629 return NULL;
630 } else {
631 fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
632 strerror(-r));
633 exit(1);
634 }
635 }
636 return cpuid;
637 }
638
639 #define R_EAX 0
640 #define R_ECX 1
641 #define R_EDX 2
642 #define R_EBX 3
643 #define R_ESP 4
644 #define R_EBP 5
645 #define R_ESI 6
646 #define R_EDI 7
647
648 uint32_t kvm_get_supported_cpuid(kvm_context_t kvm, uint32_t function, int reg)
649 {
650 struct kvm_cpuid2 *cpuid;
651 int i, max;
652 uint32_t ret = 0;
653 uint32_t cpuid_1_edx;
654
655 if (!kvm_check_extension(kvm, KVM_CAP_EXT_CPUID)) {
656 return -1U;
657 }
658
659 max = 1;
660 while ((cpuid = try_get_cpuid(kvm, max)) == NULL) {
661 max *= 2;
662 }
663
664 for (i = 0; i < cpuid->nent; ++i) {
665 if (cpuid->entries[i].function == function) {
666 switch (reg) {
667 case R_EAX:
668 ret = cpuid->entries[i].eax;
669 break;
670 case R_EBX:
671 ret = cpuid->entries[i].ebx;
672 break;
673 case R_ECX:
674 ret = cpuid->entries[i].ecx;
675 break;
676 case R_EDX:
677 ret = cpuid->entries[i].edx;
678 if (function == 1) {
679 /* kvm misreports the following features
680 */
681 ret |= 1 << 12; /* MTRR */
682 ret |= 1 << 16; /* PAT */
683 ret |= 1 << 7; /* MCE */
684 ret |= 1 << 14; /* MCA */
685 }
686
687 /* On Intel, kvm returns cpuid according to
688 * the Intel spec, so add missing bits
689 * according to the AMD spec:
690 */
691 if (function == 0x80000001) {
692 cpuid_1_edx = kvm_get_supported_cpuid(kvm, 1, R_EDX);
693 ret |= cpuid_1_edx & 0xdfeff7ff;
694 }
695 break;
696 }
697 }
698 }
699
700 free(cpuid);
701
702 return ret;
703 }
704
705 #else
706
707 uint32_t kvm_get_supported_cpuid(kvm_context_t kvm, uint32_t function, int reg)
708 {
709 return -1U;
710 }
711
712 #endif
713 int kvm_qemu_create_memory_alias(uint64_t phys_start,
714 uint64_t len,
715 uint64_t target_phys)
716 {
717 return kvm_create_memory_alias(kvm_context, phys_start, len, target_phys);
718 }
719
720 int kvm_qemu_destroy_memory_alias(uint64_t phys_start)
721 {
722 return kvm_destroy_memory_alias(kvm_context, phys_start);
723 }
724
725 int kvm_arch_qemu_create_context(void)
726 {
727 int i;
728 struct utsname utsname;
729
730 uname(&utsname);
731 lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
732
733 if (kvm_shadow_memory)
734 kvm_set_shadow_pages(kvm_context, kvm_shadow_memory);
735
736 kvm_msr_list = kvm_get_msr_list(kvm_context);
737 if (!kvm_msr_list)
738 return -1;
739 for (i = 0; i < kvm_msr_list->nmsrs; ++i) {
740 if (kvm_msr_list->indices[i] == MSR_STAR)
741 kvm_has_msr_star = 1;
742 if (kvm_msr_list->indices[i] == MSR_VM_HSAVE_PA)
743 kvm_has_vm_hsave_pa = 1;
744 }
745
746 return 0;
747 }
748
749 static void set_msr_entry(struct kvm_msr_entry *entry, uint32_t index,
750 uint64_t data)
751 {
752 entry->index = index;
753 entry->data = data;
754 }
755
756 /* returns 0 on success, non-0 on failure */
757 static int get_msr_entry(struct kvm_msr_entry *entry, CPUState *env)
758 {
759 switch (entry->index) {
760 case MSR_IA32_SYSENTER_CS:
761 env->sysenter_cs = entry->data;
762 break;
763 case MSR_IA32_SYSENTER_ESP:
764 env->sysenter_esp = entry->data;
765 break;
766 case MSR_IA32_SYSENTER_EIP:
767 env->sysenter_eip = entry->data;
768 break;
769 case MSR_STAR:
770 env->star = entry->data;
771 break;
772 #ifdef TARGET_X86_64
773 case MSR_CSTAR:
774 env->cstar = entry->data;
775 break;
776 case MSR_KERNELGSBASE:
777 env->kernelgsbase = entry->data;
778 break;
779 case MSR_FMASK:
780 env->fmask = entry->data;
781 break;
782 case MSR_LSTAR:
783 env->lstar = entry->data;
784 break;
785 #endif
786 case MSR_IA32_TSC:
787 env->tsc = entry->data;
788 break;
789 case MSR_VM_HSAVE_PA:
790 env->vm_hsave = entry->data;
791 break;
792 default:
793 printf("Warning unknown msr index 0x%x\n", entry->index);
794 return 1;
795 }
796 return 0;
797 }
798
799 #ifdef TARGET_X86_64
800 #define MSR_COUNT 9
801 #else
802 #define MSR_COUNT 5
803 #endif
804
805 static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
806 {
807 lhs->selector = rhs->selector;
808 lhs->base = rhs->base;
809 lhs->limit = rhs->limit;
810 lhs->type = 3;
811 lhs->present = 1;
812 lhs->dpl = 3;
813 lhs->db = 0;
814 lhs->s = 1;
815 lhs->l = 0;
816 lhs->g = 0;
817 lhs->avl = 0;
818 lhs->unusable = 0;
819 }
820
821 static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
822 {
823 unsigned flags = rhs->flags;
824 lhs->selector = rhs->selector;
825 lhs->base = rhs->base;
826 lhs->limit = rhs->limit;
827 lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
828 lhs->present = (flags & DESC_P_MASK) != 0;
829 lhs->dpl = rhs->selector & 3;
830 lhs->db = (flags >> DESC_B_SHIFT) & 1;
831 lhs->s = (flags & DESC_S_MASK) != 0;
832 lhs->l = (flags >> DESC_L_SHIFT) & 1;
833 lhs->g = (flags & DESC_G_MASK) != 0;
834 lhs->avl = (flags & DESC_AVL_MASK) != 0;
835 lhs->unusable = 0;
836 }
837
838 static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
839 {
840 lhs->selector = rhs->selector;
841 lhs->base = rhs->base;
842 lhs->limit = rhs->limit;
843 lhs->flags =
844 (rhs->type << DESC_TYPE_SHIFT)
845 | (rhs->present * DESC_P_MASK)
846 | (rhs->dpl << DESC_DPL_SHIFT)
847 | (rhs->db << DESC_B_SHIFT)
848 | (rhs->s * DESC_S_MASK)
849 | (rhs->l << DESC_L_SHIFT)
850 | (rhs->g * DESC_G_MASK)
851 | (rhs->avl * DESC_AVL_MASK);
852 }
853
854 void kvm_arch_load_regs(CPUState *env)
855 {
856 struct kvm_regs regs;
857 struct kvm_fpu fpu;
858 struct kvm_sregs sregs;
859 struct kvm_msr_entry msrs[MSR_COUNT];
860 int rc, n, i;
861
862 regs.rax = env->regs[R_EAX];
863 regs.rbx = env->regs[R_EBX];
864 regs.rcx = env->regs[R_ECX];
865 regs.rdx = env->regs[R_EDX];
866 regs.rsi = env->regs[R_ESI];
867 regs.rdi = env->regs[R_EDI];
868 regs.rsp = env->regs[R_ESP];
869 regs.rbp = env->regs[R_EBP];
870 #ifdef TARGET_X86_64
871 regs.r8 = env->regs[8];
872 regs.r9 = env->regs[9];
873 regs.r10 = env->regs[10];
874 regs.r11 = env->regs[11];
875 regs.r12 = env->regs[12];
876 regs.r13 = env->regs[13];
877 regs.r14 = env->regs[14];
878 regs.r15 = env->regs[15];
879 #endif
880
881 regs.rflags = env->eflags;
882 regs.rip = env->eip;
883
884 kvm_set_regs(env->kvm_cpu_state.vcpu_ctx, &regs);
885
886 memset(&fpu, 0, sizeof fpu);
887 fpu.fsw = env->fpus & ~(7 << 11);
888 fpu.fsw |= (env->fpstt & 7) << 11;
889 fpu.fcw = env->fpuc;
890 for (i = 0; i < 8; ++i)
891 fpu.ftwx |= (!env->fptags[i]) << i;
892 memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
893 memcpy(fpu.xmm, env->xmm_regs, sizeof env->xmm_regs);
894 fpu.mxcsr = env->mxcsr;
895 kvm_set_fpu(env->kvm_cpu_state.vcpu_ctx, &fpu);
896
897 memcpy(sregs.interrupt_bitmap, env->interrupt_bitmap, sizeof(sregs.interrupt_bitmap));
898
899 if ((env->eflags & VM_MASK)) {
900 set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
901 set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
902 set_v8086_seg(&sregs.es, &env->segs[R_ES]);
903 set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
904 set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
905 set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
906 } else {
907 set_seg(&sregs.cs, &env->segs[R_CS]);
908 set_seg(&sregs.ds, &env->segs[R_DS]);
909 set_seg(&sregs.es, &env->segs[R_ES]);
910 set_seg(&sregs.fs, &env->segs[R_FS]);
911 set_seg(&sregs.gs, &env->segs[R_GS]);
912 set_seg(&sregs.ss, &env->segs[R_SS]);
913
914 if (env->cr[0] & CR0_PE_MASK) {
915 /* force ss cpl to cs cpl */
916 sregs.ss.selector = (sregs.ss.selector & ~3) |
917 (sregs.cs.selector & 3);
918 sregs.ss.dpl = sregs.ss.selector & 3;
919 }
920 }
921
922 set_seg(&sregs.tr, &env->tr);
923 set_seg(&sregs.ldt, &env->ldt);
924
925 sregs.idt.limit = env->idt.limit;
926 sregs.idt.base = env->idt.base;
927 sregs.gdt.limit = env->gdt.limit;
928 sregs.gdt.base = env->gdt.base;
929
930 sregs.cr0 = env->cr[0];
931 sregs.cr2 = env->cr[2];
932 sregs.cr3 = env->cr[3];
933 sregs.cr4 = env->cr[4];
934
935 sregs.cr8 = cpu_get_apic_tpr(env);
936 sregs.apic_base = cpu_get_apic_base(env);
937
938 sregs.efer = env->efer;
939
940 kvm_set_sregs(env->kvm_cpu_state.vcpu_ctx, &sregs);
941
942 /* msrs */
943 n = 0;
944 set_msr_entry(&msrs[n++], MSR_IA32_SYSENTER_CS, env->sysenter_cs);
945 set_msr_entry(&msrs[n++], MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
946 set_msr_entry(&msrs[n++], MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
947 if (kvm_has_msr_star)
948 set_msr_entry(&msrs[n++], MSR_STAR, env->star);
949 if (kvm_has_vm_hsave_pa)
950 set_msr_entry(&msrs[n++], MSR_VM_HSAVE_PA, env->vm_hsave);
951 #ifdef TARGET_X86_64
952 if (lm_capable_kernel) {
953 set_msr_entry(&msrs[n++], MSR_CSTAR, env->cstar);
954 set_msr_entry(&msrs[n++], MSR_KERNELGSBASE, env->kernelgsbase);
955 set_msr_entry(&msrs[n++], MSR_FMASK, env->fmask);
956 set_msr_entry(&msrs[n++], MSR_LSTAR , env->lstar);
957 }
958 #endif
959
960 rc = kvm_set_msrs(env->kvm_cpu_state.vcpu_ctx, msrs, n);
961 if (rc == -1)
962 perror("kvm_set_msrs FAILED");
963 }
964
965 void kvm_load_tsc(CPUState *env)
966 {
967 int rc;
968 struct kvm_msr_entry msr;
969
970 set_msr_entry(&msr, MSR_IA32_TSC, env->tsc);
971
972 rc = kvm_set_msrs(env->kvm_cpu_state.vcpu_ctx, &msr, 1);
973 if (rc == -1)
974 perror("kvm_set_tsc FAILED.\n");
975 }
976
977 void kvm_arch_save_mpstate(CPUState *env)
978 {
979 #ifdef KVM_CAP_MP_STATE
980 int r;
981 struct kvm_mp_state mp_state;
982
983 r = kvm_get_mpstate(env->kvm_cpu_state.vcpu_ctx, &mp_state);
984 if (r < 0)
985 env->mp_state = -1;
986 else
987 env->mp_state = mp_state.mp_state;
988 #endif
989 }
990
991 void kvm_arch_load_mpstate(CPUState *env)
992 {
993 #ifdef KVM_CAP_MP_STATE
994 struct kvm_mp_state mp_state = { .mp_state = env->mp_state };
995
996 /*
997 * -1 indicates that the host did not support GET_MP_STATE ioctl,
998 * so don't touch it.
999 */
1000 if (env->mp_state != -1)
1001 kvm_set_mpstate(env->kvm_cpu_state.vcpu_ctx, &mp_state);
1002 #endif
1003 }
1004
1005 void kvm_arch_save_regs(CPUState *env)
1006 {
1007 struct kvm_regs regs;
1008 struct kvm_fpu fpu;
1009 struct kvm_sregs sregs;
1010 struct kvm_msr_entry msrs[MSR_COUNT];
1011 uint32_t hflags;
1012 uint32_t i, n, rc;
1013
1014 kvm_get_regs(env->kvm_cpu_state.vcpu_ctx, &regs);
1015
1016 env->regs[R_EAX] = regs.rax;
1017 env->regs[R_EBX] = regs.rbx;
1018 env->regs[R_ECX] = regs.rcx;
1019 env->regs[R_EDX] = regs.rdx;
1020 env->regs[R_ESI] = regs.rsi;
1021 env->regs[R_EDI] = regs.rdi;
1022 env->regs[R_ESP] = regs.rsp;
1023 env->regs[R_EBP] = regs.rbp;
1024 #ifdef TARGET_X86_64
1025 env->regs[8] = regs.r8;
1026 env->regs[9] = regs.r9;
1027 env->regs[10] = regs.r10;
1028 env->regs[11] = regs.r11;
1029 env->regs[12] = regs.r12;
1030 env->regs[13] = regs.r13;
1031 env->regs[14] = regs.r14;
1032 env->regs[15] = regs.r15;
1033 #endif
1034
1035 env->eflags = regs.rflags;
1036 env->eip = regs.rip;
1037
1038 kvm_get_fpu(env->kvm_cpu_state.vcpu_ctx, &fpu);
1039 env->fpstt = (fpu.fsw >> 11) & 7;
1040 env->fpus = fpu.fsw;
1041 env->fpuc = fpu.fcw;
1042 for (i = 0; i < 8; ++i)
1043 env->fptags[i] = !((fpu.ftwx >> i) & 1);
1044 memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
1045 memcpy(env->xmm_regs, fpu.xmm, sizeof env->xmm_regs);
1046 env->mxcsr = fpu.mxcsr;
1047
1048 kvm_get_sregs(env->kvm_cpu_state.vcpu_ctx, &sregs);
1049
1050 memcpy(env->interrupt_bitmap, sregs.interrupt_bitmap, sizeof(env->interrupt_bitmap));
1051
1052 get_seg(&env->segs[R_CS], &sregs.cs);
1053 get_seg(&env->segs[R_DS], &sregs.ds);
1054 get_seg(&env->segs[R_ES], &sregs.es);
1055 get_seg(&env->segs[R_FS], &sregs.fs);
1056 get_seg(&env->segs[R_GS], &sregs.gs);
1057 get_seg(&env->segs[R_SS], &sregs.ss);
1058
1059 get_seg(&env->tr, &sregs.tr);
1060 get_seg(&env->ldt, &sregs.ldt);
1061
1062 env->idt.limit = sregs.idt.limit;
1063 env->idt.base = sregs.idt.base;
1064 env->gdt.limit = sregs.gdt.limit;
1065 env->gdt.base = sregs.gdt.base;
1066
1067 env->cr[0] = sregs.cr0;
1068 env->cr[2] = sregs.cr2;
1069 env->cr[3] = sregs.cr3;
1070 env->cr[4] = sregs.cr4;
1071
1072 cpu_set_apic_base(env, sregs.apic_base);
1073
1074 env->efer = sregs.efer;
1075 //cpu_set_apic_tpr(env, sregs.cr8);
1076
1077 #define HFLAG_COPY_MASK ~( \
1078 HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
1079 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
1080 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
1081 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
1082
1083
1084
1085 hflags = (env->segs[R_CS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
1086 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
1087 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
1088 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
1089 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
1090 hflags |= (env->cr[4] & CR4_OSFXSR_MASK) <<
1091 (HF_OSFXSR_SHIFT - CR4_OSFXSR_SHIFT);
1092
1093 if (env->efer & MSR_EFER_LMA) {
1094 hflags |= HF_LMA_MASK;
1095 }
1096
1097 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
1098 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
1099 } else {
1100 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
1101 (DESC_B_SHIFT - HF_CS32_SHIFT);
1102 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
1103 (DESC_B_SHIFT - HF_SS32_SHIFT);
1104 if (!(env->cr[0] & CR0_PE_MASK) ||
1105 (env->eflags & VM_MASK) ||
1106 !(hflags & HF_CS32_MASK)) {
1107 hflags |= HF_ADDSEG_MASK;
1108 } else {
1109 hflags |= ((env->segs[R_DS].base |
1110 env->segs[R_ES].base |
1111 env->segs[R_SS].base) != 0) <<
1112 HF_ADDSEG_SHIFT;
1113 }
1114 }
1115 env->hflags = (env->hflags & HFLAG_COPY_MASK) | hflags;
1116
1117 /* msrs */
1118 n = 0;
1119 msrs[n++].index = MSR_IA32_SYSENTER_CS;
1120 msrs[n++].index = MSR_IA32_SYSENTER_ESP;
1121 msrs[n++].index = MSR_IA32_SYSENTER_EIP;
1122 if (kvm_has_msr_star)
1123 msrs[n++].index = MSR_STAR;
1124 msrs[n++].index = MSR_IA32_TSC;
1125 if (kvm_has_vm_hsave_pa)
1126 msrs[n++].index = MSR_VM_HSAVE_PA;
1127 #ifdef TARGET_X86_64
1128 if (lm_capable_kernel) {
1129 msrs[n++].index = MSR_CSTAR;
1130 msrs[n++].index = MSR_KERNELGSBASE;
1131 msrs[n++].index = MSR_FMASK;
1132 msrs[n++].index = MSR_LSTAR;
1133 }
1134 #endif
1135 rc = kvm_get_msrs(env->kvm_cpu_state.vcpu_ctx, msrs, n);
1136 if (rc == -1) {
1137 perror("kvm_get_msrs FAILED");
1138 }
1139 else {
1140 n = rc; /* actual number of MSRs */
1141 for (i=0 ; i<n; i++) {
1142 if (get_msr_entry(&msrs[i], env))
1143 return;
1144 }
1145 }
1146 }
1147
1148 static void do_cpuid_ent(struct kvm_cpuid_entry2 *e, uint32_t function,
1149 uint32_t count, CPUState *env)
1150 {
1151 env->regs[R_EAX] = function;
1152 env->regs[R_ECX] = count;
1153 qemu_kvm_cpuid_on_env(env);
1154 e->function = function;
1155 e->flags = 0;
1156 e->index = 0;
1157 e->eax = env->regs[R_EAX];
1158 e->ebx = env->regs[R_EBX];
1159 e->ecx = env->regs[R_ECX];
1160 e->edx = env->regs[R_EDX];
1161 }
1162
1163 struct kvm_para_features {
1164 int cap;
1165 int feature;
1166 } para_features[] = {
1167 #ifdef KVM_CAP_CLOCKSOURCE
1168 { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
1169 #endif
1170 #ifdef KVM_CAP_NOP_IO_DELAY
1171 { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
1172 #endif
1173 #ifdef KVM_CAP_PV_MMU
1174 { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
1175 #endif
1176 #ifdef KVM_CAP_CR3_CACHE
1177 { KVM_CAP_CR3_CACHE, KVM_FEATURE_CR3_CACHE },
1178 #endif
1179 { -1, -1 }
1180 };
1181
1182 static int get_para_features(kvm_context_t kvm_context)
1183 {
1184 int i, features = 0;
1185
1186 for (i = 0; i < ARRAY_SIZE(para_features)-1; i++) {
1187 if (kvm_check_extension(kvm_context, para_features[i].cap))
1188 features |= (1 << para_features[i].feature);
1189 }
1190
1191 return features;
1192 }
1193
1194 static void kvm_trim_features(uint32_t *features, uint32_t supported)
1195 {
1196 int i;
1197 uint32_t mask;
1198
1199 for (i = 0; i < 32; ++i) {
1200 mask = 1U << i;
1201 if ((*features & mask) && !(supported & mask)) {
1202 *features &= ~mask;
1203 }
1204 }
1205 }
1206
1207 int kvm_arch_qemu_init_env(CPUState *cenv)
1208 {
1209 struct kvm_cpuid_entry2 cpuid_ent[100];
1210 #ifdef KVM_CPUID_SIGNATURE
1211 struct kvm_cpuid_entry2 *pv_ent;
1212 uint32_t signature[3];
1213 #endif
1214 int cpuid_nent = 0;
1215 CPUState copy;
1216 uint32_t i, j, limit;
1217
1218 qemu_kvm_load_lapic(cenv);
1219
1220
1221 #ifdef KVM_CPUID_SIGNATURE
1222 /* Paravirtualization CPUIDs */
1223 memcpy(signature, "KVMKVMKVM\0\0\0", 12);
1224 pv_ent = &cpuid_ent[cpuid_nent++];
1225 memset(pv_ent, 0, sizeof(*pv_ent));
1226 pv_ent->function = KVM_CPUID_SIGNATURE;
1227 pv_ent->eax = 0;
1228 pv_ent->ebx = signature[0];
1229 pv_ent->ecx = signature[1];
1230 pv_ent->edx = signature[2];
1231
1232 pv_ent = &cpuid_ent[cpuid_nent++];
1233 memset(pv_ent, 0, sizeof(*pv_ent));
1234 pv_ent->function = KVM_CPUID_FEATURES;
1235 pv_ent->eax = get_para_features(kvm_context);
1236 #endif
1237
1238 kvm_trim_features(&cenv->cpuid_features,
1239 kvm_arch_get_supported_cpuid(cenv, 1, R_EDX));
1240
1241 /* prevent the hypervisor bit from being cleared by the kernel */
1242 i = cenv->cpuid_ext_features & CPUID_EXT_HYPERVISOR;
1243 kvm_trim_features(&cenv->cpuid_ext_features,
1244 kvm_arch_get_supported_cpuid(cenv, 1, R_ECX));
1245 cenv->cpuid_ext_features |= i;
1246
1247 kvm_trim_features(&cenv->cpuid_ext2_features,
1248 kvm_arch_get_supported_cpuid(cenv, 0x80000001, R_EDX));
1249 kvm_trim_features(&cenv->cpuid_ext3_features,
1250 kvm_arch_get_supported_cpuid(cenv, 0x80000001, R_ECX));
1251
1252 copy = *cenv;
1253
1254 copy.regs[R_EAX] = 0;
1255 qemu_kvm_cpuid_on_env(&copy);
1256 limit = copy.regs[R_EAX];
1257
1258 for (i = 0; i <= limit; ++i) {
1259 if (i == 4 || i == 0xb || i == 0xd) {
1260 for (j = 0; ; ++j) {
1261 do_cpuid_ent(&cpuid_ent[cpuid_nent], i, j, &copy);
1262
1263 cpuid_ent[cpuid_nent].flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1264 cpuid_ent[cpuid_nent].index = j;
1265
1266 cpuid_nent++;
1267
1268 if (i == 4 && copy.regs[R_EAX] == 0)
1269 break;
1270 if (i == 0xb && !(copy.regs[R_ECX] & 0xff00))
1271 break;
1272 if (i == 0xd && copy.regs[R_EAX] == 0)
1273 break;
1274 }
1275 } else
1276 do_cpuid_ent(&cpuid_ent[cpuid_nent++], i, 0, &copy);
1277 }
1278
1279 copy.regs[R_EAX] = 0x80000000;
1280 qemu_kvm_cpuid_on_env(&copy);
1281 limit = copy.regs[R_EAX];
1282
1283 for (i = 0x80000000; i <= limit; ++i)
1284 do_cpuid_ent(&cpuid_ent[cpuid_nent++], i, 0, &copy);
1285
1286 kvm_setup_cpuid2(cenv->kvm_cpu_state.vcpu_ctx, cpuid_nent, cpuid_ent);
1287
1288 return 0;
1289 }
1290
1291 int kvm_arch_halt(void *opaque, kvm_vcpu_context_t vcpu)
1292 {
1293 CPUState *env = cpu_single_env;
1294
1295 if (!((env->interrupt_request & CPU_INTERRUPT_HARD) &&
1296 (env->eflags & IF_MASK)) &&
1297 !(env->interrupt_request & CPU_INTERRUPT_NMI)) {
1298 env->halted = 1;
1299 }
1300 return 1;
1301 }
1302
1303 void kvm_arch_pre_kvm_run(void *opaque, CPUState *env)
1304 {
1305 if (!kvm_irqchip_in_kernel(kvm_context))
1306 kvm_set_cr8(env->kvm_cpu_state.vcpu_ctx, cpu_get_apic_tpr(env));
1307 }
1308
1309 void kvm_arch_post_kvm_run(void *opaque, CPUState *env)
1310 {
1311 cpu_single_env = env;
1312
1313 env->eflags = kvm_get_interrupt_flag(env->kvm_cpu_state.vcpu_ctx)
1314 ? env->eflags | IF_MASK : env->eflags & ~IF_MASK;
1315
1316 cpu_set_apic_tpr(env, kvm_get_cr8(env->kvm_cpu_state.vcpu_ctx));
1317 cpu_set_apic_base(env, kvm_get_apic_base(env->kvm_cpu_state.vcpu_ctx));
1318 }
1319
1320 int kvm_arch_has_work(CPUState *env)
1321 {
1322 if (((env->interrupt_request & CPU_INTERRUPT_HARD) &&
1323 (env->eflags & IF_MASK)) ||
1324 (env->interrupt_request & CPU_INTERRUPT_NMI))
1325 return 1;
1326 return 0;
1327 }
1328
1329 int kvm_arch_try_push_interrupts(void *opaque)
1330 {
1331 CPUState *env = cpu_single_env;
1332 int r, irq;
1333
1334 if (kvm_is_ready_for_interrupt_injection(env->kvm_cpu_state.vcpu_ctx) &&
1335 (env->interrupt_request & CPU_INTERRUPT_HARD) &&
1336 (env->eflags & IF_MASK)) {
1337 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
1338 irq = cpu_get_pic_interrupt(env);
1339 if (irq >= 0) {
1340 r = kvm_inject_irq(env->kvm_cpu_state.vcpu_ctx, irq);
1341 if (r < 0)
1342 printf("cpu %d fail inject %x\n", env->cpu_index, irq);
1343 }
1344 }
1345
1346 return (env->interrupt_request & CPU_INTERRUPT_HARD) != 0;
1347 }
1348
1349 #ifdef KVM_CAP_USER_NMI
1350 void kvm_arch_push_nmi(void *opaque)
1351 {
1352 CPUState *env = cpu_single_env;
1353 int r;
1354
1355 if (likely(!(env->interrupt_request & CPU_INTERRUPT_NMI)))
1356 return;
1357
1358 env->interrupt_request &= ~CPU_INTERRUPT_NMI;
1359 r = kvm_inject_nmi(env->kvm_cpu_state.vcpu_ctx);
1360 if (r < 0)
1361 printf("cpu %d fail inject NMI\n", env->cpu_index);
1362 }
1363 #endif /* KVM_CAP_USER_NMI */
1364
1365 void kvm_arch_update_regs_for_sipi(CPUState *env)
1366 {
1367 SegmentCache cs = env->segs[R_CS];
1368
1369 kvm_arch_save_regs(env);
1370 env->segs[R_CS] = cs;
1371 env->eip = 0;
1372 kvm_arch_load_regs(env);
1373 }
1374
1375 void kvm_arch_cpu_reset(CPUState *env)
1376 {
1377 kvm_arch_load_regs(env);
1378 if (!cpu_is_bsp(env)) {
1379 if (kvm_irqchip_in_kernel(kvm_context)) {
1380 #ifdef KVM_CAP_MP_STATE
1381 kvm_reset_mpstate(env->kvm_cpu_state.vcpu_ctx);
1382 #endif
1383 } else {
1384 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
1385 env->halted = 1;
1386 }
1387 }
1388 }
1389
1390 int kvm_arch_insert_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp)
1391 {
1392 uint8_t int3 = 0xcc;
1393
1394 if (cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
1395 cpu_memory_rw_debug(env, bp->pc, &int3, 1, 1))
1396 return -EINVAL;
1397 return 0;
1398 }
1399
1400 int kvm_arch_remove_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp)
1401 {
1402 uint8_t int3;
1403
1404 if (cpu_memory_rw_debug(env, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
1405 cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1))
1406 return -EINVAL;
1407 return 0;
1408 }
1409
1410 #ifdef KVM_CAP_SET_GUEST_DEBUG
1411 static struct {
1412 target_ulong addr;
1413 int len;
1414 int type;
1415 } hw_breakpoint[4];
1416
1417 static int nb_hw_breakpoint;
1418
1419 static int find_hw_breakpoint(target_ulong addr, int len, int type)
1420 {
1421 int n;
1422
1423 for (n = 0; n < nb_hw_breakpoint; n++)
1424 if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
1425 (hw_breakpoint[n].len == len || len == -1))
1426 return n;
1427 return -1;
1428 }
1429
1430 int kvm_arch_insert_hw_breakpoint(target_ulong addr,
1431 target_ulong len, int type)
1432 {
1433 switch (type) {
1434 case GDB_BREAKPOINT_HW:
1435 len = 1;
1436 break;
1437 case GDB_WATCHPOINT_WRITE:
1438 case GDB_WATCHPOINT_ACCESS:
1439 switch (len) {
1440 case 1:
1441 break;
1442 case 2:
1443 case 4:
1444 case 8:
1445 if (addr & (len - 1))
1446 return -EINVAL;
1447 break;
1448 default:
1449 return -EINVAL;
1450 }
1451 break;
1452 default:
1453 return -ENOSYS;
1454 }
1455
1456 if (nb_hw_breakpoint == 4)
1457 return -ENOBUFS;
1458
1459 if (find_hw_breakpoint(addr, len, type) >= 0)
1460 return -EEXIST;
1461
1462 hw_breakpoint[nb_hw_breakpoint].addr = addr;
1463 hw_breakpoint[nb_hw_breakpoint].len = len;
1464 hw_breakpoint[nb_hw_breakpoint].type = type;
1465 nb_hw_breakpoint++;
1466
1467 return 0;
1468 }
1469
1470 int kvm_arch_remove_hw_breakpoint(target_ulong addr,
1471 target_ulong len, int type)
1472 {
1473 int n;
1474
1475 n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
1476 if (n < 0)
1477 return -ENOENT;
1478
1479 nb_hw_breakpoint--;
1480 hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
1481
1482 return 0;
1483 }
1484
1485 void kvm_arch_remove_all_hw_breakpoints(void)
1486 {
1487 nb_hw_breakpoint = 0;
1488 }
1489
1490 static CPUWatchpoint hw_watchpoint;
1491
1492 int kvm_arch_debug(struct kvm_debug_exit_arch *arch_info)
1493 {
1494 int handle = 0;
1495 int n;
1496
1497 if (arch_info->exception == 1) {
1498 if (arch_info->dr6 & (1 << 14)) {
1499 if (cpu_single_env->singlestep_enabled)
1500 handle = 1;
1501 } else {
1502 for (n = 0; n < 4; n++)
1503 if (arch_info->dr6 & (1 << n))
1504 switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
1505 case 0x0:
1506 handle = 1;
1507 break;
1508 case 0x1:
1509 handle = 1;
1510 cpu_single_env->watchpoint_hit = &hw_watchpoint;
1511 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
1512 hw_watchpoint.flags = BP_MEM_WRITE;
1513 break;
1514 case 0x3:
1515 handle = 1;
1516 cpu_single_env->watchpoint_hit = &hw_watchpoint;
1517 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
1518 hw_watchpoint.flags = BP_MEM_ACCESS;
1519 break;
1520 }
1521 }
1522 } else if (kvm_find_sw_breakpoint(arch_info->pc))
1523 handle = 1;
1524
1525 if (!handle)
1526 kvm_update_guest_debug(cpu_single_env,
1527 (arch_info->exception == 1) ?
1528 KVM_GUESTDBG_INJECT_DB : KVM_GUESTDBG_INJECT_BP);
1529
1530 return handle;
1531 }
1532
1533 void kvm_arch_update_guest_debug(CPUState *env, struct kvm_guest_debug *dbg)
1534 {
1535 const uint8_t type_code[] = {
1536 [GDB_BREAKPOINT_HW] = 0x0,
1537 [GDB_WATCHPOINT_WRITE] = 0x1,
1538 [GDB_WATCHPOINT_ACCESS] = 0x3
1539 };
1540 const uint8_t len_code[] = {
1541 [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
1542 };
1543 int n;
1544
1545 if (!TAILQ_EMPTY(&kvm_sw_breakpoints))
1546 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
1547
1548 if (nb_hw_breakpoint > 0) {
1549 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
1550 dbg->arch.debugreg[7] = 0x0600;
1551 for (n = 0; n < nb_hw_breakpoint; n++) {
1552 dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
1553 dbg->arch.debugreg[7] |= (2 << (n * 2)) |
1554 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
1555 (len_code[hw_breakpoint[n].len] << (18 + n*4));
1556 }
1557 }
1558 }
1559 #endif
1560
1561 void kvm_arch_do_ioperm(void *_data)
1562 {
1563 struct ioperm_data *data = _data;
1564 ioperm(data->start_port, data->num, data->turn_on);
1565 }
1566
1567 /*
1568 * Setup x86 specific IRQ routing
1569 */
1570 int kvm_arch_init_irq_routing(void)
1571 {
1572 int i, r;
1573
1574 if (kvm_irqchip && kvm_has_gsi_routing(kvm_context)) {
1575 kvm_clear_gsi_routes(kvm_context);
1576 for (i = 0; i < 8; ++i) {
1577 if (i == 2)
1578 continue;
1579 r = kvm_add_irq_route(kvm_context, i, KVM_IRQCHIP_PIC_MASTER, i);
1580 if (r < 0)
1581 return r;
1582 }
1583 for (i = 8; i < 16; ++i) {
1584 r = kvm_add_irq_route(kvm_context, i, KVM_IRQCHIP_PIC_SLAVE, i - 8);
1585 if (r < 0)
1586 return r;
1587 }
1588 for (i = 0; i < 24; ++i) {
1589 if (i == 0) {
1590 r = kvm_add_irq_route(kvm_context, i, KVM_IRQCHIP_IOAPIC, 2);
1591 } else if (i != 2) {
1592 r = kvm_add_irq_route(kvm_context, i, KVM_IRQCHIP_IOAPIC, i);
1593 }
1594 if (r < 0)
1595 return r;
1596 }
1597 kvm_commit_irq_routes(kvm_context);
1598 }
1599 return 0;
1600 }
1601
1602 uint32_t kvm_arch_get_supported_cpuid(CPUState *env, uint32_t function,
1603 int reg)
1604 {
1605 return kvm_get_supported_cpuid(kvm_context, function, reg);
1606 }
1607
1608 void kvm_arch_process_irqchip_events(CPUState *env)
1609 {
1610 kvm_arch_save_regs(env);
1611 if (env->interrupt_request & CPU_INTERRUPT_INIT)
1612 do_cpu_init(env);
1613 if (env->interrupt_request & CPU_INTERRUPT_SIPI)
1614 do_cpu_sipi(env);
1615 kvm_arch_load_regs(env);
1616 }
Patches shipped by Fedora