2 * MIPS emulation micro-operations for qemu.
4 * Copyright (c) 2004-2005 Jocelyn Mayer
5 * Copyright (c) 2006 Marius Groeger (FPU operations)
6 * Copyright (c) 2007 Thiemo Seufer (64-bit FPU support)
8 * This library is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU Lesser General Public
10 * License as published by the Free Software Foundation; either
11 * version 2 of the License, or (at your option) any later version.
13 * This library is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * Lesser General Public License for more details.
18 * You should have received a copy of the GNU Lesser General Public
19 * License along with this library; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 #include "host-utils.h"
28 #define CALL_FROM_TB0(func) func()
31 #define CALL_FROM_TB1(func, arg0) func(arg0)
33 #ifndef CALL_FROM_TB1_CONST16
34 #define CALL_FROM_TB1_CONST16(func, arg0) CALL_FROM_TB1(func, arg0)
37 #define CALL_FROM_TB2(func, arg0, arg1) func(arg0, arg1)
39 #ifndef CALL_FROM_TB2_CONST16
40 #define CALL_FROM_TB2_CONST16(func, arg0, arg1) \
41 CALL_FROM_TB2(func, arg0, arg1)
44 #define CALL_FROM_TB3(func, arg0, arg1, arg2) func(arg0, arg1, arg2)
47 #define CALL_FROM_TB4(func, arg0, arg1, arg2, arg3) \
48 func(arg0, arg1, arg2, arg3)
52 #include "op_template.c"
55 #include "op_template.c"
58 #include "op_template.c"
61 #include "op_template.c"
64 #include "op_template.c"
67 #include "op_template.c"
70 #include "op_template.c"
73 #include "op_template.c"
76 #include "op_template.c"
79 #include "op_template.c"
82 #include "op_template.c"
85 #include "op_template.c"
88 #include "op_template.c"
91 #include "op_template.c"
94 #include "op_template.c"
97 #include "op_template.c"
100 #include "op_template.c"
103 #include "op_template.c"
106 #include "op_template.c"
109 #include "op_template.c"
112 #include "op_template.c"
115 #include "op_template.c"
118 #include "op_template.c"
121 #include "op_template.c"
124 #include "op_template.c"
127 #include "op_template.c"
130 #include "op_template.c"
133 #include "op_template.c"
136 #include "op_template.c"
139 #include "op_template.c"
142 #include "op_template.c"
146 #include "op_template.c"
150 #include "fop_template.c"
153 #include "fop_template.c"
156 #include "fop_template.c"
159 #include "fop_template.c"
162 #include "fop_template.c"
165 #include "fop_template.c"
168 #include "fop_template.c"
171 #include "fop_template.c"
174 #include "fop_template.c"
177 #include "fop_template.c"
180 #include "fop_template.c"
183 #include "fop_template.c"
186 #include "fop_template.c"
189 #include "fop_template.c"
192 #include "fop_template.c"
195 #include "fop_template.c"
198 #include "fop_template.c"
201 #include "fop_template.c"
204 #include "fop_template.c"
207 #include "fop_template.c"
210 #include "fop_template.c"
213 #include "fop_template.c"
216 #include "fop_template.c"
219 #include "fop_template.c"
222 #include "fop_template.c"
225 #include "fop_template.c"
228 #include "fop_template.c"
231 #include "fop_template.c"
234 #include "fop_template.c"
237 #include "fop_template.c"
240 #include "fop_template.c"
243 #include "fop_template.c"
247 #include "fop_template.c"
250 void op_dup_T0 (void)
256 void op_load_HI (void)
258 T0
= env
->HI
[env
->current_tc
][PARAM1
];
262 void op_store_HI (void)
264 env
->HI
[env
->current_tc
][PARAM1
] = T0
;
268 void op_load_LO (void)
270 T0
= env
->LO
[env
->current_tc
][PARAM1
];
274 void op_store_LO (void)
276 env
->LO
[env
->current_tc
][PARAM1
] = T0
;
281 #define MEMSUFFIX _raw
284 #if !defined(CONFIG_USER_ONLY)
285 #define MEMSUFFIX _user
289 #define MEMSUFFIX _super
293 #define MEMSUFFIX _kernel
298 /* Addresses computation */
299 void op_addr_add (void)
301 /* For compatibility with 32-bit code, data reference in user mode
302 with Status_UX = 0 should be casted to 32-bit and sign extended.
303 See the MIPS64 PRA manual, section 4.10. */
304 #if defined(TARGET_MIPS64)
305 if (((env
->hflags
& MIPS_HFLAG_KSU
) == MIPS_HFLAG_UM
) &&
306 !(env
->CP0_Status
& (1 << CP0St_UX
)))
307 T0
= (int64_t)(int32_t)(T0
+ T1
);
317 T0
= (int32_t)((int32_t)T0
+ (int32_t)T1
);
326 T0
= (int32_t)T0
+ (int32_t)T1
;
327 if (((tmp
^ T1
^ (-1)) & (T0
^ T1
)) >> 31) {
328 /* operands of same sign, result different sign */
329 CALL_FROM_TB1(do_raise_exception
, EXCP_OVERFLOW
);
337 T0
= (int32_t)((int32_t)T0
- (int32_t)T1
);
346 T0
= (int32_t)T0
- (int32_t)T1
;
347 if (((tmp
^ T1
) & (tmp
^ T0
)) >> 31) {
348 /* operands of different sign, first operand and result different sign */
349 CALL_FROM_TB1(do_raise_exception
, EXCP_OVERFLOW
);
357 T0
= (int32_t)((int32_t)T0
* (int32_t)T1
);
361 #if HOST_LONG_BITS < 64
364 CALL_FROM_TB0(do_div
);
371 env
->LO
[env
->current_tc
][0] = (int32_t)((int64_t)(int32_t)T0
/ (int32_t)T1
);
372 env
->HI
[env
->current_tc
][0] = (int32_t)((int64_t)(int32_t)T0
% (int32_t)T1
);
381 env
->LO
[env
->current_tc
][0] = (int32_t)((uint32_t)T0
/ (uint32_t)T1
);
382 env
->HI
[env
->current_tc
][0] = (int32_t)((uint32_t)T0
% (uint32_t)T1
);
387 #if defined(TARGET_MIPS64)
401 if (((tmp
^ T1
^ (-1)) & (T0
^ T1
)) >> 63) {
402 /* operands of same sign, result different sign */
403 CALL_FROM_TB1(do_raise_exception
, EXCP_OVERFLOW
);
419 T0
= (int64_t)T0
- (int64_t)T1
;
420 if (((tmp
^ T1
) & (tmp
^ T0
)) >> 63) {
421 /* operands of different sign, first operand and result different sign */
422 CALL_FROM_TB1(do_raise_exception
, EXCP_OVERFLOW
);
429 T0
= (int64_t)T0
* (int64_t)T1
;
433 /* Those might call libgcc functions. */
440 #if TARGET_LONG_BITS > HOST_LONG_BITS
450 env
->LO
[env
->current_tc
][0] = T0
/ T1
;
451 env
->HI
[env
->current_tc
][0] = T0
% T1
;
456 #endif /* TARGET_MIPS64 */
485 T0
= (int32_t)((uint32_t)T0
<< T1
);
491 T0
= (int32_t)((int32_t)T0
>> T1
);
497 T0
= (int32_t)((uint32_t)T0
>> T1
);
506 tmp
= (int32_t)((uint32_t)T0
<< (0x20 - T1
));
507 T0
= (int32_t)((uint32_t)T0
>> T1
) | tmp
;
514 T0
= (int32_t)((uint32_t)T1
<< ((uint32_t)T0
& 0x1F));
520 T0
= (int32_t)((int32_t)T1
>> (T0
& 0x1F));
526 T0
= (int32_t)((uint32_t)T1
>> (T0
& 0x1F));
536 tmp
= (int32_t)((uint32_t)T1
<< (0x20 - T0
));
537 T0
= (int32_t)((uint32_t)T1
>> T0
) | tmp
;
555 #if defined(TARGET_MIPS64)
557 #if TARGET_LONG_BITS > HOST_LONG_BITS
558 /* Those might call libgcc functions. */
561 CALL_FROM_TB0(do_dsll
);
565 void op_dsll32 (void)
567 CALL_FROM_TB0(do_dsll32
);
573 CALL_FROM_TB0(do_dsra
);
577 void op_dsra32 (void)
579 CALL_FROM_TB0(do_dsra32
);
585 CALL_FROM_TB0(do_dsrl
);
589 void op_dsrl32 (void)
591 CALL_FROM_TB0(do_dsrl32
);
597 CALL_FROM_TB0(do_drotr
);
601 void op_drotr32 (void)
603 CALL_FROM_TB0(do_drotr32
);
609 CALL_FROM_TB0(do_dsllv
);
615 CALL_FROM_TB0(do_dsrav
);
621 CALL_FROM_TB0(do_dsrlv
);
625 void op_drotrv (void)
627 CALL_FROM_TB0(do_drotrv
);
633 CALL_FROM_TB0(do_dclo
);
639 CALL_FROM_TB0(do_dclz
);
643 #else /* TARGET_LONG_BITS > HOST_LONG_BITS */
651 void op_dsll32 (void)
653 T0
= T0
<< (T1
+ 32);
659 T0
= (int64_t)T0
>> T1
;
663 void op_dsra32 (void)
665 T0
= (int64_t)T0
>> (T1
+ 32);
675 void op_dsrl32 (void)
677 T0
= T0
>> (T1
+ 32);
686 tmp
= T0
<< (0x40 - T1
);
687 T0
= (T0
>> T1
) | tmp
;
692 void op_drotr32 (void)
696 tmp
= T0
<< (0x40 - (32 + T1
));
697 T0
= (T0
>> (32 + T1
)) | tmp
;
703 T0
= T1
<< (T0
& 0x3F);
709 T0
= (int64_t)T1
>> (T0
& 0x3F);
715 T0
= T1
>> (T0
& 0x3F);
719 void op_drotrv (void)
725 tmp
= T1
<< (0x40 - T0
);
726 T0
= (T1
>> T0
) | tmp
;
743 #endif /* TARGET_LONG_BITS > HOST_LONG_BITS */
744 #endif /* TARGET_MIPS64 */
746 /* 64 bits arithmetic */
747 #if TARGET_LONG_BITS > HOST_LONG_BITS
750 CALL_FROM_TB0(do_mult
);
756 CALL_FROM_TB0(do_multu
);
762 CALL_FROM_TB0(do_madd
);
768 CALL_FROM_TB0(do_maddu
);
774 CALL_FROM_TB0(do_msub
);
780 CALL_FROM_TB0(do_msubu
);
784 /* Multiplication variants of the vr54xx. */
787 CALL_FROM_TB0(do_muls
);
793 CALL_FROM_TB0(do_mulsu
);
799 CALL_FROM_TB0(do_macc
);
803 void op_macchi (void)
805 CALL_FROM_TB0(do_macchi
);
811 CALL_FROM_TB0(do_maccu
);
814 void op_macchiu (void)
816 CALL_FROM_TB0(do_macchiu
);
822 CALL_FROM_TB0(do_msac
);
826 void op_msachi (void)
828 CALL_FROM_TB0(do_msachi
);
834 CALL_FROM_TB0(do_msacu
);
838 void op_msachiu (void)
840 CALL_FROM_TB0(do_msachiu
);
846 CALL_FROM_TB0(do_mulhi
);
850 void op_mulhiu (void)
852 CALL_FROM_TB0(do_mulhiu
);
856 void op_mulshi (void)
858 CALL_FROM_TB0(do_mulshi
);
862 void op_mulshiu (void)
864 CALL_FROM_TB0(do_mulshiu
);
868 #else /* TARGET_LONG_BITS > HOST_LONG_BITS */
870 static always_inline
uint64_t get_HILO (void)
872 return ((uint64_t)env
->HI
[env
->current_tc
][0] << 32) |
873 ((uint64_t)(uint32_t)env
->LO
[env
->current_tc
][0]);
876 static always_inline
void set_HILO (uint64_t HILO
)
878 env
->LO
[env
->current_tc
][0] = (int32_t)(HILO
& 0xFFFFFFFF);
879 env
->HI
[env
->current_tc
][0] = (int32_t)(HILO
>> 32);
882 static always_inline
void set_HIT0_LO (uint64_t HILO
)
884 env
->LO
[env
->current_tc
][0] = (int32_t)(HILO
& 0xFFFFFFFF);
885 T0
= env
->HI
[env
->current_tc
][0] = (int32_t)(HILO
>> 32);
888 static always_inline
void set_HI_LOT0 (uint64_t HILO
)
890 T0
= env
->LO
[env
->current_tc
][0] = (int32_t)(HILO
& 0xFFFFFFFF);
891 env
->HI
[env
->current_tc
][0] = (int32_t)(HILO
>> 32);
896 set_HILO((int64_t)(int32_t)T0
* (int64_t)(int32_t)T1
);
902 set_HILO((uint64_t)(uint32_t)T0
* (uint64_t)(uint32_t)T1
);
910 tmp
= ((int64_t)(int32_t)T0
* (int64_t)(int32_t)T1
);
911 set_HILO((int64_t)get_HILO() + tmp
);
919 tmp
= ((uint64_t)(uint32_t)T0
* (uint64_t)(uint32_t)T1
);
920 set_HILO(get_HILO() + tmp
);
928 tmp
= ((int64_t)(int32_t)T0
* (int64_t)(int32_t)T1
);
929 set_HILO((int64_t)get_HILO() - tmp
);
937 tmp
= ((uint64_t)(uint32_t)T0
* (uint64_t)(uint32_t)T1
);
938 set_HILO(get_HILO() - tmp
);
942 /* Multiplication variants of the vr54xx. */
945 set_HI_LOT0(0 - ((int64_t)(int32_t)T0
* (int64_t)(int32_t)T1
));
951 set_HI_LOT0(0 - ((uint64_t)(uint32_t)T0
* (uint64_t)(uint32_t)T1
));
957 set_HI_LOT0(get_HILO() + ((int64_t)(int32_t)T0
* (int64_t)(int32_t)T1
));
961 void op_macchi (void)
963 set_HIT0_LO(get_HILO() + ((int64_t)(int32_t)T0
* (int64_t)(int32_t)T1
));
969 set_HI_LOT0(get_HILO() + ((uint64_t)(uint32_t)T0
* (uint64_t)(uint32_t)T1
));
973 void op_macchiu (void)
975 set_HIT0_LO(get_HILO() + ((uint64_t)(uint32_t)T0
* (uint64_t)(uint32_t)T1
));
981 set_HI_LOT0(get_HILO() - ((int64_t)(int32_t)T0
* (int64_t)(int32_t)T1
));
985 void op_msachi (void)
987 set_HIT0_LO(get_HILO() - ((int64_t)(int32_t)T0
* (int64_t)(int32_t)T1
));
993 set_HI_LOT0(get_HILO() - ((uint64_t)(uint32_t)T0
* (uint64_t)(uint32_t)T1
));
997 void op_msachiu (void)
999 set_HIT0_LO(get_HILO() - ((uint64_t)(uint32_t)T0
* (uint64_t)(uint32_t)T1
));
1003 void op_mulhi (void)
1005 set_HIT0_LO((int64_t)(int32_t)T0
* (int64_t)(int32_t)T1
);
1009 void op_mulhiu (void)
1011 set_HIT0_LO((uint64_t)(uint32_t)T0
* (uint64_t)(uint32_t)T1
);
1015 void op_mulshi (void)
1017 set_HIT0_LO(0 - ((int64_t)(int32_t)T0
* (int64_t)(int32_t)T1
));
1021 void op_mulshiu (void)
1023 set_HIT0_LO(0 - ((uint64_t)(uint32_t)T0
* (uint64_t)(uint32_t)T1
));
1027 #endif /* TARGET_LONG_BITS > HOST_LONG_BITS */
1029 #if defined(TARGET_MIPS64)
1030 void op_dmult (void)
1032 CALL_FROM_TB4(muls64
, &(env
->LO
[env
->current_tc
][0]), &(env
->HI
[env
->current_tc
][0]), T0
, T1
);
1036 void op_dmultu (void)
1038 CALL_FROM_TB4(mulu64
, &(env
->LO
[env
->current_tc
][0]), &(env
->HI
[env
->current_tc
][0]), T0
, T1
);
1043 /* Conditional moves */
1047 env
->gpr
[env
->current_tc
][PARAM1
] = T0
;
1054 env
->gpr
[env
->current_tc
][PARAM1
] = T0
;
1060 if (!(env
->fpu
->fcr31
& PARAM1
))
1067 if (env
->fpu
->fcr31
& PARAM1
)
1073 #define OP_COND(name, cond) \
1074 void glue(op_, name) (void) \
1084 OP_COND(eq
, T0
== T1
);
1085 OP_COND(ne
, T0
!= T1
);
1086 OP_COND(ge
, (target_long
)T0
>= (target_long
)T1
);
1087 OP_COND(geu
, T0
>= T1
);
1088 OP_COND(lt
, (target_long
)T0
< (target_long
)T1
);
1089 OP_COND(ltu
, T0
< T1
);
1090 OP_COND(gez
, (target_long
)T0
>= 0);
1091 OP_COND(gtz
, (target_long
)T0
> 0);
1092 OP_COND(lez
, (target_long
)T0
<= 0);
1093 OP_COND(ltz
, (target_long
)T0
< 0);
1096 /* Branch to register */
1097 void op_save_breg_target (void)
1103 void op_restore_breg_target (void)
1111 env
->PC
[env
->current_tc
] = T2
;
1115 void op_save_btarget (void)
1117 env
->btarget
= PARAM1
;
1121 #if defined(TARGET_MIPS64)
1122 void op_save_btarget64 (void)
1124 env
->btarget
= ((uint64_t)PARAM1
<< 32) | (uint32_t)PARAM2
;
1129 /* Conditional branch */
1130 void op_set_bcond (void)
1136 void op_save_bcond (void)
1142 void op_restore_bcond (void)
1148 void op_jnz_T2 (void)
1151 GOTO_LABEL_PARAM(1);
1156 void op_mfc0_index (void)
1158 T0
= env
->CP0_Index
;
1162 void op_mfc0_mvpcontrol (void)
1164 T0
= env
->mvp
->CP0_MVPControl
;
1168 void op_mfc0_mvpconf0 (void)
1170 T0
= env
->mvp
->CP0_MVPConf0
;
1174 void op_mfc0_mvpconf1 (void)
1176 T0
= env
->mvp
->CP0_MVPConf1
;
1180 void op_mfc0_random (void)
1182 CALL_FROM_TB0(do_mfc0_random
);
1186 void op_mfc0_vpecontrol (void)
1188 T0
= env
->CP0_VPEControl
;
1192 void op_mfc0_vpeconf0 (void)
1194 T0
= env
->CP0_VPEConf0
;
1198 void op_mfc0_vpeconf1 (void)
1200 T0
= env
->CP0_VPEConf1
;
1204 void op_mfc0_yqmask (void)
1206 T0
= env
->CP0_YQMask
;
1210 void op_mfc0_vpeschedule (void)
1212 T0
= env
->CP0_VPESchedule
;
1216 void op_mfc0_vpeschefback (void)
1218 T0
= env
->CP0_VPEScheFBack
;
1222 void op_mfc0_vpeopt (void)
1224 T0
= env
->CP0_VPEOpt
;
1228 void op_mfc0_entrylo0 (void)
1230 T0
= (int32_t)env
->CP0_EntryLo0
;
1234 void op_mfc0_tcstatus (void)
1236 T0
= env
->CP0_TCStatus
[env
->current_tc
];
1240 void op_mftc0_tcstatus(void)
1242 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1244 T0
= env
->CP0_TCStatus
[other_tc
];
1248 void op_mfc0_tcbind (void)
1250 T0
= env
->CP0_TCBind
[env
->current_tc
];
1254 void op_mftc0_tcbind(void)
1256 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1258 T0
= env
->CP0_TCBind
[other_tc
];
1262 void op_mfc0_tcrestart (void)
1264 T0
= env
->PC
[env
->current_tc
];
1268 void op_mftc0_tcrestart(void)
1270 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1272 T0
= env
->PC
[other_tc
];
1276 void op_mfc0_tchalt (void)
1278 T0
= env
->CP0_TCHalt
[env
->current_tc
];
1282 void op_mftc0_tchalt(void)
1284 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1286 T0
= env
->CP0_TCHalt
[other_tc
];
1290 void op_mfc0_tccontext (void)
1292 T0
= env
->CP0_TCContext
[env
->current_tc
];
1296 void op_mftc0_tccontext(void)
1298 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1300 T0
= env
->CP0_TCContext
[other_tc
];
1304 void op_mfc0_tcschedule (void)
1306 T0
= env
->CP0_TCSchedule
[env
->current_tc
];
1310 void op_mftc0_tcschedule(void)
1312 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1314 T0
= env
->CP0_TCSchedule
[other_tc
];
1318 void op_mfc0_tcschefback (void)
1320 T0
= env
->CP0_TCScheFBack
[env
->current_tc
];
1324 void op_mftc0_tcschefback(void)
1326 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1328 T0
= env
->CP0_TCScheFBack
[other_tc
];
1332 void op_mfc0_entrylo1 (void)
1334 T0
= (int32_t)env
->CP0_EntryLo1
;
1338 void op_mfc0_context (void)
1340 T0
= (int32_t)env
->CP0_Context
;
1344 void op_mfc0_pagemask (void)
1346 T0
= env
->CP0_PageMask
;
1350 void op_mfc0_pagegrain (void)
1352 T0
= env
->CP0_PageGrain
;
1356 void op_mfc0_wired (void)
1358 T0
= env
->CP0_Wired
;
1362 void op_mfc0_srsconf0 (void)
1364 T0
= env
->CP0_SRSConf0
;
1368 void op_mfc0_srsconf1 (void)
1370 T0
= env
->CP0_SRSConf1
;
1374 void op_mfc0_srsconf2 (void)
1376 T0
= env
->CP0_SRSConf2
;
1380 void op_mfc0_srsconf3 (void)
1382 T0
= env
->CP0_SRSConf3
;
1386 void op_mfc0_srsconf4 (void)
1388 T0
= env
->CP0_SRSConf4
;
1392 void op_mfc0_hwrena (void)
1394 T0
= env
->CP0_HWREna
;
1398 void op_mfc0_badvaddr (void)
1400 T0
= (int32_t)env
->CP0_BadVAddr
;
1404 void op_mfc0_count (void)
1406 CALL_FROM_TB0(do_mfc0_count
);
1410 void op_mfc0_entryhi (void)
1412 T0
= (int32_t)env
->CP0_EntryHi
;
1416 void op_mftc0_entryhi(void)
1418 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1420 T0
= (env
->CP0_EntryHi
& ~0xff) | (env
->CP0_TCStatus
[other_tc
] & 0xff);
1424 void op_mfc0_compare (void)
1426 T0
= env
->CP0_Compare
;
1430 void op_mfc0_status (void)
1432 T0
= env
->CP0_Status
;
1436 void op_mftc0_status(void)
1438 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1439 uint32_t tcstatus
= env
->CP0_TCStatus
[other_tc
];
1441 T0
= env
->CP0_Status
& ~0xf1000018;
1442 T0
|= tcstatus
& (0xf << CP0TCSt_TCU0
);
1443 T0
|= (tcstatus
& (1 << CP0TCSt_TMX
)) >> (CP0TCSt_TMX
- CP0St_MX
);
1444 T0
|= (tcstatus
& (0x3 << CP0TCSt_TKSU
)) >> (CP0TCSt_TKSU
- CP0St_KSU
);
1448 void op_mfc0_intctl (void)
1450 T0
= env
->CP0_IntCtl
;
1454 void op_mfc0_srsctl (void)
1456 T0
= env
->CP0_SRSCtl
;
1460 void op_mfc0_srsmap (void)
1462 T0
= env
->CP0_SRSMap
;
1466 void op_mfc0_cause (void)
1468 T0
= env
->CP0_Cause
;
1472 void op_mfc0_epc (void)
1474 T0
= (int32_t)env
->CP0_EPC
;
1478 void op_mfc0_prid (void)
1484 void op_mfc0_ebase (void)
1486 T0
= env
->CP0_EBase
;
1490 void op_mfc0_config0 (void)
1492 T0
= env
->CP0_Config0
;
1496 void op_mfc0_config1 (void)
1498 T0
= env
->CP0_Config1
;
1502 void op_mfc0_config2 (void)
1504 T0
= env
->CP0_Config2
;
1508 void op_mfc0_config3 (void)
1510 T0
= env
->CP0_Config3
;
1514 void op_mfc0_config6 (void)
1516 T0
= env
->CP0_Config6
;
1520 void op_mfc0_config7 (void)
1522 T0
= env
->CP0_Config7
;
1526 void op_mfc0_lladdr (void)
1528 T0
= (int32_t)env
->CP0_LLAddr
>> 4;
1532 void op_mfc0_watchlo (void)
1534 T0
= (int32_t)env
->CP0_WatchLo
[PARAM1
];
1538 void op_mfc0_watchhi (void)
1540 T0
= env
->CP0_WatchHi
[PARAM1
];
1544 void op_mfc0_xcontext (void)
1546 T0
= (int32_t)env
->CP0_XContext
;
1550 void op_mfc0_framemask (void)
1552 T0
= env
->CP0_Framemask
;
1556 void op_mfc0_debug (void)
1558 T0
= env
->CP0_Debug
;
1559 if (env
->hflags
& MIPS_HFLAG_DM
)
1560 T0
|= 1 << CP0DB_DM
;
1564 void op_mftc0_debug(void)
1566 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1568 /* XXX: Might be wrong, check with EJTAG spec. */
1569 T0
= (env
->CP0_Debug
& ~((1 << CP0DB_SSt
) | (1 << CP0DB_Halt
))) |
1570 (env
->CP0_Debug_tcstatus
[other_tc
] &
1571 ((1 << CP0DB_SSt
) | (1 << CP0DB_Halt
)));
1575 void op_mfc0_depc (void)
1577 T0
= (int32_t)env
->CP0_DEPC
;
1581 void op_mfc0_performance0 (void)
1583 T0
= env
->CP0_Performance0
;
1587 void op_mfc0_taglo (void)
1589 T0
= env
->CP0_TagLo
;
1593 void op_mfc0_datalo (void)
1595 T0
= env
->CP0_DataLo
;
1599 void op_mfc0_taghi (void)
1601 T0
= env
->CP0_TagHi
;
1605 void op_mfc0_datahi (void)
1607 T0
= env
->CP0_DataHi
;
1611 void op_mfc0_errorepc (void)
1613 T0
= (int32_t)env
->CP0_ErrorEPC
;
1617 void op_mfc0_desave (void)
1619 T0
= env
->CP0_DESAVE
;
1623 void op_mtc0_index (void)
1626 unsigned int tmp
= env
->tlb
->nb_tlb
;
1632 env
->CP0_Index
= (env
->CP0_Index
& 0x80000000) | (T0
& (num
- 1));
1636 void op_mtc0_mvpcontrol (void)
1641 if (env
->CP0_VPEConf0
& (1 << CP0VPEC0_MVP
))
1642 mask
|= (1 << CP0MVPCo_CPA
) | (1 << CP0MVPCo_VPC
) |
1643 (1 << CP0MVPCo_EVP
);
1644 if (env
->mvp
->CP0_MVPControl
& (1 << CP0MVPCo_VPC
))
1645 mask
|= (1 << CP0MVPCo_STLB
);
1646 newval
= (env
->mvp
->CP0_MVPControl
& ~mask
) | (T0
& mask
);
1648 // TODO: Enable/disable shared TLB, enable/disable VPEs.
1650 env
->mvp
->CP0_MVPControl
= newval
;
1654 void op_mtc0_vpecontrol (void)
1659 mask
= (1 << CP0VPECo_YSI
) | (1 << CP0VPECo_GSI
) |
1660 (1 << CP0VPECo_TE
) | (0xff << CP0VPECo_TargTC
);
1661 newval
= (env
->CP0_VPEControl
& ~mask
) | (T0
& mask
);
1663 /* Yield scheduler intercept not implemented. */
1664 /* Gating storage scheduler intercept not implemented. */
1666 // TODO: Enable/disable TCs.
1668 env
->CP0_VPEControl
= newval
;
1672 void op_mtc0_vpeconf0 (void)
1677 if (env
->CP0_VPEConf0
& (1 << CP0VPEC0_MVP
)) {
1678 if (env
->CP0_VPEConf0
& (1 << CP0VPEC0_VPA
))
1679 mask
|= (0xff << CP0VPEC0_XTC
);
1680 mask
|= (1 << CP0VPEC0_MVP
) | (1 << CP0VPEC0_VPA
);
1682 newval
= (env
->CP0_VPEConf0
& ~mask
) | (T0
& mask
);
1684 // TODO: TC exclusive handling due to ERL/EXL.
1686 env
->CP0_VPEConf0
= newval
;
1690 void op_mtc0_vpeconf1 (void)
1695 if (env
->mvp
->CP0_MVPControl
& (1 << CP0MVPCo_VPC
))
1696 mask
|= (0xff << CP0VPEC1_NCX
) | (0xff << CP0VPEC1_NCP2
) |
1697 (0xff << CP0VPEC1_NCP1
);
1698 newval
= (env
->CP0_VPEConf1
& ~mask
) | (T0
& mask
);
1700 /* UDI not implemented. */
1701 /* CP2 not implemented. */
1703 // TODO: Handle FPU (CP1) binding.
1705 env
->CP0_VPEConf1
= newval
;
1709 void op_mtc0_yqmask (void)
1711 /* Yield qualifier inputs not implemented. */
1712 env
->CP0_YQMask
= 0x00000000;
1716 void op_mtc0_vpeschedule (void)
1718 env
->CP0_VPESchedule
= T0
;
1722 void op_mtc0_vpeschefback (void)
1724 env
->CP0_VPEScheFBack
= T0
;
1728 void op_mtc0_vpeopt (void)
1730 env
->CP0_VPEOpt
= T0
& 0x0000ffff;
1734 void op_mtc0_entrylo0 (void)
1736 /* Large physaddr (PABITS) not implemented */
1737 /* 1k pages not implemented */
1738 env
->CP0_EntryLo0
= T0
& 0x3FFFFFFF;
1742 void op_mtc0_tcstatus (void)
1744 uint32_t mask
= env
->CP0_TCStatus_rw_bitmask
;
1747 newval
= (env
->CP0_TCStatus
[env
->current_tc
] & ~mask
) | (T0
& mask
);
1749 // TODO: Sync with CP0_Status.
1751 env
->CP0_TCStatus
[env
->current_tc
] = newval
;
1755 void op_mttc0_tcstatus (void)
1757 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1759 // TODO: Sync with CP0_Status.
1761 env
->CP0_TCStatus
[other_tc
] = T0
;
1765 void op_mtc0_tcbind (void)
1767 uint32_t mask
= (1 << CP0TCBd_TBE
);
1770 if (env
->mvp
->CP0_MVPControl
& (1 << CP0MVPCo_VPC
))
1771 mask
|= (1 << CP0TCBd_CurVPE
);
1772 newval
= (env
->CP0_TCBind
[env
->current_tc
] & ~mask
) | (T0
& mask
);
1773 env
->CP0_TCBind
[env
->current_tc
] = newval
;
1777 void op_mttc0_tcbind (void)
1779 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1780 uint32_t mask
= (1 << CP0TCBd_TBE
);
1783 if (env
->mvp
->CP0_MVPControl
& (1 << CP0MVPCo_VPC
))
1784 mask
|= (1 << CP0TCBd_CurVPE
);
1785 newval
= (env
->CP0_TCBind
[other_tc
] & ~mask
) | (T0
& mask
);
1786 env
->CP0_TCBind
[other_tc
] = newval
;
1790 void op_mtc0_tcrestart (void)
1792 env
->PC
[env
->current_tc
] = T0
;
1793 env
->CP0_TCStatus
[env
->current_tc
] &= ~(1 << CP0TCSt_TDS
);
1794 env
->CP0_LLAddr
= 0ULL;
1795 /* MIPS16 not implemented. */
1799 void op_mttc0_tcrestart (void)
1801 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1803 env
->PC
[other_tc
] = T0
;
1804 env
->CP0_TCStatus
[other_tc
] &= ~(1 << CP0TCSt_TDS
);
1805 env
->CP0_LLAddr
= 0ULL;
1806 /* MIPS16 not implemented. */
1810 void op_mtc0_tchalt (void)
1812 env
->CP0_TCHalt
[env
->current_tc
] = T0
& 0x1;
1814 // TODO: Halt TC / Restart (if allocated+active) TC.
1819 void op_mttc0_tchalt (void)
1821 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1823 // TODO: Halt TC / Restart (if allocated+active) TC.
1825 env
->CP0_TCHalt
[other_tc
] = T0
;
1829 void op_mtc0_tccontext (void)
1831 env
->CP0_TCContext
[env
->current_tc
] = T0
;
1835 void op_mttc0_tccontext (void)
1837 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1839 env
->CP0_TCContext
[other_tc
] = T0
;
1843 void op_mtc0_tcschedule (void)
1845 env
->CP0_TCSchedule
[env
->current_tc
] = T0
;
1849 void op_mttc0_tcschedule (void)
1851 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1853 env
->CP0_TCSchedule
[other_tc
] = T0
;
1857 void op_mtc0_tcschefback (void)
1859 env
->CP0_TCScheFBack
[env
->current_tc
] = T0
;
1863 void op_mttc0_tcschefback (void)
1865 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1867 env
->CP0_TCScheFBack
[other_tc
] = T0
;
1871 void op_mtc0_entrylo1 (void)
1873 /* Large physaddr (PABITS) not implemented */
1874 /* 1k pages not implemented */
1875 env
->CP0_EntryLo1
= T0
& 0x3FFFFFFF;
1879 void op_mtc0_context (void)
1881 env
->CP0_Context
= (env
->CP0_Context
& 0x007FFFFF) | (T0
& ~0x007FFFFF);
1885 void op_mtc0_pagemask (void)
1887 /* 1k pages not implemented */
1888 env
->CP0_PageMask
= T0
& (0x1FFFFFFF & (TARGET_PAGE_MASK
<< 1));
1892 void op_mtc0_pagegrain (void)
1894 /* SmartMIPS not implemented */
1895 /* Large physaddr (PABITS) not implemented */
1896 /* 1k pages not implemented */
1897 env
->CP0_PageGrain
= 0;
1901 void op_mtc0_wired (void)
1903 env
->CP0_Wired
= T0
% env
->tlb
->nb_tlb
;
1907 void op_mtc0_srsconf0 (void)
1909 env
->CP0_SRSConf0
|= T0
& env
->CP0_SRSConf0_rw_bitmask
;
1913 void op_mtc0_srsconf1 (void)
1915 env
->CP0_SRSConf1
|= T0
& env
->CP0_SRSConf1_rw_bitmask
;
1919 void op_mtc0_srsconf2 (void)
1921 env
->CP0_SRSConf2
|= T0
& env
->CP0_SRSConf2_rw_bitmask
;
1925 void op_mtc0_srsconf3 (void)
1927 env
->CP0_SRSConf3
|= T0
& env
->CP0_SRSConf3_rw_bitmask
;
1931 void op_mtc0_srsconf4 (void)
1933 env
->CP0_SRSConf4
|= T0
& env
->CP0_SRSConf4_rw_bitmask
;
1937 void op_mtc0_hwrena (void)
1939 env
->CP0_HWREna
= T0
& 0x0000000F;
1943 void op_mtc0_count (void)
1945 CALL_FROM_TB2(cpu_mips_store_count
, env
, T0
);
1949 void op_mtc0_entryhi (void)
1951 target_ulong old
, val
;
1953 /* 1k pages not implemented */
1954 val
= T0
& ((TARGET_PAGE_MASK
<< 1) | 0xFF);
1955 #if defined(TARGET_MIPS64)
1956 val
&= env
->SEGMask
;
1958 old
= env
->CP0_EntryHi
;
1959 env
->CP0_EntryHi
= val
;
1960 if (env
->CP0_Config3
& (1 << CP0C3_MT
)) {
1961 uint32_t tcst
= env
->CP0_TCStatus
[env
->current_tc
] & ~0xff;
1962 env
->CP0_TCStatus
[env
->current_tc
] = tcst
| (val
& 0xff);
1964 /* If the ASID changes, flush qemu's TLB. */
1965 if ((old
& 0xFF) != (val
& 0xFF))
1966 CALL_FROM_TB2(cpu_mips_tlb_flush
, env
, 1);
1970 void op_mttc0_entryhi(void)
1972 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1974 env
->CP0_EntryHi
= (env
->CP0_EntryHi
& 0xff) | (T0
& ~0xff);
1975 env
->CP0_TCStatus
[other_tc
] = (env
->CP0_TCStatus
[other_tc
] & ~0xff) | (T0
& 0xff);
1979 void op_mtc0_compare (void)
1981 CALL_FROM_TB2(cpu_mips_store_compare
, env
, T0
);
1985 void op_mtc0_status (void)
1988 uint32_t mask
= env
->CP0_Status_rw_bitmask
;
1991 old
= env
->CP0_Status
;
1992 env
->CP0_Status
= (env
->CP0_Status
& ~mask
) | val
;
1993 CALL_FROM_TB1(compute_hflags
, env
);
1994 if (loglevel
& CPU_LOG_EXEC
)
1995 CALL_FROM_TB2(do_mtc0_status_debug
, old
, val
);
1996 CALL_FROM_TB1(cpu_mips_update_irq
, env
);
2000 void op_mttc0_status(void)
2002 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
2003 uint32_t tcstatus
= env
->CP0_TCStatus
[other_tc
];
2005 env
->CP0_Status
= T0
& ~0xf1000018;
2006 tcstatus
= (tcstatus
& ~(0xf << CP0TCSt_TCU0
)) | (T0
& (0xf << CP0St_CU0
));
2007 tcstatus
= (tcstatus
& ~(1 << CP0TCSt_TMX
)) | ((T0
& (1 << CP0St_MX
)) << (CP0TCSt_TMX
- CP0St_MX
));
2008 tcstatus
= (tcstatus
& ~(0x3 << CP0TCSt_TKSU
)) | ((T0
& (0x3 << CP0St_KSU
)) << (CP0TCSt_TKSU
- CP0St_KSU
));
2009 env
->CP0_TCStatus
[other_tc
] = tcstatus
;
2013 void op_mtc0_intctl (void)
2015 /* vectored interrupts not implemented, no performance counters. */
2016 env
->CP0_IntCtl
= (env
->CP0_IntCtl
& ~0x000002e0) | (T0
& 0x000002e0);
2020 void op_mtc0_srsctl (void)
2022 uint32_t mask
= (0xf << CP0SRSCtl_ESS
) | (0xf << CP0SRSCtl_PSS
);
2023 env
->CP0_SRSCtl
= (env
->CP0_SRSCtl
& ~mask
) | (T0
& mask
);
2027 void op_mtc0_srsmap (void)
2029 env
->CP0_SRSMap
= T0
;
2033 void op_mtc0_cause (void)
2035 uint32_t mask
= 0x00C00300;
2036 uint32_t old
= env
->CP0_Cause
;
2038 if (env
->insn_flags
& ISA_MIPS32R2
)
2039 mask
|= 1 << CP0Ca_DC
;
2041 env
->CP0_Cause
= (env
->CP0_Cause
& ~mask
) | (T0
& mask
);
2043 if ((old
^ env
->CP0_Cause
) & (1 << CP0Ca_DC
)) {
2044 if (env
->CP0_Cause
& (1 << CP0Ca_DC
))
2045 CALL_FROM_TB1(cpu_mips_stop_count
, env
);
2047 CALL_FROM_TB1(cpu_mips_start_count
, env
);
2050 /* Handle the software interrupt as an hardware one, as they
2052 if (T0
& CP0Ca_IP_mask
) {
2053 CALL_FROM_TB1(cpu_mips_update_irq
, env
);
2058 void op_mtc0_epc (void)
2064 void op_mtc0_ebase (void)
2066 /* vectored interrupts not implemented */
2067 /* Multi-CPU not implemented */
2068 env
->CP0_EBase
= 0x80000000 | (T0
& 0x3FFFF000);
2072 void op_mtc0_config0 (void)
2074 env
->CP0_Config0
= (env
->CP0_Config0
& 0x81FFFFF8) | (T0
& 0x00000007);
2078 void op_mtc0_config2 (void)
2080 /* tertiary/secondary caches not implemented */
2081 env
->CP0_Config2
= (env
->CP0_Config2
& 0x8FFF0FFF);
2085 void op_mtc0_watchlo (void)
2087 /* Watch exceptions for instructions, data loads, data stores
2089 env
->CP0_WatchLo
[PARAM1
] = (T0
& ~0x7);
2093 void op_mtc0_watchhi (void)
2095 env
->CP0_WatchHi
[PARAM1
] = (T0
& 0x40FF0FF8);
2096 env
->CP0_WatchHi
[PARAM1
] &= ~(env
->CP0_WatchHi
[PARAM1
] & T0
& 0x7);
2100 void op_mtc0_xcontext (void)
2102 target_ulong mask
= (1ULL << (env
->SEGBITS
- 7)) - 1;
2103 env
->CP0_XContext
= (env
->CP0_XContext
& mask
) | (T0
& ~mask
);
2107 void op_mtc0_framemask (void)
2109 env
->CP0_Framemask
= T0
; /* XXX */
2113 void op_mtc0_debug (void)
2115 env
->CP0_Debug
= (env
->CP0_Debug
& 0x8C03FC1F) | (T0
& 0x13300120);
2116 if (T0
& (1 << CP0DB_DM
))
2117 env
->hflags
|= MIPS_HFLAG_DM
;
2119 env
->hflags
&= ~MIPS_HFLAG_DM
;
2123 void op_mttc0_debug(void)
2125 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
2127 /* XXX: Might be wrong, check with EJTAG spec. */
2128 env
->CP0_Debug_tcstatus
[other_tc
] = T0
& ((1 << CP0DB_SSt
) | (1 << CP0DB_Halt
));
2129 env
->CP0_Debug
= (env
->CP0_Debug
& ((1 << CP0DB_SSt
) | (1 << CP0DB_Halt
))) |
2130 (T0
& ~((1 << CP0DB_SSt
) | (1 << CP0DB_Halt
)));
2134 void op_mtc0_depc (void)
2140 void op_mtc0_performance0 (void)
2142 env
->CP0_Performance0
= T0
& 0x000007ff;
2146 void op_mtc0_taglo (void)
2148 env
->CP0_TagLo
= T0
& 0xFFFFFCF6;
2152 void op_mtc0_datalo (void)
2154 env
->CP0_DataLo
= T0
; /* XXX */
2158 void op_mtc0_taghi (void)
2160 env
->CP0_TagHi
= T0
; /* XXX */
2164 void op_mtc0_datahi (void)
2166 env
->CP0_DataHi
= T0
; /* XXX */
2170 void op_mtc0_errorepc (void)
2172 env
->CP0_ErrorEPC
= T0
;
2176 void op_mtc0_desave (void)
2178 env
->CP0_DESAVE
= T0
;
2182 #if defined(TARGET_MIPS64)
2183 void op_dmfc0_yqmask (void)
2185 T0
= env
->CP0_YQMask
;
2189 void op_dmfc0_vpeschedule (void)
2191 T0
= env
->CP0_VPESchedule
;
2195 void op_dmfc0_vpeschefback (void)
2197 T0
= env
->CP0_VPEScheFBack
;
2201 void op_dmfc0_entrylo0 (void)
2203 T0
= env
->CP0_EntryLo0
;
2207 void op_dmfc0_tcrestart (void)
2209 T0
= env
->PC
[env
->current_tc
];
2213 void op_dmfc0_tchalt (void)
2215 T0
= env
->CP0_TCHalt
[env
->current_tc
];
2219 void op_dmfc0_tccontext (void)
2221 T0
= env
->CP0_TCContext
[env
->current_tc
];
2225 void op_dmfc0_tcschedule (void)
2227 T0
= env
->CP0_TCSchedule
[env
->current_tc
];
2231 void op_dmfc0_tcschefback (void)
2233 T0
= env
->CP0_TCScheFBack
[env
->current_tc
];
2237 void op_dmfc0_entrylo1 (void)
2239 T0
= env
->CP0_EntryLo1
;
2243 void op_dmfc0_context (void)
2245 T0
= env
->CP0_Context
;
2249 void op_dmfc0_badvaddr (void)
2251 T0
= env
->CP0_BadVAddr
;
2255 void op_dmfc0_entryhi (void)
2257 T0
= env
->CP0_EntryHi
;
2261 void op_dmfc0_epc (void)
2267 void op_dmfc0_lladdr (void)
2269 T0
= env
->CP0_LLAddr
>> 4;
2273 void op_dmfc0_watchlo (void)
2275 T0
= env
->CP0_WatchLo
[PARAM1
];
2279 void op_dmfc0_xcontext (void)
2281 T0
= env
->CP0_XContext
;
2285 void op_dmfc0_depc (void)
2291 void op_dmfc0_errorepc (void)
2293 T0
= env
->CP0_ErrorEPC
;
2296 #endif /* TARGET_MIPS64 */
2298 /* MIPS MT functions */
2299 void op_mftgpr(void)
2301 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
2303 T0
= env
->gpr
[PARAM1
][other_tc
];
2309 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
2311 T0
= env
->LO
[PARAM1
][other_tc
];
2317 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
2319 T0
= env
->HI
[PARAM1
][other_tc
];
2323 void op_mftacx(void)
2325 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
2327 T0
= env
->ACX
[PARAM1
][other_tc
];
2331 void op_mftdsp(void)
2333 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
2335 T0
= env
->DSPControl
[other_tc
];
2339 void op_mttgpr(void)
2341 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
2343 T0
= env
->gpr
[PARAM1
][other_tc
];
2349 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
2351 T0
= env
->LO
[PARAM1
][other_tc
];
2357 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
2359 T0
= env
->HI
[PARAM1
][other_tc
];
2363 void op_mttacx(void)
2365 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
2367 T0
= env
->ACX
[PARAM1
][other_tc
];
2371 void op_mttdsp(void)
2373 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
2375 T0
= env
->DSPControl
[other_tc
];
2416 // TODO: store to TC register
2423 /* No scheduling policy implemented. */
2425 if (env
->CP0_VPEControl
& (1 << CP0VPECo_YSI
) &&
2426 env
->CP0_TCStatus
[env
->current_tc
] & (1 << CP0TCSt_DT
)) {
2427 env
->CP0_VPEControl
&= ~(0x7 << CP0VPECo_EXCPT
);
2428 env
->CP0_VPEControl
|= 4 << CP0VPECo_EXCPT
;
2429 CALL_FROM_TB1(do_raise_exception
, EXCP_THREAD
);
2432 } else if (T0
== 0) {
2433 if (0 /* TODO: TC underflow */) {
2434 env
->CP0_VPEControl
&= ~(0x7 << CP0VPECo_EXCPT
);
2435 CALL_FROM_TB1(do_raise_exception
, EXCP_THREAD
);
2437 // TODO: Deallocate TC
2439 } else if (T0
> 0) {
2440 /* Yield qualifier inputs not implemented. */
2441 env
->CP0_VPEControl
&= ~(0x7 << CP0VPECo_EXCPT
);
2442 env
->CP0_VPEControl
|= 2 << CP0VPECo_EXCPT
;
2443 CALL_FROM_TB1(do_raise_exception
, EXCP_THREAD
);
2445 T0
= env
->CP0_YQMask
;
2451 # define DEBUG_FPU_STATE() CALL_FROM_TB1(dump_fpu, env)
2453 # define DEBUG_FPU_STATE() do { } while(0)
2458 CALL_FROM_TB1(do_cfc1
, PARAM1
);
2465 CALL_FROM_TB1(do_ctc1
, PARAM1
);
2484 void op_dmfc1 (void)
2491 void op_dmtc1 (void)
2498 void op_mfhc1 (void)
2505 void op_mthc1 (void)
2513 Single precition routines have a "s" suffix, double precision a
2514 "d" suffix, 32bit integer "w", 64bit integer "l", paired singe "ps",
2515 paired single lowwer "pl", paired single upper "pu". */
2517 #define FLOAT_OP(name, p) void OPPROTO op_float_##name##_##p(void)
2521 CALL_FROM_TB0(do_float_cvtd_s
);
2527 CALL_FROM_TB0(do_float_cvtd_w
);
2533 CALL_FROM_TB0(do_float_cvtd_l
);
2539 CALL_FROM_TB0(do_float_cvtl_d
);
2545 CALL_FROM_TB0(do_float_cvtl_s
);
2558 CALL_FROM_TB0(do_float_cvtps_pw
);
2564 CALL_FROM_TB0(do_float_cvtpw_ps
);
2570 CALL_FROM_TB0(do_float_cvts_d
);
2576 CALL_FROM_TB0(do_float_cvts_w
);
2582 CALL_FROM_TB0(do_float_cvts_l
);
2588 CALL_FROM_TB0(do_float_cvts_pl
);
2594 CALL_FROM_TB0(do_float_cvts_pu
);
2600 CALL_FROM_TB0(do_float_cvtw_s
);
2606 CALL_FROM_TB0(do_float_cvtw_d
);
2613 DT2
= ((uint64_t)WT0
<< 32) | WT1
;
2619 DT2
= ((uint64_t)WT0
<< 32) | WTH1
;
2625 DT2
= ((uint64_t)WTH0
<< 32) | WT1
;
2631 DT2
= ((uint64_t)WTH0
<< 32) | WTH1
;
2636 #define FLOAT_ROUNDOP(op, ttype, stype) \
2637 FLOAT_OP(op ## ttype, stype) \
2639 CALL_FROM_TB0(do_float_ ## op ## ttype ## _ ## stype); \
2640 DEBUG_FPU_STATE(); \
2644 FLOAT_ROUNDOP(round
, l
, d
)
2645 FLOAT_ROUNDOP(round
, l
, s
)
2646 FLOAT_ROUNDOP(round
, w
, d
)
2647 FLOAT_ROUNDOP(round
, w
, s
)
2649 FLOAT_ROUNDOP(trunc
, l
, d
)
2650 FLOAT_ROUNDOP(trunc
, l
, s
)
2651 FLOAT_ROUNDOP(trunc
, w
, d
)
2652 FLOAT_ROUNDOP(trunc
, w
, s
)
2654 FLOAT_ROUNDOP(ceil
, l
, d
)
2655 FLOAT_ROUNDOP(ceil
, l
, s
)
2656 FLOAT_ROUNDOP(ceil
, w
, d
)
2657 FLOAT_ROUNDOP(ceil
, w
, s
)
2659 FLOAT_ROUNDOP(floor
, l
, d
)
2660 FLOAT_ROUNDOP(floor
, l
, s
)
2661 FLOAT_ROUNDOP(floor
, w
, d
)
2662 FLOAT_ROUNDOP(floor
, w
, s
)
2663 #undef FLOAR_ROUNDOP
2667 if (!(env
->fpu
->fcr31
& PARAM1
))
2674 if (!(env
->fpu
->fcr31
& PARAM1
))
2681 if (!(env
->fpu
->fcr31
& PARAM1
)) {
2690 if (env
->fpu
->fcr31
& PARAM1
)
2697 if (env
->fpu
->fcr31
& PARAM1
)
2704 if (env
->fpu
->fcr31
& PARAM1
) {
2758 /* operations calling helpers, for s, d and ps */
2759 #define FLOAT_HOP(name) \
2762 CALL_FROM_TB0(do_float_ ## name ## _d); \
2763 DEBUG_FPU_STATE(); \
2768 CALL_FROM_TB0(do_float_ ## name ## _s); \
2769 DEBUG_FPU_STATE(); \
2772 FLOAT_OP(name, ps) \
2774 CALL_FROM_TB0(do_float_ ## name ## _ps); \
2775 DEBUG_FPU_STATE(); \
2788 /* operations calling helpers, for s and d */
2789 #define FLOAT_HOP(name) \
2792 CALL_FROM_TB0(do_float_ ## name ## _d); \
2793 DEBUG_FPU_STATE(); \
2798 CALL_FROM_TB0(do_float_ ## name ## _s); \
2799 DEBUG_FPU_STATE(); \
2806 /* operations calling helpers, for ps */
2807 #define FLOAT_HOP(name) \
2808 FLOAT_OP(name, ps) \
2810 CALL_FROM_TB0(do_float_ ## name ## _ps); \
2811 DEBUG_FPU_STATE(); \
2818 /* ternary operations */
2819 #define FLOAT_TERNOP(name1, name2) \
2820 FLOAT_OP(name1 ## name2, d) \
2822 FDT0 = float64_ ## name1 (FDT0, FDT1, &env->fpu->fp_status); \
2823 FDT2 = float64_ ## name2 (FDT0, FDT2, &env->fpu->fp_status); \
2824 DEBUG_FPU_STATE(); \
2827 FLOAT_OP(name1 ## name2, s) \
2829 FST0 = float32_ ## name1 (FST0, FST1, &env->fpu->fp_status); \
2830 FST2 = float32_ ## name2 (FST0, FST2, &env->fpu->fp_status); \
2831 DEBUG_FPU_STATE(); \
2834 FLOAT_OP(name1 ## name2, ps) \
2836 FST0 = float32_ ## name1 (FST0, FST1, &env->fpu->fp_status); \
2837 FSTH0 = float32_ ## name1 (FSTH0, FSTH1, &env->fpu->fp_status); \
2838 FST2 = float32_ ## name2 (FST0, FST2, &env->fpu->fp_status); \
2839 FSTH2 = float32_ ## name2 (FSTH0, FSTH2, &env->fpu->fp_status); \
2840 DEBUG_FPU_STATE(); \
2843 FLOAT_TERNOP(mul
, add
)
2844 FLOAT_TERNOP(mul
, sub
)
2847 /* negated ternary operations */
2848 #define FLOAT_NTERNOP(name1, name2) \
2849 FLOAT_OP(n ## name1 ## name2, d) \
2851 FDT0 = float64_ ## name1 (FDT0, FDT1, &env->fpu->fp_status); \
2852 FDT2 = float64_ ## name2 (FDT0, FDT2, &env->fpu->fp_status); \
2853 FDT2 = float64_chs(FDT2); \
2854 DEBUG_FPU_STATE(); \
2857 FLOAT_OP(n ## name1 ## name2, s) \
2859 FST0 = float32_ ## name1 (FST0, FST1, &env->fpu->fp_status); \
2860 FST2 = float32_ ## name2 (FST0, FST2, &env->fpu->fp_status); \
2861 FST2 = float32_chs(FST2); \
2862 DEBUG_FPU_STATE(); \
2865 FLOAT_OP(n ## name1 ## name2, ps) \
2867 FST0 = float32_ ## name1 (FST0, FST1, &env->fpu->fp_status); \
2868 FSTH0 = float32_ ## name1 (FSTH0, FSTH1, &env->fpu->fp_status); \
2869 FST2 = float32_ ## name2 (FST0, FST2, &env->fpu->fp_status); \
2870 FSTH2 = float32_ ## name2 (FSTH0, FSTH2, &env->fpu->fp_status); \
2871 FST2 = float32_chs(FST2); \
2872 FSTH2 = float32_chs(FSTH2); \
2873 DEBUG_FPU_STATE(); \
2876 FLOAT_NTERNOP(mul
, add
)
2877 FLOAT_NTERNOP(mul
, sub
)
2878 #undef FLOAT_NTERNOP
2880 /* unary operations, modifying fp status */
2881 #define FLOAT_UNOP(name) \
2884 FDT2 = float64_ ## name(FDT0, &env->fpu->fp_status); \
2885 DEBUG_FPU_STATE(); \
2890 FST2 = float32_ ## name(FST0, &env->fpu->fp_status); \
2891 DEBUG_FPU_STATE(); \
2897 /* unary operations, not modifying fp status */
2898 #define FLOAT_UNOP(name) \
2901 FDT2 = float64_ ## name(FDT0); \
2902 DEBUG_FPU_STATE(); \
2907 FST2 = float32_ ## name(FST0); \
2908 DEBUG_FPU_STATE(); \
2911 FLOAT_OP(name, ps) \
2913 FST2 = float32_ ## name(FST0); \
2914 FSTH2 = float32_ ## name(FSTH0); \
2915 DEBUG_FPU_STATE(); \
2949 #ifdef TARGET_WORDS_BIGENDIAN
2957 default: /* unpredictable */
2964 #ifdef CONFIG_SOFTFLOAT
2965 #define clear_invalid() do { \
2966 int flags = get_float_exception_flags(&env->fpu->fp_status); \
2967 flags &= ~float_flag_invalid; \
2968 set_float_exception_flags(flags, &env->fpu->fp_status); \
2971 #define clear_invalid() do { } while(0)
2974 extern void dump_fpu_s(CPUState
*env
);
2976 #define CMP_OP(fmt, op) \
2977 void OPPROTO op_cmp ## _ ## fmt ## _ ## op(void) \
2979 CALL_FROM_TB1(do_cmp ## _ ## fmt ## _ ## op, PARAM1); \
2980 DEBUG_FPU_STATE(); \
2983 void OPPROTO op_cmpabs ## _ ## fmt ## _ ## op(void) \
2985 CALL_FROM_TB1(do_cmpabs ## _ ## fmt ## _ ## op, PARAM1); \
2986 DEBUG_FPU_STATE(); \
2989 #define CMP_OPS(op) \
3015 T0
= !!(~GET_FP_COND(env
->fpu
) & (0x1 << PARAM1
));
3019 void op_bc1any2f (void)
3021 T0
= !!(~GET_FP_COND(env
->fpu
) & (0x3 << PARAM1
));
3025 void op_bc1any4f (void)
3027 T0
= !!(~GET_FP_COND(env
->fpu
) & (0xf << PARAM1
));
3034 T0
= !!(GET_FP_COND(env
->fpu
) & (0x1 << PARAM1
));
3038 void op_bc1any2t (void)
3040 T0
= !!(GET_FP_COND(env
->fpu
) & (0x3 << PARAM1
));
3044 void op_bc1any4t (void)
3046 T0
= !!(GET_FP_COND(env
->fpu
) & (0xf << PARAM1
));
3051 void op_tlbwi (void)
3053 CALL_FROM_TB0(env
->tlb
->do_tlbwi
);
3057 void op_tlbwr (void)
3059 CALL_FROM_TB0(env
->tlb
->do_tlbwr
);
3065 CALL_FROM_TB0(env
->tlb
->do_tlbp
);
3071 CALL_FROM_TB0(env
->tlb
->do_tlbr
);
3076 #if defined (CONFIG_USER_ONLY)
3077 void op_tls_value (void)
3079 T0
= env
->tls_value
;
3085 CALL_FROM_TB1(do_pmon
, PARAM1
);
3091 T0
= env
->CP0_Status
;
3092 env
->CP0_Status
= T0
& ~(1 << CP0St_IE
);
3093 CALL_FROM_TB1(cpu_mips_update_irq
, env
);
3099 T0
= env
->CP0_Status
;
3100 env
->CP0_Status
= T0
| (1 << CP0St_IE
);
3101 CALL_FROM_TB1(cpu_mips_update_irq
, env
);
3108 CALL_FROM_TB1(do_raise_exception
, EXCP_TRAP
);
3113 void op_debug (void)
3115 CALL_FROM_TB1(do_raise_exception
, EXCP_DEBUG
);
3119 void op_set_lladdr (void)
3121 env
->CP0_LLAddr
= T2
;
3125 void debug_pre_eret (void);
3126 void debug_post_eret (void);
3129 if (loglevel
& CPU_LOG_EXEC
)
3130 CALL_FROM_TB0(debug_pre_eret
);
3131 if (env
->CP0_Status
& (1 << CP0St_ERL
)) {
3132 env
->PC
[env
->current_tc
] = env
->CP0_ErrorEPC
;
3133 env
->CP0_Status
&= ~(1 << CP0St_ERL
);
3135 env
->PC
[env
->current_tc
] = env
->CP0_EPC
;
3136 env
->CP0_Status
&= ~(1 << CP0St_EXL
);
3138 CALL_FROM_TB1(compute_hflags
, env
);
3139 if (loglevel
& CPU_LOG_EXEC
)
3140 CALL_FROM_TB0(debug_post_eret
);
3141 env
->CP0_LLAddr
= 1;
3145 void op_deret (void)
3147 if (loglevel
& CPU_LOG_EXEC
)
3148 CALL_FROM_TB0(debug_pre_eret
);
3149 env
->PC
[env
->current_tc
] = env
->CP0_DEPC
;
3150 env
->hflags
&= MIPS_HFLAG_DM
;
3151 CALL_FROM_TB1(compute_hflags
, env
);
3152 if (loglevel
& CPU_LOG_EXEC
)
3153 CALL_FROM_TB0(debug_post_eret
);
3154 env
->CP0_LLAddr
= 1;
3158 void op_rdhwr_cpunum(void)
3160 if ((env
->hflags
& MIPS_HFLAG_CP0
) ||
3161 (env
->CP0_HWREna
& (1 << 0)))
3162 T0
= env
->CP0_EBase
& 0x3ff;
3164 CALL_FROM_TB1(do_raise_exception
, EXCP_RI
);
3168 void op_rdhwr_synci_step(void)
3170 if ((env
->hflags
& MIPS_HFLAG_CP0
) ||
3171 (env
->CP0_HWREna
& (1 << 1)))
3172 T0
= env
->SYNCI_Step
;
3174 CALL_FROM_TB1(do_raise_exception
, EXCP_RI
);
3178 void op_rdhwr_cc(void)
3180 if ((env
->hflags
& MIPS_HFLAG_CP0
) ||
3181 (env
->CP0_HWREna
& (1 << 2)))
3182 T0
= env
->CP0_Count
;
3184 CALL_FROM_TB1(do_raise_exception
, EXCP_RI
);
3188 void op_rdhwr_ccres(void)
3190 if ((env
->hflags
& MIPS_HFLAG_CP0
) ||
3191 (env
->CP0_HWREna
& (1 << 3)))
3194 CALL_FROM_TB1(do_raise_exception
, EXCP_RI
);
3198 void op_save_state (void)
3200 env
->hflags
= PARAM1
;
3204 void op_save_pc (void)
3206 env
->PC
[env
->current_tc
] = PARAM1
;
3210 #if defined(TARGET_MIPS64)
3211 void op_save_pc64 (void)
3213 env
->PC
[env
->current_tc
] = ((uint64_t)PARAM1
<< 32) | (uint32_t)PARAM2
;
3218 void op_interrupt_restart (void)
3220 if (!(env
->CP0_Status
& (1 << CP0St_EXL
)) &&
3221 !(env
->CP0_Status
& (1 << CP0St_ERL
)) &&
3222 !(env
->hflags
& MIPS_HFLAG_DM
) &&
3223 (env
->CP0_Status
& (1 << CP0St_IE
)) &&
3224 (env
->CP0_Status
& env
->CP0_Cause
& CP0Ca_IP_mask
)) {
3225 env
->CP0_Cause
&= ~(0x1f << CP0Ca_EC
);
3226 CALL_FROM_TB1(do_raise_exception
, EXCP_EXT_INTERRUPT
);
3231 void op_raise_exception (void)
3233 CALL_FROM_TB1(do_raise_exception
, PARAM1
);
3237 void op_raise_exception_err (void)
3239 CALL_FROM_TB2(do_raise_exception_err
, PARAM1
, PARAM2
);
3246 CALL_FROM_TB1(do_raise_exception
, EXCP_HLT
);
3250 /* Bitfield operations. */
3253 unsigned int pos
= PARAM1
;
3254 unsigned int size
= PARAM2
;
3256 T0
= (int32_t)((T1
>> pos
) & ((size
< 32) ? ((1 << size
) - 1) : ~0));
3262 unsigned int pos
= PARAM1
;
3263 unsigned int size
= PARAM2
;
3264 target_ulong mask
= ((size
< 32) ? ((1 << size
) - 1) : ~0) << pos
;
3266 T0
= (int32_t)((T0
& ~mask
) | ((T1
<< pos
) & mask
));
3272 T0
= (int32_t)(((T1
<< 8) & ~0x00FF00FF) | ((T1
>> 8) & 0x00FF00FF));
3276 #if defined(TARGET_MIPS64)
3279 unsigned int pos
= PARAM1
;
3280 unsigned int size
= PARAM2
;
3282 T0
= (T1
>> pos
) & ((size
< 64) ? ((1ULL << size
) - 1) : ~0ULL);
3288 unsigned int pos
= PARAM1
;
3289 unsigned int size
= PARAM2
;
3290 target_ulong mask
= ((size
< 64) ? ((1ULL << size
) - 1) : ~0ULL) << pos
;
3292 T0
= (T0
& ~mask
) | ((T1
<< pos
) & mask
);
3298 T0
= ((T1
<< 8) & ~0x00FF00FF00FF00FFULL
) | ((T1
>> 8) & 0x00FF00FF00FF00FFULL
);
3304 T1
= ((T1
<< 16) & ~0x0000FFFF0000FFFFULL
) | ((T1
>> 16) & 0x0000FFFF0000FFFFULL
);
3305 T0
= (T1
<< 32) | (T1
>> 32);
3312 T0
= ((T1
& 0xFF) ^ 0x80) - 0x80;
3318 T0
= ((T1
& 0xFFFF) ^ 0x8000) - 0x8000;