2 * QEMU TCX Frame buffer
4 * Copyright (c) 2003-2005 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
27 #include "pixel_ops.h"
31 #define TCX_DAC_NREGS 16
32 #define TCX_THC_NREGS_8 0x081c
33 #define TCX_THC_NREGS_24 0x1000
34 #define TCX_TEC_NREGS 0x1000
36 typedef struct TCXState
{
37 target_phys_addr_t addr
;
41 uint32_t *vram24
, *cplane
;
42 ram_addr_t vram_offset
, vram24_offset
, cplane_offset
;
43 uint16_t width
, height
, depth
;
44 uint8_t r
[256], g
[256], b
[256];
45 uint32_t palette
[256];
46 uint8_t dac_index
, dac_state
;
49 static void tcx_screen_dump(void *opaque
, const char *filename
);
50 static void tcx24_screen_dump(void *opaque
, const char *filename
);
51 static void tcx_invalidate_display(void *opaque
);
52 static void tcx24_invalidate_display(void *opaque
);
54 static void update_palette_entries(TCXState
*s
, int start
, int end
)
57 for(i
= start
; i
< end
; i
++) {
58 switch(s
->ds
->depth
) {
61 s
->palette
[i
] = rgb_to_pixel8(s
->r
[i
], s
->g
[i
], s
->b
[i
]);
65 s
->palette
[i
] = rgb_to_pixel15bgr(s
->r
[i
], s
->g
[i
], s
->b
[i
]);
67 s
->palette
[i
] = rgb_to_pixel15(s
->r
[i
], s
->g
[i
], s
->b
[i
]);
71 s
->palette
[i
] = rgb_to_pixel16bgr(s
->r
[i
], s
->g
[i
], s
->b
[i
]);
73 s
->palette
[i
] = rgb_to_pixel16(s
->r
[i
], s
->g
[i
], s
->b
[i
]);
77 s
->palette
[i
] = rgb_to_pixel32bgr(s
->r
[i
], s
->g
[i
], s
->b
[i
]);
79 s
->palette
[i
] = rgb_to_pixel32(s
->r
[i
], s
->g
[i
], s
->b
[i
]);
84 tcx24_invalidate_display(s
);
86 tcx_invalidate_display(s
);
89 static void tcx_draw_line32(TCXState
*s1
, uint8_t *d
,
90 const uint8_t *s
, int width
)
94 uint32_t *p
= (uint32_t *)d
;
96 for(x
= 0; x
< width
; x
++) {
98 *p
++ = s1
->palette
[val
];
102 static void tcx_draw_line16(TCXState
*s1
, uint8_t *d
,
103 const uint8_t *s
, int width
)
107 uint16_t *p
= (uint16_t *)d
;
109 for(x
= 0; x
< width
; x
++) {
111 *p
++ = s1
->palette
[val
];
115 static void tcx_draw_line8(TCXState
*s1
, uint8_t *d
,
116 const uint8_t *s
, int width
)
121 for(x
= 0; x
< width
; x
++) {
123 *d
++ = s1
->palette
[val
];
127 static inline void tcx24_draw_line32(TCXState
*s1
, uint8_t *d
,
128 const uint8_t *s
, int width
,
129 const uint32_t *cplane
,
134 uint32_t *p
= (uint32_t *)d
;
137 for(x
= 0; x
< width
; x
++, s
++, s24
++) {
138 if ((bswap32(*cplane
++) & 0xff000000) == 0x03000000) { // 24-bit direct
139 dval
= bswap32(*s24
) & 0x00ffffff;
142 dval
= s1
->palette
[val
];
148 static inline int check_dirty(ram_addr_t page
, ram_addr_t page24
,
154 ret
= cpu_physical_memory_get_dirty(page
, VGA_DIRTY_FLAG
);
155 for (off
= 0; off
< TARGET_PAGE_SIZE
* 4; off
+= TARGET_PAGE_SIZE
) {
156 ret
|= cpu_physical_memory_get_dirty(page24
+ off
, VGA_DIRTY_FLAG
);
157 ret
|= cpu_physical_memory_get_dirty(cpage
+ off
, VGA_DIRTY_FLAG
);
162 static inline void reset_dirty(TCXState
*ts
, ram_addr_t page_min
,
163 ram_addr_t page_max
, ram_addr_t page24
,
166 cpu_physical_memory_reset_dirty(page_min
, page_max
+ TARGET_PAGE_SIZE
,
168 page_min
-= ts
->vram_offset
;
169 page_max
-= ts
->vram_offset
;
170 cpu_physical_memory_reset_dirty(page24
+ page_min
* 4,
171 page24
+ page_max
* 4 + TARGET_PAGE_SIZE
,
173 cpu_physical_memory_reset_dirty(cpage
+ page_min
* 4,
174 cpage
+ page_max
* 4 + TARGET_PAGE_SIZE
,
178 /* Fixed line length 1024 allows us to do nice tricks not possible on
180 static void tcx_update_display(void *opaque
)
182 TCXState
*ts
= opaque
;
183 ram_addr_t page
, page_min
, page_max
;
184 int y
, y_start
, dd
, ds
;
186 void (*f
)(TCXState
*s1
, uint8_t *dst
, const uint8_t *src
, int width
);
188 if (ts
->ds
->depth
== 0)
190 page
= ts
->vram_offset
;
192 page_min
= 0xffffffff;
196 dd
= ts
->ds
->linesize
;
199 switch (ts
->ds
->depth
) {
215 for(y
= 0; y
< ts
->height
; y
+= 4, page
+= TARGET_PAGE_SIZE
) {
216 if (cpu_physical_memory_get_dirty(page
, VGA_DIRTY_FLAG
)) {
223 f(ts
, d
, s
, ts
->width
);
226 f(ts
, d
, s
, ts
->width
);
229 f(ts
, d
, s
, ts
->width
);
232 f(ts
, d
, s
, ts
->width
);
237 /* flush to display */
238 dpy_update(ts
->ds
, 0, y_start
,
239 ts
->width
, y
- y_start
);
247 /* flush to display */
248 dpy_update(ts
->ds
, 0, y_start
,
249 ts
->width
, y
- y_start
);
251 /* reset modified pages */
252 if (page_min
<= page_max
) {
253 cpu_physical_memory_reset_dirty(page_min
, page_max
+ TARGET_PAGE_SIZE
,
258 static void tcx24_update_display(void *opaque
)
260 TCXState
*ts
= opaque
;
261 ram_addr_t page
, page_min
, page_max
, cpage
, page24
;
262 int y
, y_start
, dd
, ds
;
264 uint32_t *cptr
, *s24
;
266 if (ts
->ds
->depth
!= 32)
268 page
= ts
->vram_offset
;
269 page24
= ts
->vram24_offset
;
270 cpage
= ts
->cplane_offset
;
272 page_min
= 0xffffffff;
278 dd
= ts
->ds
->linesize
;
281 for(y
= 0; y
< ts
->height
; y
+= 4, page
+= TARGET_PAGE_SIZE
,
282 page24
+= TARGET_PAGE_SIZE
, cpage
+= TARGET_PAGE_SIZE
) {
283 if (check_dirty(page
, page24
, cpage
)) {
290 tcx24_draw_line32(ts
, d
, s
, ts
->width
, cptr
, s24
);
295 tcx24_draw_line32(ts
, d
, s
, ts
->width
, cptr
, s24
);
300 tcx24_draw_line32(ts
, d
, s
, ts
->width
, cptr
, s24
);
305 tcx24_draw_line32(ts
, d
, s
, ts
->width
, cptr
, s24
);
312 /* flush to display */
313 dpy_update(ts
->ds
, 0, y_start
,
314 ts
->width
, y
- y_start
);
324 /* flush to display */
325 dpy_update(ts
->ds
, 0, y_start
,
326 ts
->width
, y
- y_start
);
328 /* reset modified pages */
329 if (page_min
<= page_max
) {
330 reset_dirty(ts
, page_min
, page_max
, page24
, cpage
);
334 static void tcx_invalidate_display(void *opaque
)
336 TCXState
*s
= opaque
;
339 for (i
= 0; i
< MAXX
*MAXY
; i
+= TARGET_PAGE_SIZE
) {
340 cpu_physical_memory_set_dirty(s
->vram_offset
+ i
);
344 static void tcx24_invalidate_display(void *opaque
)
346 TCXState
*s
= opaque
;
349 tcx_invalidate_display(s
);
350 for (i
= 0; i
< MAXX
*MAXY
* 4; i
+= TARGET_PAGE_SIZE
) {
351 cpu_physical_memory_set_dirty(s
->vram24_offset
+ i
);
352 cpu_physical_memory_set_dirty(s
->cplane_offset
+ i
);
356 static void tcx_save(QEMUFile
*f
, void *opaque
)
358 TCXState
*s
= opaque
;
360 qemu_put_be16s(f
, (uint16_t *)&s
->height
);
361 qemu_put_be16s(f
, (uint16_t *)&s
->width
);
362 qemu_put_be16s(f
, (uint16_t *)&s
->depth
);
363 qemu_put_buffer(f
, s
->r
, 256);
364 qemu_put_buffer(f
, s
->g
, 256);
365 qemu_put_buffer(f
, s
->b
, 256);
366 qemu_put_8s(f
, &s
->dac_index
);
367 qemu_put_8s(f
, &s
->dac_state
);
370 static int tcx_load(QEMUFile
*f
, void *opaque
, int version_id
)
372 TCXState
*s
= opaque
;
375 if (version_id
!= 3 && version_id
!= 4)
378 if (version_id
== 3) {
379 qemu_get_be32s(f
, (uint32_t *)&dummy
);
380 qemu_get_be32s(f
, (uint32_t *)&dummy
);
381 qemu_get_be32s(f
, (uint32_t *)&dummy
);
383 qemu_get_be16s(f
, (uint16_t *)&s
->height
);
384 qemu_get_be16s(f
, (uint16_t *)&s
->width
);
385 qemu_get_be16s(f
, (uint16_t *)&s
->depth
);
386 qemu_get_buffer(f
, s
->r
, 256);
387 qemu_get_buffer(f
, s
->g
, 256);
388 qemu_get_buffer(f
, s
->b
, 256);
389 qemu_get_8s(f
, &s
->dac_index
);
390 qemu_get_8s(f
, &s
->dac_state
);
391 update_palette_entries(s
, 0, 256);
393 tcx24_invalidate_display(s
);
395 tcx_invalidate_display(s
);
400 static void tcx_reset(void *opaque
)
402 TCXState
*s
= opaque
;
404 /* Initialize palette */
405 memset(s
->r
, 0, 256);
406 memset(s
->g
, 0, 256);
407 memset(s
->b
, 0, 256);
408 s
->r
[255] = s
->g
[255] = s
->b
[255] = 255;
409 update_palette_entries(s
, 0, 256);
410 memset(s
->vram
, 0, MAXX
*MAXY
);
411 cpu_physical_memory_reset_dirty(s
->vram_offset
, s
->vram_offset
+
412 MAXX
* MAXY
* (1 + 4 + 4), VGA_DIRTY_FLAG
);
417 static uint32_t tcx_dac_readl(void *opaque
, target_phys_addr_t addr
)
422 static void tcx_dac_writel(void *opaque
, target_phys_addr_t addr
, uint32_t val
)
424 TCXState
*s
= opaque
;
427 saddr
= (addr
& (TCX_DAC_NREGS
- 1)) >> 2;
430 s
->dac_index
= val
>> 24;
434 switch (s
->dac_state
) {
436 s
->r
[s
->dac_index
] = val
>> 24;
437 update_palette_entries(s
, s
->dac_index
, s
->dac_index
+ 1);
441 s
->g
[s
->dac_index
] = val
>> 24;
442 update_palette_entries(s
, s
->dac_index
, s
->dac_index
+ 1);
446 s
->b
[s
->dac_index
] = val
>> 24;
447 update_palette_entries(s
, s
->dac_index
, s
->dac_index
+ 1);
448 s
->dac_index
= (s
->dac_index
+ 1) & 255; // Index autoincrement
460 static CPUReadMemoryFunc
*tcx_dac_read
[3] = {
466 static CPUWriteMemoryFunc
*tcx_dac_write
[3] = {
472 static uint32_t tcx_dummy_readl(void *opaque
, target_phys_addr_t addr
)
477 static void tcx_dummy_writel(void *opaque
, target_phys_addr_t addr
,
482 static CPUReadMemoryFunc
*tcx_dummy_read
[3] = {
488 static CPUWriteMemoryFunc
*tcx_dummy_write
[3] = {
494 void tcx_init(DisplayState
*ds
, target_phys_addr_t addr
, uint8_t *vram_base
,
495 unsigned long vram_offset
, int vram_size
, int width
, int height
,
499 int io_memory
, dummy_memory
;
502 s
= qemu_mallocz(sizeof(TCXState
));
507 s
->vram_offset
= vram_offset
;
515 cpu_register_physical_memory(addr
+ 0x00800000ULL
, size
, vram_offset
);
519 io_memory
= cpu_register_io_memory(0, tcx_dac_read
, tcx_dac_write
, s
);
520 cpu_register_physical_memory(addr
+ 0x00200000ULL
, TCX_DAC_NREGS
,
523 dummy_memory
= cpu_register_io_memory(0, tcx_dummy_read
, tcx_dummy_write
,
525 cpu_register_physical_memory(addr
+ 0x00700000ULL
, TCX_TEC_NREGS
,
529 size
= vram_size
* 4;
530 s
->vram24
= (uint32_t *)vram_base
;
531 s
->vram24_offset
= vram_offset
;
532 cpu_register_physical_memory(addr
+ 0x02000000ULL
, size
, vram_offset
);
537 size
= vram_size
* 4;
538 s
->cplane
= (uint32_t *)vram_base
;
539 s
->cplane_offset
= vram_offset
;
540 cpu_register_physical_memory(addr
+ 0x0a000000ULL
, size
, vram_offset
);
541 s
->console
= graphic_console_init(s
->ds
, tcx24_update_display
,
542 tcx24_invalidate_display
,
543 tcx24_screen_dump
, NULL
, s
);
545 cpu_register_physical_memory(addr
+ 0x00300000ULL
, TCX_THC_NREGS_8
,
547 s
->console
= graphic_console_init(s
->ds
, tcx_update_display
,
548 tcx_invalidate_display
,
549 tcx_screen_dump
, NULL
, s
);
551 // NetBSD writes here even with 8-bit display
552 cpu_register_physical_memory(addr
+ 0x00301000ULL
, TCX_THC_NREGS_24
,
555 register_savevm("tcx", addr
, 4, tcx_save
, tcx_load
, s
);
556 qemu_register_reset(tcx_reset
, s
);
558 qemu_console_resize(s
->console
, width
, height
);
561 static void tcx_screen_dump(void *opaque
, const char *filename
)
563 TCXState
*s
= opaque
;
568 f
= fopen(filename
, "wb");
571 fprintf(f
, "P6\n%d %d\n%d\n", s
->width
, s
->height
, 255);
573 for(y
= 0; y
< s
->height
; y
++) {
575 for(x
= 0; x
< s
->width
; x
++) {
588 static void tcx24_screen_dump(void *opaque
, const char *filename
)
590 TCXState
*s
= opaque
;
593 uint32_t *s24
, *cptr
, dval
;
596 f
= fopen(filename
, "wb");
599 fprintf(f
, "P6\n%d %d\n%d\n", s
->width
, s
->height
, 255);
603 for(y
= 0; y
< s
->height
; y
++) {
605 for(x
= 0; x
< s
->width
; x
++, d
++, s24
++) {
606 if ((*cptr
++ & 0xff000000) == 0x03000000) { // 24-bit direct
607 dval
= *s24
& 0x00ffffff;
608 fputc((dval
>> 16) & 0xff, f
);
609 fputc((dval
>> 8) & 0xff, f
);
610 fputc(dval
& 0xff, f
);