2 * QEMU ETRAX Ethernet Controller.
4 * Copyright (c) 2008 Edgar E. Iglesias, Axis Communications AB.
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
29 #include "etraxfs_dma.h"
34 * The MDIO extensions in the TDK PHY model were reversed engineered from the
35 * linux driver (PHYID and Diagnostics reg).
36 * TODO: Add friendly names for the register nums.
42 unsigned int (*read
)(struct qemu_phy
*phy
, unsigned int req
);
43 void (*write
)(struct qemu_phy
*phy
, unsigned int req
,
47 static unsigned int tdk_read(struct qemu_phy
*phy
, unsigned int req
)
57 /* Speeds and modes. */
58 r
|= (1 << 13) | (1 << 14);
59 r
|= (1 << 11) | (1 << 12);
60 r
|= (1 << 5); /* Autoneg complete. */
61 r
|= (1 << 3); /* Autoneg able. */
62 r
|= (1 << 2); /* Link. */
65 /* Link partner ability.
66 We are kind; always agree with whatever best mode
67 the guest advertises. */
68 r
= 1 << 14; /* Success. */
69 /* Copy advertised modes. */
70 r
|= phy
->regs
[4] & (15 << 5);
71 /* Autoneg support. */
76 /* Diagnostics reg. */
80 /* Are we advertising 100 half or 100 duplex ? */
81 speed_100
= !!(phy
->regs
[4] & 0x180);
82 /* Are we advertising 10 duplex or 100 duplex ? */
83 duplex
= !!(phy
->regs
[4] & 0x180);
84 r
= (speed_100
<< 10) | (duplex
<< 11);
89 r
= phy
->regs
[regnum
];
92 D(printf("\n%s %x = reg[%d]\n", __func__
, r
, regnum
));
97 tdk_write(struct qemu_phy
*phy
, unsigned int req
, unsigned int data
)
102 D(printf("%s reg[%d] = %x\n", __func__
, regnum
, data
));
105 phy
->regs
[regnum
] = data
;
111 tdk_init(struct qemu_phy
*phy
)
113 phy
->regs
[0] = 0x3100;
115 phy
->regs
[2] = 0x0300;
116 phy
->regs
[3] = 0xe400;
117 /* Autonegotiation advertisement reg. */
118 phy
->regs
[4] = 0x01E1;
120 phy
->read
= tdk_read
;
121 phy
->write
= tdk_write
;
148 struct qemu_phy
*devs
[32];
152 mdio_attach(struct qemu_mdio
*bus
, struct qemu_phy
*phy
, unsigned int addr
)
154 bus
->devs
[addr
& 0x1f] = phy
;
158 mdio_detach(struct qemu_mdio
*bus
, struct qemu_phy
*phy
, unsigned int addr
)
160 bus
->devs
[addr
& 0x1f] = NULL
;
163 static void mdio_read_req(struct qemu_mdio
*bus
)
165 struct qemu_phy
*phy
;
167 phy
= bus
->devs
[bus
->addr
];
168 if (phy
&& phy
->read
)
169 bus
->data
= phy
->read(phy
, bus
->req
);
174 static void mdio_write_req(struct qemu_mdio
*bus
)
176 struct qemu_phy
*phy
;
178 phy
= bus
->devs
[bus
->addr
];
179 if (phy
&& phy
->write
)
180 phy
->write(phy
, bus
->req
, bus
->data
);
183 static void mdio_cycle(struct qemu_mdio
*bus
)
187 D(printf("mdc=%d mdio=%d state=%d cnt=%d drv=%d\n",
188 bus
->mdc
, bus
->mdio
, bus
->state
, bus
->cnt
, bus
->drive
));
191 printf("%d", bus
->mdio
);
197 if (bus
->cnt
>= (32 * 2) && !bus
->mdio
) {
207 printf("WARNING: no SOF\n");
208 if (bus
->cnt
== 1*2) {
218 bus
->opc
|= bus
->mdio
& 1;
219 if (bus
->cnt
== 2*2) {
229 bus
->addr
|= bus
->mdio
& 1;
231 if (bus
->cnt
== 5*2) {
241 bus
->req
|= bus
->mdio
& 1;
242 if (bus
->cnt
== 5*2) {
244 bus
->state
= TURNAROUND
;
249 if (bus
->mdc
&& bus
->cnt
== 2*2) {
256 bus
->mdio
= bus
->data
& 1;
264 bus
->mdio
= !!(bus
->data
& (1 << 15));
270 bus
->data
|= bus
->mdio
;
272 if (bus
->cnt
== 16 * 2) {
274 bus
->state
= PREAMBLE
;
286 /* ETRAX-FS Ethernet MAC block starts here. */
288 #define RW_MA0_LO 0x00
289 #define RW_MA0_HI 0x04
290 #define RW_MA1_LO 0x08
291 #define RW_MA1_HI 0x0c
292 #define RW_GA_LO 0x10
293 #define RW_GA_HI 0x14
294 #define RW_GEN_CTRL 0x18
295 #define RW_REC_CTRL 0x1c
296 #define RW_TR_CTRL 0x20
297 #define RW_CLR_ERR 0x24
298 #define RW_MGM_CTRL 0x28
300 #define FS_ETH_MAX_REGS 0x5c
306 target_phys_addr_t base
;
310 /* Two addrs in the filter. */
311 uint8_t macaddr
[2][6];
312 uint32_t regs
[FS_ETH_MAX_REGS
];
314 unsigned char rx_fifo
[1536];
318 struct etraxfs_dma_client
*dma_out
;
319 struct etraxfs_dma_client
*dma_in
;
322 struct qemu_mdio mdio_bus
;
327 static uint32_t eth_rinvalid (void *opaque
, target_phys_addr_t addr
)
329 struct fs_eth
*eth
= opaque
;
330 CPUState
*env
= eth
->env
;
331 cpu_abort(env
, "Unsupported short access. reg=%x pc=%x.\n",
336 static uint32_t eth_readl (void *opaque
, target_phys_addr_t addr
)
338 struct fs_eth
*eth
= opaque
;
339 D(CPUState
*env
= eth
->env
);
342 /* Make addr relative to this instances base. */
346 /* Attach an MDIO/PHY abstraction. */
347 r
= eth
->mdio_bus
.mdio
& 1;
351 D(printf ("%s %x p=%x\n", __func__
, addr
, env
->pc
));
358 eth_winvalid (void *opaque
, target_phys_addr_t addr
, uint32_t value
)
360 struct fs_eth
*eth
= opaque
;
361 CPUState
*env
= eth
->env
;
362 cpu_abort(env
, "Unsupported short access. reg=%x pc=%x.\n",
366 static void eth_update_ma(struct fs_eth
*eth
, int ma
)
377 eth
->macaddr
[ma
][i
++] = eth
->regs
[reg
];
378 eth
->macaddr
[ma
][i
++] = eth
->regs
[reg
] >> 8;
379 eth
->macaddr
[ma
][i
++] = eth
->regs
[reg
] >> 16;
380 eth
->macaddr
[ma
][i
++] = eth
->regs
[reg
] >> 24;
381 eth
->macaddr
[ma
][i
++] = eth
->regs
[reg
+ 4];
382 eth
->macaddr
[ma
][i
++] = eth
->regs
[reg
+ 4] >> 8;
384 D(printf("set mac%d=%x.%x.%x.%x.%x.%x\n", ma
,
385 eth
->macaddr
[ma
][0], eth
->macaddr
[ma
][1],
386 eth
->macaddr
[ma
][2], eth
->macaddr
[ma
][3],
387 eth
->macaddr
[ma
][4], eth
->macaddr
[ma
][5]));
391 eth_writel (void *opaque
, target_phys_addr_t addr
, uint32_t value
)
393 struct fs_eth
*eth
= opaque
;
395 /* Make addr relative to this instances base. */
400 eth
->regs
[addr
] = value
;
401 eth_update_ma(eth
, 0);
404 eth
->regs
[addr
] = value
;
405 eth_update_ma(eth
, 0);
408 eth
->regs
[addr
] = value
;
409 eth_update_ma(eth
, 1);
412 eth
->regs
[addr
] = value
;
413 eth_update_ma(eth
, 1);
417 /* Attach an MDIO/PHY abstraction. */
419 eth
->mdio_bus
.mdio
= value
& 1;
420 if (eth
->mdio_bus
.mdc
!= (value
& 4))
421 mdio_cycle(ð
->mdio_bus
);
422 eth
->mdio_bus
.mdc
= !!(value
& 4);
426 eth
->regs
[addr
] = value
;
427 D(printf ("%s %x %x\n",
428 __func__
, addr
, value
));
433 /* The ETRAX FS has a groupt address table (GAT) which works like a k=1 bloom
434 filter dropping group addresses we have not joined. The filter has 64
435 bits (m). The has function is a simple nible xor of the group addr. */
436 static int eth_match_groupaddr(struct fs_eth
*eth
, const unsigned char *sa
)
439 int m_individual
= eth
->regs
[RW_REC_CTRL
] & 4;
442 /* First bit on the wire of a MAC address signals multicast or
444 if (!m_individual
&& !sa
[0] & 1)
447 /* Calculate the hash index for the GA registers. */
450 hsh
^= ((*sa
) >> 6) & 0x03;
452 hsh
^= ((*sa
) << 2) & 0x03c;
453 hsh
^= ((*sa
) >> 4) & 0xf;
455 hsh
^= ((*sa
) << 4) & 0x30;
456 hsh
^= ((*sa
) >> 2) & 0x3f;
459 hsh
^= ((*sa
) >> 6) & 0x03;
461 hsh
^= ((*sa
) << 2) & 0x03c;
462 hsh
^= ((*sa
) >> 4) & 0xf;
464 hsh
^= ((*sa
) << 4) & 0x30;
465 hsh
^= ((*sa
) >> 2) & 0x3f;
469 match
= eth
->regs
[RW_GA_HI
] & (1 << (hsh
- 32));
471 match
= eth
->regs
[RW_GA_LO
] & (1 << hsh
);
472 D(printf("hsh=%x ga=%x.%x mtch=%d\n", hsh
,
473 eth
->regs
[RW_GA_HI
], eth
->regs
[RW_GA_LO
], match
));
477 static int eth_can_receive(void *opaque
)
479 struct fs_eth
*eth
= opaque
;
482 r
= eth
->rx_fifo_len
== 0;
484 /* TODO: signal fifo overrun. */
485 printf("PACKET LOSS!\n");
490 static void eth_receive(void *opaque
, const uint8_t *buf
, int size
)
492 unsigned char sa_bcast
[6] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
493 struct fs_eth
*eth
= opaque
;
494 int use_ma0
= eth
->regs
[RW_REC_CTRL
] & 1;
495 int use_ma1
= eth
->regs
[RW_REC_CTRL
] & 2;
496 int r_bcast
= eth
->regs
[RW_REC_CTRL
] & 8;
501 D(printf("%x.%x.%x.%x.%x.%x ma=%d %d bc=%d\n",
502 buf
[0], buf
[1], buf
[2], buf
[3], buf
[4], buf
[5],
503 use_ma0
, use_ma1
, r_bcast
));
505 /* Does the frame get through the address filters? */
506 if ((!use_ma0
|| memcmp(buf
, eth
->macaddr
[0], 6))
507 && (!use_ma1
|| memcmp(buf
, eth
->macaddr
[1], 6))
508 && (!r_bcast
|| memcmp(buf
, sa_bcast
, 6))
509 && !eth_match_groupaddr(eth
, buf
))
512 if (size
> sizeof(eth
->rx_fifo
)) {
513 /* TODO: signal error. */
514 } else if (eth
->rx_fifo_len
) {
517 memcpy(eth
->rx_fifo
, buf
, size
);
518 /* +4, HW passes the CRC to sw. */
519 eth
->rx_fifo_len
= size
+ 4;
520 eth
->rx_fifo_pos
= 0;
524 static void eth_rx_pull(void *opaque
)
526 struct fs_eth
*eth
= opaque
;
528 if (eth
->rx_fifo_len
) {
529 D(printf("%s %d\n", __func__
, eth
->rx_fifo_len
));
533 for (i
= 0; i
< 32; i
++)
534 printf("%2.2x", eth
->rx_fifo
[i
]);
538 len
= etraxfs_dmac_input(eth
->dma_in
,
539 eth
->rx_fifo
+ eth
->rx_fifo_pos
,
540 eth
->rx_fifo_len
, 1);
541 eth
->rx_fifo_len
-= len
;
542 eth
->rx_fifo_pos
+= len
;
546 static int eth_tx_push(void *opaque
, unsigned char *buf
, int len
)
548 struct fs_eth
*eth
= opaque
;
550 D(printf("%s buf=%p len=%d\n", __func__
, buf
, len
));
551 qemu_send_packet(eth
->vc
, buf
, len
);
555 static CPUReadMemoryFunc
*eth_read
[] = {
561 static CPUWriteMemoryFunc
*eth_write
[] = {
567 void *etraxfs_eth_init(NICInfo
*nd
, CPUState
*env
,
568 qemu_irq
*irq
, target_phys_addr_t base
)
570 struct etraxfs_dma_client
*dma
= NULL
;
571 struct fs_eth
*eth
= NULL
;
573 dma
= qemu_mallocz(sizeof *dma
* 2);
577 eth
= qemu_mallocz(sizeof *eth
);
581 dma
[0].client
.push
= eth_tx_push
;
582 dma
[0].client
.opaque
= eth
;
583 dma
[1].client
.opaque
= eth
;
584 dma
[1].client
.pull
= eth_rx_pull
;
590 eth
->dma_in
= dma
+ 1;
592 /* Connect the phy. */
594 mdio_attach(ð
->mdio_bus
, ð
->phy
, 0x1);
596 eth
->ethregs
= cpu_register_io_memory(0, eth_read
, eth_write
, eth
);
597 cpu_register_physical_memory (base
, 0x5c, eth
->ethregs
);
599 eth
->vc
= qemu_new_vlan_client(nd
->vlan
,
600 eth_receive
, eth_can_receive
, eth
);