6 void cpu_save(QEMUFile
*f
, void *opaque
)
8 CPUState
*env
= (CPUState
*)opaque
;
11 cpu_synchronize_state(env
, 0);
13 for (i
= 0; i
< 32; i
++)
14 qemu_put_betls(f
, &env
->gpr
[i
]);
15 #if !defined(TARGET_PPC64)
16 for (i
= 0; i
< 32; i
++)
17 qemu_put_betls(f
, &env
->gprh
[i
]);
19 qemu_put_betls(f
, &env
->lr
);
20 qemu_put_betls(f
, &env
->ctr
);
21 for (i
= 0; i
< 8; i
++)
22 qemu_put_be32s(f
, &env
->crf
[i
]);
23 qemu_put_betls(f
, &env
->xer
);
24 qemu_put_betls(f
, &env
->reserve
);
25 qemu_put_betls(f
, &env
->msr
);
26 for (i
= 0; i
< 4; i
++)
27 qemu_put_betls(f
, &env
->tgpr
[i
]);
28 for (i
= 0; i
< 32; i
++) {
34 qemu_put_be64(f
, u
.l
);
36 qemu_put_be32s(f
, &env
->fpscr
);
37 qemu_put_sbe32s(f
, &env
->access_type
);
38 #if !defined(CONFIG_USER_ONLY)
39 #if defined(TARGET_PPC64)
40 qemu_put_betls(f
, &env
->asr
);
41 qemu_put_sbe32s(f
, &env
->slb_nr
);
43 qemu_put_betls(f
, &env
->sdr1
);
44 for (i
= 0; i
< 32; i
++)
45 qemu_put_betls(f
, &env
->sr
[i
]);
46 for (i
= 0; i
< 2; i
++)
47 for (j
= 0; j
< 8; j
++)
48 qemu_put_betls(f
, &env
->DBAT
[i
][j
]);
49 for (i
= 0; i
< 2; i
++)
50 for (j
= 0; j
< 8; j
++)
51 qemu_put_betls(f
, &env
->IBAT
[i
][j
]);
52 qemu_put_sbe32s(f
, &env
->nb_tlb
);
53 qemu_put_sbe32s(f
, &env
->tlb_per_way
);
54 qemu_put_sbe32s(f
, &env
->nb_ways
);
55 qemu_put_sbe32s(f
, &env
->last_way
);
56 qemu_put_sbe32s(f
, &env
->id_tlbs
);
57 qemu_put_sbe32s(f
, &env
->nb_pids
);
60 for (i
= 0; i
< env
->nb_tlb
; i
++) {
61 qemu_put_betls(f
, &env
->tlb
[i
].tlb6
.pte0
);
62 qemu_put_betls(f
, &env
->tlb
[i
].tlb6
.pte1
);
63 qemu_put_betls(f
, &env
->tlb
[i
].tlb6
.EPN
);
66 for (i
= 0; i
< 4; i
++)
67 qemu_put_betls(f
, &env
->pb
[i
]);
69 for (i
= 0; i
< 1024; i
++)
70 qemu_put_betls(f
, &env
->spr
[i
]);
71 qemu_put_be32s(f
, &env
->vscr
);
72 qemu_put_be64s(f
, &env
->spe_acc
);
73 qemu_put_be32s(f
, &env
->spe_fscr
);
74 qemu_put_betls(f
, &env
->msr_mask
);
75 qemu_put_be32s(f
, &env
->flags
);
76 qemu_put_sbe32s(f
, &env
->error_code
);
77 qemu_put_be32s(f
, &env
->pending_interrupts
);
78 #if !defined(CONFIG_USER_ONLY)
79 qemu_put_be32s(f
, &env
->irq_input_state
);
80 for (i
= 0; i
< POWERPC_EXCP_NB
; i
++)
81 qemu_put_betls(f
, &env
->excp_vectors
[i
]);
82 qemu_put_betls(f
, &env
->excp_prefix
);
83 qemu_put_betls(f
, &env
->hreset_excp_prefix
);
84 qemu_put_betls(f
, &env
->ivor_mask
);
85 qemu_put_betls(f
, &env
->ivpr_mask
);
86 qemu_put_betls(f
, &env
->hreset_vector
);
88 qemu_put_betls(f
, &env
->nip
);
89 qemu_put_betls(f
, &env
->hflags
);
90 qemu_put_betls(f
, &env
->hflags_nmsr
);
91 qemu_put_sbe32s(f
, &env
->mmu_idx
);
92 qemu_put_sbe32s(f
, &env
->power_mode
);
95 int cpu_load(QEMUFile
*f
, void *opaque
, int version_id
)
97 CPUState
*env
= (CPUState
*)opaque
;
100 for (i
= 0; i
< 32; i
++)
101 qemu_get_betls(f
, &env
->gpr
[i
]);
102 #if !defined(TARGET_PPC64)
103 for (i
= 0; i
< 32; i
++)
104 qemu_get_betls(f
, &env
->gprh
[i
]);
106 qemu_get_betls(f
, &env
->lr
);
107 qemu_get_betls(f
, &env
->ctr
);
108 for (i
= 0; i
< 8; i
++)
109 qemu_get_be32s(f
, &env
->crf
[i
]);
110 qemu_get_betls(f
, &env
->xer
);
111 qemu_get_betls(f
, &env
->reserve
);
112 qemu_get_betls(f
, &env
->msr
);
113 for (i
= 0; i
< 4; i
++)
114 qemu_get_betls(f
, &env
->tgpr
[i
]);
115 for (i
= 0; i
< 32; i
++) {
120 u
.l
= qemu_get_be64(f
);
123 qemu_get_be32s(f
, &env
->fpscr
);
124 qemu_get_sbe32s(f
, &env
->access_type
);
125 #if !defined(CONFIG_USER_ONLY)
126 #if defined(TARGET_PPC64)
127 qemu_get_betls(f
, &env
->asr
);
128 qemu_get_sbe32s(f
, &env
->slb_nr
);
130 qemu_get_betls(f
, &env
->sdr1
);
131 for (i
= 0; i
< 32; i
++)
132 qemu_get_betls(f
, &env
->sr
[i
]);
133 for (i
= 0; i
< 2; i
++)
134 for (j
= 0; j
< 8; j
++)
135 qemu_get_betls(f
, &env
->DBAT
[i
][j
]);
136 for (i
= 0; i
< 2; i
++)
137 for (j
= 0; j
< 8; j
++)
138 qemu_get_betls(f
, &env
->IBAT
[i
][j
]);
139 qemu_get_sbe32s(f
, &env
->nb_tlb
);
140 qemu_get_sbe32s(f
, &env
->tlb_per_way
);
141 qemu_get_sbe32s(f
, &env
->nb_ways
);
142 qemu_get_sbe32s(f
, &env
->last_way
);
143 qemu_get_sbe32s(f
, &env
->id_tlbs
);
144 qemu_get_sbe32s(f
, &env
->nb_pids
);
147 for (i
= 0; i
< env
->nb_tlb
; i
++) {
148 qemu_get_betls(f
, &env
->tlb
[i
].tlb6
.pte0
);
149 qemu_get_betls(f
, &env
->tlb
[i
].tlb6
.pte1
);
150 qemu_get_betls(f
, &env
->tlb
[i
].tlb6
.EPN
);
153 for (i
= 0; i
< 4; i
++)
154 qemu_get_betls(f
, &env
->pb
[i
]);
156 for (i
= 0; i
< 1024; i
++)
157 qemu_get_betls(f
, &env
->spr
[i
]);
158 qemu_get_be32s(f
, &env
->vscr
);
159 qemu_get_be64s(f
, &env
->spe_acc
);
160 qemu_get_be32s(f
, &env
->spe_fscr
);
161 qemu_get_betls(f
, &env
->msr_mask
);
162 qemu_get_be32s(f
, &env
->flags
);
163 qemu_get_sbe32s(f
, &env
->error_code
);
164 qemu_get_be32s(f
, &env
->pending_interrupts
);
165 #if !defined(CONFIG_USER_ONLY)
166 qemu_get_be32s(f
, &env
->irq_input_state
);
167 for (i
= 0; i
< POWERPC_EXCP_NB
; i
++)
168 qemu_get_betls(f
, &env
->excp_vectors
[i
]);
169 qemu_get_betls(f
, &env
->excp_prefix
);
170 qemu_get_betls(f
, &env
->hreset_excp_prefix
);
171 qemu_get_betls(f
, &env
->ivor_mask
);
172 qemu_get_betls(f
, &env
->ivpr_mask
);
173 qemu_get_betls(f
, &env
->hreset_vector
);
175 qemu_get_betls(f
, &env
->nip
);
176 qemu_get_betls(f
, &env
->hflags
);
177 qemu_get_betls(f
, &env
->hflags_nmsr
);
178 qemu_get_sbe32s(f
, &env
->mmu_idx
);
179 qemu_get_sbe32s(f
, &env
->power_mode
);
181 cpu_synchronize_state(env
, 1);