target-i386/cpu.h

   1 /*
   2  * i386 virtual CPU header
   3  *
   4  *  Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  19  */
  20 #ifndef CPU_I386_H
  21 #define CPU_I386_H
  22
  23 #include "config.h"
  24
  25 #ifdef TARGET_X86_64
  26 #define TARGET_LONG_BITS 64
  27 #else
  28 #define TARGET_LONG_BITS 32
  29 #endif
  30
  31 /* target supports implicit self modifying code */
  32 #define TARGET_HAS_SMC
  33 /* support for self modifying code even if the modified instruction is
  34    close to the modifying instruction */
  35 #define TARGET_HAS_PRECISE_SMC
  36
  37 #define TARGET_HAS_ICE 1
  38
  39 #ifdef TARGET_X86_64
  40 #define ELF_MACHINE     EM_X86_64
  41 #else
  42 #define ELF_MACHINE     EM_386
  43 #endif
  44
  45 #include "cpu-defs.h"
  46
  47 #include "softfloat.h"
  48
  49 #if defined(__i386__) && !defined(CONFIG_SOFTMMU) && !defined(__APPLE__)
  50 #define USE_CODE_COPY
  51 #endif
  52
  53 #define R_EAX 0
  54 #define R_ECX 1
  55 #define R_EDX 2
  56 #define R_EBX 3
  57 #define R_ESP 4
  58 #define R_EBP 5
  59 #define R_ESI 6
  60 #define R_EDI 7
  61
  62 #define R_AL 0
  63 #define R_CL 1
  64 #define R_DL 2
  65 #define R_BL 3
  66 #define R_AH 4
  67 #define R_CH 5
  68 #define R_DH 6
  69 #define R_BH 7
  70
  71 #define R_ES 0
  72 #define R_CS 1
  73 #define R_SS 2
  74 #define R_DS 3
  75 #define R_FS 4
  76 #define R_GS 5
  77
  78 /* segment descriptor fields */
  79 #define DESC_G_MASK     (1 << 23)
  80 #define DESC_B_SHIFT    22
  81 #define DESC_B_MASK     (1 << DESC_B_SHIFT)
  82 #define DESC_L_SHIFT    21 /* x86_64 only : 64 bit code segment */
  83 #define DESC_L_MASK     (1 << DESC_L_SHIFT)
  84 #define DESC_AVL_MASK   (1 << 20)
  85 #define DESC_P_MASK     (1 << 15)
  86 #define DESC_DPL_SHIFT  13
  87 #define DESC_DPL_MASK   (1 << DESC_DPL_SHIFT)
  88 #define DESC_S_MASK     (1 << 12)
  89 #define DESC_TYPE_SHIFT 8
  90 #define DESC_A_MASK     (1 << 8)
  91
  92 #define DESC_CS_MASK    (1 << 11) /* 1=code segment 0=data segment */
  93 #define DESC_C_MASK     (1 << 10) /* code: conforming */
  94 #define DESC_R_MASK     (1 << 9)  /* code: readable */
  95
  96 #define DESC_E_MASK     (1 << 10) /* data: expansion direction */
  97 #define DESC_W_MASK     (1 << 9)  /* data: writable */
  98
  99 #define DESC_TSS_BUSY_MASK (1 << 9)
 100
 101 /* eflags masks */
 102 #define CC_C    0x0001
 103 #define CC_P    0x0004
 104 #define CC_A    0x0010
 105 #define CC_Z    0x0040
 106 #define CC_S    0x0080
 107 #define CC_O    0x0800
 108
 109 #define TF_SHIFT   8
 110 #define IOPL_SHIFT 12
 111 #define VM_SHIFT   17
 112
 113 #define TF_MASK                 0x00000100
 114 #define IF_MASK                 0x00000200
 115 #define DF_MASK                 0x00000400
 116 #define IOPL_MASK               0x00003000
 117 #define NT_MASK                 0x00004000
 118 #define RF_MASK                 0x00010000
 119 #define VM_MASK                 0x00020000
 120 #define AC_MASK                 0x00040000
 121 #define VIF_MASK                0x00080000
 122 #define VIP_MASK                0x00100000
 123 #define ID_MASK                 0x00200000
 124
 125 /* hidden flags - used internally by qemu to represent additional cpu
 126    states. Only the CPL, INHIBIT_IRQ and HALTED are not redundant. We avoid
 127    using the IOPL_MASK, TF_MASK and VM_MASK bit position to ease oring
 128    with eflags. */
 129 /* current cpl */
 130 #define HF_CPL_SHIFT         0
 131 /* true if soft mmu is being used */
 132 #define HF_SOFTMMU_SHIFT     2
 133 /* true if hardware interrupts must be disabled for next instruction */
 134 #define HF_INHIBIT_IRQ_SHIFT 3
 135 /* 16 or 32 segments */
 136 #define HF_CS32_SHIFT        4
 137 #define HF_SS32_SHIFT        5
 138 /* zero base for DS, ES and SS : can be '0' only in 32 bit CS segment */
 139 #define HF_ADDSEG_SHIFT      6
 140 /* copy of CR0.PE (protected mode) */
 141 #define HF_PE_SHIFT          7
 142 #define HF_TF_SHIFT          8 /* must be same as eflags */
 143 #define HF_MP_SHIFT          9 /* the order must be MP, EM, TS */
 144 #define HF_EM_SHIFT         10
 145 #define HF_TS_SHIFT         11
 146 #define HF_IOPL_SHIFT       12 /* must be same as eflags */
 147 #define HF_LMA_SHIFT        14 /* only used on x86_64: long mode active */
 148 #define HF_CS64_SHIFT       15 /* only used on x86_64: 64 bit code segment  */
 149 #define HF_OSFXSR_SHIFT     16 /* CR4.OSFXSR */
 150 #define HF_VM_SHIFT         17 /* must be same as eflags */
 151 #define HF_HALTED_SHIFT     18 /* CPU halted */
 152 #define HF_SMM_SHIFT        19 /* CPU in SMM mode */
 153 #define HF_GIF_SHIFT        20 /* if set CPU takes interrupts */
 154 #define HF_HIF_SHIFT        21 /* shadow copy of IF_MASK when in SVM */
 155
 156 #define HF_CPL_MASK          (3 << HF_CPL_SHIFT)
 157 #define HF_SOFTMMU_MASK      (1 << HF_SOFTMMU_SHIFT)
 158 #define HF_INHIBIT_IRQ_MASK  (1 << HF_INHIBIT_IRQ_SHIFT)
 159 #define HF_CS32_MASK         (1 << HF_CS32_SHIFT)
 160 #define HF_SS32_MASK         (1 << HF_SS32_SHIFT)
 161 #define HF_ADDSEG_MASK       (1 << HF_ADDSEG_SHIFT)
 162 #define HF_PE_MASK           (1 << HF_PE_SHIFT)
 163 #define HF_TF_MASK           (1 << HF_TF_SHIFT)
 164 #define HF_MP_MASK           (1 << HF_MP_SHIFT)
 165 #define HF_EM_MASK           (1 << HF_EM_SHIFT)
 166 #define HF_TS_MASK           (1 << HF_TS_SHIFT)
 167 #define HF_IOPL_MASK         (3 << HF_IOPL_SHIFT)
 168 #define HF_LMA_MASK          (1 << HF_LMA_SHIFT)
 169 #define HF_CS64_MASK         (1 << HF_CS64_SHIFT)
 170 #define HF_OSFXSR_MASK       (1 << HF_OSFXSR_SHIFT)
 171 #define HF_VM_MASK           (1 << HF_VM_SHIFT)
 172 #define HF_HALTED_MASK       (1 << HF_HALTED_SHIFT)
 173 #define HF_SMM_MASK          (1 << HF_SMM_SHIFT)
 174 #define HF_GIF_MASK          (1 << HF_GIF_SHIFT)
 175 #define HF_HIF_MASK          (1 << HF_HIF_SHIFT)
 176
 177 #define CR0_PE_SHIFT 0
 178 #define CR0_MP_SHIFT 1
 179
 180 #define CR0_PE_MASK  (1 << 0)
 181 #define CR0_MP_MASK  (1 << 1)
 182 #define CR0_EM_MASK  (1 << 2)
 183 #define CR0_TS_MASK  (1 << 3)
 184 #define CR0_ET_MASK  (1 << 4)
 185 #define CR0_NE_MASK  (1 << 5)
 186 #define CR0_WP_MASK  (1 << 16)
 187 #define CR0_AM_MASK  (1 << 18)
 188 #define CR0_PG_MASK  (1 << 31)
 189
 190 #define CR4_VME_MASK  (1 << 0)
 191 #define CR4_PVI_MASK  (1 << 1)
 192 #define CR4_TSD_MASK  (1 << 2)
 193 #define CR4_DE_MASK   (1 << 3)
 194 #define CR4_PSE_MASK  (1 << 4)
 195 #define CR4_PAE_MASK  (1 << 5)
 196 #define CR4_PGE_MASK  (1 << 7)
 197 #define CR4_PCE_MASK  (1 << 8)
 198 #define CR4_OSFXSR_SHIFT 9
 199 #define CR4_OSFXSR_MASK (1 << CR4_OSFXSR_SHIFT)
 200 #define CR4_OSXMMEXCPT_MASK  (1 << 10)
 201
 202 #define PG_PRESENT_BIT  0
 203 #define PG_RW_BIT       1
 204 #define PG_USER_BIT     2
 205 #define PG_PWT_BIT      3
 206 #define PG_PCD_BIT      4
 207 #define PG_ACCESSED_BIT 5
 208 #define PG_DIRTY_BIT    6
 209 #define PG_PSE_BIT      7
 210 #define PG_GLOBAL_BIT   8
 211 #define PG_NX_BIT       63
 212
 213 #define PG_PRESENT_MASK  (1 << PG_PRESENT_BIT)
 214 #define PG_RW_MASK       (1 << PG_RW_BIT)
 215 #define PG_USER_MASK     (1 << PG_USER_BIT)
 216 #define PG_PWT_MASK      (1 << PG_PWT_BIT)
 217 #define PG_PCD_MASK      (1 << PG_PCD_BIT)
 218 #define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT)
 219 #define PG_DIRTY_MASK    (1 << PG_DIRTY_BIT)
 220 #define PG_PSE_MASK      (1 << PG_PSE_BIT)
 221 #define PG_GLOBAL_MASK   (1 << PG_GLOBAL_BIT)
 222 #define PG_NX_MASK       (1LL << PG_NX_BIT)
 223
 224 #define PG_ERROR_W_BIT     1
 225
 226 #define PG_ERROR_P_MASK    0x01
 227 #define PG_ERROR_W_MASK    (1 << PG_ERROR_W_BIT)
 228 #define PG_ERROR_U_MASK    0x04
 229 #define PG_ERROR_RSVD_MASK 0x08
 230 #define PG_ERROR_I_D_MASK  0x10
 231
 232 #define MSR_IA32_APICBASE               0x1b
 233 #define MSR_IA32_APICBASE_BSP           (1<<8)
 234 #define MSR_IA32_APICBASE_ENABLE        (1<<11)
 235 #define MSR_IA32_APICBASE_BASE          (0xfffff<<12)
 236
 237 #define MSR_IA32_SYSENTER_CS            0x174
 238 #define MSR_IA32_SYSENTER_ESP           0x175
 239 #define MSR_IA32_SYSENTER_EIP           0x176
 240
 241 #define MSR_MCG_CAP                     0x179
 242 #define MSR_MCG_STATUS                  0x17a
 243 #define MSR_MCG_CTL                     0x17b
 244
 245 #define MSR_PAT                         0x277
 246
 247 #define MSR_EFER                        0xc0000080
 248
 249 #define MSR_EFER_SCE   (1 << 0)
 250 #define MSR_EFER_LME   (1 << 8)
 251 #define MSR_EFER_LMA   (1 << 10)
 252 #define MSR_EFER_NXE   (1 << 11)
 253 #define MSR_EFER_FFXSR (1 << 14)
 254
 255 #define MSR_STAR                        0xc0000081
 256 #define MSR_LSTAR                       0xc0000082
 257 #define MSR_CSTAR                       0xc0000083
 258 #define MSR_FMASK                       0xc0000084
 259 #define MSR_FSBASE                      0xc0000100
 260 #define MSR_GSBASE                      0xc0000101
 261 #define MSR_KERNELGSBASE                0xc0000102
 262
 263 #define MSR_VM_HSAVE_PA                 0xc0010117
 264
 265 /* cpuid_features bits */
 266 #define CPUID_FP87 (1 << 0)
 267 #define CPUID_VME  (1 << 1)
 268 #define CPUID_DE   (1 << 2)
 269 #define CPUID_PSE  (1 << 3)
 270 #define CPUID_TSC  (1 << 4)
 271 #define CPUID_MSR  (1 << 5)
 272 #define CPUID_PAE  (1 << 6)
 273 #define CPUID_MCE  (1 << 7)
 274 #define CPUID_CX8  (1 << 8)
 275 #define CPUID_APIC (1 << 9)
 276 #define CPUID_SEP  (1 << 11) /* sysenter/sysexit */
 277 #define CPUID_MTRR (1 << 12)
 278 #define CPUID_PGE  (1 << 13)
 279 #define CPUID_MCA  (1 << 14)
 280 #define CPUID_CMOV (1 << 15)
 281 #define CPUID_PAT  (1 << 16)
 282 #define CPUID_PSE36   (1 << 17)
 283 #define CPUID_CLFLUSH (1 << 19)
 284 /* ... */
 285 #define CPUID_MMX  (1 << 23)
 286 #define CPUID_FXSR (1 << 24)
 287 #define CPUID_SSE  (1 << 25)
 288 #define CPUID_SSE2 (1 << 26)
 289
 290 #define CPUID_EXT_SSE3     (1 << 0)
 291 #define CPUID_EXT_MONITOR  (1 << 3)
 292 #define CPUID_EXT_CX16     (1 << 13)
 293
 294 #define CPUID_EXT2_SYSCALL (1 << 11)
 295 #define CPUID_EXT2_NX      (1 << 20)
 296 #define CPUID_EXT2_FFXSR   (1 << 25)
 297 #define CPUID_EXT2_LM      (1 << 29)
 298
 299 #define CPUID_EXT3_SVM     (1 << 2)
 300
 301 #define EXCP00_DIVZ     0
 302 #define EXCP01_SSTP     1
 303 #define EXCP02_NMI      2
 304 #define EXCP03_INT3     3
 305 #define EXCP04_INTO     4
 306 #define EXCP05_BOUND    5
 307 #define EXCP06_ILLOP    6
 308 #define EXCP07_PREX     7
 309 #define EXCP08_DBLE     8
 310 #define EXCP09_XERR     9
 311 #define EXCP0A_TSS      10
 312 #define EXCP0B_NOSEG    11
 313 #define EXCP0C_STACK    12
 314 #define EXCP0D_GPF      13
 315 #define EXCP0E_PAGE     14
 316 #define EXCP10_COPR     16
 317 #define EXCP11_ALGN     17
 318 #define EXCP12_MCHK     18
 319
 320 enum {
 321     CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */
 322     CC_OP_EFLAGS,  /* all cc are explicitely computed, CC_SRC = flags */
 323
 324     CC_OP_MULB, /* modify all flags, C, O = (CC_SRC != 0) */
 325     CC_OP_MULW,
 326     CC_OP_MULL,
 327     CC_OP_MULQ,
 328
 329     CC_OP_ADDB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
 330     CC_OP_ADDW,
 331     CC_OP_ADDL,
 332     CC_OP_ADDQ,
 333
 334     CC_OP_ADCB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
 335     CC_OP_ADCW,
 336     CC_OP_ADCL,
 337     CC_OP_ADCQ,
 338
 339     CC_OP_SUBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
 340     CC_OP_SUBW,
 341     CC_OP_SUBL,
 342     CC_OP_SUBQ,
 343
 344     CC_OP_SBBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
 345     CC_OP_SBBW,
 346     CC_OP_SBBL,
 347     CC_OP_SBBQ,
 348
 349     CC_OP_LOGICB, /* modify all flags, CC_DST = res */
 350     CC_OP_LOGICW,
 351     CC_OP_LOGICL,
 352     CC_OP_LOGICQ,
 353
 354     CC_OP_INCB, /* modify all flags except, CC_DST = res, CC_SRC = C */
 355     CC_OP_INCW,
 356     CC_OP_INCL,
 357     CC_OP_INCQ,
 358
 359     CC_OP_DECB, /* modify all flags except, CC_DST = res, CC_SRC = C  */
 360     CC_OP_DECW,
 361     CC_OP_DECL,
 362     CC_OP_DECQ,
 363
 364     CC_OP_SHLB, /* modify all flags, CC_DST = res, CC_SRC.msb = C */
 365     CC_OP_SHLW,
 366     CC_OP_SHLL,
 367     CC_OP_SHLQ,
 368
 369     CC_OP_SARB, /* modify all flags, CC_DST = res, CC_SRC.lsb = C */
 370     CC_OP_SARW,
 371     CC_OP_SARL,
 372     CC_OP_SARQ,
 373
 374     CC_OP_NB,
 375 };
 376
 377 #ifdef FLOATX80
 378 #define USE_X86LDOUBLE
 379 #endif
 380
 381 #ifdef USE_X86LDOUBLE
 382 typedef floatx80 CPU86_LDouble;
 383 #else
 384 typedef float64 CPU86_LDouble;
 385 #endif
 386
 387 typedef struct SegmentCache {
 388     uint32_t selector;
 389     target_ulong base;
 390     uint32_t limit;
 391     uint32_t flags;
 392 } SegmentCache;
 393
 394 typedef union {
 395     uint8_t _b[16];
 396     uint16_t _w[8];
 397     uint32_t _l[4];
 398     uint64_t _q[2];
 399     float32 _s[4];
 400     float64 _d[2];
 401 } XMMReg;
 402
 403 typedef union {
 404     uint8_t _b[8];
 405     uint16_t _w[2];
 406     uint32_t _l[1];
 407     uint64_t q;
 408 } MMXReg;
 409
 410 #ifdef WORDS_BIGENDIAN
 411 #define XMM_B(n) _b[15 - (n)]
 412 #define XMM_W(n) _w[7 - (n)]
 413 #define XMM_L(n) _l[3 - (n)]
 414 #define XMM_S(n) _s[3 - (n)]
 415 #define XMM_Q(n) _q[1 - (n)]
 416 #define XMM_D(n) _d[1 - (n)]
 417
 418 #define MMX_B(n) _b[7 - (n)]
 419 #define MMX_W(n) _w[3 - (n)]
 420 #define MMX_L(n) _l[1 - (n)]
 421 #else
 422 #define XMM_B(n) _b[n]
 423 #define XMM_W(n) _w[n]
 424 #define XMM_L(n) _l[n]
 425 #define XMM_S(n) _s[n]
 426 #define XMM_Q(n) _q[n]
 427 #define XMM_D(n) _d[n]
 428
 429 #define MMX_B(n) _b[n]
 430 #define MMX_W(n) _w[n]
 431 #define MMX_L(n) _l[n]
 432 #endif
 433 #define MMX_Q(n) q
 434
 435 #ifdef TARGET_X86_64
 436 #define CPU_NB_REGS 16
 437 #else
 438 #define CPU_NB_REGS 8
 439 #endif
 440
 441 typedef struct CPUX86State {
 442 #if TARGET_LONG_BITS > HOST_LONG_BITS
 443     /* temporaries if we cannot store them in host registers */
 444     target_ulong t0, t1, t2;
 445 #endif
 446
 447     /* standard registers */
 448     target_ulong regs[CPU_NB_REGS];
 449     target_ulong eip;
 450     target_ulong eflags; /* eflags register. During CPU emulation, CC
 451                         flags and DF are set to zero because they are
 452                         stored elsewhere */
 453
 454     /* emulator internal eflags handling */
 455     target_ulong cc_src;
 456     target_ulong cc_dst;
 457     uint32_t cc_op;
 458     int32_t df; /* D flag : 1 if D = 0, -1 if D = 1 */
 459     uint32_t hflags; /* hidden flags, see HF_xxx constants */
 460
 461     /* segments */
 462     SegmentCache segs[6]; /* selector values */
 463     SegmentCache ldt;
 464     SegmentCache tr;
 465     SegmentCache gdt; /* only base and limit are used */
 466     SegmentCache idt; /* only base and limit are used */
 467
 468     target_ulong cr[5]; /* NOTE: cr1 is unused */
 469     uint32_t a20_mask;
 470
 471     /* FPU state */
 472     unsigned int fpstt; /* top of stack index */
 473     unsigned int fpus;
 474     unsigned int fpuc;
 475     uint8_t fptags[8];   /* 0 = valid, 1 = empty */
 476     union {
 477 #ifdef USE_X86LDOUBLE
 478         CPU86_LDouble d __attribute__((aligned(16)));
 479 #else
 480         CPU86_LDouble d;
 481 #endif
 482         MMXReg mmx;
 483     } fpregs[8];
 484
 485     /* emulator internal variables */
 486     float_status fp_status;
 487     CPU86_LDouble ft0;
 488     union {
 489         float f;
 490         double d;
 491         int i32;
 492         int64_t i64;
 493     } fp_convert;
 494
 495     float_status sse_status;
 496     uint32_t mxcsr;
 497     XMMReg xmm_regs[CPU_NB_REGS];
 498     XMMReg xmm_t0;
 499     MMXReg mmx_t0;
 500
 501     /* sysenter registers */
 502     uint32_t sysenter_cs;
 503     uint32_t sysenter_esp;
 504     uint32_t sysenter_eip;
 505     uint64_t efer;
 506     uint64_t star;
 507
 508     target_phys_addr_t vm_hsave;
 509     target_phys_addr_t vm_vmcb;
 510     uint64_t intercept;
 511     uint16_t intercept_cr_read;
 512     uint16_t intercept_cr_write;
 513     uint16_t intercept_dr_read;
 514     uint16_t intercept_dr_write;
 515     uint32_t intercept_exceptions;
 516
 517 #ifdef TARGET_X86_64
 518     target_ulong lstar;
 519     target_ulong cstar;
 520     target_ulong fmask;
 521     target_ulong kernelgsbase;
 522 #endif
 523
 524 #ifdef USE_KVM
 525     uint64_t tsc; /* time stamp counter */
 526     uint8_t ready_for_interrupt_injection;
 527 #endif
 528     uint64_t pat;
 529
 530     /* temporary data for USE_CODE_COPY mode */
 531 #ifdef USE_CODE_COPY
 532     uint32_t tmp0;
 533     uint32_t saved_esp;
 534     int native_fp_regs; /* if true, the FPU state is in the native CPU regs */
 535 #endif
 536
 537     /* exception/interrupt handling */
 538     jmp_buf jmp_env;
 539     int exception_index;
 540     int error_code;
 541     int exception_is_int;
 542     target_ulong exception_next_eip;
 543     target_ulong dr[8]; /* debug registers */
 544     uint32_t smbase;
 545     int interrupt_request;
 546     int user_mode_only; /* user mode only simulation */
 547     int old_exception;  /* exception in flight */
 548
 549     CPU_COMMON
 550
 551     /* processor features (e.g. for CPUID insn) */
 552     uint32_t cpuid_level;
 553     uint32_t cpuid_vendor1;
 554     uint32_t cpuid_vendor2;
 555     uint32_t cpuid_vendor3;
 556     uint32_t cpuid_version;
 557     uint32_t cpuid_features;
 558     uint32_t cpuid_ext_features;
 559     uint32_t cpuid_xlevel;
 560     uint32_t cpuid_model[12];
 561     uint32_t cpuid_ext2_features;
 562     uint32_t cpuid_ext3_features;
 563     uint32_t cpuid_apic_id;
 564
 565 #ifdef USE_KQEMU
 566     int kqemu_enabled;
 567     int last_io_time;
 568 #endif
 569
 570 #ifdef USE_KVM
 571 #define BITS_PER_LONG (8 * sizeof (uint32_t))
 572 #define NR_IRQ_WORDS (256/ BITS_PER_LONG)
 573     uint32_t kvm_interrupt_bitmap[NR_IRQ_WORDS];
 574 #endif
 575
 576     /* in order to simplify APIC support, we leave this pointer to the
 577        user */
 578     struct APICState *apic_state;
 579 } CPUX86State;
 580
 581 CPUX86State *cpu_x86_init(void);
 582 int cpu_x86_exec(CPUX86State *s);
 583 void cpu_x86_close(CPUX86State *s);
 584 int cpu_get_pic_interrupt(CPUX86State *s);
 585 /* MSDOS compatibility mode FPU exception support */
 586 void cpu_set_ferr(CPUX86State *s);
 587
 588 /* this function must always be used to load data in the segment
 589    cache: it synchronizes the hflags with the segment cache values */
 590 static inline void cpu_x86_load_seg_cache(CPUX86State *env,
 591                                           int seg_reg, unsigned int selector,
 592                                           target_ulong base,
 593                                           unsigned int limit,
 594                                           unsigned int flags)
 595 {
 596     SegmentCache *sc;
 597     unsigned int new_hflags;
 598
 599     sc = &env->segs[seg_reg];
 600     sc->selector = selector;
 601     sc->base = base;
 602     sc->limit = limit;
 603     sc->flags = flags;
 604
 605     /* update the hidden flags */
 606     {
 607         if (seg_reg == R_CS) {
 608 #ifdef TARGET_X86_64
 609             if ((env->hflags & HF_LMA_MASK) && (flags & DESC_L_MASK)) {
 610                 /* long mode */
 611                 env->hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
 612                 env->hflags &= ~(HF_ADDSEG_MASK);
 613             } else
 614 #endif
 615             {
 616                 /* legacy / compatibility case */
 617                 new_hflags = (env->segs[R_CS].flags & DESC_B_MASK)
 618                     >> (DESC_B_SHIFT - HF_CS32_SHIFT);
 619                 env->hflags = (env->hflags & ~(HF_CS32_MASK | HF_CS64_MASK)) |
 620                     new_hflags;
 621             }
 622         }
 623         new_hflags = (env->segs[R_SS].flags & DESC_B_MASK)
 624             >> (DESC_B_SHIFT - HF_SS32_SHIFT);
 625         if (env->hflags & HF_CS64_MASK) {
 626             /* zero base assumed for DS, ES and SS in long mode */
 627         } else if (!(env->cr[0] & CR0_PE_MASK) ||
 628                    (env->eflags & VM_MASK) ||
 629                    !(env->hflags & HF_CS32_MASK)) {
 630             /* XXX: try to avoid this test. The problem comes from the
 631                fact that is real mode or vm86 mode we only modify the
 632                'base' and 'selector' fields of the segment cache to go
 633                faster. A solution may be to force addseg to one in
 634                translate-i386.c. */
 635             new_hflags |= HF_ADDSEG_MASK;
 636         } else {
 637             new_hflags |= ((env->segs[R_DS].base |
 638                             env->segs[R_ES].base |
 639                             env->segs[R_SS].base) != 0) <<
 640                 HF_ADDSEG_SHIFT;
 641         }
 642         env->hflags = (env->hflags &
 643                        ~(HF_SS32_MASK | HF_ADDSEG_MASK)) | new_hflags;
 644     }
 645 }
 646
 647 /* wrapper, just in case memory mappings must be changed */
 648 static inline void cpu_x86_set_cpl(CPUX86State *s, int cpl)
 649 {
 650 #if HF_CPL_MASK == 3
 651     s->hflags = (s->hflags & ~HF_CPL_MASK) | cpl;
 652 #else
 653 #error HF_CPL_MASK is hardcoded
 654 #endif
 655 }
 656
 657 /* used for debug or cpu save/restore */
 658 void cpu_get_fp80(uint64_t *pmant, uint16_t *pexp, CPU86_LDouble f);
 659 CPU86_LDouble cpu_set_fp80(uint64_t mant, uint16_t upper);
 660
 661 /* the following helpers are only usable in user mode simulation as
 662    they can trigger unexpected exceptions */
 663 void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector);
 664 void cpu_x86_fsave(CPUX86State *s, uint8_t *ptr, int data32);
 665 void cpu_x86_frstor(CPUX86State *s, uint8_t *ptr, int data32);
 666
 667 /* you can call this signal handler from your SIGBUS and SIGSEGV
 668    signal handlers to inform the virtual CPU of exceptions. non zero
 669    is returned if the signal was handled by the virtual CPU.  */
 670 int cpu_x86_signal_handler(int host_signum, void *pinfo,
 671                            void *puc);
 672 void cpu_x86_set_a20(CPUX86State *env, int a20_state);
 673
 674 uint64_t cpu_get_tsc(CPUX86State *env);
 675
 676 void cpu_set_apic_base(CPUX86State *env, uint64_t val);
 677 uint64_t cpu_get_apic_base(CPUX86State *env);
 678 void cpu_set_apic_tpr(CPUX86State *env, uint8_t val);
 679 #ifndef NO_CPU_IO_DEFS
 680 uint8_t cpu_get_apic_tpr(CPUX86State *env);
 681 #endif
 682 void cpu_smm_update(CPUX86State *env);
 683
 684 /* will be suppressed */
 685 void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0);
 686
 687 /* used to debug */
 688 #define X86_DUMP_FPU  0x0001 /* dump FPU state too */
 689 #define X86_DUMP_CCOP 0x0002 /* dump qemu flag cache */
 690
 691 #ifdef USE_KQEMU
 692 static inline int cpu_get_time_fast(void)
 693 {
 694     int low, high;
 695     asm volatile("rdtsc" : "=a" (low), "=d" (high));
 696     return low;
 697 }
 698 #endif
 699
 700 #define TARGET_PAGE_BITS 12
 701
 702 #define CPUState CPUX86State
 703 #define cpu_init cpu_x86_init
 704 #define cpu_exec cpu_x86_exec
 705 #define cpu_gen_code cpu_x86_gen_code
 706 #define cpu_signal_handler cpu_x86_signal_handler
 707
 708 #include "cpu-all.h"
 709
 710 #include "svm.h"
 711
 712 #endif /* CPU_I386_H */