hw/i8259.c

   1 /*
   2  * QEMU 8259 interrupt controller emulation
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "vl.h"
  25
  26 /* debug PIC */
  27 //#define DEBUG_PIC
  28
  29 //#define DEBUG_IRQ_LATENCY
  30 //#define DEBUG_IRQ_COUNT
  31
  32 typedef struct PicState {
  33     uint8_t last_irr; /* edge detection */
  34     uint8_t irr; /* interrupt request register */
  35     uint8_t imr; /* interrupt mask register */
  36     uint8_t isr; /* interrupt service register */
  37     uint8_t priority_add; /* highest irq priority */
  38     uint8_t irq_base;
  39     uint8_t read_reg_select;
  40     uint8_t poll;
  41     uint8_t special_mask;
  42     uint8_t init_state;
  43     uint8_t auto_eoi;
  44     uint8_t rotate_on_auto_eoi;
  45     uint8_t special_fully_nested_mode;
  46     uint8_t init4; /* true if 4 byte init */
  47     uint8_t single_mode; /* true if slave pic is not initialized */
  48     uint8_t elcr; /* PIIX edge/trigger selection*/
  49     uint8_t elcr_mask;
  50     PicState2 *pics_state;
  51 } PicState;
  52
  53 struct PicState2 {
  54     /* 0 is master pic, 1 is slave pic */
  55     /* XXX: better separation between the two pics */
  56     PicState pics[2];
  57     qemu_irq parent_irq;
  58     void *irq_request_opaque;
  59     /* IOAPIC callback support */
  60     SetIRQFunc *alt_irq_func;
  61     void *alt_irq_opaque;
  62 };
  63
  64 #if defined(DEBUG_PIC) || defined (DEBUG_IRQ_COUNT)
  65 static int irq_level[16];
  66 #endif
  67 #ifdef DEBUG_IRQ_COUNT
  68 static uint64_t irq_count[16];
  69 #endif
  70
  71 /* set irq level. If an edge is detected, then the IRR is set to 1 */
  72 static inline void pic_set_irq1(PicState *s, int irq, int level)
  73 {
  74     int mask;
  75     mask = 1 << irq;
  76     if (s->elcr & mask) {
  77         /* level triggered */
  78         if (level) {
  79             s->irr |= mask;
  80             s->last_irr |= mask;
  81         } else {
  82             s->irr &= ~mask;
  83             s->last_irr &= ~mask;
  84         }
  85     } else {
  86         /* edge triggered */
  87         if (level) {
  88             if ((s->last_irr & mask) == 0)
  89                 s->irr |= mask;
  90             s->last_irr |= mask;
  91         } else {
  92             s->last_irr &= ~mask;
  93         }
  94     }
  95 }
  96
  97 /* return the highest priority found in mask (highest = smallest
  98    number). Return 8 if no irq */
  99 static inline int get_priority(PicState *s, int mask)
 100 {
 101     int priority;
 102     if (mask == 0)
 103         return 8;
 104     priority = 0;
 105     while ((mask & (1 << ((priority + s->priority_add) & 7))) == 0)
 106         priority++;
 107     return priority;
 108 }
 109
 110 /* return the pic wanted interrupt. return -1 if none */
 111 static int pic_get_irq(PicState *s)
 112 {
 113     int mask, cur_priority, priority;
 114
 115     mask = s->irr & ~s->imr;
 116     priority = get_priority(s, mask);
 117     if (priority == 8)
 118         return -1;
 119     /* compute current priority. If special fully nested mode on the
 120        master, the IRQ coming from the slave is not taken into account
 121        for the priority computation. */
 122     mask = s->isr;
 123     if (s->special_fully_nested_mode && s == &s->pics_state->pics[0])
 124         mask &= ~(1 << 2);
 125     cur_priority = get_priority(s, mask);
 126     if (priority < cur_priority) {
 127         /* higher priority found: an irq should be generated */
 128         return (priority + s->priority_add) & 7;
 129     } else {
 130         return -1;
 131     }
 132 }
 133
 134 /* raise irq to CPU if necessary. must be called every time the active
 135    irq may change */
 136 /* XXX: should not export it, but it is needed for an APIC kludge */
 137 void pic_update_irq(PicState2 *s)
 138 {
 139     int irq2, irq;
 140
 141     /* first look at slave pic */
 142     irq2 = pic_get_irq(&s->pics[1]);
 143     if (irq2 >= 0) {
 144         /* if irq request by slave pic, signal master PIC */
 145         pic_set_irq1(&s->pics[0], 2, 1);
 146         pic_set_irq1(&s->pics[0], 2, 0);
 147     }
 148     /* look at requested irq */
 149     irq = pic_get_irq(&s->pics[0]);
 150     if (irq >= 0) {
 151 #if defined(DEBUG_PIC)
 152         {
 153             int i;
 154             for(i = 0; i < 2; i++) {
 155                 printf("pic%d: imr=%x irr=%x padd=%d\n",
 156                        i, s->pics[i].imr, s->pics[i].irr,
 157                        s->pics[i].priority_add);
 158
 159             }
 160         }
 161         printf("pic: cpu_interrupt\n");
 162 #endif
 163         qemu_irq_raise(s->parent_irq);
 164     }
 165
 166 /* all targets should do this rather than acking the IRQ in the cpu */
 167 #if defined(TARGET_MIPS)
 168     else {
 169         qemu_irq_lower(s->parent_irq);
 170     }
 171 #endif
 172 }
 173
 174 #ifdef DEBUG_IRQ_LATENCY
 175 int64_t irq_time[16];
 176 #endif
 177
 178 void i8259_set_irq(void *opaque, int irq, int level)
 179 {
 180     PicState2 *s = opaque;
 181 #ifdef USE_KVM
 182     extern int kvm_set_irq(int irq, int level);
 183
 184     if (kvm_allowed)
 185         if (kvm_set_irq(irq, level))
 186             return;
 187 #endif
 188 #if defined(DEBUG_PIC) || defined(DEBUG_IRQ_COUNT)
 189     if (level != irq_level[irq]) {
 190 #if defined(DEBUG_PIC)
 191         printf("i8259_set_irq: irq=%d level=%d\n", irq, level);
 192 #endif
 193         irq_level[irq] = level;
 194 #ifdef DEBUG_IRQ_COUNT
 195         if (level == 1)
 196             irq_count[irq]++;
 197 #endif
 198     }
 199 #endif
 200 #ifdef DEBUG_IRQ_LATENCY
 201     if (level) {
 202         irq_time[irq] = qemu_get_clock(vm_clock);
 203     }
 204 #endif
 205     pic_set_irq1(&s->pics[irq >> 3], irq & 7, level);
 206     /* used for IOAPIC irqs */
 207     if (s->alt_irq_func)
 208         s->alt_irq_func(s->alt_irq_opaque, irq, level);
 209     pic_update_irq(s);
 210 }
 211
 212 /* acknowledge interrupt 'irq' */
 213 static inline void pic_intack(PicState *s, int irq)
 214 {
 215     if (s->auto_eoi) {
 216         if (s->rotate_on_auto_eoi)
 217             s->priority_add = (irq + 1) & 7;
 218     } else {
 219         s->isr |= (1 << irq);
 220     }
 221
 222     /* We don't clear a level sensitive interrupt here */
 223     if (!(s->elcr & (1 << irq)))
 224         s->irr &= ~(1 << irq);
 225
 226 }
 227
 228 int pic_read_irq(PicState2 *s)
 229 {
 230     int irq, irq2, intno;
 231
 232     irq = pic_get_irq(&s->pics[0]);
 233     if (irq >= 0) {
 234
 235         if (time_drift_fix && irq == 0) {
 236             extern int64_t timer_acks, timer_ints_to_push;
 237             timer_acks++;
 238             if (timer_ints_to_push > 0) {
 239                 timer_ints_to_push--;
 240                 qemu_irq_lower(s->parent_irq);
 241                 qemu_irq_raise(s->parent_irq);
 242             }
 243         }
 244
 245         pic_intack(&s->pics[0], irq);
 246         if (irq == 2) {
 247             irq2 = pic_get_irq(&s->pics[1]);
 248             if (irq2 >= 0) {
 249                 pic_intack(&s->pics[1], irq2);
 250             } else {
 251                 /* spurious IRQ on slave controller */
 252                 irq2 = 7;
 253             }
 254             intno = s->pics[1].irq_base + irq2;
 255             irq = irq2 + 8;
 256         } else {
 257             intno = s->pics[0].irq_base + irq;
 258         }
 259     } else {
 260         /* spurious IRQ on host controller */
 261         irq = 7;
 262         intno = s->pics[0].irq_base + irq;
 263     }
 264     pic_update_irq(s);
 265
 266 #ifdef DEBUG_IRQ_LATENCY
 267     printf("IRQ%d latency=%0.3fus\n",
 268            irq,
 269            (double)(qemu_get_clock(vm_clock) - irq_time[irq]) * 1000000.0 / ticks_per_sec);
 270 #endif
 271 #if defined(DEBUG_PIC)
 272     printf("pic_interrupt: irq=%d\n", irq);
 273 #endif
 274     return intno;
 275 }
 276
 277 static void pic_reset(void *opaque)
 278 {
 279     PicState *s = opaque;
 280
 281     s->last_irr = 0;
 282     s->irr = 0;
 283     s->imr = 0;
 284     s->isr = 0;
 285     s->priority_add = 0;
 286     s->irq_base = 0;
 287     s->read_reg_select = 0;
 288     s->poll = 0;
 289     s->special_mask = 0;
 290     s->init_state = 0;
 291     s->auto_eoi = 0;
 292     s->rotate_on_auto_eoi = 0;
 293     s->special_fully_nested_mode = 0;
 294     s->init4 = 0;
 295     s->single_mode = 0;
 296     /* Note: ELCR is not reset */
 297 }
 298
 299 static void pic_ioport_write(void *opaque, uint32_t addr, uint32_t val)
 300 {
 301     PicState *s = opaque;
 302     int priority, cmd, irq;
 303
 304 #ifdef DEBUG_PIC
 305     printf("pic_write: addr=0x%02x val=0x%02x\n", addr, val);
 306 #endif
 307     addr &= 1;
 308     if (addr == 0) {
 309         if (val & 0x10) {
 310             /* init */
 311             pic_reset(s);
 312             /* deassert a pending interrupt */
 313             qemu_irq_lower(s->pics_state->parent_irq);
 314             s->init_state = 1;
 315             s->init4 = val & 1;
 316             s->single_mode = val & 2;
 317             if (val & 0x08)
 318                 hw_error("level sensitive irq not supported");
 319         } else if (val & 0x08) {
 320             if (val & 0x04)
 321                 s->poll = 1;
 322             if (val & 0x02)
 323                 s->read_reg_select = val & 1;
 324             if (val & 0x40)
 325                 s->special_mask = (val >> 5) & 1;
 326         } else {
 327             cmd = val >> 5;
 328             switch(cmd) {
 329             case 0:
 330             case 4:
 331                 s->rotate_on_auto_eoi = cmd >> 2;
 332                 break;
 333             case 1: /* end of interrupt */
 334             case 5:
 335                 priority = get_priority(s, s->isr);
 336                 if (priority != 8) {
 337                     irq = (priority + s->priority_add) & 7;
 338                     s->isr &= ~(1 << irq);
 339                     if (cmd == 5)
 340                         s->priority_add = (irq + 1) & 7;
 341                     pic_update_irq(s->pics_state);
 342                 }
 343                 break;
 344             case 3:
 345                 irq = val & 7;
 346                 s->isr &= ~(1 << irq);
 347                 pic_update_irq(s->pics_state);
 348                 break;
 349             case 6:
 350                 s->priority_add = (val + 1) & 7;
 351                 pic_update_irq(s->pics_state);
 352                 break;
 353             case 7:
 354                 irq = val & 7;
 355                 s->isr &= ~(1 << irq);
 356                 s->priority_add = (irq + 1) & 7;
 357                 pic_update_irq(s->pics_state);
 358                 break;
 359             default:
 360                 /* no operation */
 361                 break;
 362             }
 363         }
 364     } else {
 365         switch(s->init_state) {
 366         case 0:
 367             /* normal mode */
 368             s->imr = val;
 369             pic_update_irq(s->pics_state);
 370             break;
 371         case 1:
 372             s->irq_base = val & 0xf8;
 373             s->init_state = s->single_mode ? (s->init4 ? 3 : 0) : 2;
 374             break;
 375         case 2:
 376             if (s->init4) {
 377                 s->init_state = 3;
 378             } else {
 379                 s->init_state = 0;
 380             }
 381             break;
 382         case 3:
 383             s->special_fully_nested_mode = (val >> 4) & 1;
 384             s->auto_eoi = (val >> 1) & 1;
 385             s->init_state = 0;
 386             break;
 387         }
 388     }
 389 }
 390
 391 static uint32_t pic_poll_read (PicState *s, uint32_t addr1)
 392 {
 393     int ret;
 394
 395     ret = pic_get_irq(s);
 396     if (ret >= 0) {
 397         if (addr1 >> 7) {
 398             s->pics_state->pics[0].isr &= ~(1 << 2);
 399             s->pics_state->pics[0].irr &= ~(1 << 2);
 400         }
 401         s->irr &= ~(1 << ret);
 402         s->isr &= ~(1 << ret);
 403         if (addr1 >> 7 || ret != 2)
 404             pic_update_irq(s->pics_state);
 405     } else {
 406         ret = 0x07;
 407         pic_update_irq(s->pics_state);
 408     }
 409
 410     return ret;
 411 }
 412
 413 static uint32_t pic_ioport_read(void *opaque, uint32_t addr1)
 414 {
 415     PicState *s = opaque;
 416     unsigned int addr;
 417     int ret;
 418
 419     addr = addr1;
 420     addr &= 1;
 421     if (s->poll) {
 422         ret = pic_poll_read(s, addr1);
 423         s->poll = 0;
 424     } else {
 425         if (addr == 0) {
 426             if (s->read_reg_select)
 427                 ret = s->isr;
 428             else
 429                 ret = s->irr;
 430         } else {
 431             ret = s->imr;
 432         }
 433     }
 434 #ifdef DEBUG_PIC
 435     printf("pic_read: addr=0x%02x val=0x%02x\n", addr1, ret);
 436 #endif
 437     return ret;
 438 }
 439
 440 /* memory mapped interrupt status */
 441 /* XXX: may be the same than pic_read_irq() */
 442 uint32_t pic_intack_read(PicState2 *s)
 443 {
 444     int ret;
 445
 446     ret = pic_poll_read(&s->pics[0], 0x00);
 447     if (ret == 2)
 448         ret = pic_poll_read(&s->pics[1], 0x80) + 8;
 449     /* Prepare for ISR read */
 450     s->pics[0].read_reg_select = 1;
 451
 452     return ret;
 453 }
 454
 455 static void elcr_ioport_write(void *opaque, uint32_t addr, uint32_t val)
 456 {
 457     PicState *s = opaque;
 458     s->elcr = val & s->elcr_mask;
 459 }
 460
 461 static uint32_t elcr_ioport_read(void *opaque, uint32_t addr1)
 462 {
 463     PicState *s = opaque;
 464     return s->elcr;
 465 }
 466
 467 #ifdef USE_KVM
 468 #include "qemu-kvm.h"
 469 extern int kvm_allowed;
 470 extern kvm_context_t kvm_context;
 471
 472 static void kvm_kernel_pic_save_to_user(PicState *s)
 473 {
 474     struct kvm_irqchip chip;
 475     struct kvm_pic_state *kpic;
 476
 477     chip.chip_id = (&s->pics_state->pics[0] == s) ?
 478                    KVM_IRQCHIP_PIC_MASTER :
 479                    KVM_IRQCHIP_PIC_SLAVE;
 480     kvm_get_irqchip(kvm_context, &chip);
 481     kpic = &chip.chip.pic;
 482
 483     s->last_irr = kpic->last_irr;
 484     s->irr = kpic->irr;
 485     s->imr = kpic->imr;
 486     s->isr = kpic->isr;
 487     s->priority_add = kpic->priority_add;
 488     s->irq_base = kpic->irq_base;
 489     s->read_reg_select = kpic->read_reg_select;
 490     s->poll = kpic->poll;
 491     s->special_mask = kpic->special_mask;
 492     s->init_state = kpic->init_state;
 493     s->auto_eoi = kpic->auto_eoi;
 494     s->rotate_on_auto_eoi = kpic->rotate_on_auto_eoi;
 495     s->special_fully_nested_mode = kpic->special_fully_nested_mode;
 496     s->init4 = kpic->init4;
 497     s->elcr = kpic->elcr;
 498     s->elcr_mask = kpic->elcr_mask;
 499 }
 500
 501 static void kvm_kernel_pic_load_from_user(PicState *s)
 502 {
 503     struct kvm_irqchip chip;
 504     struct kvm_pic_state *kpic;
 505
 506     chip.chip_id = (&s->pics_state->pics[0] == s) ?
 507                    KVM_IRQCHIP_PIC_MASTER :
 508                    KVM_IRQCHIP_PIC_SLAVE;
 509     kpic = &chip.chip.pic;
 510
 511     kpic->last_irr = s->last_irr;
 512     kpic->irr = s->irr;
 513     kpic->imr = s->imr;
 514     kpic->isr = s->isr;
 515     kpic->priority_add = s->priority_add;
 516     kpic->irq_base = s->irq_base;
 517     kpic->read_reg_select = s->read_reg_select;
 518     kpic->poll = s->poll;
 519     kpic->special_mask = s->special_mask;
 520     kpic->init_state = s->init_state;
 521     kpic->auto_eoi = s->auto_eoi;
 522     kpic->rotate_on_auto_eoi = s->rotate_on_auto_eoi;
 523     kpic->special_fully_nested_mode = s->special_fully_nested_mode;
 524     kpic->init4 = s->init4;
 525     kpic->elcr = s->elcr;
 526     kpic->elcr_mask = s->elcr_mask;
 527
 528     kvm_set_irqchip(kvm_context, &chip);
 529 }
 530 #endif
 531
 532 static void pic_save(QEMUFile *f, void *opaque)
 533 {
 534     PicState *s = opaque;
 535
 536 #ifdef USE_KVM
 537     if (kvm_allowed && kvm_irqchip_in_kernel(kvm_context)) {
 538         kvm_kernel_pic_save_to_user(s);
 539     }
 540 #endif
 541
 542     qemu_put_8s(f, &s->last_irr);
 543     qemu_put_8s(f, &s->irr);
 544     qemu_put_8s(f, &s->imr);
 545     qemu_put_8s(f, &s->isr);
 546     qemu_put_8s(f, &s->priority_add);
 547     qemu_put_8s(f, &s->irq_base);
 548     qemu_put_8s(f, &s->read_reg_select);
 549     qemu_put_8s(f, &s->poll);
 550     qemu_put_8s(f, &s->special_mask);
 551     qemu_put_8s(f, &s->init_state);
 552     qemu_put_8s(f, &s->auto_eoi);
 553     qemu_put_8s(f, &s->rotate_on_auto_eoi);
 554     qemu_put_8s(f, &s->special_fully_nested_mode);
 555     qemu_put_8s(f, &s->init4);
 556     qemu_put_8s(f, &s->single_mode);
 557     qemu_put_8s(f, &s->elcr);
 558 }
 559
 560 static int pic_load(QEMUFile *f, void *opaque, int version_id)
 561 {
 562     PicState *s = opaque;
 563
 564     if (version_id != 1)
 565         return -EINVAL;
 566
 567     qemu_get_8s(f, &s->last_irr);
 568     qemu_get_8s(f, &s->irr);
 569     qemu_get_8s(f, &s->imr);
 570     qemu_get_8s(f, &s->isr);
 571     qemu_get_8s(f, &s->priority_add);
 572     qemu_get_8s(f, &s->irq_base);
 573     qemu_get_8s(f, &s->read_reg_select);
 574     qemu_get_8s(f, &s->poll);
 575     qemu_get_8s(f, &s->special_mask);
 576     qemu_get_8s(f, &s->init_state);
 577     qemu_get_8s(f, &s->auto_eoi);
 578     qemu_get_8s(f, &s->rotate_on_auto_eoi);
 579     qemu_get_8s(f, &s->special_fully_nested_mode);
 580     qemu_get_8s(f, &s->init4);
 581     qemu_get_8s(f, &s->single_mode);
 582     qemu_get_8s(f, &s->elcr);
 583
 584 #ifdef USE_KVM
 585     if (kvm_allowed && kvm_irqchip_in_kernel(kvm_context)) {
 586         kvm_kernel_pic_load_from_user(s);
 587     }
 588 #endif
 589
 590     return 0;
 591 }
 592
 593 /* XXX: add generic master/slave system */
 594 static void pic_init1(int io_addr, int elcr_addr, PicState *s)
 595 {
 596     register_ioport_write(io_addr, 2, 1, pic_ioport_write, s);
 597     register_ioport_read(io_addr, 2, 1, pic_ioport_read, s);
 598     if (elcr_addr >= 0) {
 599         register_ioport_write(elcr_addr, 1, 1, elcr_ioport_write, s);
 600         register_ioport_read(elcr_addr, 1, 1, elcr_ioport_read, s);
 601     }
 602     register_savevm("i8259", io_addr, 1, pic_save, pic_load, s);
 603     qemu_register_reset(pic_reset, s);
 604 }
 605
 606 void pic_info(void)
 607 {
 608     int i;
 609     PicState *s;
 610
 611     if (!isa_pic)
 612         return;
 613
 614     for(i=0;i<2;i++) {
 615         s = &isa_pic->pics[i];
 616         term_printf("pic%d: irr=%02x imr=%02x isr=%02x hprio=%d irq_base=%02x rr_sel=%d elcr=%02x fnm=%d\n",
 617                     i, s->irr, s->imr, s->isr, s->priority_add,
 618                     s->irq_base, s->read_reg_select, s->elcr,
 619                     s->special_fully_nested_mode);
 620     }
 621 }
 622
 623 void irq_info(void)
 624 {
 625 #ifndef DEBUG_IRQ_COUNT
 626     term_printf("irq statistic code not compiled.\n");
 627 #else
 628     int i;
 629     int64_t count;
 630
 631     term_printf("IRQ statistics:\n");
 632     for (i = 0; i < 16; i++) {
 633         count = irq_count[i];
 634         if (count > 0)
 635             term_printf("%2d: %" PRId64 "\n", i, count);
 636     }
 637 #endif
 638 }
 639
 640 qemu_irq *i8259_init(qemu_irq parent_irq)
 641 {
 642     PicState2 *s;
 643
 644     s = qemu_mallocz(sizeof(PicState2));
 645     if (!s)
 646         return NULL;
 647     pic_init1(0x20, 0x4d0, &s->pics[0]);
 648     pic_init1(0xa0, 0x4d1, &s->pics[1]);
 649     s->pics[0].elcr_mask = 0xf8;
 650     s->pics[1].elcr_mask = 0xde;
 651     s->parent_irq = parent_irq;
 652     s->pics[0].pics_state = s;
 653     s->pics[1].pics_state = s;
 654     isa_pic = s;
 655     return qemu_allocate_irqs(i8259_set_irq, s, 16);
 656 }
 657
 658 void pic_set_alt_irq_func(PicState2 *s, SetIRQFunc *alt_irq_func,
 659                           void *alt_irq_opaque)
 660 {
 661     s->alt_irq_func = alt_irq_func;
 662     s->alt_irq_opaque = alt_irq_opaque;
 663 }